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thinking about the design rules - voltage and current

Asked by pidhunter

Thinking about the design rules

this nice feature may help to make the design of the board easier, but what occurs in the real life ?

If i try to mix lines with high/low voltage with high/low current in all possible combinations, this
feature will not produce optimal results, because the current may only affect the minmal
thickness of lines. This fact need a local parameter "maximal current" in A and a global
parameter "maximal current per mm" in A/mm

The voltage may only affect the distance beetwen lines of different potentials.

This fact need 2 local parameters with the lowest negative and the highest positive peak to peak
potential in V, because 3x230V AC is not the same potential as 230AC and one global parameter
"maximal voltage per mm" in kV per mm.

Examples:
------------
- 8A need about 3mm at minimum, but the distance is only affected by voltage - it may high or low ?? - but this is important.
- 5V/1mA may need 0,2mm thickness and 0,2mm distance
- 5V/8A may need 3mm thickness and 0.2mm distance
- 230V/8A AC need also 3mm thickness but a distance of 2,2mm
- 3x230AC/8A may need also thickness of 3mm, but a distance of 4mm because it has 400V effective voltage between each of the other 3 potentials, the distance between 230VL1 and Ground is 2,2mm and the distance to 230VL2 is 4mm and double distance for safety is 2x2,2mm=4,4mm to 5V DC.

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Lorenzo Marcantonio (l-marcantonio) said : 		#1

On Thu, 13 May 2010, pidhunter wrote:

> New question #110858 on KiCad:
> https://answers.launchpad.net/kicad/+question/110858
>
> Thinking about the design rules
>
> this nice feature may help to make the design of the board easier, but what occurs in the real life ?
>
> If i try to mix lines with high/low voltage with high/low current in all possible combinations, this
> feature will not produce optimal results, because the current may only affect the minmal
> thickness of lines. This fact need a local parameter "maximal current" in A and a global
> parameter "maximal current per mm" in A/mm
>
> The voltage may only affect the distance beetwen lines of different potentials.

There are of course a *lot* of condition governing the effective track
width to be used, the design rule only exists to give a useful
default... it's the pcb designer that should consider the effective
signal usage in the lines.

A really simple example: a 5A power supply has an output line of sizable
dimension (depending on copper thickness, working temperature,
acceptable rise and so on). But the voltage sense for the feedback
amplifier, while technically part of the same net, carries no current at
all (just the input bias current of the error amplifier), so a measly
6 mil track would suffice *for that segment*.

That's the reason for the 'additional track sizes' in the global design
rule dialog page.

--
Lorenzo Marcantonio
Logos Srl

Revision history for this message
pidhunter (pidhunter) said : 		#2

i think the erc-check need also a knowledge of current and voltage for each line to check
the dimensions of the copper wire i use.

Revision history for this message
pidhunter (pidhunter) said : 		#3

@Lorenzo Marcantonio

the conclusion for bias - i have to split this potential logical into two potentials, but i have to connect both potentials
togehther in copper ?

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