What does it mean the d16 in fpu option of fpv4-sp-d16?

For FPU defined in Cortex-M profile, it has an FP register bank, which can be viewed by software as below:
1. Thirty-two 32 bit single-precision registers, S0-S31.
2. Sixteen 64 bit double-precision registers, D0-d15.
The relation is something like:
               d0 <-> (s0,s1)
               d1 <-> (s2,s3)
               d2 <-> (s4,s5)
               .......
               d15 <-> (s30,s31)

For double word floating registers, the FPU only supports data transferring instructions.
For more information, you can refer to ARM architecture reference manual for Cortex-M profile.

Hoping this help.

Thanks for the answer. Just little more need to be clarified.
1. What the exact ARM document you are referring? Can you provide the exact document's name?

    I saw <<ARMv7-M Architecture Reference Manual>>, but this is only for Cortex-M3. I can't find <<ARMv7E-M Architecture Reference Manual>>.
   I saw <<Cortex™-M4 Devices Generic User Guide>> and <<Cortex®-M4 Technical Reference Manual>>, but nowhere can find <<ARM Architecture Reference Manual for Cortex®-M4>>.

2. What is the difference if w/o -d16?

   I saw that the GNU Tools for ARM Embedded has no option -mfpu=fpv4-sp but only -mfpu=fpv4-sp-d16.
   To ARM Compiler toolchain Compiler, there are options of --fpu= vfpv4, vfpv4_d16 and fpv4-sp. I quote comments for each option as below:
     vfpv4
             Selects a hardware floating-point unit conforming to the VFPv4 architecture.
     vfpv4_d16
            Selects a hardware floating-point unit conforming to the VFPv4-D16 architecture.
     fpv4-sp
           Selects a hardware floating-point unit conforming to the single precision variant of the FPv4 architecture.

   I understand that the implementation of vfpv4 and vfpv4_d16 were for Cortex-A only. I'm guessing wildly that fpv4-sp means "Floating Point unit Version 4, Single Precision, only access as thirty-two 32-bit register. (can't access as sixteen double word registers)" ?

Thanks chengbin, that solved my question.

One correction: yes, <<ARMv7-M Architecture Reference Manual>> is for
Cortex-M3/M4, but not for Cortex-M0/M1/M0+

- Joey

On Tue, Oct 16, 2012 at 11:35 AM, chengbin <
<email address hidden>> wrote:

> Question #211248 on GCC ARM Embedded changed:
> https://answers.launchpad.net/gcc-arm-embedded/+question/211248
>
> chengbin proposed the following answer:
> Hi,
> I referred to <<ARMv7-M Architecture Reference Manual>>, it is manual for
> M-profile, rather than only M3.
>
> As far as I know, fpv4-sp-d16 in GCC and fpv4-sp in ARM Toolchain are
> different names for the same thing, they both supports :
> • FP extension registers that software can view as either 32
> single-precision or 16 doubleword registers
> • single-precision floating-point arithmetic
> • conversions between integer, single-precision floating-point, and
> half-precision floating point formats.
> • data transfers of single-precision and doubleword registers.
>
>
> Hoping this can help.
>
> --
> You received this question notification because you are an answer
> contact for GCC ARM Embedded.
>

Hi,
The option fpv4-sp-d16 from gcc is not equivalent to fpv4-sp in armcc/armlink.
The fromelf utiliy shows:
- with gcc:
Tag_ABI_HardFP_use = SP and DP operations are permitted to use VFP instructions (=3)
- with armcc
Tag_ABI_HardFP_use = SP operations are permitted to use VFP instructions (=1)

And if you try to link an obj file build with gcc using armlink you'll have this link error:
Object toto.o contains Build Attributes that are incompatible with the CPU attributes.
    Tag_ABI_HardFP_use = Permitted VFP use is implied by Tag_VFP_arch (=0)