diff -Nru gcc-4.8-4.8.1/debian/changelog gcc-4.8-4.8.2/debian/changelog --- gcc-4.8-4.8.1/debian/changelog 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/changelog 2013-10-17 15:57:25.000000000 +0000 @@ -1,8 +1,139 @@ -gcc-4.8 (4.8.1-8ubuntu2~ppa1) saucy; urgency=low +gcc-4.8 (4.8.2-1ubuntu1) saucy; urgency=low - * Pull two Linaro updates. + * Merge with Debian; remaining changes: + - Build from the upstream source. + + -- Matthias Klose Wed, 16 Oct 2013 13:43:20 +0200 + +gcc-4.8 (4.8.2-1) unstable; urgency=low + + * GCC 4.8.2 release. + + * Update to SVN 20131017 (r203751) from the gcc-4_8-branch. + * Update the Linaro support to the 4.8-2013.10 release. + * Fix PR c++/57850, option -fdump-translation-unit not working. + * Don't run the testsuite on aarch64. + * Fix PR target/58578, wrong-code regression on ARM. LP: #1232017. + * [ARM] Fix bug in add patterns due to commutativity modifier, + backport from trunk. LP: #1234060. + * Build libatomic on AArch64. + * Fix dependency generation for the cross gcc-4.8 package. + * Make the libstdc++ pretty printers compatible with Python3, if + gdb is built with Python3 support. + * Fix loading of libstdc++ pretty printers. Closes: #701935. + * Don't let gcc-snapshot build-depend on gnat on AArch64. + + -- Matthias Klose Thu, 17 Oct 2013 14:37:55 +0200 + +gcc-4.8 (4.8.1-10ubuntu7) saucy; urgency=low + + * Update to SVN 20131008 (r203273) from the gcc-4_8-branch. + - Fix PR libstdc++/57641, PR libstdc++/57465, PR libstdc++/58569. + - S390 updates, fix PR target/58460 (AArch64). + - Fix PR c++/58535 (ice on invalid), PR fortran/57697, PR fortran/58469. + - Go updates. + * Fix dependency generation for the cross gcc-4.8 package. + * Re-enable gcj on AArch64. + + -- Matthias Klose Tue, 08 Oct 2013 14:51:58 +0200 + +gcc-4.8 (4.8.1-10ubuntu6) saucy; urgency=low + + * [ARM] Fix bug in add patterns due to commutativity modifier, + backport from trunk. LP: #1234060. + * Build libatomic on AArch64. + + -- Matthias Klose Wed, 02 Oct 2013 14:57:31 +0200 + +gcc-4.8 (4.8.1-10ubuntu5) saucy; urgency=low + + * Update to SVN 20131001 (r203063) from the gcc-4_8-branch. + - Fix PR libstdc++/58437, PR middle-end/58463, PR tree-optimization/56716, + PR middle-end/58564, PR target/58574 (s390). + - Go updates. + * Fix PR target/58578, wrong-code regression on ARM. LP: #1232017. + + -- Matthias Klose Tue, 01 Oct 2013 18:48:31 +0200 + +gcc-4.8 (4.8.1-10ubuntu4) saucy; urgency=low + + * Update to SVN 20130927 (r202974) from the gcc-4_8-branch. + * Fix PR c++/57850, option -fdump-translation-unit not working. + * For a first arm64 build in launchpad, disable the testsuite + and don't build gcj packages. + + -- Matthias Klose Fri, 27 Sep 2013 19:00:06 +0200 + +gcc-4.8 (4.8.1-10ubuntu3) saucy; urgency=low + + * Update to SVN 20130915 (r202601) from the gcc-4_8-branch. + * Update the Linaro support to the 4.8-2013.09 release. + + -- Matthias Klose Mon, 16 Sep 2013 10:43:58 +0200 + +gcc-4.8 (4.8.1-10ubuntu2) saucy; urgency=low + + * Disable gcc-default-format-security on non-ssp arches, as it + appears to depend on the SSP patch also being applied to work. + + -- Adam Conrad Fri, 13 Sep 2013 21:19:05 -0400 + +gcc-4.8 (4.8.1-10ubuntu1) saucy; urgency=low + + * Merge with Debian, remaining changes: + - Build from the upstream source. + + -- Matthias Klose Thu, 05 Sep 2013 00:36:37 +0200 + +gcc-4.8 (4.8.1-10) unstable; urgency=low + + * Update to SVN 20130904 (r202243) from the gcc-4_8-branch. + + [ Matthias Klose ] + * Don't rely on the most recent Debian release name for configuration + of the package. Addresses: #720263. Closes: #711824. + * Fix a cross build issue without DEB_* env vars set (Eleanor Chen). + Closes: #718614. + * Add packaging support for mips64(el) and mipsn32(el) including multilib + configurations (YunQiang Su). Addresses: #708143. + * Fix gcc dependencies for stage1 builds (YunQiang Su). Closes: #710240. + * Fix boehm-gc test failures with a linker defaulting to + --no-copy-dt-needed-entries. + * Fix libstdc++ and libjava test failures with a linker defaulting + to --as-needed. + * Mark the libjava/sourcelocation test as expected to fail on amd64 cpus. + * Fix some gcc and g++ test failures for a compiler with hardening + defaults enabled. + * Fix gcc-default-format-security.diff for GCC 4.8. + * Run the testsuite again on armel and armhf. + * Disable running the testsuite on mips. Fails on the buildds, preventing + migration to testing for three months. No feedback from the mips porters. + + [ Thorsten Glaser ] + * Merge several old m68k-specific patches from gcc-4.6 package: + - libffi-m68k: Rebased against gcc-4.8 and libffi 3.0.13-4. + - m68k-revert-pr45144: Needed for Ada. + - pr52714: Revert optimisation that breaks CC0 arch. + * Fix PR49847 (Mikael Pettersson). Closes: #711558. + * Use -fno-auto-inc-dec for PR52306 (Mikael Pettersson). + + -- Matthias Klose Wed, 04 Sep 2013 21:30:07 +0200 + +gcc-4.8 (4.8.1-9ubuntu1) saucy; urgency=low + + * Merge with Debian, remaining changes: + - Build from the upstream source. + * Re-enable running the testsuite on armhf. + + -- Matthias Klose Thu, 15 Aug 2013 14:40:11 +0200 + +gcc-4.8 (4.8.1-9) unstable; urgency=low + + * Update to SVN 20130815 (r201764) from the gcc-4_8-branch. + * Enable gomp on AArch64. + * Update the Linaro support to the 4.8-2013.08 release. - -- Matthias Klose Sat, 03 Aug 2013 23:59:57 +0200 + -- Matthias Klose Thu, 15 Aug 2013 10:47:38 +0200 gcc-4.8 (4.8.1-8ubuntu1) saucy; urgency=low diff -Nru gcc-4.8-4.8.1/debian/control gcc-4.8-4.8.2/debian/control --- gcc-4.8-4.8.1/debian/control 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/control 2013-10-17 15:57:25.000000000 +0000 @@ -5,10 +5,8 @@ XSBC-Original-Maintainer: Debian GCC Maintainers Uploaders: Matthias Klose Standards-Version: 3.9.4 -Build-Depends: debhelper (>= 5.0.62), g++-multilib [amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc sparc64 x32], - libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6), libc6-dev (>= 2.13-31) [armel armhf], - libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-sparc [sparc64], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32], libn32gcc1 [mips mipsel], lib64gcc1 [i386 mips mipsel powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel], libc6-dev-mipsn32 [mips mipsel], libc6-dev-x32 [amd64 i386], libx32gcc1 [amd64 i386], libc6-dev-armhf [armel], libhfgcc1 [armel], libc6-dev-armel [armhf], libsfgcc1 [armhf], - libc6.1-dbg [alpha ia64] | libc0.3-dbg [hurd-i386] | libc0.1-dbg [kfreebsd-i386 kfreebsd-amd64] | libc6-dbg, +Build-Depends: debhelper (>= 5.0.62), g++-multilib [amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32], + libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6), libc6-dev (>= 2.13-31) [armel armhf], libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-sparc [sparc64], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 mipsn32 mipsn32el mips64 mips64el s390x sparc64 x32], libn32gcc1 [mips mipsel mips64 mips64el], lib64gcc1 [i386 mips mipsel mipsn32 mipsn32el powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel mipsn32 mipsn32el], libc6-dev-mipsn32 [mips mipsel mips64 mips64el], libc6-dev-mips32 [mipsn32 mipsn32el mips64 mips64el], libc6-dev-x32 [amd64 i386], libx32gcc1 [amd64 i386], libc6-dev-armhf [armel], libhfgcc1 [armel], libc6-dev-armel [armhf], libsfgcc1 [armhf], libc6.1-dbg [alpha ia64] | libc0.3-dbg [hurd-i386] | libc0.1-dbg [kfreebsd-i386 kfreebsd-amd64] | libc6-dbg, kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], m4, libtool, autoconf2.64, libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], @@ -18,7 +16,7 @@ texinfo (>= 4.3), locales, sharutils, procps, zlib1g-dev, libantlr-java, python, libffi-dev, fastjar, libmagic-dev, libecj-java (>= 3.3.0-2), zip, libasound2-dev [ !hurd-any !kfreebsd-any], libxtst-dev, libxt-dev, libgtk2.0-dev (>= 2.4.4-2), libart-2.0-dev, libcairo2-dev, g++-4.8 [armel armhf], netbase, libcloog-isl-dev (>= 0.18), libmpc-dev (>= 1.0), libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), - dejagnu [!m68k !hurd-amd64 !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, quilt + dejagnu [!arm64 !m68k !hurd-amd64 !hurd-i386 !hurd-alpha], autogen, realpath (>= 1.9.12), chrpath, lsb-release, quilt Build-Depends-Indep: doxygen (>= 1.7.2), graphviz (>= 2.2), ghostscript, texlive-latex-base, xsltproc, libxml2-utils, docbook-xsl-ns, Homepage: http://gcc.gnu.org/ XS-Vcs-Browser: http://svn.debian.org/viewsvn/gcccvs/branches/sid/gcc-4.8/ @@ -116,7 +114,7 @@ Debug symbols for the GCC support library. Package: lib64gcc1 -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: libs Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} @@ -127,7 +125,7 @@ special needs for some languages. Package: lib64gcc1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} @@ -135,7 +133,7 @@ Debug symbols for the GCC support library. Package: lib64gcc-4.8-dev -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: libdevel Priority: optional Recommends: ${dep:libcdev} @@ -145,7 +143,7 @@ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. Package: lib32gcc1 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: libs Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} @@ -156,7 +154,7 @@ special needs for some languages. Package: lib32gcc1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} @@ -164,7 +162,7 @@ Debug symbols for the GCC support library. Package: lib32gcc-4.8-dev -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: libdevel Priority: optional Recommends: ${dep:libcdev} @@ -234,7 +232,7 @@ building C programs which use libgcc, libgomp, libquadmath, libssp or libitm. Package: libn32gcc1 -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: libs Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${misc:Depends} @@ -245,7 +243,7 @@ special needs for some languages. Package: libn32gcc1-dbg -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32gcc1 (= ${gcc:EpochVersion}), ${misc:Depends} @@ -253,7 +251,7 @@ Debug symbols for the GCC support library. Package: libn32gcc-4.8-dev -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: libdevel Priority: optional Recommends: ${dep:libcdev} @@ -294,7 +292,9 @@ Architecture: any Section: devel Priority: optional -Depends: gcc-4.8-base (= ${gcc:Version}), cpp-4.8 (= ${gcc:Version}), binutils (>= ${binutils:Version}), libgcc-4.8-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} +Depends: cpp-4.8 (= ${gcc:Version}), gcc-4.8-base (= ${gcc:Version}), + binutils (>= ${binutils:Version}), + libgcc-4.8-dev (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Recommends: ${dep:libcdev} Suggests: ${gcc:multilib}, libmudflap0-4.8-dev (= ${gcc:Version}), gcc-4.8-doc (>= ${gcc:SoftVersion}), gcc-4.8-locales (>= ${gcc:SoftVersion}), libgcc1-dbg (>= ${libgcc:Version}), libgomp1-dbg (>= ${gcc:Version}), libitm1-dbg (>= ${gcc:Version}), libatomic1-dbg (>= ${gcc:Version}), libasan0-dbg (>= ${gcc:Version}), libtsan0-dbg (>= ${gcc:Version}), libbacktrace1-dbg (>= ${gcc:Version}), libquadmath0-dbg (>= ${gcc:Version}), libmudflap0-dbg (>= ${gcc:Version}), ${dep:libcloog}, ${dep:gold} Provides: c-compiler @@ -302,7 +302,7 @@ This is the GNU C compiler, a fairly portable optimizing compiler for C. Package: gcc-4.8-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc sparc64 x32 +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32 Section: devel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), gcc-4.8 (= ${gcc:Version}), ${dep:libcbiarchdev}, ${dep:libgccbiarchdev}, ${shlibs:Depends}, ${misc:Depends} @@ -378,7 +378,7 @@ This is the GNU C++ compiler, a fairly portable optimizing compiler for C++. Package: g++-4.8-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc sparc64 x32 +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32 Section: devel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), g++-4.8 (= ${gcc:Version}), gcc-4.8-multilib (= ${gcc:Version}), ${dep:libcxxbiarchdev}, ${shlibs:Depends}, ${misc:Depends} @@ -414,7 +414,7 @@ dereferencing operations. Package: lib32mudflap0 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: libs Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} @@ -425,7 +425,7 @@ dereferencing operations. Package: lib32mudflap0-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32mudflap0 (= ${gcc:Version}), ${misc:Depends} @@ -434,7 +434,7 @@ dereferencing operations. Package: lib64mudflap0 -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: libs Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} @@ -444,7 +444,7 @@ dereferencing operations. Package: lib64mudflap0-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64mudflap0 (= ${gcc:Version}), ${misc:Depends} @@ -453,7 +453,7 @@ dereferencing operations. Package: libn32mudflap0 -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: libs Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} @@ -463,7 +463,7 @@ dereferencing operations. Package: libn32mudflap0-dbg -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32mudflap0 (= ${gcc:Version}), ${misc:Depends} @@ -569,7 +569,7 @@ Package: lib32gomp1 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -578,7 +578,7 @@ in the GNU Compiler Collection. Package: lib32gomp1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32gomp1 (= ${gcc:Version}), ${misc:Depends} @@ -588,7 +588,7 @@ Package: lib64gomp1 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: GCC OpenMP (GOMP) support library (64bit) @@ -596,7 +596,7 @@ in the GNU Compiler Collection. Package: lib64gomp1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64gomp1 (= ${gcc:Version}), ${misc:Depends} @@ -606,7 +606,7 @@ Package: libn32gomp1 Section: libs -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: GCC OpenMP (GOMP) support library (n32) @@ -614,7 +614,7 @@ in the GNU Compiler Collection. Package: libn32gomp1-dbg -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32gomp1 (= ${gcc:Version}), ${misc:Depends} @@ -703,7 +703,7 @@ Package: lib32itm1 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -713,7 +713,7 @@ accesses to shared memory by several threads. Package: lib32itm1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32itm1 (= ${gcc:Version}), ${misc:Depends} @@ -724,7 +724,7 @@ Package: lib64itm1 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: GNU Transactional Memory Library (64bit) @@ -733,7 +733,7 @@ accesses to shared memory by several threads. Package: lib64itm1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64itm1 (= ${gcc:Version}), ${misc:Depends} @@ -744,7 +744,7 @@ Package: libn32itm1 Section: libs -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: GNU Transactional Memory Library (n32) @@ -753,7 +753,7 @@ accesses to shared memory by several threads. Package: libn32itm1-dbg -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32itm1 (= ${gcc:Version}), ${misc:Depends} @@ -849,7 +849,7 @@ Package: lib32atomic1 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -858,7 +858,7 @@ be turned into lock-free instructions, GCC will make calls into this library. Package: lib32atomic1-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32atomic1 (= ${gcc:Version}), ${misc:Depends} @@ -868,7 +868,7 @@ Package: lib64atomic1 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: support library providing __atomic built-in functions (64bit) @@ -876,7 +876,7 @@ be turned into lock-free instructions, GCC will make calls into this library. Package: lib64atomic1-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64atomic1 (= ${gcc:Version}), ${misc:Depends} @@ -886,7 +886,7 @@ Package: libn32atomic1 Section: libs -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: support library providing __atomic built-in functions (n32) @@ -894,7 +894,7 @@ be turned into lock-free instructions, GCC will make calls into this library. Package: libn32atomic1-dbg -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32atomic1 (= ${gcc:Version}), ${misc:Depends} @@ -983,7 +983,7 @@ Package: lib32asan0 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -992,7 +992,7 @@ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs. Package: lib32asan0-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32asan0 (= ${gcc:Version}), ${misc:Depends} @@ -1002,7 +1002,7 @@ Package: lib64asan0 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: AddressSanitizer -- a fast memory error detector (64bit) @@ -1010,7 +1010,7 @@ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs. Package: lib64asan0-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64asan0 (= ${gcc:Version}), ${misc:Depends} @@ -1020,7 +1020,7 @@ Package: libn32asan0 Section: libs -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: AddressSanitizer -- a fast memory error detector (n32) @@ -1028,7 +1028,7 @@ use-after-free and {heap,stack,global}-buffer overflow bugs in C/C++ programs. Package: libn32asan0-dbg -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32asan0 (= ${gcc:Version}), ${misc:Depends} @@ -1139,7 +1139,7 @@ Package: lib32quadmath0 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -1149,7 +1149,7 @@ targets the REAL(16) type in the GNU Fortran compiler. Package: lib32quadmath0-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32quadmath0 (= ${gcc:Version}), ${misc:Depends} @@ -1159,7 +1159,7 @@ Package: lib64quadmath0 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: GCC Quad-Precision Math Library (64bit) @@ -1168,7 +1168,7 @@ targets the REAL(16) type in the GNU Fortran compiler. Package: lib64quadmath0-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64quadmath0 (= ${gcc:Version}), ${misc:Depends} @@ -1178,7 +1178,7 @@ Package: libn32quadmath0 Section: libs -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: GCC Quad-Precision Math Library (n32) @@ -1187,7 +1187,7 @@ targets the REAL(16) type in the GNU Fortran compiler. Package: libn32quadmath0-dbg -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32quadmath0 (= ${gcc:Version}), ${misc:Depends} @@ -1264,7 +1264,7 @@ gcc backend to generate optimized code. Package: gobjc++-4.8-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc sparc64 x32 +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32 Section: devel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), gobjc++-4.8 (= ${gcc:Version}), g++-4.8-multilib (= ${gcc:Version}), gobjc-4.8-multilib (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -1287,7 +1287,7 @@ gcc backend to generate optimized code. Package: gobjc-4.8-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc sparc64 x32 +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32 Section: devel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), gobjc-4.8 (= ${gcc:Version}), gcc-4.8-multilib (= ${gcc:Version}), ${dep:libobjcbiarchdev}, ${shlibs:Depends}, ${misc:Depends} @@ -1309,7 +1309,7 @@ GNU ObjC applications. Package: lib64objc-4.8-dev -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), lib64gcc-4.8-dev (= ${gcc:Version}), lib64objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -1318,7 +1318,7 @@ GNU ObjC applications. Package: lib32objc-4.8-dev -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), lib32gcc-4.8-dev (= ${gcc:Version}), lib32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -1327,7 +1327,7 @@ GNU ObjC applications. Package: libn32objc-4.8-dev -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), libn32gcc-4.8-dev (= ${gcc:Version}), libn32objc4 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -1385,7 +1385,7 @@ Package: lib64objc4 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: Runtime library for GNU Objective-C applications (64bit) @@ -1393,7 +1393,7 @@ Package: lib64objc4-dbg Section: debug -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64objc4 (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends} Description: Runtime library for GNU Objective-C applications (64 bit debug symbols) @@ -1401,7 +1401,7 @@ Package: lib32objc4 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -1410,7 +1410,7 @@ Package: lib32objc4-dbg Section: debug -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32objc4 (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends} Description: Runtime library for GNU Objective-C applications (32 bit debug symbols) @@ -1418,7 +1418,7 @@ Package: libn32objc4 Section: libs -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: Runtime library for GNU Objective-C applications (n32) @@ -1426,7 +1426,7 @@ Package: libn32objc4-dbg Section: debug -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32objc4 (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}), ${misc:Depends} Description: Runtime library for GNU Objective-C applications (n32 debug symbols) @@ -1496,7 +1496,7 @@ gcc backend to generate optimized code. Package: gfortran-4.8-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc sparc64 x32 +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32 Section: devel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), gfortran-4.8 (= ${gcc:Version}), gcc-4.8-multilib (= ${gcc:Version}), ${dep:libgfortranbiarchdev}, ${shlibs:Depends}, ${misc:Depends} @@ -1526,7 +1526,7 @@ GNU Fortran applications. Package: lib64gfortran-4.8-dev -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), lib64gcc-4.8-dev (= ${gcc:Version}), lib64gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -1535,7 +1535,7 @@ GNU Fortran applications. Package: lib32gfortran-4.8-dev -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), lib32gcc-4.8-dev (= ${gcc:Version}), lib32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -1544,7 +1544,7 @@ GNU Fortran applications. Package: libn32gfortran-4.8-dev -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), libn32gcc-4.8-dev (= ${gcc:Version}), libn32gfortran3 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -1605,7 +1605,7 @@ Package: lib64gfortran3 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: Runtime library for GNU Fortran applications (64bit) @@ -1614,7 +1614,7 @@ Package: lib64gfortran3-dbg Section: debug -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64gfortran3 (= ${gcc:Version}), ${misc:Depends} Description: Runtime library for GNU Fortran applications (64bit debug symbols) @@ -1623,7 +1623,7 @@ Package: lib32gfortran3 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -1633,7 +1633,7 @@ Package: lib32gfortran3-dbg Section: debug -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32gfortran3 (= ${gcc:Version}), ${misc:Depends} Description: Runtime library for GNU Fortran applications (32 bit debug symbols) @@ -1642,7 +1642,7 @@ Package: libn32gfortran3 Section: libs -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Description: Runtime library for GNU Fortran applications (n32) @@ -1651,7 +1651,7 @@ Package: libn32gfortran3-dbg Section: debug -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32gfortran3 (= ${gcc:Version}), ${misc:Depends} Description: Runtime library for GNU Fortran applications (n32 debug symbols) @@ -1727,7 +1727,7 @@ by the gcc compiler. It uses the gcc backend to generate optimized code. Package: gccgo-4.8-multilib -Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mipsel powerpc ppc64 s390 s390x sparc sparc64 x32 +Architecture: amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32 Section: devel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), gccgo-4.8 (= ${gcc:Version}), gcc-4.8-multilib (= ${gcc:Version}), ${dep:libgobiarch}, ${shlibs:Depends}, ${misc:Depends} @@ -1773,7 +1773,7 @@ Package: lib64go4 Section: libs -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: lib64go3 @@ -1783,7 +1783,7 @@ Package: lib64go4-dbg Section: debug -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64go4 (= ${gcc:Version}), ${misc:Depends} Description: Runtime library for GNU Go applications (64bit debug symbols) @@ -1792,7 +1792,7 @@ Package: lib32go4 Section: libs -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Conflicts: ${confl:lib32} @@ -1803,7 +1803,7 @@ Package: lib32go4-dbg Section: debug -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32go4 (= ${gcc:Version}), ${misc:Depends} Description: Runtime library for GNU Go applications (32 bit debug symbols) @@ -1812,7 +1812,7 @@ Package: libn32go4 Section: libs -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), ${dep:libcbiarch}, ${shlibs:Depends}, ${misc:Depends} Replaces: libn32go3 @@ -1822,7 +1822,7 @@ Package: libn32go4-dbg Section: debug -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32go4 (= ${gcc:Version}), ${misc:Depends} Description: Runtime library for GNU Go applications (n32 debug symbols) @@ -2018,7 +2018,7 @@ in g++-3.0. Package: lib32stdc++6 -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: libs Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -2028,7 +2028,7 @@ built with the GNU compiler. Package: lib64stdc++6 -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: libs Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), lib64gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -2041,7 +2041,7 @@ in g++-3.0. Package: libn32stdc++6 -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: libs Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), libn32gcc1 (>= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} @@ -2137,7 +2137,7 @@ debugging symbols. Package: lib32stdc++-4.8-dev -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), lib32gcc-4.8-dev (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}), libstdc++-4.8-dev (= ${gcc:Version}), ${misc:Depends} @@ -2150,7 +2150,7 @@ in g++-3.0. Package: lib32stdc++6-4.8-dbg -Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 +Architecture: amd64 ppc64 kfreebsd-amd64 s390x sparc64 x32 mipsn32 mipsn32el mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib32stdc++6 (>= ${gcc:Version}), libstdc++-4.8-dev (= ${gcc:Version}), lib32gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} @@ -2160,7 +2160,7 @@ debugging symbols. Package: lib64stdc++-4.8-dev -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), lib64gcc-4.8-dev (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}), libstdc++-4.8-dev (= ${gcc:Version}), ${misc:Depends} @@ -2173,7 +2173,7 @@ in g++-3.0. Package: lib64stdc++6-4.8-dbg -Architecture: i386 powerpc sparc s390 mips mipsel x32 +Architecture: i386 powerpc sparc s390 mips mipsel mipsn32 mipsn32el x32 Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), lib64stdc++6 (>= ${gcc:Version}), libstdc++-4.8-dev (= ${gcc:Version}), lib64gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} @@ -2183,7 +2183,7 @@ debugging symbols. Package: libn32stdc++-4.8-dev -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: libdevel Priority: optional Depends: gcc-4.8-base (= ${gcc:Version}), libn32gcc-4.8-dev (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}), libstdc++-4.8-dev (= ${gcc:Version}), ${misc:Depends} @@ -2196,7 +2196,7 @@ in g++-3.0. Package: libn32stdc++6-4.8-dbg -Architecture: mips mipsel +Architecture: mips mipsel mips64 mips64el Section: debug Priority: extra Depends: gcc-4.8-base (= ${gcc:Version}), libn32stdc++6 (>= ${gcc:Version}), libstdc++-4.8-dev (= ${gcc:Version}), libn32gcc1-dbg (>= ${gcc:EpochVersion}), ${shlibs:Depends}, ${misc:Depends} diff -Nru gcc-4.8-4.8.1/debian/control.m4 gcc-4.8-4.8.2/debian/control.m4 --- gcc-4.8-4.8.1/debian/control.m4 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/control.m4 2013-10-17 15:57:25.000000000 +0000 @@ -61,9 +61,7 @@ bison (>= 1:2.3), flex, realpath (>= 1.9.12), lsb-release, quilt ',`dnl native Build-Depends: debhelper (>= 5.0.62), GCC_MULTILIB_BUILD_DEP - LIBC_BUILD_DEP, - LIBC_BIARCH_BUILD_DEP - LIBC_DBG_DEP + LIBC_BUILD_DEP, LIBC_BIARCH_BUILD_DEP LIBC_DBG_DEP kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], AUTO_BUILD_DEP AUTOGEN_BUILD_DEP libunwind7-dev (>= 0.98.5-6) [ia64], libatomic-ops-dev [ia64], @@ -701,7 +699,9 @@ Architecture: any Section: devel Priority: ifdef(`TARGET',`extra',`PRI(optional)') -Depends: BASEDEP, cpp`'PV`'TS (= ${gcc:Version}), binutils`'TS (>= ${binutils:Version}), libdevdep(gcc`'PV-dev`',), ${shlibs:Depends}, ${misc:Depends} +Depends: cpp`'PV`'TS (= ${gcc:Version}),ifenabled(`gccbase',` BASEDEP,') + binutils`'TS (>= ${binutils:Version}), + ifenabled(`libgcc',`libdevdep(gcc`'PV-dev`',), ')${shlibs:Depends}, ${misc:Depends} Recommends: ${dep:libcdev} Suggests: ${gcc:multilib}, libdevdep(mudflap`'MF_SO`'PV-dev,,=), gcc`'PV-doc (>= ${gcc:SoftVersion}), gcc`'PV-locales (>= ${gcc:SoftVersion}), libdbgdep(gcc`'GCC_SO-dbg,,>=,${libgcc:Version}), libdbgdep(gomp`'GOMP_SO-dbg,), libdbgdep(itm`'ITM_SO-dbg,), libdbgdep(atomic`'ATOMIC_SO-dbg,), libdbgdep(asan`'ASAN_SO-dbg,), libdbgdep(tsan`'TSAN_SO-dbg,), libdbgdep(backtrace`'BTRACE_SO-dbg,), libdbgdep(quadmath`'QMATH_SO-dbg,), libdbgdep(mudflap`'MF_SO-dbg,), ${dep:libcloog}, ${dep:gold} Provides: c-compiler`'TS diff -Nru gcc-4.8-4.8.1/debian/lib32gfortran3.symbols.mips64 gcc-4.8-4.8.2/debian/lib32gfortran3.symbols.mips64 --- gcc-4.8-4.8.1/debian/lib32gfortran3.symbols.mips64 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/lib32gfortran3.symbols.mips64 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,2 @@ +libgfortran.so.3 lib32gfortran3 #MINVER# +#include "libgfortran3.symbols.common" diff -Nru gcc-4.8-4.8.1/debian/lib32gfortran3.symbols.mips64el gcc-4.8-4.8.2/debian/lib32gfortran3.symbols.mips64el --- gcc-4.8-4.8.1/debian/lib32gfortran3.symbols.mips64el 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/lib32gfortran3.symbols.mips64el 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,2 @@ +libgfortran.so.3 lib32gfortran3 #MINVER# +#include "libgfortran3.symbols.common" diff -Nru gcc-4.8-4.8.1/debian/lib32gfortran3.symbols.mipsn32 gcc-4.8-4.8.2/debian/lib32gfortran3.symbols.mipsn32 --- gcc-4.8-4.8.1/debian/lib32gfortran3.symbols.mipsn32 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/lib32gfortran3.symbols.mipsn32 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,2 @@ +libgfortran.so.3 lib32gfortran3 #MINVER# +#include "libgfortran3.symbols.common" diff -Nru gcc-4.8-4.8.1/debian/lib32gfortran3.symbols.mipsn32el gcc-4.8-4.8.2/debian/lib32gfortran3.symbols.mipsn32el --- gcc-4.8-4.8.1/debian/lib32gfortran3.symbols.mipsn32el 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/lib32gfortran3.symbols.mipsn32el 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,2 @@ +libgfortran.so.3 lib32gfortran3 #MINVER# +#include "libgfortran3.symbols.common" diff -Nru gcc-4.8-4.8.1/debian/patches/aarch64-libatomic.diff gcc-4.8-4.8.2/debian/patches/aarch64-libatomic.diff --- gcc-4.8-4.8.1/debian/patches/aarch64-libatomic.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/aarch64-libatomic.diff 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,16 @@ +# DP: Build libatomic on AArch64. + +--- a/src/libatomic/configure.tgt ++++ b/src/libatomic/configure.tgt +@@ -95,11 +95,6 @@ + + # Other system configury + case "${target}" in +- aarch64*) +- # This is currently not supported in AArch64. +- UNSUPPORTED=1 +- ;; +- + arm*-*-linux*) + # OS support for atomic primitives. + config_path="${config_path} linux/arm posix" diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-aarch64-reentrant.diff gcc-4.8-4.8.2/debian/patches/gcc-aarch64-reentrant.diff --- gcc-4.8-4.8.1/debian/patches/gcc-aarch64-reentrant.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-aarch64-reentrant.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,15 +0,0 @@ -# DP: Define CPP_SPEC for aarch64. - - * config/aarch64/aarch64-linux.h (CPP_SPEC): Define. - ---- a/src/gcc/config/aarch64/aarch64-linux.h -+++ b/src/gcc/config/aarch64/aarch64-linux.h -@@ -23,6 +23,8 @@ - - #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64.so.1" - -+#define CPP_SPEC "%{pthread:-D_REENTRANT}" -+ - #define LINUX_TARGET_LINK_SPEC "%{h*} \ - %{static:-Bstatic} \ - %{shared:-shared} \ diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-as-needed.diff gcc-4.8-4.8.2/debian/patches/gcc-as-needed.diff --- gcc-4.8-4.8.1/debian/patches/gcc-as-needed.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-as-needed.diff 2013-10-17 15:57:25.000000000 +0000 @@ -132,3 +132,664 @@ %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ SUBTARGET_EXTRA_LINK_SPEC +--- a/src/libjava/Makefile.am ++++ b/src/libjava/Makefile.am +@@ -625,7 +625,7 @@ + rm .libs/libgcj_bc.so; \ + mv .libs/libgcj_bc.so.1.0.0 .libs/libgcj_bc.so; \ + $(libgcj_bc_dummy_LINK) -xc /dev/null -Wl,-soname,libgcj_bc.so.1 \ +- -o .libs/libgcj_bc.so.1.0.0 -lgcj || exit; \ ++ -o .libs/libgcj_bc.so.1.0.0 -Wl,--no-as-needed -lgcj || exit; \ + rm .libs/libgcj_bc.so.1; \ + $(LN_S) libgcj_bc.so.1.0.0 .libs/libgcj_bc.so.1 + +--- a/src/libjava/Makefile.in ++++ b/src/libjava/Makefile.in +@@ -10573,7 +10573,7 @@ + rm .libs/libgcj_bc.so; \ + mv .libs/libgcj_bc.so.1.0.0 .libs/libgcj_bc.so; \ + $(libgcj_bc_dummy_LINK) -xc /dev/null -Wl,-soname,libgcj_bc.so.1 \ +- -o .libs/libgcj_bc.so.1.0.0 -lgcj || exit; \ ++ -o .libs/libgcj_bc.so.1.0.0 -Wl,--no-as-needed -lgcj || exit; \ + rm .libs/libgcj_bc.so.1; \ + $(LN_S) libgcj_bc.so.1.0.0 .libs/libgcj_bc.so.1 + +--- a/src/libstdc++-v3/testsuite/30_threads/try_lock/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/try_lock/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/try_lock/4.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/try_lock/4.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable/54185.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/condition_variable/members/1.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable/members/1.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/condition_variable/members/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable/members/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_for.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait_until.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/valid.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/get2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/shared_future/members/wait.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/condition_variable_any/50862.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable_any/50862.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/condition_variable_any/members/1.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable_any/members/1.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/condition_variable_any/members/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/condition_variable_any/members/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/mutex/try_lock/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/mutex/try_lock/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/async/any.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/async/any.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/async/42819.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/async/42819.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/async/sync.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/async/sync.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/async/async.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/async/async.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/async/49668.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/async/49668.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/get_future.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/swap.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/swap.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value3.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move_assign.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/alloc.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/promise/cons/move.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/promise/cons/move.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/call_once/39909.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/call_once/39909.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/call_once/49668.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/call_once/49668.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/call_once/call_once1.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/call_once/call_once1.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/alloc.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/cons/3.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/49668.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/get_future.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke3.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke4.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke5.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/invoke.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/packaged_task/members/reset2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/3.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_for/3.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/lock/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/lock/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/lock/4.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/lock/4.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/this_thread/1.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/this_thread/1.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/members/1.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/members/1.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/members/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/members/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/members/3.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/members/3.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/swap/1.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/swap/1.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/moveable.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/moveable.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/49668.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/49668.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/3.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/3.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/4.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/4.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/5.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/5.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/6.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/6.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/7.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/7.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/8.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/8.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/9.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/9.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/future/members/valid.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/valid.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/future/members/get2.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/get2.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/future/members/share.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/share.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_for.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/future/members/get.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/get.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/future/members/45133.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/45133.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } +--- a/src/libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc ++++ b/src/libstdc++-v3/testsuite/30_threads/future/members/wait_until.cc +@@ -1,5 +1,5 @@ + // { dg-do run { target *-*-freebsd* *-*-netbsd* *-*-linux* *-*-solaris* *-*-cygwin *-*-darwin* powerpc-ibm-aix* } } +-// { dg-options " -std=gnu++0x -pthread" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } ++// { dg-options " -std=gnu++0x -pthread -Wl,--no-as-needed" { target *-*-freebsd* *-*-netbsd* *-*-linux* powerpc-ibm-aix* } } + // { dg-options " -std=gnu++0x -pthreads" { target *-*-solaris* } } + // { dg-options " -std=gnu++0x " { target *-*-cygwin *-*-darwin* } } + // { dg-require-cstdint "" } diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-base-version.diff gcc-4.8-4.8.2/debian/patches/gcc-base-version.diff --- gcc-4.8-4.8.1/debian/patches/gcc-base-version.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-base-version.diff 2013-10-17 15:57:25.000000000 +0000 @@ -5,14 +5,14 @@ --- a/src/gcc/BASE-VER +++ b/src/gcc/BASE-VER @@ -1 +1 @@ --4.8.1 +-4.8.2 +4.8 Index: b/src/gcc/FULL-VER =================================================================== --- /dev/null +++ b/src/gcc/FULL-VER @@ -0,0 +1 @@ -+4.8.1 ++4.8.2 Index: b/src/gcc/Makefile.in =================================================================== --- a/src/gcc/Makefile.in diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-default-format-security.diff gcc-4.8-4.8.2/debian/patches/gcc-default-format-security.diff --- gcc-4.8-4.8.1/debian/patches/gcc-default-format-security.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-default-format-security.diff 2013-10-17 15:57:25.000000000 +0000 @@ -1,24 +1,5 @@ # DP: Turn on -Wformat -Wformat-security by default for C, C++, ObjC, ObjC++. ---- - gcc/c-common.c | 2 +- - gcc/c.opt | 2 +- - gcc/doc/invoke.texi | 8 ++++++++ - 3 files changed, 10 insertions(+), 2 deletions(-) - -Index: b/src/gcc/c-family/c.opt -=================================================================== ---- a/src/gcc/c-family/c.opt -+++ b/src/gcc/c-family/c.opt -@@ -401,7 +401,7 @@ - Warn about format strings that are not literals - - Wformat-security --C ObjC C++ ObjC++ Var(warn_format_security) Warning LangEnabledBy(C ObjC C++ ObjC++,Wformat=, warn_format >= 2, 0) -+C ObjC C++ ObjC++ Var(warn_format_security) Init(1) Warning LangEnabledBy(C ObjC C++ ObjC++,Wformat=, warn_format >= 2, 0) - Warn about possible security problems with format functions - - Wformat-y2k Index: b/src/gcc/doc/invoke.texi =================================================================== --- a/src/gcc/doc/invoke.texi @@ -35,3 +16,22 @@ @item -Wformat-y2k @opindex Wformat-y2k @opindex Wno-format-y2k +--- a/src/gcc/gcc.c ++++ b/src/gcc/gcc.c +@@ -654,11 +654,14 @@ + #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G" + #endif + ++/* no separate spec, just shove it into the ssp default spec */ ++#define FORMAT_SECURITY_SPEC "%{!Wno-format-security:%{!Wformat|!Wformat=2|!Wall:-Wformat} -Wformat-security}" ++ + #ifndef SSP_DEFAULT_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP +-#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}}" ++#define SSP_DEFAULT_SPEC "%{!fno-stack-protector:%{!fstack-protector-all:%{!ffreestanding:%{!nostdlib:-fstack-protector}}}} " FORMAT_SECURITY_SPEC + #else +-#define SSP_DEFAULT_SPEC "" ++#define SSP_DEFAULT_SPEC FORMAT_SECURITY_SPEC + #endif + #endif + diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-linaro-doc.diff gcc-4.8-4.8.2/debian/patches/gcc-linaro-doc.diff --- gcc-4.8-4.8.1/debian/patches/gcc-linaro-doc.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-linaro-doc.diff 2013-10-17 15:57:25.000000000 +0000 @@ -1,4 +1,4 @@ -# DP: Changes for the Linaro 4.8-2013.07 release (documentation). +# DP: Changes for the Linaro 4.8-2013.10 release (documentation). --- a/src/gcc/doc/tm.texi +++ b/src/gcc/doc/tm.texi @@ -54,7 +54,16 @@ @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol -@@ -11263,8 +11265,8 @@ +@@ -10966,6 +10968,8 @@ + the following: + + @table @samp ++@item crc ++Enable CRC extension. + @item crypto + Enable Crypto extension. This implies Advanced SIMD is enabled. + @item fp +@@ -11263,8 +11267,8 @@ @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @@ -65,7 +74,7 @@ @samp{cortex-m1}, @samp{cortex-m0}, @samp{cortex-m0plus}, -@@ -11527,6 +11529,17 @@ +@@ -11527,6 +11531,17 @@ preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be defined. diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-linaro-update1.diff gcc-4.8-4.8.2/debian/patches/gcc-linaro-update1.diff --- gcc-4.8-4.8.1/debian/patches/gcc-linaro-update1.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-linaro-update1.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,413 +0,0 @@ -2013-08-01 Christophe Lyon - - Backport from trunk r198928,198973,199203,201240,201241,201307. - 2013-05-15 Ramana Radhakrishnan - - PR target/19599 - * config/arm/predicates.md (call_insn_operand): New predicate. - * config/arm/constraints.md ("Cs", "Ss"): New constraints. - * config/arm/arm.md (*call_insn, *call_value_insn): Match only - if insn is not a tail call. - (*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through - registers. - * config/arm/arm.h (enum reg_class): New caller save register class. - (REG_CLASS_NAMES): Likewise. - (REG_CLASS_CONTENTS): Likewise. - * config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling - without decls. - - 2013-05-16 Ramana Radhakrishnan - - PR target/19599 - * config/arm/arm.c (arm_function_ok_for_sibcall): Add check - for NULL decl. - - 2013-05-22 Ramana Radhakrishnan - - PR target/19599 - PR target/57340 - * config/arm/arm.c (any_sibcall_uses_r3): Rename to .. - (any_sibcall_could_use_r3): this and handle indirect calls. - (arm_get_frame_offsets): Rename use of any_sibcall_uses_r3. - - 2013-07-25 Ramana Radhakrishnan - - PR target/19599 - PR target/57731 - PR target/57748 - * config/arm/arm.md ("*sibcall_value_insn): Replace use of - Ss with US. Adjust output for v5 and v4t. - (*sibcall_value_insn): Likewise and loosen predicate on - operand0. - * config/arm/constraints.md ("Ss"): Rename to US. - - 2013-07-25 Ramana Radhakrishnan - - * config/arm/arm.md (*sibcall_insn): Remove unnecessary space. - - 2013-07-29 Ramana Radhakrishnan - Fix incorrect changelog entry. - - Replace - PR target/57748 - with - PR target/57837 - -2013-08-01 Christophe Lyon - - Backport from trunk r198928,198973,199203,201240,201241. - 2013-05-15 Ramana Radhakrishnan - - PR target/19599 - * gcc.target/arm/pr40887.c: Adjust testcase. - * gcc.target/arm/pr19599.c: New test. - ---- a/src/gcc/config/arm/arm.c -+++ b/src/gcc/config/arm/arm.c -@@ -5385,9 +5385,8 @@ - if (cfun->machine->sibcall_blocked) - return false; - -- /* Never tailcall something for which we have no decl, or if we -- are generating code for Thumb-1. */ -- if (decl == NULL || TARGET_THUMB1) -+ /* Never tailcall something if we are generating code for Thumb-1. */ -+ if (TARGET_THUMB1) - return false; - - /* The PIC register is live on entry to VxWorks PLT entries, so we -@@ -5397,13 +5396,14 @@ - - /* Cannot tail-call to long calls, since these are out of range of - a branch instruction. */ -- if (arm_is_long_call_p (decl)) -+ if (decl && arm_is_long_call_p (decl)) - return false; - - /* If we are interworking and the function is not declared static - then we can't tail-call it unless we know that it exists in this - compilation unit (since it might be a Thumb routine). */ -- if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) -+ if (TARGET_INTERWORK && decl && TREE_PUBLIC (decl) -+ && !TREE_ASM_WRITTEN (decl)) - return false; - - func_type = arm_current_func_type (); -@@ -5435,6 +5435,7 @@ - sibling calls. */ - if (TARGET_AAPCS_BASED - && arm_abi == ARM_ABI_AAPCS -+ && decl - && DECL_WEAK (decl)) - return false; - -@@ -17575,11 +17576,27 @@ - || df_regs_ever_live_p (LR_REGNUM)); - } - -+/* We do not know if r3 will be available because -+ we do have an indirect tailcall happening in this -+ particular case. */ -+static bool -+is_indirect_tailcall_p (rtx call) -+{ -+ rtx pat = PATTERN (call); -+ -+ /* Indirect tail call. */ -+ pat = XVECEXP (pat, 0, 0); -+ if (GET_CODE (pat) == SET) -+ pat = SET_SRC (pat); -+ -+ pat = XEXP (XEXP (pat, 0), 0); -+ return REG_P (pat); -+} - - /* Return true if r3 is used by any of the tail call insns in the - current function. */ - static bool --any_sibcall_uses_r3 (void) -+any_sibcall_could_use_r3 (void) - { - edge_iterator ei; - edge e; -@@ -17593,7 +17610,8 @@ - if (!CALL_P (call)) - call = prev_nonnote_nondebug_insn (call); - gcc_assert (CALL_P (call) && SIBLING_CALL_P (call)); -- if (find_regno_fusage (call, USE, 3)) -+ if (find_regno_fusage (call, USE, 3) -+ || is_indirect_tailcall_p (call)) - return true; - } - return false; -@@ -17760,7 +17778,7 @@ - /* If it is safe to use r3, then do so. This sometimes - generates better code on Thumb-2 by avoiding the need to - use 32-bit push/pop instructions. */ -- if (! any_sibcall_uses_r3 () -+ if (! any_sibcall_could_use_r3 () - && arm_size_return_regs () <= 12 - && (offsets->saved_regs_mask & (1 << 3)) == 0 - && (TARGET_THUMB2 || !current_tune->prefer_ldrd_strd)) ---- a/src/gcc/config/arm/arm.h -+++ b/src/gcc/config/arm/arm.h -@@ -1140,6 +1140,7 @@ - STACK_REG, - BASE_REGS, - HI_REGS, -+ CALLER_SAVE_REGS, - GENERAL_REGS, - CORE_REGS, - VFP_D0_D7_REGS, -@@ -1166,6 +1167,7 @@ - "STACK_REG", \ - "BASE_REGS", \ - "HI_REGS", \ -+ "CALLER_SAVE_REGS", \ - "GENERAL_REGS", \ - "CORE_REGS", \ - "VFP_D0_D7_REGS", \ -@@ -1191,6 +1193,7 @@ - { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ - { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ - { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ -+ { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ - { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ - { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ - { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ ---- a/src/gcc/config/arm/arm.md -+++ b/src/gcc/config/arm/arm.md -@@ -8947,7 +8947,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && arm_arch5" -+ "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" - "blx%?\\t%0" - [(set_attr "type" "call")] - ) -@@ -8957,7 +8957,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && !arm_arch5" -+ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" - "* - return output_call (operands); - " -@@ -8976,7 +8976,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && !arm_arch5" -+ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" - "* - return output_call_mem (operands); - " -@@ -8989,7 +8989,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_THUMB1 && arm_arch5" -+ "TARGET_THUMB1 && arm_arch5 && !SIBLING_CALL_P (insn)" - "blx\\t%0" - [(set_attr "length" "2") - (set_attr "type" "call")] -@@ -9000,7 +9000,7 @@ - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_THUMB1 && !arm_arch5" -+ "TARGET_THUMB1 && !arm_arch5 && !SIBLING_CALL_P (insn)" - "* - { - if (!TARGET_CALLER_INTERWORKING) -@@ -9059,7 +9059,7 @@ - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && arm_arch5" -+ "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" - "blx%?\\t%1" - [(set_attr "type" "call")] - ) -@@ -9070,7 +9070,7 @@ - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && !arm_arch5" -+ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" - "* - return output_call (&operands[1]); - " -@@ -9086,7 +9086,8 @@ - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))] -- "TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))" -+ "TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) -+ && !SIBLING_CALL_P (insn)" - "* - return output_call_mem (&operands[1]); - " -@@ -9136,6 +9137,7 @@ - (use (match_operand 2 "" "")) - (clobber (reg:SI LR_REGNUM))] - "TARGET_32BIT -+ && !SIBLING_CALL_P (insn) - && (GET_CODE (operands[0]) == SYMBOL_REF) - && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" - "* -@@ -9152,6 +9154,7 @@ - (use (match_operand 3 "" "")) - (clobber (reg:SI LR_REGNUM))] - "TARGET_32BIT -+ && !SIBLING_CALL_P (insn) - && (GET_CODE (operands[1]) == SYMBOL_REF) - && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" - "* -@@ -9197,6 +9200,10 @@ - "TARGET_32BIT" - " - { -+ if (!REG_P (XEXP (operands[0], 0)) -+ && (GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ - if (operands[2] == NULL_RTX) - operands[2] = const0_rtx; - }" -@@ -9211,32 +9218,52 @@ - "TARGET_32BIT" - " - { -+ if (!REG_P (XEXP (operands[1], 0)) && -+ (GET_CODE (XEXP (operands[1],0)) != SYMBOL_REF)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ - if (operands[3] == NULL_RTX) - operands[3] = const0_rtx; - }" - ) - - (define_insn "*sibcall_insn" -- [(call (mem:SI (match_operand:SI 0 "" "X")) -+ [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "Cs, US")) - (match_operand 1 "" "")) - (return) - (use (match_operand 2 "" ""))] -- "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF" -+ "TARGET_32BIT && SIBLING_CALL_P (insn)" - "* -- return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; -+ if (which_alternative == 1) -+ return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; -+ else -+ { -+ if (arm_arch5 || arm_arch4t) -+ return \"bx%?\\t%0\\t%@ indirect register sibling call\"; -+ else -+ return \"mov%?\\t%|pc, %0\\t%@ indirect register sibling call\"; -+ } - " - [(set_attr "type" "call")] - ) - - (define_insn "*sibcall_value_insn" - [(set (match_operand 0 "" "") -- (call (mem:SI (match_operand:SI 1 "" "X")) -+ (call (mem:SI (match_operand:SI 1 "call_insn_operand" "Cs,US")) - (match_operand 2 "" ""))) - (return) - (use (match_operand 3 "" ""))] -- "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF" -+ "TARGET_32BIT && SIBLING_CALL_P (insn)" - "* -- return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; -+ if (which_alternative == 1) -+ return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; -+ else -+ { -+ if (arm_arch5 || arm_arch4t) -+ return \"bx%?\\t%1\"; -+ else -+ return \"mov%?\\t%|pc, %1\\t@ indirect sibling call \"; -+ } - " - [(set_attr "type" "call")] - ) ---- a/src/gcc/config/arm/constraints.md -+++ b/src/gcc/config/arm/constraints.md -@@ -21,7 +21,7 @@ - ;; The following register constraints have been used: - ;; - in ARM/Thumb-2 state: t, w, x, y, z - ;; - in Thumb state: h, b --;; - in both states: l, c, k, q -+;; - in both states: l, c, k, q, US - ;; In ARM state, 'l' is an alias for 'r' - ;; 'f' and 'v' were previously used for FPA and MAVERICK registers. - -@@ -96,6 +96,9 @@ - (define_register_constraint "c" "CC_REG" - "@internal The condition code register.") - -+(define_register_constraint "Cs" "CALLER_SAVE_REGS" -+ "@internal The caller save registers. Useful for sibcalls.") -+ - (define_constraint "I" - "In ARM/Thumb-2 state a constant that can be used as an immediate value in a - Data Processing instruction. In Thumb-1 state a constant in the range -@@ -394,9 +397,16 @@ - 0) - && GET_CODE (XEXP (op, 0)) != POST_INC"))) - -+(define_constraint "US" -+ "@internal -+ US is a symbol reference." -+ (match_code "symbol_ref") -+) -+ - ;; We used to have constraint letters for S and R in ARM state, but - ;; all uses of these now appear to have been removed. - - ;; Additionally, we used to have a Q constraint in Thumb state, but - ;; this wasn't really a valid memory constraint. Again, all uses of - ;; this now seem to have been removed. -+ ---- a/src/gcc/config/arm/predicates.md -+++ b/src/gcc/config/arm/predicates.md -@@ -635,3 +635,7 @@ - (define_predicate "mem_noofs_operand" - (and (match_code "mem") - (match_code "reg" "0"))) -+ -+(define_predicate "call_insn_operand" -+ (ior (match_code "symbol_ref") -+ (match_operand 0 "s_register_operand"))) ---- a/src/gcc/testsuite/gcc.target/arm/pr19599.c -+++ b/src/gcc/testsuite/gcc.target/arm/pr19599.c -@@ -0,0 +1,10 @@ -+/* { dg-skip-if "need at least armv5te" { *-*-* } { "-march=armv[234]*" } { "" } } */ -+/* { dg-options "-O2 -march=armv5te -marm" } */ -+/* { dg-final { scan-assembler "bx" } } */ -+ -+int (*indirect_func)(); -+ -+int indirect_call() -+{ -+ return indirect_func(); -+} ---- a/src/gcc/testsuite/gcc.target/arm/pr40887.c -+++ b/src/gcc/testsuite/gcc.target/arm/pr40887.c -@@ -2,9 +2,9 @@ - /* { dg-options "-O2 -march=armv5te" } */ - /* { dg-final { scan-assembler "blx" } } */ - --int (*indirect_func)(); -+int (*indirect_func)(int x); - - int indirect_call() - { -- return indirect_func(); -+ return indirect_func(20) + indirect_func (40); - } diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-linaro-update2.diff gcc-4.8-4.8.2/debian/patches/gcc-linaro-update2.diff --- gcc-4.8-4.8.1/debian/patches/gcc-linaro-update2.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-linaro-update2.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,786 +0,0 @@ -2013-08-01 Christophe Lyon - - Backport from trunk r199438,199439,201326. - - 2013-05-30 Zhenqiang Chen - - * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added. - (arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes. - (arm_emit_vfp_multi_reg_pop): Likewise. - (thumb2_emit_ldrd_pop): Likewise. - (arm_expand_epilogue): Add misc REG_CFA notes. - (arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE. - - 2013-05-30 Bernd Schmidt - Zhenqiang Chen - - * config/arm/arm-protos.h: Add and update function protos. - * config/arm/arm.c (use_simple_return_p): New added. - (thumb2_expand_return): Check simple_return flag. - * config/arm/arm.md: Add simple_return and conditional simple_return. - * config/arm/iterators.md: Add iterator for return and simple_return. - - 2013-07-30 Zhenqiang Chen - - PR rtl-optimization/57637 - * function.c (move_insn_for_shrink_wrap): Also check the - GEN set of the LIVE problem for the liveness analysis - if it exists, otherwise give up. - -2013-08-01 Christophe Lyon - - Backport from trunk r199439,199533,201326. - - 2013-05-30 Zhenqiang Chen - - * gcc.dg/shrink-wrap-alloca.c: New added. - * gcc.dg/shrink-wrap-pretend.c: New added. - * gcc.dg/shrink-wrap-sibcall.c: New added. - - 2013-05-31 Rainer Orth - - * gcc.dg/shrink-wrap-alloca.c: Use __builtin_alloca. - - 2013-07-30 Zhenqiang Chen - - * gcc.target/arm/pr57637.c: New testcase. - ---- a/src/gcc/config/arm/arm-protos.h -+++ b/src/gcc/config/arm/arm-protos.h -@@ -24,12 +24,13 @@ - - extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); - extern int use_return_insn (int, rtx); -+extern bool use_simple_return_p (void); - extern enum reg_class arm_regno_class (int); - extern void arm_load_pic_register (unsigned long); - extern int arm_volatile_func (void); - extern void arm_expand_prologue (void); - extern void arm_expand_epilogue (bool); --extern void thumb2_expand_return (void); -+extern void thumb2_expand_return (bool); - extern const char *arm_strip_name_encoding (const char *); - extern void arm_asm_output_labelref (FILE *, const char *); - extern void thumb2_asm_output_opcode (FILE *); ---- a/src/gcc/config/arm/arm.c -+++ b/src/gcc/config/arm/arm.c -@@ -2177,6 +2177,14 @@ - global_options.x_param_values, - global_options_set.x_param_values); - -+ /* Disable shrink-wrap when optimizing function for size, since it tends to -+ generate additional returns. */ -+ if (optimize_function_for_size_p (cfun) && TARGET_THUMB2) -+ flag_shrink_wrap = false; -+ /* TBD: Dwarf info for apcs frame is not handled yet. */ -+ if (TARGET_APCS_FRAME) -+ flag_shrink_wrap = false; -+ - /* Register global variables with the garbage collector. */ - arm_add_gc_roots (); - } -@@ -2526,6 +2534,18 @@ - return 1; - } - -+/* Return TRUE if we should try to use a simple_return insn, i.e. perform -+ shrink-wrapping if possible. This is the case if we need to emit a -+ prologue, which we can test by looking at the offsets. */ -+bool -+use_simple_return_p (void) -+{ -+ arm_stack_offsets *offsets; -+ -+ offsets = arm_get_frame_offsets (); -+ return offsets->outgoing_args != 0; -+} -+ - /* Return TRUE if int I is a valid immediate ARM constant. */ - - int -@@ -17129,6 +17149,19 @@ - return par; - } - -+/* Add a REG_CFA_ADJUST_CFA REG note to INSN. -+ SIZE is the offset to be adjusted. -+ DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx. */ -+static void -+arm_add_cfa_adjust_cfa_note (rtx insn, int size, rtx dest, rtx src) -+{ -+ rtx dwarf; -+ -+ RTX_FRAME_RELATED_P (insn) = 1; -+ dwarf = gen_rtx_SET (VOIDmode, dest, plus_constant (Pmode, src, size)); -+ add_reg_note (insn, REG_CFA_ADJUST_CFA, dwarf); -+} -+ - /* Generate and emit an insn pattern that we will recognize as a pop_multi. - SAVED_REGS_MASK shows which registers need to be restored. - -@@ -17219,6 +17252,9 @@ - par = emit_insn (par); - - REG_NOTES (par) = dwarf; -+ if (!return_in_pc) -+ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs, -+ stack_pointer_rtx, stack_pointer_rtx); - } - - /* Generate and emit an insn pattern that we will recognize as a pop_multi -@@ -17289,6 +17325,9 @@ - - par = emit_insn (par); - REG_NOTES (par) = dwarf; -+ -+ arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs, -+ base_reg, base_reg); - } - - /* Generate and emit a pattern that will be recognized as LDRD pattern. If even -@@ -17364,6 +17403,7 @@ - pattern can be emitted now. */ - par = emit_insn (par); - REG_NOTES (par) = dwarf; -+ RTX_FRAME_RELATED_P (par) = 1; - } - - i++; -@@ -17380,7 +17420,12 @@ - stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, 4 * i)); - RTX_FRAME_RELATED_P (tmp) = 1; -- emit_insn (tmp); -+ tmp = emit_insn (tmp); -+ if (!return_in_pc) -+ { -+ arm_add_cfa_adjust_cfa_note (tmp, UNITS_PER_WORD * i, -+ stack_pointer_rtx, stack_pointer_rtx); -+ } - - dwarf = NULL_RTX; - -@@ -17414,9 +17459,11 @@ - else - { - par = emit_insn (tmp); -+ REG_NOTES (par) = dwarf; -+ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD, -+ stack_pointer_rtx, stack_pointer_rtx); - } - -- REG_NOTES (par) = dwarf; - } - else if ((num_regs % 2) == 1 && return_in_pc) - { -@@ -23963,7 +24010,7 @@ - all we really need to check here is if single register is to be - returned, or multiple register return. */ - void --thumb2_expand_return (void) -+thumb2_expand_return (bool simple_return) - { - int i, num_regs; - unsigned long saved_regs_mask; -@@ -23976,7 +24023,7 @@ - if (saved_regs_mask & (1 << i)) - num_regs++; - -- if (saved_regs_mask) -+ if (!simple_return && saved_regs_mask) - { - if (num_regs == 1) - { -@@ -24254,6 +24301,7 @@ - - if (frame_pointer_needed) - { -+ rtx insn; - /* Restore stack pointer if necessary. */ - if (TARGET_ARM) - { -@@ -24264,9 +24312,12 @@ - /* Force out any pending memory operations that reference stacked data - before stack de-allocation occurs. */ - emit_insn (gen_blockage ()); -- emit_insn (gen_addsi3 (stack_pointer_rtx, -- hard_frame_pointer_rtx, -- GEN_INT (amount))); -+ insn = emit_insn (gen_addsi3 (stack_pointer_rtx, -+ hard_frame_pointer_rtx, -+ GEN_INT (amount))); -+ arm_add_cfa_adjust_cfa_note (insn, amount, -+ stack_pointer_rtx, -+ hard_frame_pointer_rtx); - - /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not - deleted. */ -@@ -24276,16 +24327,25 @@ - { - /* In Thumb-2 mode, the frame pointer points to the last saved - register. */ -- amount = offsets->locals_base - offsets->saved_regs; -- if (amount) -- emit_insn (gen_addsi3 (hard_frame_pointer_rtx, -- hard_frame_pointer_rtx, -- GEN_INT (amount))); -+ amount = offsets->locals_base - offsets->saved_regs; -+ if (amount) -+ { -+ insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, -+ hard_frame_pointer_rtx, -+ GEN_INT (amount))); -+ arm_add_cfa_adjust_cfa_note (insn, amount, -+ hard_frame_pointer_rtx, -+ hard_frame_pointer_rtx); -+ } - - /* Force out any pending memory operations that reference stacked data - before stack de-allocation occurs. */ - emit_insn (gen_blockage ()); -- emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); -+ insn = emit_insn (gen_movsi (stack_pointer_rtx, -+ hard_frame_pointer_rtx)); -+ arm_add_cfa_adjust_cfa_note (insn, 0, -+ stack_pointer_rtx, -+ hard_frame_pointer_rtx); - /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not - deleted. */ - emit_insn (gen_force_register_use (stack_pointer_rtx)); -@@ -24298,12 +24358,15 @@ - amount = offsets->outgoing_args - offsets->saved_regs; - if (amount) - { -+ rtx tmp; - /* Force out any pending memory operations that reference stacked data - before stack de-allocation occurs. */ - emit_insn (gen_blockage ()); -- emit_insn (gen_addsi3 (stack_pointer_rtx, -- stack_pointer_rtx, -- GEN_INT (amount))); -+ tmp = emit_insn (gen_addsi3 (stack_pointer_rtx, -+ stack_pointer_rtx, -+ GEN_INT (amount))); -+ arm_add_cfa_adjust_cfa_note (tmp, amount, -+ stack_pointer_rtx, stack_pointer_rtx); - /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is - not deleted. */ - emit_insn (gen_force_register_use (stack_pointer_rtx)); -@@ -24356,6 +24419,8 @@ - REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (V2SImode, i), - NULL_RTX); -+ arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, -+ stack_pointer_rtx, stack_pointer_rtx); - } - - if (saved_regs_mask) -@@ -24403,6 +24468,9 @@ - REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, - gen_rtx_REG (SImode, i), - NULL_RTX); -+ arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, -+ stack_pointer_rtx, -+ stack_pointer_rtx); - } - } - } -@@ -24427,9 +24495,33 @@ - } - - if (crtl->args.pretend_args_size) -- emit_insn (gen_addsi3 (stack_pointer_rtx, -- stack_pointer_rtx, -- GEN_INT (crtl->args.pretend_args_size))); -+ { -+ int i, j; -+ rtx dwarf = NULL_RTX; -+ rtx tmp = emit_insn (gen_addsi3 (stack_pointer_rtx, -+ stack_pointer_rtx, -+ GEN_INT (crtl->args.pretend_args_size))); -+ -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ -+ if (cfun->machine->uses_anonymous_args) -+ { -+ /* Restore pretend args. Refer arm_expand_prologue on how to save -+ pretend_args in stack. */ -+ int num_regs = crtl->args.pretend_args_size / 4; -+ saved_regs_mask = (0xf0 >> num_regs) & 0xf; -+ for (j = 0, i = 0; j < num_regs; i++) -+ if (saved_regs_mask & (1 << i)) -+ { -+ rtx reg = gen_rtx_REG (SImode, i); -+ dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); -+ j++; -+ } -+ REG_NOTES (tmp) = dwarf; -+ } -+ arm_add_cfa_adjust_cfa_note (tmp, crtl->args.pretend_args_size, -+ stack_pointer_rtx, stack_pointer_rtx); -+ } - - if (!really_return) - return; -@@ -26097,9 +26189,17 @@ - handled_one = true; - break; - -+ /* The INSN is generated in epilogue. It is set as RTX_FRAME_RELATED_P -+ to get correct dwarf information for shrink-wrap. We should not -+ emit unwind information for it because these are used either for -+ pretend arguments or notes to adjust sp and restore registers from -+ stack. */ -+ case REG_CFA_ADJUST_CFA: -+ case REG_CFA_RESTORE: -+ return; -+ - case REG_CFA_DEF_CFA: - case REG_CFA_EXPRESSION: -- case REG_CFA_ADJUST_CFA: - case REG_CFA_OFFSET: - /* ??? Only handling here what we actually emit. */ - gcc_unreachable (); ---- a/src/gcc/config/arm/arm.md -+++ b/src/gcc/config/arm/arm.md -@@ -9241,17 +9241,17 @@ - [(set_attr "type" "call")] - ) - --(define_expand "return" -- [(return)] -+(define_expand "return" -+ [(returns)] - "(TARGET_ARM || (TARGET_THUMB2 - && ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL - && !IS_STACKALIGN (arm_current_func_type ()))) -- && USE_RETURN_INSN (FALSE)" -+ " - " - { - if (TARGET_THUMB2) - { -- thumb2_expand_return (); -+ thumb2_expand_return (); - DONE; - } - } -@@ -9276,13 +9276,13 @@ - (set_attr "predicable" "yes")] - ) - --(define_insn "*cond_return" -+(define_insn "*cond_return" - [(set (pc) - (if_then_else (match_operator 0 "arm_comparison_operator" - [(match_operand 1 "cc_register" "") (const_int 0)]) -- (return) -+ (returns) - (pc)))] -- "TARGET_ARM && USE_RETURN_INSN (TRUE)" -+ "TARGET_ARM " - "* - { - if (arm_ccfsm_state == 2) -@@ -9290,20 +9290,21 @@ - arm_ccfsm_state += 2; - return \"\"; - } -- return output_return_instruction (operands[0], true, false, false); -+ return output_return_instruction (operands[0], true, false, -+ ); - }" - [(set_attr "conds" "use") - (set_attr "length" "12") - (set_attr "type" "load1")] - ) - --(define_insn "*cond_return_inverted" -+(define_insn "*cond_return_inverted" - [(set (pc) - (if_then_else (match_operator 0 "arm_comparison_operator" - [(match_operand 1 "cc_register" "") (const_int 0)]) - (pc) -- (return)))] -- "TARGET_ARM && USE_RETURN_INSN (TRUE)" -+ (returns)))] -+ "TARGET_ARM " - "* - { - if (arm_ccfsm_state == 2) -@@ -9311,7 +9312,8 @@ - arm_ccfsm_state += 2; - return \"\"; - } -- return output_return_instruction (operands[0], true, true, false); -+ return output_return_instruction (operands[0], true, true, -+ ); - }" - [(set_attr "conds" "use") - (set_attr "length" "12") ---- a/src/gcc/config/arm/iterators.md -+++ b/src/gcc/config/arm/iterators.md -@@ -496,3 +496,11 @@ - (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") - (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") - (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) -+;; Both kinds of return insn. -+(define_code_iterator returns [return simple_return]) -+(define_code_attr return_str [(return "") (simple_return "simple_")]) -+(define_code_attr return_simple_p [(return "false") (simple_return "true")]) -+(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") -+ (simple_return " && use_simple_return_p ()")]) -+(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") -+ (simple_return " && use_simple_return_p ()")]) ---- a/src/gcc/function.c -+++ b/src/gcc/function.c -@@ -5509,22 +5509,45 @@ - except for any part that overlaps SRC (next loop). */ - bb_uses = &DF_LR_BB_INFO (bb)->use; - bb_defs = &DF_LR_BB_INFO (bb)->def; -- for (i = dregno; i < end_dregno; i++) -+ if (df_live) - { -- if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i)) -- next_block = NULL; -- CLEAR_REGNO_REG_SET (live_out, i); -- CLEAR_REGNO_REG_SET (live_in, i); -+ for (i = dregno; i < end_dregno; i++) -+ { -+ if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i) -+ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i)) -+ next_block = NULL; -+ CLEAR_REGNO_REG_SET (live_out, i); -+ CLEAR_REGNO_REG_SET (live_in, i); -+ } -+ -+ /* Check whether BB clobbers SRC. We need to add INSN to BB if so. -+ Either way, SRC is now live on entry. */ -+ for (i = sregno; i < end_sregno; i++) -+ { -+ if (REGNO_REG_SET_P (bb_defs, i) -+ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i)) -+ next_block = NULL; -+ SET_REGNO_REG_SET (live_out, i); -+ SET_REGNO_REG_SET (live_in, i); -+ } - } -+ else -+ { -+ /* DF_LR_BB_INFO (bb)->def does not comprise the DF_REF_PARTIAL and -+ DF_REF_CONDITIONAL defs. So if DF_LIVE doesn't exist, i.e. -+ at -O1, just give up searching NEXT_BLOCK. */ -+ next_block = NULL; -+ for (i = dregno; i < end_dregno; i++) -+ { -+ CLEAR_REGNO_REG_SET (live_out, i); -+ CLEAR_REGNO_REG_SET (live_in, i); -+ } - -- /* Check whether BB clobbers SRC. We need to add INSN to BB if so. -- Either way, SRC is now live on entry. */ -- for (i = sregno; i < end_sregno; i++) -- { -- if (REGNO_REG_SET_P (bb_defs, i)) -- next_block = NULL; -- SET_REGNO_REG_SET (live_out, i); -- SET_REGNO_REG_SET (live_in, i); -+ for (i = sregno; i < end_sregno; i++) -+ { -+ SET_REGNO_REG_SET (live_out, i); -+ SET_REGNO_REG_SET (live_in, i); -+ } - } - - /* If we don't need to add the move to BB, look for a single ---- a/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c -+++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c -@@ -0,0 +1,11 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -g" } */ -+ -+int *p; -+ -+void -+test (int a) -+{ -+ if (a > 0) -+ p = __builtin_alloca (4); -+} ---- a/src/gcc/testsuite/gcc.dg/shrink-wrap-pretend.c -+++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-pretend.c -@@ -0,0 +1,36 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -g" } */ -+ -+#include -+#include -+#include -+ -+#define DEBUG_BUFFER_SIZE 80 -+int unifi_debug = 5; -+ -+void -+unifi_trace (void* ospriv, int level, const char *fmt, ...) -+{ -+ static char s[DEBUG_BUFFER_SIZE]; -+ va_list args; -+ unsigned int len; -+ -+ if (!ospriv) -+ return; -+ -+ if (unifi_debug >= level) -+ { -+ va_start (args, fmt); -+ len = vsnprintf (&(s)[0], (DEBUG_BUFFER_SIZE), fmt, args); -+ va_end (args); -+ -+ if (len >= DEBUG_BUFFER_SIZE) -+ { -+ (s)[DEBUG_BUFFER_SIZE - 2] = '\n'; -+ (s)[DEBUG_BUFFER_SIZE - 1] = 0; -+ } -+ -+ printf ("%s", s); -+ } -+} -+ ---- a/src/gcc/testsuite/gcc.dg/shrink-wrap-sibcall.c -+++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-sibcall.c -@@ -0,0 +1,26 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -g" } */ -+ -+unsigned char a, b, d, f, g; -+ -+int test (void); -+ -+int -+baz (int c) -+{ -+ if (c == 0) return test (); -+ if (b & 1) -+ { -+ g = 0; -+ int e = (a & 0x0f) - (g & 0x0f); -+ -+ if (!a) b |= 0x80; -+ a = e + test (); -+ f = g/5 + a*3879 + b *2985; -+ } -+ else -+ { -+ f = g + a*39879 + b *25; -+ } -+ return test (); -+} ---- a/src/gcc/testsuite/gcc.target/arm/pr57637.c -+++ b/src/gcc/testsuite/gcc.target/arm/pr57637.c -@@ -0,0 +1,206 @@ -+/* { dg-do run } */ -+/* { dg-options "-O2 -fno-inline" } */ -+ -+typedef struct _GtkCssStyleProperty GtkCssStyleProperty; -+ -+struct _GtkCssStyleProperty -+{ -+ int *initial_value; -+ unsigned int id; -+ unsigned int inherit :1; -+ unsigned int animated :1; -+ unsigned int affects_size :1; -+ unsigned int affects_font :1; -+ -+ int * parse_value; -+ int * query_value; -+ int * assign_value; -+}; -+ -+void -+g_assertion_message_expr (const char *domain, -+ const char *file, -+ int line, -+ const char *func, -+ const char *expr) __attribute__((__noreturn__)); -+ -+void -+g_assertion_message_expr (const char *domain, -+ const char *file, -+ int line, -+ const char *func, -+ const char *expr) -+{ -+ __builtin_abort (); -+} -+int -+get_id (GtkCssStyleProperty *property) -+{ -+ return 1; -+} -+int -+_gtk_css_style_property_get_type () -+{ -+ return 1; -+} -+ -+GtkCssStyleProperty * -+g_object_new (int object_type, -+ const char *first_property_name, -+ ...) -+{ -+ return (GtkCssStyleProperty *) __builtin_malloc (sizeof (GtkCssStyleProperty)); -+} -+ -+typedef enum { -+ INHERIT = (1 << 0), -+ ANIMATED = (1 << 1), -+ RESIZE = (1 << 2), -+ FONT = (1 << 3) -+} GtkStylePropertyFlags; -+ -+int t = 0; -+void -+gtk_css_style_property_register (const char * name, -+ int expected_id, -+ int value_type, -+ int flags, -+ int *parse_value, -+ int *query_value, -+ int *assign_value, -+ int *initial_value) -+{ -+ GtkCssStyleProperty *node; -+ -+ do -+ { -+ if (__builtin_expect (__extension__ ( -+ { -+ int _g_boolean_var_; -+ if (initial_value != ((void *)0)) -+ _g_boolean_var_ = 1; -+ else -+ _g_boolean_var_ = 0; -+ _g_boolean_var_; -+ }), -+ 1)) -+ ; -+ else -+ g_assertion_message_expr ("Gtk", -+ "gtkcssstylepropertyimpl.c", -+ 85, -+ ((const char*) (__PRETTY_FUNCTION__)), -+ "initial_value != NULL"); -+ } while (0); -+ -+ do -+ { -+ if (__builtin_expect (__extension__ ( -+ { -+ int _g_boolean_var_; -+ if (parse_value != ((void *)0)) -+ _g_boolean_var_ = 1; -+ else -+ _g_boolean_var_ = 0; -+ _g_boolean_var_; -+ }), -+ 1)) -+ ; -+ else -+ g_assertion_message_expr ("Gtk", -+ "gtkcssstylepropertyimpl.c", -+ 86, -+ ((const char*) (__PRETTY_FUNCTION__)), -+ "parse_value != NULL"); -+ } while (0); -+ -+ do -+ { -+ if (__builtin_expect (__extension__ ( -+ { -+ int _g_boolean_var_; -+ if (value_type == ((int) ((1) << (2))) -+ || query_value != ((void *)0)) -+ _g_boolean_var_ = 1; -+ else -+ _g_boolean_var_ = 0; -+ _g_boolean_var_; -+ }), -+ 1)) -+ ; -+ else -+ g_assertion_message_expr ("Gtk", -+ "gtkcssstylepropertyimpl.c", -+ 87, ((const char*) (__PRETTY_FUNCTION__)), -+ "value_type == NONE || query_value != NULL"); -+ } while (0); -+ -+ /* FLAGS is changed in a cond_exec instruction with pr57637. */ -+ if (flags == 15) -+ t = 15; -+ -+ do -+ { -+ if (__builtin_expect (__extension__ ( -+ { -+ int _g_boolean_var_; -+ if (value_type == ((1) << (2)) -+ || assign_value != ((void *)0)) -+ _g_boolean_var_ = 1; -+ else -+ _g_boolean_var_ = 0; -+ _g_boolean_var_; -+ }), -+ 1)) -+ ; -+ else -+ g_assertion_message_expr ("Gtk", -+ "gtkcssstylepropertyimpl.c", -+ 88, ((const char*) (__PRETTY_FUNCTION__)), -+ "value_type == NONE || assign_value != NULL"); -+ } while (0); -+ -+ node = g_object_new ((_gtk_css_style_property_get_type ()), -+ "value-type", value_type, -+ "affects-size", (flags & RESIZE) ? (0) : (!(0)), -+ "affects-font", (flags & FONT) ? (!(0)) : (0), -+ "animated", (flags & ANIMATED) ? (!(0)) : (0), -+ "inherit", (flags & INHERIT) ? (!(0)) : (0), -+ "initial-value", initial_value, -+ "name", name, -+ ((void *)0)); -+ -+ node->parse_value = parse_value; -+ node->query_value = query_value; -+ node->assign_value = assign_value; -+ -+ do -+ { -+ if (__builtin_expect (__extension__ ( -+ { -+ int _g_boolean_var_; -+ if (get_id (node) == expected_id) -+ _g_boolean_var_ = 1; -+ else -+ _g_boolean_var_ = 0; -+ _g_boolean_var_; -+ }), -+ 1)) -+ ; -+ else -+ g_assertion_message_expr ("Gtk", -+ "gtkcssstylepropertyimpl.c", -+ 106, -+ ((const char*) (__PRETTY_FUNCTION__)), -+ "get_id (node) == expected_id"); -+ } while (0); -+} -+ -+int main () -+{ -+ gtk_css_style_property_register ("test", 1, 4, 15, &t, &t, &t, &t); -+ -+ if (t != 15) -+ __builtin_abort (); -+ return 0; -+} diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-linaro.diff gcc-4.8-4.8.2/debian/patches/gcc-linaro.diff --- gcc-4.8-4.8.1/debian/patches/gcc-linaro.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-linaro.diff 2013-10-17 15:57:25.000000000 +0000 @@ -1,12 +1,28 @@ -# DP: Changes for the Linaro 4.8-2013.07 release. +# DP: Changes for the Linaro 4.8-2013.10 release. -LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@200355 \ - svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@200692 \ +LANG=C svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@203510 \ + svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_8-branch@203615 \ | filterdiff --remove-timestamps --addoldprefix=a/src/ --addnewprefix=b/src/ --- a/src/libitm/ChangeLog.linaro +++ b/src/libitm/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -20,7 +36,31 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgomp/ChangeLog.linaro +++ b/src/libgomp/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,35 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-22 Yvan Roux ++ ++ Backport from trunk r200521. ++ 2013-06-28 Marcus Shawcroft ++ ++ * testsuite/libgomp.fortran/strassen.f90: ++ Add dg-skip-if aarch64_tiny. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -32,9 +72,33 @@ +2013-04-09 Matthew Gretton-Dann + + * GCC Linaro 4.8-2013.04 released. +--- a/src/libgomp/testsuite/libgomp.fortran/strassen.f90 ++++ b/src/libgomp/testsuite/libgomp.fortran/strassen.f90 +@@ -1,4 +1,5 @@ + ! { dg-options "-O2" } ++! { dg-skip-if "AArch64 tiny code model does not support programs larger than 1MiB" {aarch64_tiny} {"*"} {""} } + + program strassen_matmul + use omp_lib --- a/src/libquadmath/ChangeLog.linaro +++ b/src/libquadmath/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -61,7 +125,23 @@ current_++; --- a/src/libsanitizer/ChangeLog.linaro +++ b/src/libsanitizer/ChangeLog.linaro -@@ -0,0 +1,26 @@ +@@ -0,0 +1,42 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-20 Christophe Lyon + + Backport from trunk r198683. @@ -101,7 +181,23 @@ ;; --- a/src/zlib/ChangeLog.linaro +++ b/src/zlib/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -115,7 +211,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libstdc++-v3/ChangeLog.linaro +++ b/src/libstdc++-v3/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -129,7 +241,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/intl/ChangeLog.linaro +++ b/src/intl/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -143,7 +271,28 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/ChangeLog.linaro +++ b/src/ChangeLog.linaro -@@ -0,0 +1,16 @@ +@@ -0,0 +1,37 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-09 Christophe Lyon ++ ++ gcc/ ++ * LINARO-VERSION: Bump version. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-18 Rob Savoye + + gcc/ @@ -162,7 +311,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libmudflap/ChangeLog.linaro +++ b/src/libmudflap/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -176,7 +341,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/boehm-gc/ChangeLog.linaro +++ b/src/boehm-gc/ChangeLog.linaro -@@ -0,0 +1,24 @@ +@@ -0,0 +1,40 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -271,7 +452,23 @@ # define MACH_TYPE "ARM32" --- a/src/include/ChangeLog.linaro +++ b/src/include/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -285,7 +482,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libiberty/ChangeLog.linaro +++ b/src/libiberty/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -299,7 +512,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/lto-plugin/ChangeLog.linaro +++ b/src/lto-plugin/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -313,7 +542,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/regression/ChangeLog.linaro +++ b/src/contrib/regression/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -339,7 +584,23 @@ arm-linux-androideabi arm-uclinux_eabi arm-eabi \ --- a/src/contrib/ChangeLog.linaro +++ b/src/contrib/ChangeLog.linaro -@@ -0,0 +1,18 @@ +@@ -0,0 +1,34 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -360,7 +621,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/contrib/reghunt/ChangeLog.linaro +++ b/src/contrib/reghunt/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -374,7 +651,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libatomic/ChangeLog.linaro +++ b/src/libatomic/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -388,7 +681,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/config/ChangeLog.linaro +++ b/src/config/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -402,7 +711,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libbacktrace/ChangeLog.linaro +++ b/src/libbacktrace/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -416,7 +741,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/libltdl/ChangeLog.linaro +++ b/src/libjava/libltdl/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -430,7 +771,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/ChangeLog.linaro +++ b/src/libjava/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -444,7 +801,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libjava/classpath/ChangeLog.linaro +++ b/src/libjava/classpath/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -458,7 +831,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gnattools/ChangeLog.linaro +++ b/src/gnattools/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -472,7 +861,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/maintainer-scripts/ChangeLog.linaro +++ b/src/maintainer-scripts/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -486,7 +891,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgcc/ChangeLog.linaro +++ b/src/libgcc/ChangeLog.linaro -@@ -0,0 +1,21 @@ +@@ -0,0 +1,37 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -510,8 +931,8 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgcc/config/aarch64/sfp-machine.h +++ b/src/libgcc/config/aarch64/sfp-machine.h -@@ -19,8 +19,8 @@ - . */ +@@ -24,8 +24,8 @@ + . */ #define _FP_W_TYPE_SIZE 64 -#define _FP_W_TYPE unsigned long @@ -523,7 +944,23 @@ typedef int TItype __attribute__ ((mode (TI))); --- a/src/libgcc/config/libbid/ChangeLog.linaro +++ b/src/libgcc/config/libbid/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -537,7 +974,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libdecnumber/ChangeLog.linaro +++ b/src/libdecnumber/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -552,7 +1005,7 @@ --- a/src/gcc/LINARO-VERSION +++ b/src/gcc/LINARO-VERSION @@ -0,0 +1 @@ -+4.8-2013.06 ++release=4.8-2013.09-1~dev --- a/src/gcc/hooks.c +++ b/src/gcc/hooks.c @@ -147,6 +147,14 @@ @@ -582,7 +1035,23 @@ HOST_WIDE_INT, --- a/src/gcc/c-family/ChangeLog.linaro +++ b/src/gcc/c-family/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -596,7 +1065,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/java/ChangeLog.linaro +++ b/src/gcc/java/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -610,7 +1095,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/c/ChangeLog.linaro +++ b/src/gcc/c/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -684,6 +1185,18 @@ fi +@@ -25913,8 +25914,9 @@ + # ??? Once 2.11 is released, probably need to add first known working + # version to the per-target configury. + case "$cpu_type" in +- alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze | mips \ +- | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 | xtensa) ++ aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \ ++ | mips | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 \ ++ | xtensa) + insn="nop" + ;; + ia64 | s390) --- a/src/gcc/gensupport.c +++ b/src/gcc/gensupport.c @@ -1717,6 +1717,21 @@ @@ -710,7 +1223,7 @@ alternatives, max_operand); --- a/src/gcc/fold-const.c +++ b/src/gcc/fold-const.c -@@ -2457,9 +2457,13 @@ +@@ -2474,9 +2474,13 @@ } if (TREE_CODE (arg0) != TREE_CODE (arg1) @@ -729,7 +1242,23 @@ return 0; --- a/src/gcc/objc/ChangeLog.linaro +++ b/src/gcc/objc/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -743,382 +1272,1216 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/gcc/ChangeLog.linaro +++ b/src/gcc/ChangeLog.linaro -@@ -0,0 +1,1248 @@ -+2013-07-03 Christophe Lyon +@@ -0,0 +1,2631 @@ ++2013-10-09 Christophe Lyon + -+ Revert backport from trunk r198928,198973,199203. -+ 2013-05-22 Ramana Radhakrishnan ++ Backport from trunk r198526,198527,200020,200595. ++ 2013-05-02 Ian Bolton + -+ PR target/19599 -+ PR target/57340 -+ * config/arm/arm.c (any_sibcall_uses_r3): Rename to .. -+ (any_sibcall_could_use_r3): this and handle indirect calls. -+ (arm_get_frame_offsets): Rename use of any_sibcall_uses_r3. ++ * config/aarch64/aarch64.md (*and_one_cmpl3_compare0): ++ New pattern. ++ (*and_one_cmplsi3_compare0_uxtw): Likewise. ++ (*and_one_cmpl_3_compare0): Likewise. ++ (*and_one_cmpl_si3_compare0_uxtw): Likewise. + -+ 2013-05-16 Ramana Radhakrishnan ++ 2013-05-02 Ian Bolton + -+ PR target/19599 -+ * config/arm/arm.c (arm_function_ok_for_sibcall): Add check -+ for NULL decl. ++ * config/aarch64/aarch64.md (movsi_aarch64): Only allow to/from ++ S reg when fp attribute set. ++ (movdi_aarch64): Only allow to/from D reg when fp attribute set. + -+ 2013-05-15 Ramana Radhakrishnan ++ 2013-06-12 Sofiane Naci + -+ PR target/19599 -+ * config/arm/predicates.md (call_insn_operand): New predicate. -+ * config/arm/constraints.md ("Cs", "Ss"): New constraints. -+ * config/arm/arm.md (*call_insn, *call_value_insn): Match only -+ if insn is not a tail call. -+ (*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through -+ registers. -+ * config/arm/arm.h (enum reg_class): New caller save register class. -+ (REG_CLASS_NAMES): Likewise. -+ (REG_CLASS_CONTENTS): Likewise. -+ * config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling -+ without decls. ++ * config/aarch64/aarch64-simd.md (aarch64_combine): convert to split. ++ (aarch64_simd_combine): New instruction expansion. ++ * config/aarch64/aarch64-protos.h (aarch64_split_simd_combine): New ++ function prototype. ++ * config/aarch64/aarch64.c (aarch64_split_combine): New function. ++ * config/aarch64/iterators.md (Vdbl): Add entry for DF. + -+2013-07-03 Christophe Lyon ++ 2013-07-02 Ian Bolton + -+ Revert backport from mainline (r199438, r199439) -+ 2013-05-30 Zhenqiang Chen ++ * config/aarch64/aarch64.md (*extr_insv_reg): New pattern. + -+ * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added. -+ (arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes. -+ (arm_emit_vfp_multi_reg_pop): Likewise. -+ (thumb2_emit_ldrd_pop): Likewise. -+ (arm_expand_epilogue): Add misc REG_CFA notes. -+ (arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE. ++2013-10-09 Christophe Lyon + -+ 2013-05-30 Bernd Schmidt -+ Zhenqiang Chen ++ Backport from trunk r201879. ++ 2013-08-20 Matthew Gretton-Dann + -+ * config/arm/arm-protos.h: Add and update function protos. -+ * config/arm/arm.c (use_simple_return_p): New added. -+ (thumb2_expand_return): Check simple_return flag. -+ * config/arm/arm.md: Add simple_return and conditional simple_return. -+ * config/arm/iterators.md: Add iterator for return and simple_return. -+ * gcc.dg/shrink-wrap-alloca.c: New added. -+ * gcc.dg/shrink-wrap-pretend.c: New added. -+ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ * config/arm/linux-elf.h (MULTILIB_DEFAULTS): Remove definition. ++ * config/arm/t-linux-eabi (MULTILIB_OPTIONS): Document association ++ with MULTLIB_DEFAULTS. + -+2013-07-03 Christophe Lyon ++2013-10-09 Christophe Lyon + -+ Backport from trunk r199640, 199705, 199733, 199734, 199739. -+ 2013-06-04 Kyrylo Tkachov ++ Backport from trunk r201871. ++ 2013-08-20 Pavel Chupin + -+ * rtl.def: Add extra fourth optional field to define_cond_exec. -+ * gensupport.c (process_one_cond_exec): Process attributes from -+ define_cond_exec. -+ * doc/md.texi: Document fourth field in define_cond_exec. ++ Fix LIB_SPEC for systems without libpthread. + -+ 2013-06-05 Kyrylo Tkachov ++ * config/gnu-user.h: Introduce GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC. ++ * config/arm/linux-eabi.h: Use GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC ++ for Android. ++ * config/i386/linux-common.h: Likewise. ++ * config/mips/linux-common.h: Likewise. + -+ * config/arm/arm.md (enabled_for_depr_it): New attribute. -+ (predicable_short_it): Likewise. -+ (predicated): Likewise. -+ (enabled): Handle above. -+ (define_cond_exec): Set predicated attribute to yes. ++2013-10-08 Christophe Lyon + -+ 2013-06-06 Kyrylo Tkachov ++ Backport from trunk r202702. ++ 2013-09-18 Richard Earnshaw + -+ * config/arm/sync.md (atomic_loaddi_1): -+ Disable predication for arm_restrict_it. -+ (arm_load_exclusive): Likewise. -+ (arm_load_exclusivesi): Likewise. -+ (arm_load_exclusivedi): Likewise. -+ (arm_load_acquire_exclusive): Likewise. -+ (arm_load_acquire_exclusivesi): Likewise. -+ (arm_load_acquire_exclusivedi): Likewise. -+ (arm_store_exclusive): Likewise. -+ (arm_store_exclusive): Likewise. -+ (arm_store_release_exclusivedi): Likewise. -+ (arm_store_release_exclusive): Likewise. ++ * arm.c (arm_get_frame_offsets): Validate architecture supports ++ LDRD/STRD before accepting the tuning preference. ++ (arm_expand_prologue): Likewise. ++ (arm_expand_epilogue): Likewise. + -+ 2013-06-06 Kyrylo Tkachov ++2013-10-04 Venkataramanan.Kumar + -+ * config/arm/arm-ldmstm.ml: Set "predicable_short_it" to "no" -+ where appropriate. -+ * config/arm/ldmstm.md: Regenerate. ++ Backport from trunk r203028. ++ 2013-09-30 Venkataramanan Kumar + -+ 2013-06-06 Kyrylo Tkachov ++ * config/aarch64/aarch64.h (MCOUNT_NAME): Define. ++ (NO_PROFILE_COUNTERS): Likewise. ++ (PROFILE_HOOK): Likewise. ++ (FUNCTION_PROFILER): Likewise. ++ * config/aarch64/aarch64.c (aarch64_function_profiler): Remove. + -+ * config/arm/arm-fixed.md (add3,usadd3,ssadd3, -+ sub3, ussub3, sssub3, arm_ssatsihi_shift, -+ arm_usatsihi): Adjust alternatives for arm_restrict_it. ++2013-10-03 Christophe Lyon + -+2013-07-02 Rob Savoye ++ Backport from trunk r201923,201927. ++ 2013-08-22 Julian Brown + -+ Backport from trunk 200096 ++ * configure.ac: Add aarch64 to list of arches which use "nop" in ++ debug_line test. ++ * configure: Regenerate. + -+ 2013-06-14 Vidya Praveen ++ 2013-08-22 Paolo Carlini + -+ * config/aarch64/aarch64-simd.md (aarch64_mlal_lo): -+ New pattern. -+ (aarch64_mlal_hi, aarch64_mlsl_lo): Likewise. -+ (aarch64_mlsl_hi, aarch64_mlal): Likewise. -+ (aarch64_mlsl): Likewise. ++ * configure.ac: Add backslashes missing from the last change. ++ * configure: Regenerate. + -+2013-07-02 Rob Savoye ++2013-10-03 Christophe Lyon + -+ Backport from trunk 200062 ++ Backport from trunk r202023,202108. ++ 2013-08-27 Tejas Belagod + -+ 2013-06-13 Bin Cheng -+ * fold-const.c (operand_equal_p): Consider NOP_EXPR and -+ CONVERT_EXPR as equal nodes. ++ * config/aarch64/arm_neon.h: Replace all inline asm implementations ++ of vget_low_* with implementations in terms of other intrinsics. + -+2013-07-02 Rob Savoye -+ Backport from trunk 199810 ++ 2013-08-30 Tejas Belagod + -+ 2013-06-07 Kyrylo Tkachov ++ * config/aarch64/arm_neon.h (__AARCH64_UINT64_C, __AARCH64_INT64_C): New ++ arm_neon.h's internal macros to specify 64-bit constants. Avoid using ++ stdint.h's macros. + -+ * config/arm/arm.md (anddi3_insn): Remove duplicate alternatives. -+ Clean up alternatives. ++2013-10-03 Christophe Lyon + -+2013-06-20 Rob Savoye ++ Backport from trunk r201260,202400. ++ 2013-07-26 Kyrylo Tkachov ++ Richard Earnshaw + -+ Backport from trunk 200152 -+ 2013-06-17 Sofiane Naci ++ * combine.c (simplify_comparison): Re-canonicalize operands ++ where appropriate. ++ * config/arm/arm.md (movcond_addsi): New splitter. + -+ * config/aarch64/aarch64-simd.md (aarch64_dup_lane): Add r<-w -+ alternative and update. -+ (aarch64_dup_lanedi): Delete. -+ * config/aarch64/arm_neon.h (vdup_lane_*): Update. -+ * config/aarch64/aarch64-simd-builtins.def: Update. ++ 2013-09-09 Kyrylo Tkachov + -+2013-06-20 Rob Savoye ++ * config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for ++ comparison with negated operand. ++ * config/aarch64/aarch64.md (compare_neg): Match canonical ++ RTL form. + -+ Backport from trunk 200061 -+ 2013-06-13 Bin Cheng ++2013-10-03 Christophe Lyon + -+ * rtlanal.c (noop_move_p): Check the code to be executed for -+ COND_EXEC. ++ Backport from trunk r202164. ++ 2013-09-02 Bin Cheng + -+2013-06-20 Rob Savoye ++ * tree-ssa-loop-ivopts.c (set_autoinc_for_original_candidates): ++ Find auto-increment use both before and after candidate. + -+ Backport from trunk 199694 -+ 2013-06-05 Kyrylo Tkachov ++2013-10-03 Christophe Lyon + -+ * config/arm/arm.c (MAX_INSN_PER_IT_BLOCK): New macro. -+ (arm_option_override): Override arm_restrict_it where appropriate. -+ (thumb2_final_prescan_insn): Use MAX_INSN_PER_IT_BLOCK. -+ * config/arm/arm.opt (mrestrict-it): New command-line option. -+ * doc/invoke.texi: Document -mrestrict-it. ++ Backport from trunk r202279. ++ 2013-09-05 Richard Earnshaw + -+2013-06-20 Christophe Lyon ++ * arm.c (thumb2_emit_strd_push): Rewrite to use pre-decrement on ++ initial store. ++ * thumb2.md (thumb2_storewb_parisi): New pattern. + -+ Backport from trunk r198683. -+ 2013-05-07 Christophe Lyon ++2013-10-03 Christophe Lyon + -+ * config/arm/arm.c (arm_asan_shadow_offset): New function. -+ (TARGET_ASAN_SHADOW_OFFSET): Define. -+ * config/arm/linux-eabi.h (ASAN_CC1_SPEC): Define. -+ (LINUX_OR_ANDROID_CC): Add ASAN_CC1_SPEC. ++ Backport from trunk r202275. ++ 2013-09-05 Yufeng Zhang + -+2013-06-11 Rob Savoye ++ * config/aarch64/aarch64-option-extensions.def: Add ++ AARCH64_OPT_EXTENSION of 'crc'. ++ * config/aarch64/aarch64.h (AARCH64_FL_CRC): New define. ++ (AARCH64_ISA_CRC): Ditto. ++ * doc/invoke.texi (-march and -mcpu feature modifiers): Add ++ description of the CRC extension. + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++2013-10-01 Christophe Lyon + -+2013-06-06 Zhenqiang Chen ++ Backport from trunk r201250. ++ 2013-07-25 Kyrylo Tkachov + -+ Backport from mainline (r199438, r199439) -+ 2013-05-30 Zhenqiang Chen ++ * config/arm/arm.md (arm_addsi3, addsi3_carryin_, ++ addsi3_carryin_alt2_): Correct output template. + -+ * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added. -+ (arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes. -+ (arm_emit_vfp_multi_reg_pop): Likewise. -+ (thumb2_emit_ldrd_pop): Likewise. -+ (arm_expand_epilogue): Add misc REG_CFA notes. -+ (arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE. ++2013-10-01 Kugan Vivekanandarajah + -+ 2013-05-30 Bernd Schmidt -+ Zhenqiang Chen ++ Backport from trunk r203059,203116. ++ 2013-10-01 Kugan Vivekanandarajah + -+ * config/arm/arm-protos.h: Add and update function protos. -+ * config/arm/arm.c (use_simple_return_p): New added. -+ (thumb2_expand_return): Check simple_return flag. -+ * config/arm/arm.md: Add simple_return and conditional simple_return. -+ * config/arm/iterators.md: Add iterator for return and simple_return. -+ * gcc.dg/shrink-wrap-alloca.c: New added. -+ * gcc.dg/shrink-wrap-pretend.c: New added. -+ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ PR target/58578 ++ Revert ++ 2013-04-05 Greta Yorsh ++ * config/arm/arm.md (arm_ashldi3_1bit): define_insn into ++ define_insn_and_split. ++ (arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise. ++ (shiftsi3_compare): New pattern. ++ (rrx): New pattern. ++ * config/arm/unspecs.md (UNSPEC_RRX): New. + -+2013-06-06 Kugan Vivekanandarajah ++2013-09-11 Christophe Lyon + -+ Backport from mainline r198879: ++ * LINARO-VERSION: Bump version. + -+ 2013-05-14 Chung-Lin Tang -+ PR target/42017 -+ * config/arm/arm.h (EPILOGUE_USES): Only return true -+ for LR_REGNUM after epilogue_completed. ++2013-09-10 Christophe Lyon + -+2013-06-05 Christophe Lyon ++ GCC Linaro 4.8-2013.09 released. + -+ Backport from trunk r199652,199653,199656,199657,199658. ++2013-09-10 Venkataramanan Kumar + -+ 2013-06-04 Ian Bolton ++ Backport from trunk r200197, 201411. ++ 2013-06-19 Richard Earnshaw + -+ * config/aarch64/aarch64.md (*mov_aarch64): Call -+ into function to generate MOVI instruction. -+ * config/aarch64/aarch64.c (aarch64_simd_container_mode): -+ New function. -+ (aarch64_preferred_simd_mode): Turn into wrapper. -+ (aarch64_output_scalar_simd_mov_immediate): New function. -+ * config/aarch64/aarch64-protos.h: Add prototype for above. ++ arm.md (split for eq(reg, 0)): Add variants for ARMv5 and Thumb2. ++ (peepholes for eq(reg, not-0)): Ensure condition register is dead after ++ pattern. Use more efficient sequences on ARMv5 and Thumb2. + -+ 2013-06-04 Ian Bolton ++ 2013-08-01 Kyrylo Tkachov + -+ * config/aarch64/aarch64.c (simd_immediate_info): Remove -+ element_char member. -+ (sizetochar): Return signed char. -+ (aarch64_simd_valid_immediate): Remove elchar and other -+ unnecessary variables. -+ (aarch64_output_simd_mov_immediate): Take rtx instead of &rtx. -+ Calculate element_char as required. -+ * config/aarch64/aarch64-protos.h: Update and move prototype -+ for aarch64_output_simd_mov_immediate. -+ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): -+ Update arguments. ++ * config/arm/arm.md (peepholes for eq (reg1) (reg2/imm)): ++ Generate canonical plus rtx with negated immediate instead of minus ++ where appropriate. ++ * config/arm/arm.c (thumb2_reorg): Handle ADCS , case. + -+ 2013-06-04 Ian Bolton ++2013-09-10 Christophe Lyon + -+ * config/aarch64/aarch64.c (simd_immediate_info): Struct to hold -+ information completed by aarch64_simd_valid_immediate. -+ (aarch64_legitimate_constant_p): Update arguments. -+ (aarch64_simd_valid_immediate): Work with struct rather than many -+ pointers. -+ (aarch64_simd_scalar_immediate_valid_for_move): Update arguments. -+ (aarch64_simd_make_constant): Update arguments. -+ (aarch64_output_simd_mov_immediate): Work with struct rather than -+ many pointers. Output immediate directly rather than as operand. -+ * config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate): -+ Update prototype. -+ * config/aarch64/constraints.md (Dn): Update arguments. ++ Backport from trunk r200593,201024,201025,201122,201124,201126. ++ 2013-07-02 Kyrylo Tkachov + -+ 2013-06-04 Ian Bolton ++ * config/arm/arm.md (arm_andsi3_insn): Add alternatives for 16-bit ++ encoding. ++ (iorsi3_insn): Likewise. ++ (arm_xorsi3): Likewise. ++ ++ 2013-07-18 Sofiane Naci ++ ++ * config/arm/arm.md (attribute "type"): Rename "simple_alu_imm" to ++ "arlo_imm". Rename "alu_reg" to "arlo_reg". Rename "simple_alu_shift" to ++ "extend". Split "alu_shift" into "shift" and "arlo_shift". Split ++ "alu_shift_reg" into "shift_reg" and "arlo_shift_reg". List types ++ in alphabetical order. ++ (attribute "core_cycles"): Update for attribute changes. ++ (arm_addsi3): Likewise. ++ (addsi3_compare0): Likewise. ++ (addsi3_compare0_scratch): Likewise. ++ (addsi3_compare_op1): Likewise. ++ (addsi3_compare_op2): Likewise. ++ (compare_addsi2_op0): Likewise. ++ (compare_addsi2_op1): Likewise. ++ (addsi3_carryin_shift_): Likewise. ++ (subsi3_carryin_shift): Likewise. ++ (rsbsi3_carryin_shift): Likewise. ++ (arm_subsi3_insn): Likewise. ++ (subsi3_compare0): Likewise. ++ (subsi3_compare): Likewise. ++ (arm_andsi3_insn): Likewise. ++ (thumb1_andsi3_insn): Likewise. ++ (andsi3_compare0): Likewise. ++ (andsi3_compare0_scratch): Likewise. ++ (zeroextractsi_compare0_scratch ++ (andsi_not_shiftsi_si): Likewise. ++ (iorsi3_insn): Likewise. ++ (iorsi3_compare0): Likewise. ++ (iorsi3_compare0_scratch): Likewise. ++ (arm_xorsi3): Likewise. ++ (thumb1_xorsi3_insn): Likewise. ++ (xorsi3_compare0): Likewise. ++ (xorsi3_compare0_scratch): Likewise. ++ (satsi__shift): Likewise. ++ (rrx): Likewise. ++ (arm_shiftsi3): Likewise. ++ (shiftsi3_compare0): Likewise. ++ (not_shiftsi): Likewise. ++ (not_shiftsi_compare0): Likewise. ++ (not_shiftsi_compare0_scratch): Likewise. ++ (arm_one_cmplsi2): Likewise. ++ (thumb_one_complsi2): Likewise. ++ (notsi_compare0): Likewise. ++ (notsi_compare0_scratch): Likewise. ++ (thumb1_zero_extendhisi2): Likewise. ++ (arm_zero_extendhisi2): Likewise. ++ (arm_zero_extendhisi2_v6): Likewise. ++ (arm_zero_extendhisi2addsi): Likewise. ++ (thumb1_zero_extendqisi2): Likewise. ++ (thumb1_zero_extendqisi2_v6): Likewise. ++ (arm_zero_extendqisi2): Likewise. ++ (arm_zero_extendqisi2_v6): Likewise. ++ (arm_zero_extendqisi2addsi): Likewise. ++ (thumb1_extendhisi2): Likewise. ++ (arm_extendhisi2): Likewise. ++ (arm_extendhisi2_v6): Likewise. ++ (arm_extendqisi): Likewise. ++ (arm_extendqisi_v6): Likewise. ++ (arm_extendqisi2addsi): Likewise. ++ (thumb1_extendqisi2): Likewise. ++ (thumb1_movdi_insn): Likewise. ++ (arm_movsi_insn): Likewise. ++ (movsi_compare0): Likewise. ++ (movhi_insn_arch4): Likewise. ++ (movhi_bytes): Likewise. ++ (arm_movqi_insn): Likewise. ++ (thumb1_movqi_insn): Likewise. ++ (arm32_movhf): Likewise. ++ (thumb1_movhf): Likewise. ++ (arm_movsf_soft_insn): Likewise. ++ (thumb1_movsf_insn): Likewise. ++ (movdf_soft_insn): Likewise. ++ (thumb_movdf_insn): Likewise. ++ (arm_cmpsi_insn): Likewise. ++ (cmpsi_shiftsi): Likewise. ++ (cmpsi_shiftsi_swp): Likewise. ++ (arm_cmpsi_negshiftsi_si): Likewise. ++ (movsicc_insn): Likewise. ++ (movsfcc_soft_insn): Likewise. ++ (arith_shiftsi): Likewise. ++ (arith_shiftsi_compare0 ++ (arith_shiftsi_compare0_scratch ++ (sub_shiftsi): Likewise. ++ (sub_shiftsi_compare0 ++ (sub_shiftsi_compare0_scratch ++ (and_scc): Likewise. ++ (cond_move): Likewise. ++ (if_plus_move): Likewise. ++ (if_move_plus): Likewise. ++ (if_move_not): Likewise. ++ (if_not_move): Likewise. ++ (if_shift_move): Likewise. ++ (if_move_shift): Likewise. ++ (if_shift_shift): Likewise. ++ (if_not_arith): Likewise. ++ (if_arith_not): Likewise. ++ (cond_move_not): Likewise. ++ (thumb1_ashlsi3): Set type attribute. ++ (thumb1_ashrsi3): Likewise. ++ (thumb1_lshrsi3): Likewise. ++ (thumb1_rotrsi3): Likewise. ++ (shiftsi3_compare0_scratch): Likewise. ++ * config/arm/neon.md (neon_mov): Update for attribute changes. ++ (neon_mov): Likewise. ++ * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): Update for attribute ++ changes. ++ (thumb2_movsi_insn): Likewise. ++ (thumb2_cmpsi_neg_shiftsi): Likewise. ++ (thumb2_extendqisi_v6): Likewise. ++ (thumb2_zero_extendhisi2_v6): Likewise. ++ (thumb2_zero_extendqisi2_v6): Likewise. ++ (thumb2_shiftsi3_short): Likewise. ++ (thumb2_addsi3_compare0_scratch): Likewise. ++ (orsi_not_shiftsi_si): Likewise. ++ * config/arm/vfp.md (arm_movsi_vfp): Update for attribute changes. ++ * config/arm/arm-fixed.md (arm_ssatsihi_shift): Update for attribute ++ changes. ++ * config/arm/arm1020e.md (1020alu_op): Update for attribute changes. ++ (1020alu_shift_op): Likewise. ++ (1020alu_shift_reg_op): Likewise. ++ * config/arm/arm1026ejs.md (alu_op): Update for attribute changes. ++ (alu_shift_op): Likewise. ++ (alu_shift_reg_op): Likewise. ++ * config/arm/arm1136jfs.md (11_alu_op): Update for attribute changes. ++ (11_alu_shift_op): Likewise. ++ (11_alu_shift_reg_op): Likewise. ++ * config/arm/arm926ejs.md (9_alu_op): Update for attribute changes. ++ (9_alu_shift_reg_op): Likewise. ++ * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute changes. ++ (cortex_a15_alu_shift): Likewise. ++ (cortex_a15_alu_shift_reg): Likewise. ++ * config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute changes. ++ (cortex_a5_alu_shift): Likewise. ++ * config/arm/cortex-a53.md (cortex_a53_alu) : Update for attribute ++ changes. ++ (cortex_a53_alu_shift): Likewise. ++ * config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute ++ changes. ++ (cortex_a7_alu_reg): Likewise. ++ (cortex_a7_alu_shift): Likewise. ++ * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute changes. ++ (cortex_a8_alu_shift): Likewise. ++ (cortex_a8_alu_shift_reg): Likewise. ++ (cortex_a8_mov): Likewise. ++ * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute changes. ++ (cortex_a9_dp_shift): Likewise. ++ * config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute changes. ++ * config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute changes. ++ (cortex_r4_mov): Likewise. ++ (cortex_r4_alu_shift): Likewise. ++ (cortex_r4_alu_shift_reg): Likewise. ++ * config/arm/fa526.md (526_alu_op): Update for attribute changes. ++ (526_alu_shift_op): Likewise. ++ * config/arm/fa606te.md (606te_alu_op): Update for attribute changes. ++ * config/arm/fa626te.md (626te_alu_op): Update for attribute changes. ++ (626te_alu_shift_op): Likewise. ++ * config/arm/fa726te.md (726te_shift_op): Update for attribute changes. ++ (726te_alu_op): Likewise. ++ (726te_alu_shift_op): Likewise. ++ (726te_alu_shift_reg_op): Likewise. ++ * config/arm/fmp626.md (mp626_alu_op): Update for attribute changes. ++ (mp626_alu_shift_op): Likewise. ++ * config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute changes. ++ (pj4_alu_e1_conds): Likewise. ++ (pj4_alu): Likewise. ++ (pj4_alu_conds): Likewise. ++ (pj4_shift): Likewise. ++ (pj4_shift_conds): Likewise. ++ (pj4_alu_shift): Likewise. ++ (pj4_alu_shift_conds): Likewise. ++ * config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute changes. ++ (cortexa7_older_only): Likewise. ++ (cortexa7_younger): Likewise. ++ ++ 2013-07-18 Sofiane Naci ++ ++ * config/arm/arm.md (attribute "insn"): Delete values "mrs", "msr", ++ "xtab" and "sat". Move value "clz" from here to ... ++ (attriubte "type"): ... here. ++ (satsi_): Delete "insn" attribute. ++ (satsi__shift): Likewise. ++ (arm_zero_extendqisi2addsi): Likewise. ++ (arm_extendqisi2addsi): Likewise. ++ (clzsi2): Update for attribute changes. ++ (rbitsi2): Likewise. ++ * config/arm/arm-fixed.md (arm_ssatsihi_shift): Delete "insn" attribute. ++ (arm_usatsihi): Likewise. ++ * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. ++ ++ 2013-07-22 Kyrylo Tkachov ++ ++ * config/arm/predicates.md (shiftable_operator_strict_it): ++ New predicate. ++ * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si): ++ Disable cond_exec version for arm_restrict_it. ++ (thumb2_smaxsi3): Convert to generate cond_exec. ++ (thumb2_sminsi3): Likewise. ++ (thumb32_umaxsi3): Likewise. ++ (thumb2_uminsi3): Likewise. ++ (thumb2_abssi2): Adjust constraints for arm_restrict_it. ++ (thumb2_neg_abssi2): Likewise. ++ (thumb2_mov_scc): Add alternative for 16-bit encoding. ++ (thumb2_movsicc_insn): Adjust alternatives. ++ (thumb2_mov_negscc): Disable for arm_restrict_it. ++ (thumb2_mov_negscc_strict_it): New pattern. ++ (thumb2_mov_notscc_strict_it): New pattern. ++ (thumb2_mov_notscc): Disable for arm_restrict_it. ++ (thumb2_ior_scc): Likewise. ++ (thumb2_ior_scc_strict_it): New pattern. ++ (thumb2_cond_move): Adjust for arm_restrict_it. ++ (thumb2_cond_arith): Disable for arm_restrict_it. ++ (thumb2_cond_arith_strict_it): New pattern. ++ (thumb2_cond_sub): Adjust for arm_restrict_it. ++ (thumb2_movcond): Likewise. ++ (thumb2_extendqisi_v6): Disable cond_exec variant for arm_restrict_it. ++ (thumb2_zero_extendhisi2_v6): Likewise. ++ (thumb2_zero_extendqisi2_v6): Likewise. ++ (orsi_notsi_si): Likewise. ++ (orsi_not_shiftsi_si): Likewise. ++ ++ 2013-07-22 Sofiane Naci ++ ++ * config/arm/arm.md (attribute "insn"): Delete. ++ (attribute "type"): Add "mov_imm", "mov_reg", "mov_shift", ++ "mov_shift_reg", "mvn_imm", "mvn_reg", "mvn_shift" and "mvn_shift_reg". ++ (not_shiftsi): Update for attribute change. ++ (not_shiftsi_compare0): Likewise. ++ (not_shiftsi_compare0_scratch): Likewise. ++ (arm_one_cmplsi2): Likewise. ++ (thumb1_one_cmplsi2): Likewise. ++ (notsi_compare0): Likewise. ++ (notsi_compare0_scratch): Likewise. ++ (thumb1_movdi_insn): Likewise. ++ (arm_movsi_insn): Likewise. ++ (movhi_insn_arch4): Likewise. ++ (movhi_bytes): Likewise. ++ (arm_movqi_insn): Likewise. ++ (thumb1_movqi_insn): Likewise. ++ (arm32_movhf): Likewise. ++ (thumb1_movhf): Likewise. ++ (arm_movsf_soft_insn): Likewise. ++ (thumb1_movsf_insn): Likewise. ++ (thumb_movdf_insn): Likewise. ++ (movsicc_insn): Likewise. ++ (movsfcc_soft_insn): Likewise. ++ (and_scc): Likewise. ++ (cond_move): Likewise. ++ (if_move_not): Likewise. ++ (if_not_move): Likewise. ++ (if_shift_move): Likewise. ++ (if_move_shift): Likewise. ++ (if_shift_shift): Likewise. ++ (if_not_arith): Likewise. ++ (if_arith_not): Likewise. ++ (cond_move_not): Likewise. ++ * config/arm/neon.md (neon_mov): Update for attribute change. ++ (neon_mov): Likewise. ++ * config/arm/vfp.md (arm_movsi_vfp): Update for attribute change. ++ (thumb2_movsi_vfp): Likewise. ++ (movsf_vfp): Likewise. ++ (thumb2_movsf_vfp): Likewise. ++ * config/arm/arm.c (xscale_sched_adjust_cost): Update for attribute change. ++ (cortexa7_older_only): Likewise. ++ (cortexa7_younger): Likewise. ++ * config/arm/arm1020e.md (1020alu_op): Update for attribute change. ++ (1020alu_shift_op): Likewise. ++ (1020alu_shift_reg_op): Likewise. ++ * config/arm/arm1026ejs.md (alu_op): Update for attribute change. ++ (alu_shift_op): Likewise. ++ (alu_shift_reg_op): Likewise. ++ * config/arm/arm1136jfs.md (11_alu_op): Update for attribute change. ++ (11_alu_shift_op): Likewise. ++ (11_alu_shift_reg_op): Likewise. ++ * config/arm/arm926ejs.md (9_alu_op): Update for attribute change. ++ (9_alu_shift_reg_op): Likewise. ++ * config/arm/cortex-a15.md (cortex_a15_alu): Update for attribute change. ++ (cortex_a15_alu_shift): Likewise. ++ (cortex_a15_alu_shift_reg): Likewise. ++ * config/arm/cortex-a5.md (cortex_a5_alu): Update for attribute change. ++ (cortex_a5_alu_shift): Likewise. ++ * config/arm/cortex-a53.md (cortex_a53_alu): Update for attribute change. ++ (cortex_a53_alu_shift): Likewise. ++ * config/arm/cortex-a7.md (cortex_a7_alu_imm): Update for attribute change. ++ (cortex_a7_alu_reg): Likewise. ++ (cortex_a7_alu_shift): Likewise. ++ * config/arm/cortex-a8.md (cortex_a8_alu): Update for attribute change. ++ (cortex_a8_alu_shift): Likewise. ++ (cortex_a8_alu_shift_reg): Likewise. ++ (cortex_a8_mov): Likewise. ++ * config/arm/cortex-a9.md (cortex_a9_dp): Update for attribute change. ++ (cortex_a9_dp_shift): Likewise. ++ * config/arm/cortex-m4.md (cortex_m4_alu): Update for attribute change. ++ * config/arm/cortex-r4.md (cortex_r4_alu): Update for attribute change. ++ (cortex_r4_mov): Likewise. ++ (cortex_r4_alu_shift): Likewise. ++ (cortex_r4_alu_shift_reg): Likewise. ++ * config/arm/fa526.md (526_alu_op): Update for attribute change. ++ (526_alu_shift_op): Likewise. ++ * config/arm/fa606te.md (606te_alu_op): Update for attribute change. ++ * config/arm/fa626te.md (626te_alu_op): Update for attribute change. ++ (626te_alu_shift_op): Likewise. ++ * config/arm/fa726te.md (726te_shift_op): Update for attribute change. ++ (726te_alu_op): Likewise. ++ (726te_alu_shift_op): Likewise. ++ (726te_alu_shift_reg_op): Likewise. ++ * config/arm/fmp626.md (mp626_alu_op): Update for attribute change. ++ (mp626_alu_shift_op): Likewise. ++ * config/arm/marvell-pj4.md (pj4_alu_e1): Update for attribute change. ++ (pj4_alu_e1_conds): Likewise. ++ (pj4_alu): Likewise. ++ (pj4_alu_conds): Likewise. ++ (pj4_shift): Likewise. ++ (pj4_shift_conds): Likewise. ++ (pj4_alu_shift): Likewise. ++ (pj4_alu_shift_conds): Likewise. ++ ++ 2013-07-22 Kyrylo Tkachov ++ ++ * config/arm/constraints.md (Pd): Allow TARGET_THUMB ++ instead of TARGET_THUMB1. ++ (Pz): New constraint. ++ * config/arm/arm.md (arm_addsi3): Add alternatives for 16-bit ++ encodings. ++ (compare_negsi_si): Likewise. ++ (compare_addsi2_op0): Likewise. ++ (compare_addsi2_op1): Likewise. ++ (addsi3_carryin_): Likewise. ++ (addsi3_carryin_alt2_): Likewise. ++ (addsi3_carryin_shift_): Disable cond_exec variant ++ for arm_restrict_it. ++ (subsi3_carryin): Likewise. ++ (arm_subsi3_insn): Add alternatives for 16-bit encoding. ++ (minmax_arithsi): Disable for arm_restrict_it. ++ (minmax_arithsi_non_canon): Adjust for arm_restrict_it. ++ (satsi_): Disable cond_exec variant for arm_restrict_it. ++ (satsi__shift): Likewise. ++ (arm_shiftsi3): Add alternative for 16-bit encoding. ++ (arm32_movhf): Disable for arm_restrict_it. ++ (arm_cmpdi_unsigned): Add alternatives for 16-bit encoding. ++ (arm_movtas_ze): Disable cond_exec variant for arm_restrict_it. ++ ++2013-09-09 Kugan Vivekanandarajah ++ ++ Backport from trunk r201412. ++ 2013-08-01 Kyrylo Tkachov ++ ++ * config/arm/arm.md (minmax_arithsi_non_canon): Emit canonical RTL form ++ when subtracting a constant. ++ ++2013-09-05 Yvan Roux ++ ++ Backport from trunk r201249. ++ 2013-07-25 Kyrylo Tkachov ++ ++ * config/arm/arm-fixed.md (ssmulsa3, usmulusa3): ++ Adjust for arm_restrict_it. ++ Remove trailing whitespace. ++ ++2013-09-05 Yvan Roux ++ ++ Backport from trunk r201342. ++ 2013-07-30 Richard Earnshaw ++ ++ * config.gcc (arm): Require 64-bit host-wide-int for all ARM target ++ configs. ++ ++2013-09-05 Christophe Lyon ++ ++ Backport from trunk r199527,199792,199814. ++ 2013-05-31 Kyrylo Tkachov ++ ++ PR target/56315 ++ * config/arm/arm.c (const_ok_for_dimode_op): Handle IOR. ++ * config/arm/arm.md (*iordi3_insn): Change to insn_and_split. ++ * config/arm/neon.md (iordi3_neon): Remove. ++ (neon_vorr): Generate iordi3 instead of iordi3_neon. ++ * config/arm/predicates.md (imm_for_neon_logic_operand): ++ Move to earlier in the file. ++ (neon_logic_op2): Likewise. ++ (arm_iordi_operand_neon): New predicate. + -+ * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): No -+ longer static. -+ (aarch64_simd_immediate_valid_for_move): Remove. -+ (aarch64_simd_scalar_immediate_valid_for_move): Update call. -+ (aarch64_simd_make_constant): Update call. -+ (aarch64_output_simd_mov_immediate): Update call. -+ * config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate): -+ Add prototype. -+ * config/aarch64/constraints.md (Dn): Update call. ++ 2013-06-07 Kyrylo Tkachov + -+ 2013-06-04 Ian Bolton ++ * config/arm/constraints.md (Df): New constraint. ++ * config/arm/arm.md (iordi3_insn): Use Df constraint instead of De. ++ Correct length attribute for last two alternatives. + -+ * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Change -+ return type to bool for prototype. -+ (aarch64_legitimate_constant_p): Check for true instead of not -1. -+ (aarch64_simd_valid_immediate): Fix up each return to return a bool. -+ (aarch64_simd_immediate_valid_for_move): Update retval for bool. ++ 2013-06-07 Kyrylo Tkachov + -+2013-06-04 Christophe Lyon ++ PR target/56315 ++ * config/arm/arm.md (*xordi3_insn): Change to insn_and_split. ++ (xordi3): Change operand 2 constraint to arm_xordi_operand. ++ * config/arm/arm.c (const_ok_for_dimode_op): Handle XOR. ++ * config/arm/constraints.md (Dg): New constraint. ++ * config/arm/neon.md (xordi3_neon): Remove. ++ (neon_veor): Generate xordi3 instead of xordi3_neon. ++ * config/arm/predicates.md (arm_xordi_operand): New predicate. + -+ Backport from trunk r199261. -+ 2013-05-23 Christian Bruel ++2013-09-05 Christophe Lyon + -+ PR debug/57351 -+ * config/arm/arm.c (arm_dwarf_register_span): Do not use dbx number. ++ Backport from trunk r201599. ++ 2013-08-08 Richard Earnshaw + -+2013-06-03 Christophe Lyon ++ PR target/57431 ++ * arm/neon.md (neon_vld1_dupdi): New expand pattern. ++ (neon_vld1_dup VD iterator): Iterate over VD not VDX. ++ ++2013-09-05 Christophe Lyon ++ ++ Backport from trunk r201589. ++ 2013-08-08 Bernd Edlinger ++ ++ PR target/58065 ++ * config/arm/arm.h (MALLOC_ABI_ALIGNMENT): Define. ++ ++2013-09-03 Venkataramanan Kumar + + Backport from trunk -+ r198890,199254,199259,199260,199293,199407,199408,199454,199544,199545. ++ r201624, r201666. ++ 2013-08-09 James Greenhalgh + -+ 2013-05-31 Marcus Shawcroft ++ * config/aarch64/aarch64-simd-builtins.def (get_lane_signed): Remove. ++ (get_lane_unsigned): Likewise. ++ (dup_lane_scalar): Likewise. ++ (get_lane): enable for VALL. ++ * config/aarch64/aarch64-simd.md ++ (aarch64_dup_lane_scalar): Remove. ++ (aarch64_get_lane_signed): Likewise. ++ (aarch64_get_lane_unsigned): Likewise. ++ (aarch64_get_lane_extend): New. ++ (aarch64_get_lane_zero_extendsi): Likewise. ++ (aarch64_get_lane): Enable for all vector modes. ++ (aarch64_get_lanedi): Remove misleading constraints. ++ * config/aarch64/arm_neon.h ++ (__aarch64_vget_lane_any): Define. ++ (__aarch64_vget_lane_<8,16,32,64>): Likewise. ++ (vget_lane_<8,16,32,64>): Use __aarch64_vget_lane macros. ++ (vdup_lane_<8,16,32,64>): Likewise. ++ * config/aarch64/iterators.md (VDQQH): New. ++ (VDQQHS): Likewise. ++ (vwcore): Likewise. + -+ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): -+ Remove un-necessary braces. ++ 2013-08-12 James Greenhalgh + -+ 2013-05-31 Marcus Shawcroft ++ * config/aarch64/arm_none.h ++ (vdup_lane_<8,16,32,64>): Fix macro call. + -+ * config/aarch64/aarch64.c (aarch64_classify_symbol): -+ Use SYMBOL_TINY_ABSOLUTE for AARCH64_CMODEL_TINY_PIC. ++2013-08-26 Kugan Vivekanandarajah + -+ 2013-05-30 Ian Bolton ++ Backport from trunk r201341. ++ 2013-07-30 Richard Earnshaw + -+ * config/aarch64/aarch64.md (insv): New define_expand. -+ (*insv_reg): New define_insn. ++ * arm.md (mulhi3): New expand pattern. + -+ 2012-05-29 Chris Schlumberger-Socha -+ Marcus Shawcroft ++2013-08-16 Christophe Lyon + -+ * config/aarch64/aarch64-protos.h (aarch64_symbol_type): Define -+ SYMBOL_TINY_ABSOLUTE. -+ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Handle -+ SYMBOL_TINY_ABSOLUTE. -+ (aarch64_expand_mov_immediate): Likewise. -+ (aarch64_classify_symbol): Likewise. -+ (aarch64_mov_operand_p): Remove ATTRIBUTE_UNUSED. -+ Permit SYMBOL_TINY_ABSOLUTE. -+ * config/aarch64/predicates.md (aarch64_mov_operand): Permit CONST. ++ * LINARO-VERSION: Bump version. + -+ 2013-05-29 Chris Schlumberger-Socha -+ Marcus Shawcroft ++2013-08-14 Christophe Lyon + -+ * config/aarch64/aarch64.c (aarch64_classify_symbol): Remove comment. -+ Refactor if/switch. Replace gcc_assert with if. ++ GCC Linaro 4.8-2013.08 released. + -+ 2013-05-24 Ian Bolton ++2013-08-08 Christophe Lyon + -+ * config/aarch64/aarch64.c (aarch64_print_operand): Change the -+ X format specifier to only display bottom 16 bits. -+ * config/aarch64/aarch64.md (insv_imm): Allow any size of -+ immediate to match for operand 2, since it will be masked. ++ Backport from trunk ++ r198489,200167,200199,200510,200513,200515,200576. ++ 2013-05-01 Greta Yorsh + -+ 2013-05-23 Chris Schlumberger-Socha -+ Marcus Shawcroft ++ * config/arm/thumb2.md (thumb2_smaxsi3,thumb2_sminsi3): Convert ++ define_insn to define_insn_and_split. ++ (thumb32_umaxsi3,thumb2_uminsi3): Likewise. ++ (thumb2_negdi2,thumb2_abssi2,thumb2_neg_abssi2): Likewise. ++ (thumb2_mov_scc,thumb2_mov_negscc,thumb2_mov_notscc): Likewise. ++ (thumb2_movsicc_insn,thumb2_and_scc,thumb2_ior_scc): Likewise. ++ (thumb2_negscc): Likewise. ++ ++ 2013-06-18 Sofiane Naci ++ ++ * config/arm/arm.md (attribute "insn"): Move multiplication and division ++ attributes to... ++ (attribute "type"): ... here. Remove mult. ++ (attribute "mul32"): New attribute. ++ (attribute "mul64"): Add umaal. ++ (*arm_mulsi3): Update attributes. ++ (*arm_mulsi3_v6): Likewise. ++ (*thumb_mulsi3): Likewise. ++ (*thumb_mulsi3_v6): Likewise. ++ (*mulsi3_compare0): Likewise. ++ (*mulsi3_compare0_v6): Likewise. ++ (*mulsi_compare0_scratch): Likewise. ++ (*mulsi_compare0_scratch_v6): Likewise. ++ (*mulsi3addsi): Likewise. ++ (*mulsi3addsi_v6): Likewise. ++ (*mulsi3addsi_compare0): Likewise. ++ (*mulsi3addsi_compare0_v6): Likewise. ++ (*mulsi3addsi_compare0_scratch): Likewise. ++ (*mulsi3addsi_compare0_scratch_v6): Likewise. ++ (*mulsi3subsi): Likewise. ++ (*mulsidi3adddi): Likewise. ++ (*mulsi3addsi_v6): Likewise. ++ (*mulsidi3adddi_v6): Likewise. ++ (*mulsidi3_nov6): Likewise. ++ (*mulsidi3_v6): Likewise. ++ (*umulsidi3_nov6): Likewise. ++ (*umulsidi3_v6): Likewise. ++ (*umulsidi3adddi): Likewise. ++ (*umulsidi3adddi_v6): Likewise. ++ (*smulsi3_highpart_nov6): Likewise. ++ (*smulsi3_highpart_v6): Likewise. ++ (*umulsi3_highpart_nov6): Likewise. ++ (*umulsi3_highpart_v6): Likewise. ++ (mulhisi3): Likewise. ++ (*mulhisi3tb): Likewise. ++ (*mulhisi3bt): Likewise. ++ (*mulhisi3tt): Likewise. ++ (maddhisi4): Likewise. ++ (*maddhisi4tb): Likewise. ++ (*maddhisi4tt): Likewise. ++ (maddhidi4): Likewise. ++ (*maddhidi4tb): Likewise. ++ (*maddhidi4tt): Likewise. ++ (divsi3): Likewise. ++ (udivsi3): Likewise. ++ * config/arm/thumb2.md (thumb2_mulsi_short): Update attributes. ++ (thumb2_mulsi_short_compare0): Likewise. ++ (thumb2_mulsi_short_compare0_scratch): Likewise. ++ * config/arm/arm1020e.md (1020mult1): Update attribute change. ++ (1020mult2): Likewise. ++ (1020mult3): Likewise. ++ (1020mult4): Likewise. ++ (1020mult5): Likewise. ++ (1020mult6): Likewise. ++ * config/arm/cortex-a15.md (cortex_a15_mult32): Update attribute change. ++ (cortex_a15_mult64): Likewise. ++ (cortex_a15_sdiv): Likewise. ++ (cortex_a15_udiv): Likewise. ++ * config/arm/arm1026ejs.md (mult1): Update attribute change. ++ (mult2): Likewise. ++ (mult3): Likewise. ++ (mult4): Likewise. ++ (mult5): Likewise. ++ (mult6): Likewise. ++ * config/arm/marvell-pj4.md (pj4_ir_mul): Update attribute change. ++ (pj4_ir_div): Likewise. ++ * config/arm/arm1136jfs.md (11_mult1): Update attribute change. ++ (11_mult2): Likewise. ++ (11_mult3): Likewise. ++ (11_mult4): Likewise. ++ (11_mult5): Likewise. ++ (11_mult6): Likewise. ++ (11_mult7): Likewise. ++ * config/arm/cortex-a8.md (cortex_a8_mul): Update attribute change. ++ (cortex_a8_mla): Likewise. ++ (cortex_a8_mull): Likewise. ++ (cortex_a8_smulwy): Likewise. ++ (cortex_a8_smlald): Likewise. ++ * config/arm/cortex-m4.md (cortex_m4_alu): Update attribute change. ++ * config/arm/cortex-r4.md (cortex_r4_mul_4): Update attribute change. ++ (cortex_r4_mul_3): Likewise. ++ (cortex_r4_mla_4): Likewise. ++ (cortex_r4_mla_3): Likewise. ++ (cortex_r4_smlald): Likewise. ++ (cortex_r4_mull): Likewise. ++ (cortex_r4_sdiv): Likewise. ++ (cortex_r4_udiv): Likewise. ++ * config/arm/cortex-a7.md (cortex_a7_mul): Update attribute change. ++ (cortex_a7_idiv): Likewise. ++ * config/arm/arm926ejs.md (9_mult1): Update attribute change. ++ (9_mult2): Likewise. ++ (9_mult3): Likewise. ++ (9_mult4): Likewise. ++ (9_mult5): Likewise. ++ (9_mult6): Likewise. ++ * config/arm/cortex-a53.md (cortex_a53_mul): Update attribute change. ++ (cortex_a53_sdiv): Likewise. ++ (cortex_a53_udiv): Likewise. ++ * config/arm/fa726te.md (726te_mult_op): Update attribute change. ++ * config/arm/fmp626.md (mp626_mult1): Update attribute change. ++ (mp626_mult2): Likewise. ++ (mp626_mult3): Likewise. ++ (mp626_mult4): Likewise. ++ * config/arm/fa526.md (526_mult1): Update attribute change. ++ (526_mult2): Likewise. ++ * config/arm/arm-generic.md (mult): Update attribute change. ++ (mult_ldsched_strongarm): Likewise. ++ (mult_ldsched): Likewise. ++ (multi_cycle): Likewise. ++ * config/arm/cortex-a5.md (cortex_a5_mul): Update attribute change. ++ * config/arm/fa606te.md (606te_mult1): Update attribute change. ++ (606te_mult2): Likewise. ++ (606te_mult3): Likewise. ++ (606te_mult4): Likewise. ++ * config/arm/cortex-a9.md (cortex_a9_mult16): Update attribute change. ++ (cortex_a9_mac16): Likewise. ++ (cortex_a9_multiply): Likewise. ++ (cortex_a9_mac): Likewise. ++ (cortex_a9_multiply_long): Likewise. ++ * config/arm/fa626te.md (626te_mult1): Update attribute change. ++ (626te_mult2): Likewise. ++ (626te_mult3): Likewise. ++ (626te_mult4): Likewise. ++ ++ 2013-06-19 Sofiane Naci ++ ++ * config/arm/vfp.md: Move VFP instruction classification documentation ++ to ... ++ * config/arm/arm.md: ... here. Update instruction classification ++ documentation. ++ ++ 2013-06-28 Kyrylo Tkachov ++ ++ * config/arm/predicates.md (arm_cond_move_operator): New predicate. ++ * config/arm/arm.md (movsfcc): Use arm_cond_move_operator predicate. ++ (movdfcc): Likewise. ++ * config/arm/vfp.md (*thumb2_movsf_vfp): ++ Disable predication for arm_restrict_it. ++ (*thumb2_movsfcc_vfp): Disable for arm_restrict_it. ++ (*thumb2_movdfcc_vfp): Likewise. ++ (*abssf2_vfp, *absdf2_vfp, *negsf2_vfp, *negdf2_vfp,*addsf3_vfp, ++ *adddf3_vfp, *subsf3_vfp, *subdf3_vfpc, *divsf3_vfp,*divdf3_vfp, ++ *mulsf3_vfp, *muldf3_vfp, *mulsf3negsf_vfp, *muldf3negdf_vfp, ++ *mulsf3addsf_vfp, *muldf3adddf_vfp, *mulsf3subsf_vfp, ++ *muldf3subdf_vfp, *mulsf3negsfaddsf_vfp, *fmuldf3negdfadddf_vfp, ++ *mulsf3negsfsubsf_vfp, *muldf3negdfsubdf_vfp, *fma4, ++ *fmsub4, *fnmsub4, *fnmadd4, ++ *extendsfdf2_vfp, *truncdfsf2_vfp, *extendhfsf2, *truncsfhf2, ++ *truncsisf2_vfp, *truncsidf2_vfp, fixuns_truncsfsi2, fixuns_truncdfsi2, ++ *floatsisf2_vfp, *floatsidf2_vfp, floatunssisf2, floatunssidf2, ++ *sqrtsf2_vfp, *sqrtdf2_vfp, *cmpsf_vfp, *cmpsf_trap_vfp, *cmpdf_vfp, ++ *cmpdf_trap_vfp, 2): ++ Disable predication for arm_restrict_it. + -+ * config/aarch64/aarch64.md (*movdi_aarch64): Replace Usa with S. -+ * config/aarch64/constraints.md (Usa): Remove. -+ * doc/md.texi (AArch64 Usa): Remove. ++ 2013-06-28 Kyrylo Tkachov + -+ 2013-05-23 Chris Schlumberger-Socha -+ Marcus Shawcroft ++ * config/arm/arm.md (arm_mulsi3_v6): Add alternative for 16-bit ++ encoding. ++ (mulsi3addsi_v6): Disable predicable variant for arm_restrict_it. ++ (mulsi3subsi): Likewise. ++ (mulsidi3adddi): Likewise. ++ (mulsidi3_v6): Likewise. ++ (umulsidi3_v6): Likewise. ++ (umulsidi3adddi_v6): Likewise. ++ (smulsi3_highpart_v6): Likewise. ++ (umulsi3_highpart_v6): Likewise. ++ (mulhisi3tb): Likewise. ++ (mulhisi3bt): Likewise. ++ (mulhisi3tt): Likewise. ++ (maddhisi4): Likewise. ++ (maddhisi4tb): Likewise. ++ (maddhisi4tt): Likewise. ++ (maddhidi4): Likewise. ++ (maddhidi4tb): Likewise. ++ (maddhidi4tt): Likewise. ++ (zeroextractsi_compare0_scratch): Likewise. ++ (insv_zero): Likewise. ++ (insv_t2): Likewise. ++ (anddi_notzesidi_di): Likewise. ++ (anddi_notsesidi_di): Likewise. ++ (andsi_notsi_si): Likewise. ++ (iordi_zesidi_di): Likewise. ++ (xordi_zesidi_di): Likewise. ++ (andsi_iorsi3_notsi): Likewise. ++ (smax_0): Likewise. ++ (smax_m1): Likewise. ++ (smin_0): Likewise. ++ (not_shiftsi): Likewise. ++ (unaligned_loadsi): Likewise. ++ (unaligned_loadhis): Likewise. ++ (unaligned_loadhiu): Likewise. ++ (unaligned_storesi): Likewise. ++ (unaligned_storehi): Likewise. ++ (extv_reg): Likewise. ++ (extzv_t2): Likewise. ++ (divsi3): Likewise. ++ (udivsi3): Likewise. ++ (arm_zero_extendhisi2addsi): Likewise. ++ (arm_zero_extendqisi2addsi): Likewise. ++ (compareqi_eq0): Likewise. ++ (arm_extendhisi2_v6): Likewise. ++ (arm_extendqisi2addsi): Likewise. ++ (arm_movt): Likewise. ++ (thumb2_ldrd): Likewise. ++ (thumb2_ldrd_base): Likewise. ++ (thumb2_ldrd_base_neg): Likewise. ++ (thumb2_strd): Likewise. ++ (thumb2_strd_base): Likewise. ++ (thumb2_strd_base_neg): Likewise. ++ (arm_negsi2): Add alternative for 16-bit encoding. ++ (arm_one_cmplsi2): Likewise. ++ ++ 2013-06-28 Kyrylo Tkachov ++ ++ * config/arm/constraints.md (Ts): New constraint. ++ * config/arm/arm.md (arm_movqi_insn): Add alternatives for ++ 16-bit encodings. ++ (compare_scc): Use "Ts" constraint for operand 0. ++ (ior_scc_scc): Likewise. ++ (and_scc_scc): Likewise. ++ (and_scc_scc_nodom): Likewise. ++ (ior_scc_scc_cmp): Likewise for operand 7. ++ (and_scc_scc_cmp): Likewise. ++ * config/arm/thumb2.md (thumb2_movsi_insn): ++ Add alternatives for 16-bit encodings. ++ (thumb2_movhi_insn): Likewise. ++ (thumb2_movsicc_insn): Likewise. ++ (thumb2_and_scc): Take 'and' outside cond_exec. Use "Ts" constraint. ++ (thumb2_negscc): Use "Ts" constraint. ++ Move mvn instruction outside cond_exec block. ++ * config/arm/vfp.md (thumb2_movsi_vfp): Add alternatives ++ for 16-bit encodings. ++ ++ 2013-07-01 Sofiane Naci ++ ++ * arm.md (attribute "wtype"): Delete. Move attribute values from here ++ to ... ++ (attribute "type"): ... here, and prefix with "wmmx_". ++ (attribute "core_cycles"): Update for attribute changes. ++ * iwmmxt.md (tbcstv8qi): Update for attribute changes. ++ (tbcstv4hi): Likewise. ++ (tbcstv2si): Likewise. ++ (iwmmxt_iordi3): Likewise. ++ (iwmmxt_xordi3): Likewise. ++ (iwmmxt_anddi3): Likewise. ++ (iwmmxt_nanddi3): Likewise. ++ (iwmmxt_arm_movdi): Likewise. ++ (iwmmxt_movsi_insn): Likewise. ++ (mov_internal): Likewise. ++ (and3_iwmmxt): Likewise. ++ (ior3_iwmmxt): Likewise. ++ (xor3_iwmmxt): Likewise. ++ (add3_iwmmxt): Likewise. ++ (ssaddv8qi3): Likewise. ++ (ssaddv4hi3): Likewise. ++ (ssaddv2si3): Likewise. ++ (usaddv8qi3): Likewise. ++ (usaddv4hi3): Likewise. ++ (usaddv2si3): Likewise. ++ (sub3_iwmmxt): Likewise. ++ (sssubv8qi3): Likewise. ++ (sssubv4hi3): Likewise. ++ (sssubv2si3): Likewise. ++ (ussubv8qi3): Likewise. ++ (ussubv4hi3): Likewise. ++ (ussubv2si3): Likewise. ++ (mulv4hi3_iwmmxt): Likewise. ++ (smulv4hi3_highpart): Likewise. ++ (umulv4hi3_highpart): Likewise. ++ (iwmmxt_wmacs): Likewise. ++ (iwmmxt_wmacsz): Likewise. ++ (iwmmxt_wmacu): Likewise. ++ (iwmmxt_wmacuz): Likewise. ++ (iwmmxt_clrdi): Likewise. ++ (iwmmxt_clrv8qi): Likewise. ++ (iwmmxt_clr4hi): Likewise. ++ (iwmmxt_clr2si): Likewise. ++ (iwmmxt_uavgrndv8qi3): Likewise. ++ (iwmmxt_uavgrndv4hi3): Likewise. ++ (iwmmxt_uavgv8qi3): Likewise. ++ (iwmmxt_uavgv4hi3): Likewise. ++ (iwmmxt_tinsrb): Likewise. ++ (iwmmxt_tinsrh): Likewise. ++ (iwmmxt_tinsrw): Likewise. ++ (iwmmxt_textrmub): Likewise. ++ (iwmmxt_textrmsb): Likewise. ++ (iwmmxt_textrmuh): Likewise. ++ (iwmmxt_textrmsh): Likewise. ++ (iwmmxt_textrmw): Likewise. ++ (iwmxxt_wshufh): Likewise. ++ (eqv8qi3): Likewise. ++ (eqv4hi3): Likewise. ++ (eqv2si3): Likewise. ++ (gtuv8qi3): Likewise. ++ (gtuv4hi3): Likewise. ++ (gtuv2si3): Likewise. ++ (gtv8qi3): Likewise. ++ (gtv4hi3): Likewise. ++ (gtv2si3): Likewise. ++ (smax3_iwmmxt): Likewise. ++ (umax3_iwmmxt): Likewise. ++ (smin3_iwmmxt): Likewise. ++ (umin3_iwmmxt): Likewise. ++ (iwmmxt_wpackhss): Likewise. ++ (iwmmxt_wpackwss): Likewise. ++ (iwmmxt_wpackdss): Likewise. ++ (iwmmxt_wpackhus): Likewise. ++ (iwmmxt_wpackwus): Likewise. ++ (iwmmxt_wpackdus): Likewise. ++ (iwmmxt_wunpckihb): Likewise. ++ (iwmmxt_wunpckihh): Likewise. ++ (iwmmxt_wunpckihw): Likewise. ++ (iwmmxt_wunpckilb): Likewise. ++ (iwmmxt_wunpckilh): Likewise. ++ (iwmmxt_wunpckilw): Likewise. ++ (iwmmxt_wunpckehub): Likewise. ++ (iwmmxt_wunpckehuh): Likewise. ++ (iwmmxt_wunpckehuw): Likewise. ++ (iwmmxt_wunpckehsb): Likewise. ++ (iwmmxt_wunpckehsh): Likewise. ++ (iwmmxt_wunpckehsw): Likewise. ++ (iwmmxt_wunpckelub): Likewise. ++ (iwmmxt_wunpckeluh): Likewise. ++ (iwmmxt_wunpckeluw): Likewise. ++ (iwmmxt_wunpckelsb): Likewise. ++ (iwmmxt_wunpckelsh): Likewise. ++ (iwmmxt_wunpckelsw): Likewise. ++ (ror3): Likewise. ++ (ashr3_iwmmxt): Likewise. ++ (lshr3_iwmmxt): Likewise. ++ (ashl3_iwmmxt): Likewise. ++ (ror3_di): Likewise. ++ (ashr3_di): Likewise. ++ (lshr3_di): Likewise. ++ (ashl3_di): Likewise. ++ (iwmmxt_wmadds): Likewise. ++ (iwmmxt_wmaddu): Likewise. ++ (iwmmxt_tmia): Likewise. ++ (iwmmxt_tmiaph): Likewise. ++ (iwmmxt_tmiabb): Likewise. ++ (iwmmxt_tmiatb): Likewise. ++ (iwmmxt_tmiabt): Likewise. ++ (iwmmxt_tmiatt): Likewise. ++ (iwmmxt_tmovmskb): Likewise. ++ (iwmmxt_tmovmskh): Likewise. ++ (iwmmxt_tmovmskw): Likewise. ++ (iwmmxt_waccb): Likewise. ++ (iwmmxt_wacch): Likewise. ++ (iwmmxt_waccw): Likewise. ++ (iwmmxt_waligni): Likewise. ++ (iwmmxt_walignr): Likewise. ++ (iwmmxt_walignr0): Likewise. ++ (iwmmxt_walignr1): Likewise. ++ (iwmmxt_walignr2): Likewise. ++ (iwmmxt_walignr3): Likewise. ++ (iwmmxt_wsadb): Likewise. ++ (iwmmxt_wsadh): Likewise. ++ (iwmmxt_wsadbz): Likewise. ++ (iwmmxt_wsadhz): Likewise. ++ * iwmmxt2.md (iwmmxt_wabs3): Update for attribute changes. ++ (iwmmxt_wabsdiffb): Likewise. ++ (iwmmxt_wabsdiffh): Likewise. ++ (iwmmxt_wabsdiffw): Likewise. ++ (iwmmxt_waddsubhx): Likewise ++ (iwmmxt_wsubaddhx): Likewise. ++ (addc3): Likewise. ++ (iwmmxt_avg4): Likewise. ++ (iwmmxt_avg4r): Likewise. ++ (iwmmxt_wmaddsx): Likewise. ++ (iwmmxt_wmaddux): Likewise. ++ (iwmmxt_wmaddsn): Likewise. ++ (iwmmxt_wmaddun): Likewise. ++ (iwmmxt_wmulwsm): Likewise. ++ (iwmmxt_wmulwum): Likewise. ++ (iwmmxt_wmulsmr): Likewise. ++ (iwmmxt_wmulumr): Likewise. ++ (iwmmxt_wmulwsmr): Likewise. ++ (iwmmxt_wmulwumr): Likewise. ++ (iwmmxt_wmulwl): Likewise. ++ (iwmmxt_wqmulm): Likewise. ++ (iwmmxt_wqmulwm): Likewise. ++ (iwmmxt_wqmulmr): Likewise. ++ (iwmmxt_wqmulwmr): Likewise. ++ (iwmmxt_waddbhusm): Likewise. ++ (iwmmxt_waddbhusl): Likewise. ++ (iwmmxt_wqmiabb): Likewise. ++ (iwmmxt_wqmiabt): Likewise. ++ (iwmmxt_wqmiatb): Likewise. ++ (iwmmxt_wqmiatt): Likewise. ++ (iwmmxt_wqmiabbn): Likewise. ++ (iwmmxt_wqmiabtn): Likewise. ++ (iwmmxt_wqmiatbn): Likewise. ++ (iwmmxt_wqmiattn): Likewise. ++ (iwmmxt_wmiabb): Likewise. ++ (iwmmxt_wmiabt): Likewise. ++ (iwmmxt_wmiatb): Likewise. ++ (iwmmxt_wmiatt): Likewise. ++ (iwmmxt_wmiabbn): Likewise. ++ (iwmmxt_wmiabtn): Likewise. ++ (iwmmxt_wmiatbn): Likewise. ++ (iwmmxt_wmiattn): Likewise. ++ (iwmmxt_wmiawbb): Likewise. ++ (iwmmxt_wmiawbt): Likewise. ++ (iwmmxt_wmiawtb): Likewise. ++ (iwmmxt_wmiawtt): Likewise. ++ (iwmmxt_wmiawbbn): Likewise. ++ (iwmmxt_wmiawbtn): Likewise. ++ (iwmmxt_wmiawtbn): Likewise. ++ (iwmmxt_wmiawttn): Likewise. ++ (iwmmxt_wmerge): Likewise. ++ (iwmmxt_tandc3): Likewise. ++ (iwmmxt_torc3): Likewise. ++ (iwmmxt_torvsc3): Likewise. ++ (iwmmxt_textrc3): Likewise. ++ * marvell-f-iwmmxt.md (wmmxt_shift): Update for attribute changes. ++ (wmmxt_pack): Likewise. ++ (wmmxt_mult_c1): Likewise. ++ (wmmxt_mult_c2): Likewise. ++ (wmmxt_alu_c1): Likewise. ++ (wmmxt_alu_c2): Likewise. ++ (wmmxt_alu_c3): Likewise. ++ (wmmxt_transfer_c1): Likewise. ++ (wmmxt_transfer_c2): Likewise. ++ (wmmxt_transfer_c3): Likewise. ++ (marvell_f_iwmmxt_wstr): Likewise. ++ (marvell_f_iwmmxt_wldr): Likewise. ++ ++2013-08-07 Christophe Lyon ++ ++ Backport from trunk r201237. ++ 2013-07-25 Terry Guo ++ ++ * config/arm/arm.c (thumb1_size_rtx_costs): Assign proper cost for ++ shift_add/shift_sub0/shift_sub1 RTXs. ++ ++2013-08-06 Christophe Lyon ++ ++ Backport from trunk r200596,201067,201083. ++ 2013-07-02 Ian Bolton + -+ * config/aarch64/aarch64-protos.h (aarch64_mov_operand_p): Define. -+ * config/aarch64/aarch64.c (aarch64_mov_operand_p): Define. -+ * config/aarch64/predicates.md (aarch64_const_address): Remove. -+ (aarch64_mov_operand): Use aarch64_mov_operand_p. ++ * config/aarch64/aarch64-simd.md (absdi2): Support abs for ++ DI mode. + -+ 2013-05-23 Vidya Praveen ++ 2013-07-19 Ian Bolton ++ ++ * config/aarch64/arm_neon.h (vabs_s64): New function ++ ++ 2013-07-20 James Greenhalgh + -+ * config/aarch64/aarch64-simd.md (clzv4si2): Support for CLZ -+ instruction (AdvSIMD). + * config/aarch64/aarch64-builtins.c -+ (aarch64_builtin_vectorized_function): Handler for BUILT_IN_CLZ. -+ * config/aarch64/aarch-simd-builtins.def: Entry for CLZ. ++ (aarch64_fold_builtin): Fold abs in all modes. ++ * config/aarch64/aarch64-simd-builtins.def ++ (abs): Enable for all modes. ++ * config/aarch64/arm_neon.h ++ (vabs_s<8,16,32,64): Rewrite using builtins. ++ (vabs_f64): Add missing intrinsic. + -+ 2013-05-14 James Greenhalgh ++2013-08-06 Christophe Lyon + -+ * config/aarch64/aarch64-simd.md -+ (aarch64_vcond_internal): Rename to... -+ (aarch64_vcond_internal): ...This, for integer modes. -+ (aarch64_vcond_internal): ...This for -+ float modes. Clarify all iterator modes. -+ (vcond): Use new name for vcond expanders. -+ (vcond): Likewise. -+ (vcondu: Likewise. -+ * config/aarch64/iterators.md (VDQF_COND): New. ++ Backport from trunk r198735,198831,199959. ++ 2013-05-09 Sofiane Naci + -+2013-05-29 Christophe Lyon ++ * config/aarch64/aarch64.md: New movtf split. ++ (*movtf_aarch64): Update. ++ (aarch64_movdi_tilow): Handle TF modes and rename to ++ aarch64_movdi_low. ++ (aarch64_movdi_tihigh): Handle TF modes and rename to ++ aarch64_movdi_high ++ (aarch64_movtihigh_di): Handle TF modes and rename to ++ aarch64_movhigh_di ++ (aarch64_movtilow_di): Handle TF modes and rename to ++ aarch64_movlow_di ++ (aarch64_movtilow_tilow): Remove spurious whitespace. ++ * config/aarch64/aarch64.c (aarch64_split_128bit_move): Handle TFmode ++ splits. ++ (aarch64_print_operand): Update. ++ ++ 2013-05-13 Sofiane Naci ++ ++ * config/aarch64/aarch64-simd.md (aarch64_simd_mov): Group ++ similar switch cases. ++ (aarch64_simd_mov): Rename to aarch64_split_simd_mov. Update. ++ (aarch64_simd_mov_to_low): Delete. ++ (aarch64_simd_mov_to_high): Delete. ++ (move_lo_quad_): Add w<-r alternative. ++ (aarch64_simd_move_hi_quad_): Likewise. ++ (aarch64_simd_mov_from_*): Update type attribute. ++ * config/aarch64/aarch64.c (aarch64_split_simd_move): Refacror switch ++ statement. + -+ Backport from trunk r198928,198973,199203. -+ 2013-05-22 Ramana Radhakrishnan ++ 2013-06-11 Sofiane Naci + -+ PR target/19599 -+ PR target/57340 -+ * config/arm/arm.c (any_sibcall_uses_r3): Rename to .. -+ (any_sibcall_could_use_r3): this and handle indirect calls. -+ (arm_get_frame_offsets): Rename use of any_sibcall_uses_r3. ++ * config/aarch64/aarch64-simd.md (move_lo_quad_): Update. + -+ 2013-05-16 Ramana Radhakrishnan ++2013-08-06 Christophe Lyon + -+ PR target/19599 -+ * config/arm/arm.c (arm_function_ok_for_sibcall): Add check -+ for NULL decl. ++ Backport from trunk r199438,199439,201326. ++ ++ 2013-05-30 Zhenqiang Chen ++ ++ * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added. ++ (arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes. ++ (arm_emit_vfp_multi_reg_pop): Likewise. ++ (thumb2_emit_ldrd_pop): Likewise. ++ (arm_expand_epilogue): Add misc REG_CFA notes. ++ (arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE. ++ ++ 2013-05-30 Bernd Schmidt ++ Zhenqiang Chen ++ ++ * config/arm/arm-protos.h: Add and update function protos. ++ * config/arm/arm.c (use_simple_return_p): New added. ++ (thumb2_expand_return): Check simple_return flag. ++ * config/arm/arm.md: Add simple_return and conditional simple_return. ++ * config/arm/iterators.md: Add iterator for return and simple_return. ++ ++ 2013-07-30 Zhenqiang Chen ++ ++ PR rtl-optimization/57637 ++ * function.c (move_insn_for_shrink_wrap): Also check the ++ GEN set of the LIVE problem for the liveness analysis ++ if it exists, otherwise give up. + ++2013-08-06 Christophe Lyon ++ ++ Backport from trunk r198928,198973,199203,201240,201241,201307. + 2013-05-15 Ramana Radhakrishnan + + PR target/19599 @@ -1134,4061 +2497,3604 @@ + * config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling + without decls. + -+2013-05-28 Christophe Lyon ++ 2013-05-16 Ramana Radhakrishnan + -+ Backport from trunk r198680. -+ 2013-05-07 Sofiane Naci ++ PR target/19599 ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Add check ++ for NULL decl. + -+ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): call splitter. -+ (aarch64_simd_mov): New expander. -+ (aarch64_simd_mov_to_low): New instruction pattern. -+ (aarch64_simd_mov_to_high): Likewise. -+ (aarch64_simd_mov_from_low): Likewise. -+ (aarch64_simd_mov_from_high): Likewise. -+ (aarch64_dup_lane): Update. -+ (aarch64_dup_lanedi): New instruction pattern. -+ * config/aarch64/aarch64-protos.h (aarch64_split_simd_move): New prototype. -+ * config/aarch64/aarch64.c (aarch64_split_simd_move): New function. ++ 2013-05-22 Ramana Radhakrishnan + -+2013-05-28 Christophe Lyon ++ PR target/19599 ++ PR target/57340 ++ * config/arm/arm.c (any_sibcall_uses_r3): Rename to .. ++ (any_sibcall_could_use_r3): this and handle indirect calls. ++ (arm_get_frame_offsets): Rename use of any_sibcall_uses_r3. + -+ Backport from trunk r198497-198500. -+ 2013-05-01 James Greenhalgh ++ 2013-07-25 Ramana Radhakrishnan + -+ * config/aarch64/aarch64-builtins.c -+ (aarch64_gimple_fold_builtin.c): Fold more modes for reduc_splus_. -+ * config/aarch64/aarch64-simd-builtins.def -+ (reduc_splus_): Add new modes. -+ (reduc_uplus_): New. -+ * config/aarch64/aarch64-simd.md (aarch64_addvv4sf): Remove. -+ (reduc_uplus_v4sf): Likewise. -+ (reduc_splus_v4sf): Likewise. -+ (aarch64_addv): Likewise. -+ (reduc_uplus_): Likewise. -+ (reduc_splus_): Likewise. -+ (aarch64_addvv2di): Likewise. -+ (reduc_uplus_v2di): Likewise. -+ (reduc_splus_v2di): Likewise. -+ (aarch64_addvv2si): Likewise. -+ (reduc_uplus_v2si): Likewise. -+ (reduc_splus_v2si): Likewise. -+ (reduc_plus_): New. -+ (reduc_plus_v2di): Likewise. -+ (reduc_plus_v2si): Likewise. -+ (reduc_plus_v4sf): Likewise. -+ (aarch64_addpv4sf): Likewise. -+ * config/aarch64/arm_neon.h -+ (vaddv_<8, 16, 32, 64): Rewrite using builtins. -+ * config/aarch64/iterators.md (unspec): Remove UNSPEC_ADDV, -+ add UNSPEC_SADDV, UNSPEC_UADDV. -+ (SUADDV): New. -+ (sur): Add UNSPEC_SADDV, UNSPEC_UADDV. ++ PR target/19599 ++ PR target/57731 ++ PR target/57748 ++ * config/arm/arm.md ("*sibcall_value_insn): Replace use of ++ Ss with US. Adjust output for v5 and v4t. ++ (*sibcall_value_insn): Likewise and loosen predicate on ++ operand0. ++ * config/arm/constraints.md ("Ss"): Rename to US. ++ ++ 2013-07-25 Ramana Radhakrishnan ++ ++ * config/arm/arm.md (*sibcall_insn): Remove unnecessary space. ++ ++ 2013-07-29 Ramana Radhakrishnan ++ Fix incorrect changelog entry. ++ ++ Replace ++ PR target/57748 ++ with ++ PR target/57837 + -+ 2013-05-01 James Greenhalgh ++2013-08-05 Yvan Roux + -+ * config/aarch64/arm_neon.h -+ (v_<8, 16, 32, 64>): Rewrite using builtins. ++ Backport from trunk r200922. ++ 2013-07-12 Tejas Belagod + -+ 2013-05-01 James Greenhalgh ++ * config/aarch64/aarch64-protos.h ++ (aarch64_simd_immediate_valid_for_move): Remove. ++ * config/aarch64/aarch64.c (simd_immediate_info): New member. ++ (aarch64_simd_valid_immediate): Recognize idioms for shifting ones ++ cases. ++ (aarch64_output_simd_mov_immediate): Print the correct shift specifier. + -+ * config/aarch64/aarch64-builtins -+ (aarch64_gimple_fold_builtin): Fold reduc__ builtins. ++2013-08-05 Yvan Roux + -+ 2013-05-01 James Greenhalgh ++ Backport from trunk r200670. ++ 2013-07-04 Tejas Belagod + -+ * config/aarch64/aarch64-simd-builtins.def -+ (reduc_smax_): New. -+ (reduc_smin_): Likewise. -+ (reduc_umax_): Likewise. -+ (reduc_umin_): Likewise. -+ (reduc_smax_nan_): Likewise. -+ (reduc_smin_nan_): Likewise. -+ (fmax): Remove. -+ (fmin): Likewise. -+ (smax): Update for V2SF, V4SF and V2DF modes. -+ (smin): Likewise. -+ (smax_nan): New. -+ (smin_nan): Likewise. -+ * config/aarch64/aarch64-simd.md (3): Rename to... -+ (3): ...This, refactor. -+ (s3): New. -+ (3): Likewise. -+ (reduc__): Refactor. -+ (reduc__v4sf): Likewise. -+ (reduc__v2si): Likewise. -+ (aarch64_: Remove. -+ * config/aarch64/arm_neon.h (vmax_f<32,64>): Rewrite to use -+ new builtin names. -+ (vmin_f<32,64>): Likewise. -+ * config/iterators.md (unspec): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. -+ (FMAXMIN): New. -+ (su): Add mappings for smax, smin, umax, umin. -+ (maxmin): New. -+ (FMAXMINV): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. -+ (FMAXMIN): Rename as... -+ (FMAXMIN_UNS): ...This. -+ (maxminv): Remove. -+ (fmaxminv): Likewise. -+ (fmaxmin): Likewise. -+ (maxmin_uns): New. -+ (maxmin_uns_op): Likewise. ++ * config/aarch64/aarch64-protos.h (cpu_vector_cost): New. ++ (tune_params): New member 'const vec_costs'. ++ * config/aarch64/aarch64.c (generic_vector_cost): New. ++ (generic_tunings): New member 'generic_vector_cost'. ++ (aarch64_builtin_vectorization_cost): New. ++ (aarch64_add_stmt_cost): New. ++ (TARGET_VECTORIZE_ADD_STMT_COST): New. ++ (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): New. + -+2013-05-28 Christophe Lyon ++2013-08-05 Yvan Roux + -+ Backport from trunk r199241. -+ 2013-05-23 James Greenhalgh ++ Backport from trunk r200637. ++ 2013-07-03 Yufeng Zhang + -+ * config/aarch64/aarch64-simd.md -+ (aarch64_cmdi): Add clobber of CC_REGNUM to unsplit pattern. ++ * config/aarch64/aarch64.h (enum arm_abi_type): Remove. ++ (ARM_ABI_AAPCS64): Ditto. ++ (arm_abi): Ditto. ++ (ARM_DEFAULT_ABI): Ditto. + -+2013-05-23 Christophe Lyon ++2013-08-05 Yvan Roux + -+ Backport from trunk r198970. -+ 2013-05-16 Greta Yorsh ++ Backport from trunk r200532, r200565. ++ 2013-06-28 Marcus Shawcroft + -+ * config/arm/arm-protos.h (gen_movmem_ldrd_strd): New declaration. -+ * config/arm/arm.c (next_consecutive_mem): New function. -+ (gen_movmem_ldrd_strd): Likewise. -+ * config/arm/arm.md (movmemqi): Update condition and code. -+ (unaligned_loaddi, unaligned_storedi): New patterns. ++ * config/aarch64/aarch64.c (aarch64_cannot_force_const_mem): Adjust ++ layout. + -+2013-05-19 Matthew Gretton-Dann ++ 2013-06-29 Yufeng Zhang + -+ * LINARO-VERSION: Bump version number. ++ * config/aarch64/aarch64.c: Remove junk from the beginning of the ++ file. + -+2013-05-14 Matthew Gretton-Dann ++2013-08-05 Yvan Roux + -+ GCC Linaro 4.8-2013.05 released. ++ Backport from trunk r200531. ++ 2013-06-28 Marcus Shawcroft + -+2013-05-14 Matthew Gretton-Dann ++ * config/aarch64/aarch64-protos.h (aarch64_symbol_type): ++ Update comment w.r.t SYMBOL_TINY_ABSOLUTE. + -+ Backport from trunk r198677. -+ 2013-05-07 Naveen H.S ++2013-08-05 Yvan Roux + -+ * config/aarch64/aarch64.md -+ (cmp_swp__shft_): Restrict the -+ shift value between 0-4. ++ Backport from trunk r200519. ++ 2013-06-28 Marcus Shawcroft + -+2013-05-14 Matthew Gretton-Dann ++ * config/aarch64/aarch64-protos.h ++ aarch64_classify_symbol_expression): Define. ++ (aarch64_symbolic_constant_p): Remove. ++ * config/aarch64/aarch64.c (aarch64_classify_symbol_expression): Remove ++ static. Fix line length and white space. ++ (aarch64_symbolic_constant_p): Remove. ++ * config/aarch64/predicates.md (aarch64_valid_symref): ++ Use aarch64_classify_symbol_expression. ++ ++2013-08-05 Yvan Roux ++ ++ Backport from trunk r200466, r200467. ++ 2013-06-27 Yufeng Zhang ++ ++ * config/aarch64/aarch64.c (aarch64_force_temporary): Add an extra ++ parameter 'mode' of type 'enum machine_mode mode'; change to pass ++ 'mode' to force_reg. ++ (aarch64_add_offset): Update calls to aarch64_force_temporary. ++ (aarch64_expand_mov_immediate): Likewise. + -+ Backport from trunk r198574-198575. -+ 2013-05-03 Vidya Praveen ++ 2013-06-27 Yufeng Zhang + -+ * config/aarch64/aarch64-simd.md (simd_fabd): Correct the description. ++ * config/aarch64/aarch64.c (aarch64_add_offset): Change to pass ++ 'mode' to aarch64_plus_immediate and gen_rtx_PLUS. + -+ 2013-05-03 Vidya Praveen ++2013-08-05 Yvan Roux + -+ * config/aarch64/aarch64-simd.md (*fabd_scalar3): Support -+ scalar form of FABD instruction. -+ -+2013-05-14 Matthew Gretton-Dann ++ Backport from trunk r200419. ++ 2013-06-26 Greta Yorsh + -+ Backport from trunk r198490-198496 -+ 2013-05-01 James Greenhalgh ++ * config/arm/arm.h (MAX_CONDITIONAL_EXECUTE): Define macro. ++ * config/arm/arm-protos.h (arm_max_conditional_execute): New ++ declaration. ++ (tune_params): Update comment. ++ * config/arm/arm.c (arm_cortex_a15_tune): Set max_cond_insns to 2. ++ (arm_max_conditional_execute): New function. ++ (thumb2_final_prescan_insn): Use max_insn_skipped and ++ MAX_INSN_PER_IT_BLOCK to compute maximum instructions in a block. + -+ * config/aarch64/arm_neon.h -+ (vac_f<32, 64>): Rename to... -+ (vca_f<32, 64>): ...this, reimpliment in C. -+ (vca_f<32, 64>): Reimpliment in C. ++2013-07-24 Matthew Gretton-Dann + -+ 2013-05-01 James Greenhalgh ++ * LINARO-VERSION: Bump version. + -+ * config/aarch64/aarch64-simd.md (*aarch64_fac): New. -+ * config/aarch64/iterators.md (FAC_COMPARISONS): New. ++2013-07-19 Matthew Gretton-Dann + -+ 2013-05-01 James Greenhalgh ++ GCC Linaro 4.8-2013.07-1 released. + -+ * config/aarch64/aarch64-simd.md -+ (vcond_internal): Handle special cases for constant masks. -+ (vcond): Allow nonmemory_operands for outcome vectors. -+ (vcondu): Likewise. -+ (vcond): New. ++2013-07-19 Matthew Gretton-Dann + -+ 2013-05-01 James Greenhalgh ++ Backport from trunk r201005. ++ 2013-07-17 Yvan Roux + -+ * config/aarch64/aarch64-builtins.c (BUILTIN_VALLDI): Define. -+ (aarch64_fold_builtin): Add folding for cm. -+ * config/aarch64/aarch64-simd-builtins.def -+ (cmeq): Update to BUILTIN_VALLDI. -+ (cmgt): Likewise. -+ (cmge): Likewise. -+ (cmle): Likewise. -+ (cmlt): Likewise. -+ * config/aarch64/arm_neon.h -+ (vc_<8,16,32,64>): Remap -+ to builtins or C as appropriate. ++ PR target/57909 ++ * config/arm/arm.c (gen_movmem_ldrd_strd): Fix unaligned load/store ++ usage in HI mode. + -+ 2013-05-01 James Greenhalgh ++2013-07-05 Christophe Lyon + -+ * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to... -+ (cmgeu): ...This. -+ (cmhi): Rename to... -+ (cmgtu): ...This. -+ * config/aarch64/aarch64-simd.md -+ (simd_mode): Add SF. -+ (aarch64_vcond_internal): Use new names for unsigned comparison insns. -+ (aarch64_cm): Rewrite to not use UNSPECs. -+ * config/aarch64/aarch64.md (*cstore_neg): Rename to... -+ (cstore_neg): ...This. -+ * config/aarch64/iterators.md -+ (VALLF): new. -+ (unspec): Remove UNSPEC_CM. -+ (COMPARISONS): New. -+ (UCOMPARISONS): Likewise. -+ (optab): Add missing comparisons. -+ (n_optab): New. -+ (cmp_1): Likewise. -+ (cmp_2): Likewise. -+ (CMP): Likewise. -+ (cmp): Remove. -+ (VCMP_S): Likewise. -+ (VCMP_U): Likewise. -+ (V_cmp_result): Add DF, SF modes. -+ (v_cmp_result): Likewise. -+ (v): Likewise. -+ (vmtype): Likewise. -+ * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New. ++ GCC Linaro 4.8-2013.07 released. + -+2013-05-14 Matthew Gretton-Dann ++2013-07-03 Christophe Lyon + -+ Backport from trunk r198191. -+ 2013-04-23 Sofiane Naci ++ Revert backport from trunk r198928,198973,199203. ++ 2013-05-22 Ramana Radhakrishnan + -+ * config/aarch64/aarch64.md (*mov_aarch64): Add simd attribute. ++ PR target/19599 ++ PR target/57340 ++ * config/arm/arm.c (any_sibcall_uses_r3): Rename to .. ++ (any_sibcall_could_use_r3): this and handle indirect calls. ++ (arm_get_frame_offsets): Rename use of any_sibcall_uses_r3. + -+2013-05-14 Matthew Gretton-Dann ++ 2013-05-16 Ramana Radhakrishnan + -+ Backport from trunk r197838. -+ 2013-04-11 Naveen H.S ++ PR target/19599 ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Add check ++ for NULL decl. + -+ * config/aarch64/aarch64.c (aarch64_select_cc_mode): Allow NEG -+ code in CC_NZ mode. -+ * config/aarch64/aarch64.md (*neg_3_compare0): New -+ pattern. ++ 2013-05-15 Ramana Radhakrishnan + -+2013-05-02 Matthew Gretton-Dann ++ PR target/19599 ++ * config/arm/predicates.md (call_insn_operand): New predicate. ++ * config/arm/constraints.md ("Cs", "Ss"): New constraints. ++ * config/arm/arm.md (*call_insn, *call_value_insn): Match only ++ if insn is not a tail call. ++ (*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through ++ registers. ++ * config/arm/arm.h (enum reg_class): New caller save register class. ++ (REG_CLASS_NAMES): Likewise. ++ (REG_CLASS_CONTENTS): Likewise. ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling ++ without decls. + -+ Backport from trunk r198019. -+ 2013-04-16 Naveen H.S ++2013-07-03 Christophe Lyon + -+ * config/aarch64/aarch64.md (*adds_mul_imm_): New pattern. -+ (*subs_mul_imm_): New pattern. ++ Revert backport from mainline (r199438, r199439) ++ 2013-05-30 Zhenqiang Chen + -+2013-05-02 Matthew Gretton-Dann ++ * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added. ++ (arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes. ++ (arm_emit_vfp_multi_reg_pop): Likewise. ++ (thumb2_emit_ldrd_pop): Likewise. ++ (arm_expand_epilogue): Add misc REG_CFA notes. ++ (arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE. + -+ Backport from trunk r198424-198425. -+ 2013-04-29 Ian Bolton ++ 2013-05-30 Bernd Schmidt ++ Zhenqiang Chen + -+ * config/aarch64/aarch64.md (movsi_aarch64): Support LDR/STR -+ from/to S register. -+ (movdi_aarch64): Support LDR/STR from/to D register. ++ * config/arm/arm-protos.h: Add and update function protos. ++ * config/arm/arm.c (use_simple_return_p): New added. ++ (thumb2_expand_return): Check simple_return flag. ++ * config/arm/arm.md: Add simple_return and conditional simple_return. ++ * config/arm/iterators.md: Add iterator for return and simple_return. ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. + -+ 2013-04-29 Ian Bolton ++2013-07-03 Christophe Lyon + -+ * common/config/aarch64/aarch64-common.c: Enable REE pass at O2 -+ or higher by default. ++ Backport from trunk r199640, 199705, 199733, 199734, 199739. ++ 2013-06-04 Kyrylo Tkachov + -+2013-05-02 Matthew Gretton-Dann ++ * rtl.def: Add extra fourth optional field to define_cond_exec. ++ * gensupport.c (process_one_cond_exec): Process attributes from ++ define_cond_exec. ++ * doc/md.texi: Document fourth field in define_cond_exec. + -+ Backport from trunk r198412. -+ 2013-04-29 Kyrylo Tkachov ++ 2013-06-05 Kyrylo Tkachov + -+ * config/arm/arm.md (store_minmaxsi): Use only when -+ optimize_insn_for_size_p. ++ * config/arm/arm.md (enabled_for_depr_it): New attribute. ++ (predicable_short_it): Likewise. ++ (predicated): Likewise. ++ (enabled): Handle above. ++ (define_cond_exec): Set predicated attribute to yes. + -+2013-05-02 Matthew Gretton-Dann ++ 2013-06-06 Kyrylo Tkachov + -+ Backport from trunk 198394,198396-198400,198402-198404. -+ 2013-04-29 James Greenhalgh ++ * config/arm/sync.md (atomic_loaddi_1): ++ Disable predication for arm_restrict_it. ++ (arm_load_exclusive): Likewise. ++ (arm_load_exclusivesi): Likewise. ++ (arm_load_exclusivedi): Likewise. ++ (arm_load_acquire_exclusive): Likewise. ++ (arm_load_acquire_exclusivesi): Likewise. ++ (arm_load_acquire_exclusivedi): Likewise. ++ (arm_store_exclusive): Likewise. ++ (arm_store_exclusive): Likewise. ++ (arm_store_release_exclusivedi): Likewise. ++ (arm_store_release_exclusive): Likewise. + -+ * config/aarch64/arm_neon.h -+ (vcvt_f<32,64>_s<32,64>): Rewrite in C. -+ (vcvt_f<32,64>_s<32,64>): Rewrite using builtins. -+ (vcvt__f<32,64>_f<32,64>): Likewise. -+ (vcvt_<32,64>_f<32,64>): Likewise. -+ (vcvta_<32,64>_f<32,64>): Likewise. -+ (vcvtm_<32,64>_f<32,64>): Likewise. -+ (vcvtn_<32,64>_f<32,64>): Likewise. -+ (vcvtp_<32,64>_f<32,64>): Likewise. ++ 2013-06-06 Kyrylo Tkachov + -+ 2013-04-29 James Greenhalgh ++ * config/arm/arm-ldmstm.ml: Set "predicable_short_it" to "no" ++ where appropriate. ++ * config/arm/ldmstm.md: Regenerate. + -+ * config/aarch64/aarch64-simd.md -+ (2): New, maps to fix, fixuns. -+ (2): New, maps to -+ fix_trunc, fixuns_trunc. -+ (ftrunc2): New. -+ * config/aarch64/iterators.md (optab): Add fix, fixuns. -+ (fix_trunc_optab): New. ++ 2013-06-06 Kyrylo Tkachov + -+ 2013-04-29 James Greenhalgh ++ * config/arm/arm-fixed.md (add3,usadd3,ssadd3, ++ sub3, ussub3, sssub3, arm_ssatsihi_shift, ++ arm_usatsihi): Adjust alternatives for arm_restrict_it. + -+ * config/aarch64/aarch64-builtins.c -+ (aarch64_builtin_vectorized_function): Vectorize over ifloorf, -+ iceilf, lround, iroundf. ++2013-07-02 Rob Savoye + -+ 2013-04-29 James Greenhalgh ++ Backport from trunk 200096 + -+ * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi_): New. -+ (float_truncate_hi_): Likewise. -+ (float_extend_lo_): Likewise. -+ (float_truncate_lo_): Likewise. -+ * config/aarch64/aarch64-simd.md (vec_unpacks_lo_v4sf): New. -+ (aarch64_float_extend_lo_v2df): Likewise. -+ (vec_unpacks_hi_v4sf): Likewise. -+ (aarch64_float_truncate_lo_v2sf): Likewise. -+ (aarch64_float_truncate_hi_v4sf): Likewise. -+ (vec_pack_trunc_v2df): Likewise. -+ (vec_pack_trunc_df): Likewise. ++ 2013-06-14 Vidya Praveen + -+ 2013-04-29 James Greenhalgh ++ * config/aarch64/aarch64-simd.md (aarch64_mlal_lo): ++ New pattern. ++ (aarch64_mlal_hi, aarch64_mlsl_lo): Likewise. ++ (aarch64_mlsl_hi, aarch64_mlal): Likewise. ++ (aarch64_mlsl): Likewise. + -+ * config/aarch64/aarch64-builtins.c -+ (aarch64_fold_builtin): Fold float conversions. -+ * config/aarch64/aarch64-simd-builtins.def -+ (floatv2si, floatv4si, floatv2di): New. -+ (floatunsv2si, floatunsv4si, floatunsv2di): Likewise. -+ * config/aarch64/aarch64-simd.md -+ (2): New, expands to float and floatuns. -+ * config/aarch64/iterators.md (FLOATUORS): New. -+ (optab): Add float, floatuns. -+ (su_optab): Likewise. ++2013-07-02 Rob Savoye + -+ 2013-04-29 James Greenhalgh ++ Backport from trunk 200062 + -+ * config/aarch64/aarch64-builtins.c -+ (aarch64_builtin_vectorized_function): Fold to standard pattern names. -+ * config/aarch64/aarch64-simd-builtins.def (frintn): New. -+ (frintz): Rename to... -+ (btrunc): ...this. -+ (frintp): Rename to... -+ (ceil): ...this. -+ (frintm): Rename to... -+ (floor): ...this. -+ (frinti): Rename to... -+ (nearbyint): ...this. -+ (frintx): Rename to... -+ (rint): ...this. -+ (frinta): Rename to... -+ (round): ...this. -+ * config/aarch64/aarch64-simd.md -+ (aarch64_frint): Delete. -+ (2): Convert to insn. -+ * config/aarch64/aarch64.md (unspec): Add UNSPEC_FRINTN. -+ * config/aarch64/iterators.md (FRINT): Add UNSPEC_FRINTN. -+ (frint_pattern): Likewise. -+ (frint_suffix): Likewise. ++ 2013-06-13 Bin Cheng ++ * fold-const.c (operand_equal_p): Consider NOP_EXPR and ++ CONVERT_EXPR as equal nodes. + -+2013-05-02 Matthew Gretton-Dann ++2013-07-02 Rob Savoye ++ Backport from trunk 199810 + -+ Backport from trunk r198302-198306,198316. -+ 2013-04-25 James Greenhalgh ++ 2013-06-07 Kyrylo Tkachov + -+ * config/aarch64/aarch64-simd.md -+ (aarch64_simd_bsl_internal): Rewrite RTL to not use UNSPEC_BSL. -+ (aarch64_simd_bsl): Likewise. -+ * config/aarch64/iterators.md (unspec): Remove UNSPEC_BSL. ++ * config/arm/arm.md (anddi3_insn): Remove duplicate alternatives. ++ Clean up alternatives. + -+ 2013-04-25 James Greenhalgh ++2013-06-20 Rob Savoye + -+ * config/aarch64/aarch64-simd.md (neg2): Use VDQ iterator. ++ Backport from trunk 200152 ++ 2013-06-17 Sofiane Naci + -+ 2013-04-25 James Greenhalgh ++ * config/aarch64/aarch64-simd.md (aarch64_dup_lane): Add r<-w ++ alternative and update. ++ (aarch64_dup_lanedi): Delete. ++ * config/aarch64/arm_neon.h (vdup_lane_*): Update. ++ * config/aarch64/aarch64-simd-builtins.def: Update. + -+ * config/aarch64/aarch64-builtins.c -+ (aarch64_fold_builtin): New. -+ * config/aarch64/aarch64-protos.h (aarch64_fold_builtin): New. -+ * config/aarch64/aarch64.c (TARGET_FOLD_BUILTIN): Define. -+ * config/aarch64/aarch64-simd-builtins.def (abs): New. -+ * config/aarch64/arm_neon.h -+ (vabs_): Implement using __builtin_aarch64_fabs. ++2013-06-20 Rob Savoye + -+ 2013-04-25 James Greenhalgh -+ Tejas Belagod ++ Backport from trunk 200061 ++ 2013-06-13 Bin Cheng + -+ * config/aarch64/aarch64-builtins.c -+ (aarch64_gimple_fold_builtin): New. -+ * config/aarch64/aarch64-protos.h (aarch64_gimple_fold_builtin): New. -+ * config/aarch64/aarch64-simd-builtins.def (addv): New. -+ * config/aarch64/aarch64-simd.md (addpv4sf): New. -+ (addvv4sf): Update. -+ * config/aarch64/aarch64.c (TARGET_GIMPLE_FOLD_BUILTIN): Define. ++ * rtlanal.c (noop_move_p): Check the code to be executed for ++ COND_EXEC. + -+ 2013-04-25 Naveen H.S ++2013-06-20 Rob Savoye + -+ * config/aarch64/aarch64.md -+ (*cmp_swp__shft_): New pattern. ++ Backport from trunk 199694 ++ 2013-06-05 Kyrylo Tkachov + -+ 2013-04-25 Naveen H.S ++ * config/arm/arm.c (MAX_INSN_PER_IT_BLOCK): New macro. ++ (arm_option_override): Override arm_restrict_it where appropriate. ++ (thumb2_final_prescan_insn): Use MAX_INSN_PER_IT_BLOCK. ++ * config/arm/arm.opt (mrestrict-it): New command-line option. ++ * doc/invoke.texi: Document -mrestrict-it. + -+ * config/aarch64/aarch64.md (*ngc): New pattern. -+ (*ngcsi_uxtw): New pattern. ++2013-06-20 Christophe Lyon + -+2013-05-02 Matthew Gretton-Dann ++ Backport from trunk r198683. ++ 2013-05-07 Christophe Lyon + -+ Backport from trunk 198298. -+ 2013-04-25 Kyrylo Tkachov -+ Julian Brown ++ * config/arm/arm.c (arm_asan_shadow_offset): New function. ++ (TARGET_ASAN_SHADOW_OFFSET): Define. ++ * config/arm/linux-eabi.h (ASAN_CC1_SPEC): Define. ++ (LINUX_OR_ANDROID_CC): Add ASAN_CC1_SPEC. + -+ * config/arm/arm.c (neon_builtin_type_mode): Add T_V4HF. -+ (TB_DREG): Add T_V4HF. -+ (v4hf_UP): New macro. -+ (neon_itype): Add NEON_FLOAT_WIDEN, NEON_FLOAT_NARROW. -+ (arm_init_neon_builtins): Handle NEON_FLOAT_WIDEN, -+ NEON_FLOAT_NARROW. -+ Handle initialisation of V4HF. Adjust initialisation of reinterpret -+ built-ins. -+ (arm_expand_neon_builtin): Handle NEON_FLOAT_WIDEN, -+ NEON_FLOAT_NARROW. -+ (arm_vector_mode_supported_p): Handle V4HF. -+ (arm_mangle_map): Handle V4HFmode. -+ * config/arm/arm.h (VALID_NEON_DREG_MODE): Add V4HF. -+ * config/arm/arm_neon_builtins.def: Add entries for -+ vcvtv4hfv4sf, vcvtv4sfv4hf. -+ * config/arm/neon.md (neon_vcvtv4sfv4hf): New pattern. -+ (neon_vcvtv4hfv4sf): Likewise. -+ * config/arm/neon-gen.ml: Handle half-precision floating point -+ features. -+ * config/arm/neon-testgen.ml: Handle Requires_FP_bit feature. -+ * config/arm/arm_neon.h: Regenerate. -+ * config/arm/neon.ml (type elts): Add F16. -+ (type vectype): Add T_float16x4, T_floatHF. -+ (type vecmode): Add V4HF. -+ (type features): Add Requires_FP_bit feature. -+ (elt_width): Handle F16. -+ (elt_class): Likewise. -+ (elt_of_class_width): Likewise. -+ (mode_of_elt): Refactor. -+ (type_for_elt): Handle F16, fix error messages. -+ (vectype_size): Handle T_float16x4. -+ (vcvt_sh): New function. -+ (ops): Add entries for vcvt_f16_f32, vcvt_f32_f16. -+ (string_of_vectype): Handle T_floatHF, T_float16, T_float16x4. -+ (string_of_mode): Handle V4HF. -+ * doc/arm-neon-intrinsics.texi: Regenerate. ++2013-06-11 Rob Savoye + -+2013-05-02 Matthew Gretton-Dann ++ GCC Linaro gcc-linaro-4.8-2013.06 released. + -+ Backport from trunk r198136-198137,198142,198176. -+ 2013-04-23 Andreas Schwab ++2013-06-06 Zhenqiang Chen + -+ * coretypes.h (gimple_stmt_iterator): Add struct to make -+ compatible with C. ++ Backport from mainline (r199438, r199439) ++ 2013-05-30 Zhenqiang Chen + -+ 2013-04-22 James Greenhalgh ++ * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): New added. ++ (arm_emit_multi_reg_pop): Add REG_CFA_ADJUST_CFA notes. ++ (arm_emit_vfp_multi_reg_pop): Likewise. ++ (thumb2_emit_ldrd_pop): Likewise. ++ (arm_expand_epilogue): Add misc REG_CFA notes. ++ (arm_unwind_emit): Skip REG_CFA_ADJUST_CFA and REG_CFA_RESTORE. + -+ * coretypes.h (gimple_stmt_iterator_d): Forward declare. -+ (gimple_stmt_iterator): New typedef. -+ * gimple.h (gimple_stmt_iterator): Rename to... -+ (gimple_stmt_iterator_d): ... This. -+ * doc/tm.texi.in (TARGET_FOLD_BUILTIN): Detail restriction that -+ trees be valid for GIMPLE and GENERIC. -+ (TARGET_GIMPLE_FOLD_BUILTIN): New. -+ * gimple-fold.c (gimple_fold_call): Call target hook -+ gimple_fold_builtin. -+ * hooks.c (hook_bool_gsiptr_false): New. -+ * hooks.h (hook_bool_gsiptr_false): New. -+ * target.def (fold_stmt): New. -+ * doc/tm.texi: Regenerate. ++ 2013-05-30 Bernd Schmidt ++ Zhenqiang Chen + -+ 2013-04-22 James Greenhalgh ++ * config/arm/arm-protos.h: Add and update function protos. ++ * config/arm/arm.c (use_simple_return_p): New added. ++ (thumb2_expand_return): Check simple_return flag. ++ * config/arm/arm.md: Add simple_return and conditional simple_return. ++ * config/arm/iterators.md: Add iterator for return and simple_return. ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. + -+ * config/aarch64/aarch64-builtins.c -+ (CF): Remove. -+ (CF0, CF1, CF2, CF3, CF4, CF10): New. -+ (VAR<1-12>): Add MAP parameter. -+ (BUILTIN_*): Likewise. -+ * config/aarch64/aarch64-simd-builtins.def: Set MAP parameter. -+ * config/aarch64/aarch64-simd.md (aarch64_sshl_n): Remove. -+ (aarch64_ushl_n): Likewise. -+ (aarch64_sshr_n): Likewise. -+ (aarch64_ushr_n): Likewise. -+ (aarch64_): Likewise. -+ (aarch64_sqrt): Likewise. -+ * config/aarch64/arm_neon.h (vshl_n_*): Use new builtin names. -+ (vshr_n_*): Likewise. ++2013-06-06 Kugan Vivekanandarajah + -+ 2013-04-22 James Greenhalgh ++ Backport from mainline r198879: + -+ * config/aarch64/aarch64-builtins.c -+ (aarch64_simd_builtin_type_mode): Handle SF types. -+ (sf_UP): Define. -+ (BUILTIN_GPF): Define. -+ (aarch64_init_simd_builtins): Handle SF types. -+ * config/aarch64/aarch64-simd-builtins.def (frecpe): Add support. -+ (frecps): Likewise. -+ (frecpx): Likewise. -+ * config/aarch64/aarch64-simd.md -+ (simd_types): Update simd_frcp to simd_frecp. -+ (aarch64_frecpe): New. -+ (aarch64_frecps): Likewise. -+ * config/aarch64/aarch64.md (unspec): Add UNSPEC_FRECP. -+ (v8type): Add frecp. -+ (aarch64_frecp): New. -+ (aarch64_frecps): Likewise. -+ * config/aarch64/iterators.md (FRECP): New. -+ (frecp_suffix): Likewise. -+ * config/aarch64/arm_neon.h -+ (vrecp_<32, 64>): Convert to using builtins. ++ 2013-05-14 Chung-Lin Tang ++ PR target/42017 ++ * config/arm/arm.h (EPILOGUE_USES): Only return true ++ for LR_REGNUM after epilogue_completed. + -+2013-05-02 Matthew Gretton-Dann ++2013-06-05 Christophe Lyon + -+ Backport from trunk r198030. -+ 2013-04-17 Greta Yorsh ++ Backport from trunk r199652,199653,199656,199657,199658. + -+ * config/arm/arm.md (movsicc_insn): Convert define_insn into -+ define_insn_and_split. -+ (and_scc,ior_scc,negscc): Likewise. -+ (cmpsi2_addneg, subsi3_compare): Convert to named patterns. ++ 2013-06-04 Ian Bolton + -+2013-05-02 Matthew Gretton-Dann ++ * config/aarch64/aarch64.md (*mov_aarch64): Call ++ into function to generate MOVI instruction. ++ * config/aarch64/aarch64.c (aarch64_simd_container_mode): ++ New function. ++ (aarch64_preferred_simd_mode): Turn into wrapper. ++ (aarch64_output_scalar_simd_mov_immediate): New function. ++ * config/aarch64/aarch64-protos.h: Add prototype for above. + -+ Backport from trunk r198020. -+ 2013-04-16 Naveen H.S ++ 2013-06-04 Ian Bolton + -+ * config/aarch64/aarch64.md (*adds__multp2): -+ New pattern. -+ (*subs__multp2): New pattern. -+ (*adds__): New pattern. -+ (*subs__): New pattern. ++ * config/aarch64/aarch64.c (simd_immediate_info): Remove ++ element_char member. ++ (sizetochar): Return signed char. ++ (aarch64_simd_valid_immediate): Remove elchar and other ++ unnecessary variables. ++ (aarch64_output_simd_mov_immediate): Take rtx instead of &rtx. ++ Calculate element_char as required. ++ * config/aarch64/aarch64-protos.h: Update and move prototype ++ for aarch64_output_simd_mov_immediate. ++ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): ++ Update arguments. + -+2013-05-02 Matthew Gretton-Dann ++ 2013-06-04 Ian Bolton + -+ Backport from trunk r198004,198029. -+ 2013-04-17 Greta Yorsh ++ * config/aarch64/aarch64.c (simd_immediate_info): Struct to hold ++ information completed by aarch64_simd_valid_immediate. ++ (aarch64_legitimate_constant_p): Update arguments. ++ (aarch64_simd_valid_immediate): Work with struct rather than many ++ pointers. ++ (aarch64_simd_scalar_immediate_valid_for_move): Update arguments. ++ (aarch64_simd_make_constant): Update arguments. ++ (aarch64_output_simd_mov_immediate): Work with struct rather than ++ many pointers. Output immediate directly rather than as operand. ++ * config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate): ++ Update prototype. ++ * config/aarch64/constraints.md (Dn): Update arguments. + -+ * config/arm/arm.c (use_return_insn): Return 0 for targets that -+ can benefit from using a sequence of LDRD instructions in epilogue -+ instead of a single LDM instruction. ++ 2013-06-04 Ian Bolton + -+ 2013-04-16 Greta Yorsh ++ * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): No ++ longer static. ++ (aarch64_simd_immediate_valid_for_move): Remove. ++ (aarch64_simd_scalar_immediate_valid_for_move): Update call. ++ (aarch64_simd_make_constant): Update call. ++ (aarch64_output_simd_mov_immediate): Update call. ++ * config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate): ++ Add prototype. ++ * config/aarch64/constraints.md (Dn): Update call. + -+ * config/arm/arm.c (emit_multi_reg_push): New declaration -+ for an existing function. -+ (arm_emit_strd_push): New function. -+ (arm_expand_prologue): Used here. -+ (arm_emit_ldrd_pop): New function. -+ (arm_expand_epilogue): Used here. -+ (arm_get_frame_offsets): Update condition. -+ (arm_emit_multi_reg_pop): Add a special case for load of a single -+ register with writeback. -+ -+2013-05-02 Matthew Gretton-Dann -+ -+ Backport from trunk r197965. -+ 2013-04-15 Kyrylo Tkachov -+ -+ * config/arm/arm.c (const_ok_for_dimode_op): Handle AND case. -+ * config/arm/arm.md (*anddi3_insn): Change to insn_and_split. -+ * config/arm/constraints.md (De): New constraint. -+ * config/arm/neon.md (anddi3_neon): Delete. -+ (neon_vand): Expand to standard anddi3 pattern. -+ * config/arm/predicates.md (imm_for_neon_inv_logic_operand): -+ Move earlier in the file. -+ (neon_inv_logic_op2): Likewise. -+ (arm_anddi_operand_neon): New predicate. ++ 2013-06-04 Ian Bolton + -+2013-05-02 Matthew Gretton-Dann ++ * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Change ++ return type to bool for prototype. ++ (aarch64_legitimate_constant_p): Check for true instead of not -1. ++ (aarch64_simd_valid_immediate): Fix up each return to return a bool. ++ (aarch64_simd_immediate_valid_for_move): Update retval for bool. + -+ Backport from trunk r197925. -+ 2013-04-12 Greta Yorsh ++2013-06-04 Christophe Lyon + -+ * config/arm/arm.md (mov_scc,mov_negscc,mov_notscc): Convert -+ define_insn into define_insn_and_split and emit movsicc patterns. ++ Backport from trunk r199261. ++ 2013-05-23 Christian Bruel + -+2013-05-02 Matthew Gretton-Dann ++ PR debug/57351 ++ * config/arm/arm.c (arm_dwarf_register_span): Do not use dbx number. + -+ Backport from trunk r197807. -+ 2013-04-11 Naveen H.S ++2013-06-03 Christophe Lyon + -+ * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Define. ++ Backport from trunk ++ r198890,199254,199259,199260,199293,199407,199408,199454,199544,199545. + -+2013-05-02 Matthew Gretton-Dann ++ 2013-05-31 Marcus Shawcroft + -+ Backport from trunk r197642. -+ 2013-04-09 Kyrylo Tkachov ++ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): ++ Remove un-necessary braces. + -+ * config/arm/arm.md (minmax_arithsi_non_canon): New pattern. ++ 2013-05-31 Marcus Shawcroft + -+2013-05-02 Matthew Gretton-Dann ++ * config/aarch64/aarch64.c (aarch64_classify_symbol): ++ Use SYMBOL_TINY_ABSOLUTE for AARCH64_CMODEL_TINY_PIC. + -+ Backport from trunk r197530,197921. -+ 2013-04-12 Greta Yorsh ++ 2013-05-30 Ian Bolton + -+ * config/arm/arm.c (gen_operands_ldrd_strd): Initialize "base". ++ * config/aarch64/aarch64.md (insv): New define_expand. ++ (*insv_reg): New define_insn. + -+ 2013-04-05 Greta Yorsh ++ 2012-05-29 Chris Schlumberger-Socha ++ Marcus Shawcroft + -+ * config/arm/constraints.md (q): New constraint. -+ * config/arm/ldrdstrd.md: New file. -+ * config/arm/arm.md (ldrdstrd.md) New include. -+ (arm_movdi): Use "q" instead of "r" constraint -+ for double-word memory access. -+ (movdf_soft_insn): Likewise. -+ * config/arm/vfp.md (movdi_vfp): Likewise. -+ * config/arm/t-arm (MD_INCLUDES): Add ldrdstrd.md. -+ * config/arm/arm-protos.h (gen_operands_ldrd_strd): New declaration. -+ * config/arm/arm.c (gen_operands_ldrd_strd): New function. -+ (mem_ok_for_ldrd_strd): Likewise. -+ (output_move_double): Update assertion. ++ * config/aarch64/aarch64-protos.h (aarch64_symbol_type): Define ++ SYMBOL_TINY_ABSOLUTE. ++ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Handle ++ SYMBOL_TINY_ABSOLUTE. ++ (aarch64_expand_mov_immediate): Likewise. ++ (aarch64_classify_symbol): Likewise. ++ (aarch64_mov_operand_p): Remove ATTRIBUTE_UNUSED. ++ Permit SYMBOL_TINY_ABSOLUTE. ++ * config/aarch64/predicates.md (aarch64_mov_operand): Permit CONST. + -+2013-05-02 Matthew Gretton-Dann ++ 2013-05-29 Chris Schlumberger-Socha ++ Marcus Shawcroft + -+ Backport of trunk r197518-197522,197526-197528. -+ 2013-04-05 Greta Yorsh ++ * config/aarch64/aarch64.c (aarch64_classify_symbol): Remove comment. ++ Refactor if/switch. Replace gcc_assert with if. + -+ * config/arm/arm.md (arm_smax_insn): Convert define_insn into -+ define_insn_and_split. -+ (arm_smin_insn,arm_umaxsi3,arm_uminsi3): Likewise. ++ 2013-05-24 Ian Bolton + -+ 2013-04-05 Greta Yorsh ++ * config/aarch64/aarch64.c (aarch64_print_operand): Change the ++ X format specifier to only display bottom 16 bits. ++ * config/aarch64/aarch64.md (insv_imm): Allow any size of ++ immediate to match for operand 2, since it will be masked. + -+ * config/arm/arm.md (arm_ashldi3_1bit): Convert define_insn into -+ define_insn_and_split. -+ (arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise. -+ (shiftsi3_compare): New pattern. -+ (rrx): New pattern. -+ * config/arm/unspecs.md (UNSPEC_RRX): New. ++ 2013-05-23 Chris Schlumberger-Socha ++ Marcus Shawcroft + -+ 2013-04-05 Greta Yorsh ++ * config/aarch64/aarch64.md (*movdi_aarch64): Replace Usa with S. ++ * config/aarch64/constraints.md (Usa): Remove. ++ * doc/md.texi (AArch64 Usa): Remove. + -+ * config/arm/arm.md (negdi_extendsidi): New pattern. -+ (negdi_zero_extendsidi): Likewise. ++ 2013-05-23 Chris Schlumberger-Socha ++ Marcus Shawcroft + -+ 2013-04-05 Greta Yorsh ++ * config/aarch64/aarch64-protos.h (aarch64_mov_operand_p): Define. ++ * config/aarch64/aarch64.c (aarch64_mov_operand_p): Define. ++ * config/aarch64/predicates.md (aarch64_const_address): Remove. ++ (aarch64_mov_operand): Use aarch64_mov_operand_p. + -+ * config/arm/arm.md (andsi_iorsi3_notsi): Convert define_insn into -+ define_insn_and_split. -+ (arm_negdi2,arm_abssi2,arm_neg_abssi2): Likewise. -+ (arm_cmpdi_insn,arm_cmpdi_unsigned): Likewise. ++ 2013-05-23 Vidya Praveen + -+ 2013-04-05 Greta Yorsh ++ * config/aarch64/aarch64-simd.md (clzv4si2): Support for CLZ ++ instruction (AdvSIMD). ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_builtin_vectorized_function): Handler for BUILT_IN_CLZ. ++ * config/aarch64/aarch-simd-builtins.def: Entry for CLZ. + -+ * config/arm/arm.md (arm_subdi3): Convert define_insn into -+ define_insn_and_split. -+ (subdi_di_zesidi,subdi_di_sesidi): Likewise. -+ (subdi_zesidi_di,subdi_sesidi_di,subdi_zesidi_zesidi): Likewise. ++ 2013-05-14 James Greenhalgh + -+ 2013-04-05 Greta Yorsh ++ * config/aarch64/aarch64-simd.md ++ (aarch64_vcond_internal): Rename to... ++ (aarch64_vcond_internal): ...This, for integer modes. ++ (aarch64_vcond_internal): ...This for ++ float modes. Clarify all iterator modes. ++ (vcond): Use new name for vcond expanders. ++ (vcond): Likewise. ++ (vcondu: Likewise. ++ * config/aarch64/iterators.md (VDQF_COND): New. + -+ * config/arm/arm.md (subsi3_carryin): New pattern. -+ (subsi3_carryin_const): Likewise. -+ (subsi3_carryin_compare,subsi3_carryin_compare_const): Likewise. -+ (subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise. ++2013-05-29 Christophe Lyon + -+ 2013-04-05 Greta Yorsh ++ Backport from trunk r198928,198973,199203. ++ 2013-05-22 Ramana Radhakrishnan + -+ * config/arm/arm.md (incscc,arm_incscc,decscc,arm_decscc): Delete. ++ PR target/19599 ++ PR target/57340 ++ * config/arm/arm.c (any_sibcall_uses_r3): Rename to .. ++ (any_sibcall_could_use_r3): this and handle indirect calls. ++ (arm_get_frame_offsets): Rename use of any_sibcall_uses_r3. + -+ 2013-04-05 Greta Yorsh ++ 2013-05-16 Ramana Radhakrishnan + -+ * config/arm/arm.md (addsi3_carryin_): Set attribute predicable. -+ (addsi3_carryin_alt2_,addsi3_carryin_shift_): Likewise. ++ PR target/19599 ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Add check ++ for NULL decl. + -+2013-05-02 Matthew Gretton-Dann ++ 2013-05-15 Ramana Radhakrishnan + -+ Backport of trunk r197517. -+ 2013-04-05 Kyrylo Tkachov ++ PR target/19599 ++ * config/arm/predicates.md (call_insn_operand): New predicate. ++ * config/arm/constraints.md ("Cs", "Ss"): New constraints. ++ * config/arm/arm.md (*call_insn, *call_value_insn): Match only ++ if insn is not a tail call. ++ (*sibcall_insn, *sibcall_value_insn): Adjust for tailcalling through ++ registers. ++ * config/arm/arm.h (enum reg_class): New caller save register class. ++ (REG_CLASS_NAMES): Likewise. ++ (REG_CLASS_CONTENTS): Likewise. ++ * config/arm/arm.c (arm_function_ok_for_sibcall): Allow tailcalling ++ without decls. + -+ * config/arm/arm.c (arm_expand_builtin): Change fcode -+ type to unsigned int. ++2013-05-28 Christophe Lyon + -+2013-05-02 Matthew Gretton-Dann ++ Backport from trunk r198680. ++ 2013-05-07 Sofiane Naci + -+ Backport of trunk r197513. -+ 2013-04-05 Ramana Radhakrishnan ++ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): call splitter. ++ (aarch64_simd_mov): New expander. ++ (aarch64_simd_mov_to_low): New instruction pattern. ++ (aarch64_simd_mov_to_high): Likewise. ++ (aarch64_simd_mov_from_low): Likewise. ++ (aarch64_simd_mov_from_high): Likewise. ++ (aarch64_dup_lane): Update. ++ (aarch64_dup_lanedi): New instruction pattern. ++ * config/aarch64/aarch64-protos.h (aarch64_split_simd_move): New prototype. ++ * config/aarch64/aarch64.c (aarch64_split_simd_move): New function. + -+ * doc/invoke.texi (ARM Options): Document cortex-a53 support. ++2013-05-28 Christophe Lyon + -+2013-05-02 Matthew Gretton-Dann ++ Backport from trunk r198497-198500. ++ 2013-05-01 James Greenhalgh + -+ Backport of trunk r197489-197491. -+ 2013-04-04 Kyrylo Tkachov ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_gimple_fold_builtin.c): Fold more modes for reduc_splus_. ++ * config/aarch64/aarch64-simd-builtins.def ++ (reduc_splus_): Add new modes. ++ (reduc_uplus_): New. ++ * config/aarch64/aarch64-simd.md (aarch64_addvv4sf): Remove. ++ (reduc_uplus_v4sf): Likewise. ++ (reduc_splus_v4sf): Likewise. ++ (aarch64_addv): Likewise. ++ (reduc_uplus_): Likewise. ++ (reduc_splus_): Likewise. ++ (aarch64_addvv2di): Likewise. ++ (reduc_uplus_v2di): Likewise. ++ (reduc_splus_v2di): Likewise. ++ (aarch64_addvv2si): Likewise. ++ (reduc_uplus_v2si): Likewise. ++ (reduc_splus_v2si): Likewise. ++ (reduc_plus_): New. ++ (reduc_plus_v2di): Likewise. ++ (reduc_plus_v2si): Likewise. ++ (reduc_plus_v4sf): Likewise. ++ (aarch64_addpv4sf): Likewise. ++ * config/aarch64/arm_neon.h ++ (vaddv_<8, 16, 32, 64): Rewrite using builtins. ++ * config/aarch64/iterators.md (unspec): Remove UNSPEC_ADDV, ++ add UNSPEC_SADDV, UNSPEC_UADDV. ++ (SUADDV): New. ++ (sur): Add UNSPEC_SADDV, UNSPEC_UADDV. + -+ * config/arm/arm-protos.h (arm_builtin_vectorized_function): -+ New function prototype. -+ * config/arm/arm.c (TARGET_VECTORIZE_BUILTINS): Define. -+ (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise. -+ (arm_builtin_vectorized_function): New function. ++ 2013-05-01 James Greenhalgh + -+ 2013-04-04 Kyrylo Tkachov ++ * config/aarch64/arm_neon.h ++ (v_<8, 16, 32, 64>): Rewrite using builtins. + -+ * config/arm/arm_neon_builtins.def: New file. -+ * config/arm/arm.c (neon_builtin_data): Move contents to -+ arm_neon_builtins.def. -+ (enum arm_builtins): Include neon builtin definitions. -+ (ARM_BUILTIN_NEON_BASE): Move from enum to macro. -+ * config/arm/t-arm (arm.o): Add dependency on -+ arm_neon_builtins.def. ++ 2013-05-01 James Greenhalgh + -+2013-05-02 Matthew Gretton-Dann ++ * config/aarch64/aarch64-builtins ++ (aarch64_gimple_fold_builtin): Fold reduc__ builtins. + -+ Backport of trunk 196795-196797,196957 -+ 2013-03-19 Ian Bolton ++ 2013-05-01 James Greenhalgh + -+ * config/aarch64/aarch64.md (*sub3_carryin): New pattern. -+ (*subsi3_carryin_uxtw): Likewise. ++ * config/aarch64/aarch64-simd-builtins.def ++ (reduc_smax_): New. ++ (reduc_smin_): Likewise. ++ (reduc_umax_): Likewise. ++ (reduc_umin_): Likewise. ++ (reduc_smax_nan_): Likewise. ++ (reduc_smin_nan_): Likewise. ++ (fmax): Remove. ++ (fmin): Likewise. ++ (smax): Update for V2SF, V4SF and V2DF modes. ++ (smin): Likewise. ++ (smax_nan): New. ++ (smin_nan): Likewise. ++ * config/aarch64/aarch64-simd.md (3): Rename to... ++ (3): ...This, refactor. ++ (s3): New. ++ (3): Likewise. ++ (reduc__): Refactor. ++ (reduc__v4sf): Likewise. ++ (reduc__v2si): Likewise. ++ (aarch64_: Remove. ++ * config/aarch64/arm_neon.h (vmax_f<32,64>): Rewrite to use ++ new builtin names. ++ (vmin_f<32,64>): Likewise. ++ * config/iterators.md (unspec): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. ++ (FMAXMIN): New. ++ (su): Add mappings for smax, smin, umax, umin. ++ (maxmin): New. ++ (FMAXMINV): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. ++ (FMAXMIN): Rename as... ++ (FMAXMIN_UNS): ...This. ++ (maxminv): Remove. ++ (fmaxminv): Likewise. ++ (fmaxmin): Likewise. ++ (maxmin_uns): New. ++ (maxmin_uns_op): Likewise. + -+ 2013-03-19 Ian Bolton ++2013-05-28 Christophe Lyon + -+ * config/aarch64/aarch64.md (*ror3_insn): New pattern. -+ (*rorsi3_insn_uxtw): Likewise. ++ Backport from trunk r199241. ++ 2013-05-23 James Greenhalgh + -+ 2013-03-19 Ian Bolton ++ * config/aarch64/aarch64-simd.md ++ (aarch64_cmdi): Add clobber of CC_REGNUM to unsplit pattern. + -+ * config/aarch64/aarch64.md (*extr5_insn): New pattern. -+ (*extrsi5_insn_uxtw): Likewise. ++2013-05-23 Christophe Lyon + -+2013-04-10 Matthew Gretton-Dann ++ Backport from trunk r198970. ++ 2013-05-16 Greta Yorsh + -+ * LINARO-VERSION: Bump version number. ++ * config/arm/arm-protos.h (gen_movmem_ldrd_strd): New declaration. ++ * config/arm/arm.c (next_consecutive_mem): New function. ++ (gen_movmem_ldrd_strd): Likewise. ++ * config/arm/arm.md (movmemqi): Update condition and code. ++ (unaligned_loaddi, unaligned_storedi): New patterns. + -+2013-04-09 Matthew Gretton-Dann ++2013-05-19 Matthew Gretton-Dann + -+ * GCC Linaro 4.8-2013.04 released. -+ -+ * LINARO-VERSION: New file. -+ * configure.ac: Add Linaro version string. -+ * configure: Regenerate. ++ * LINARO-VERSION: Bump version number. + -+2013-04-08 Matthew Gretton-Dann ++2013-05-14 Matthew Gretton-Dann + -+ Backport of trunk r197346. -+ 2013-04-02 Ian Caulfield -+ Ramana Radhakrishnan ++ GCC Linaro 4.8-2013.05 released. + -+ * config/arm/arm-arches.def (armv8-a): Default to cortex-a53. -+ * config/arm/t-arm (MD_INCLUDES): Depend on cortex-a53.md. -+ * config/arm/cortex-a53.md: New file. -+ * config/arm/bpabi.h (BE8_LINK_SPEC): Handle cortex-a53. -+ * config/arm/arm.md (generic_sched, generic_vfp): Handle cortex-a53. -+ * config/arm/arm.c (arm_issue_rate): Likewise. -+ * config/arm/arm-tune.md: Regenerate -+ * config/arm/arm-tables.opt: Regenerate. -+ * config/arm/arm-cores.def: Add cortex-a53. ++2013-05-14 Matthew Gretton-Dann + -+2013-04-08 Matthew Gretton-Dann ++ Backport from trunk r198677. ++ 2013-05-07 Naveen H.S + -+ Backport of trunk r197342. -+ 2013-04-02 Sofiane Naci ++ * config/aarch64/aarch64.md ++ (cmp_swp__shft_): Restrict the ++ shift value between 0-4. + -+ * config/aarch64/aarch64.md (*mov_aarch64): Add variants for -+ scalar load/store operations using B/H registers. -+ (*zero_extend2_aarch64): Likewise. ++2013-05-14 Matthew Gretton-Dann + -+2013-04-08 Matthew Gretton-Dann ++ Backport from trunk r198574-198575. ++ 2013-05-03 Vidya Praveen + -+ Backport of trunk r197341. -+ 2013-04-02 Sofiane Naci ++ * config/aarch64/aarch64-simd.md (simd_fabd): Correct the description. + -+ * config/aarch64/aarch64.md (*mov_aarch64): Add alternatives for -+ scalar move. -+ * config/aarch64/aarch64.c -+ (aarch64_simd_scalar_immediate_valid_for_move): New. -+ * config/aarch64/aarch64-protos.h -+ (aarch64_simd_scalar_immediate_valid_for_move): New. -+ * config/aarch64/constraints.md (Dh, Dq): New. -+ * config/aarch64/iterators.md (hq): New. ++ 2013-05-03 Vidya Praveen + -+2013-04-08 Matthew Gretton-Dann ++ * config/aarch64/aarch64-simd.md (*fabd_scalar3): Support ++ scalar form of FABD instruction. + -+ Backport from trunk r197207. -+ 2013-03-28 Naveen H.S ++2013-05-14 Matthew Gretton-Dann + -+ * config/aarch64/aarch64.md (*and3_compare0): New pattern. -+ (*andsi3_compare0_uxtw): New pattern. -+ (*and_3_compare0): New pattern. -+ (*and_si3_compare0_uxtw): New pattern. ++ Backport from trunk r198490-198496 ++ 2013-05-01 James Greenhalgh + -+2013-04-08 Matthew Gretton-Dann ++ * config/aarch64/arm_neon.h ++ (vac_f<32, 64>): Rename to... ++ (vca_f<32, 64>): ...this, reimpliment in C. ++ (vca_f<32, 64>): Reimpliment in C. + -+ Backport from trunk r197153. -+ 2013-03-27 Terry Guo ++ 2013-05-01 James Greenhalgh + -+ * config/arm/arm-cores.def: Added core cortex-r7. -+ * config/arm/arm-tune.md: Regenerated. -+ * config/arm/arm-tables.opt: Regenerated. -+ * doc/invoke.texi: Added entry for core cortex-r7. ++ * config/aarch64/aarch64-simd.md (*aarch64_fac): New. ++ * config/aarch64/iterators.md (FAC_COMPARISONS): New. + -+2013-04-08 Matthew Gretton-Dann ++ 2013-05-01 James Greenhalgh + -+ Backport from trunk r197052. -+ 2013-03-25 Kyrylo Tkachov ++ * config/aarch64/aarch64-simd.md ++ (vcond_internal): Handle special cases for constant masks. ++ (vcond): Allow nonmemory_operands for outcome vectors. ++ (vcondu): Likewise. ++ (vcond): New. + -+ * config/arm/arm.md (f_sels, f_seld): New types. -+ (*cmov): New pattern. -+ * config/arm/predicates.md (arm_vsel_comparison_operator): New -+ predicate. ++ 2013-05-01 James Greenhalgh + -+2013-04-08 Matthew Gretton-Dann ++ * config/aarch64/aarch64-builtins.c (BUILTIN_VALLDI): Define. ++ (aarch64_fold_builtin): Add folding for cm. ++ * config/aarch64/aarch64-simd-builtins.def ++ (cmeq): Update to BUILTIN_VALLDI. ++ (cmgt): Likewise. ++ (cmge): Likewise. ++ (cmle): Likewise. ++ (cmlt): Likewise. ++ * config/aarch64/arm_neon.h ++ (vc_<8,16,32,64>): Remap ++ to builtins or C as appropriate. + -+ Backport from trunk r197046. -+ 2013-03-25 Kyrylo Tkachov ++ 2013-05-01 James Greenhalgh + -+ * config/arm/arm.c (arm_emit_load_exclusive): Add acq parameter. -+ Emit load-acquire versions when acq is true. -+ (arm_emit_store_exclusive): Add rel parameter. -+ Emit store-release versions when rel is true. -+ (arm_split_compare_and_swap): Use acquire-release instructions -+ instead. -+ of barriers when appropriate. -+ (arm_split_atomic_op): Likewise. -+ * config/arm/arm.h (TARGET_HAVE_LDACQ): New macro. -+ * config/arm/unspecs.md (VUNSPEC_LAX): New unspec. -+ (VUNSPEC_SLX): Likewise. -+ (VUNSPEC_LDA): Likewise. -+ (VUNSPEC_STL): Likewise. -+ * config/arm/sync.md (atomic_load): New pattern. -+ (atomic_store): Likewise. -+ (arm_load_acquire_exclusive): Likewise. -+ (arm_load_acquire_exclusivesi): Likewise. -+ (arm_load_acquire_exclusivedi): Likewise. -+ (arm_store_release_exclusive): Likewise. ++ * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to... ++ (cmgeu): ...This. ++ (cmhi): Rename to... ++ (cmgtu): ...This. ++ * config/aarch64/aarch64-simd.md ++ (simd_mode): Add SF. ++ (aarch64_vcond_internal): Use new names for unsigned comparison insns. ++ (aarch64_cm): Rewrite to not use UNSPECs. ++ * config/aarch64/aarch64.md (*cstore_neg): Rename to... ++ (cstore_neg): ...This. ++ * config/aarch64/iterators.md ++ (VALLF): new. ++ (unspec): Remove UNSPEC_CM. ++ (COMPARISONS): New. ++ (UCOMPARISONS): Likewise. ++ (optab): Add missing comparisons. ++ (n_optab): New. ++ (cmp_1): Likewise. ++ (cmp_2): Likewise. ++ (CMP): Likewise. ++ (cmp): Remove. ++ (VCMP_S): Likewise. ++ (VCMP_U): Likewise. ++ (V_cmp_result): Add DF, SF modes. ++ (v_cmp_result): Likewise. ++ (v): Likewise. ++ (vmtype): Likewise. ++ * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New. + -+2013-04-08 Matthew Gretton-Dann ++2013-05-14 Matthew Gretton-Dann + -+ Backport from trunk r196876. -+ 2013-03-21 Christophe Lyon ++ Backport from trunk r198191. ++ 2013-04-23 Sofiane Naci + -+ * config/arm/arm-protos.h (tune_params): Add -+ prefer_neon_for_64bits field. -+ * config/arm/arm.c (prefer_neon_for_64bits): New variable. -+ (arm_slowmul_tune): Default prefer_neon_for_64bits to false. -+ (arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune): Ditto. -+ (arm_9e_tune, arm_v6t2_tune, arm_cortex_tune): Ditto. -+ (arm_cortex_a15_tune, arm_cortex_a5_tune): Ditto. -+ (arm_cortex_a9_tune, arm_v6m_tune, arm_fa726te_tune): Ditto. -+ (arm_option_override): Handle -mneon-for-64bits new option. -+ * config/arm/arm.h (TARGET_PREFER_NEON_64BITS): New macro. -+ (prefer_neon_for_64bits): Declare new variable. -+ * config/arm/arm.md (arch): Rename neon_onlya8 and neon_nota8 to -+ avoid_neon_for_64bits and neon_for_64bits. Remove onlya8 and -+ nota8. -+ (arch_enabled): Handle new arch types. Remove support for onlya8 -+ and nota8. -+ (one_cmpldi2): Use new arch names. -+ * config/arm/arm.opt (mneon-for-64bits): Add option. -+ * config/arm/neon.md (adddi3_neon, subdi3_neon, iordi3_neon) -+ (anddi3_neon, xordi3_neon, ashldi3_neon, di3_neon): Use -+ neon_for_64bits instead of nota8 and avoid_neon_for_64bits instead -+ of onlya8. -+ * doc/invoke.texi (-mneon-for-64bits): Document. ++ * config/aarch64/aarch64.md (*mov_aarch64): Add simd attribute. + -+2013-04-08 Matthew Gretton-Dann ++2013-05-14 Matthew Gretton-Dann + -+ Backport from trunk r196858. -+ 2013-03-21 Naveen H.S ++ Backport from trunk r197838. ++ 2013-04-11 Naveen H.S + -+ * config/aarch64/aarch64-simd.md (simd_fabd): New Attribute. -+ (abd_3): New pattern. -+ (aba_3): New pattern. -+ (fabd_3): New pattern. ++ * config/aarch64/aarch64.c (aarch64_select_cc_mode): Allow NEG ++ code in CC_NZ mode. ++ * config/aarch64/aarch64.md (*neg_3_compare0): New ++ pattern. + -+2013-04-08 Matthew Gretton-Dann -+ -+ Backport from trunk r196856. -+ 2013-03-21 Naveen H.S ++2013-05-02 Matthew Gretton-Dann + -+ * config/aarch64/aarch64-elf.h (REGISTER_PREFIX): Remove. -+ * config/aarch64/aarch64.c (aarch64_print_operand): Remove all -+ occurrence of REGISTER_PREFIX as its empty string. ---- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c -@@ -0,0 +1,18 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_neon_ok } */ -+/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ -+/* { dg-add-options arm_v8_neon } */ ++ Backport from trunk r198019. ++ 2013-04-16 Naveen H.S + -+#define N 32 ++ * config/aarch64/aarch64.md (*adds_mul_imm_): New pattern. ++ (*subs_mul_imm_): New pattern. + -+void -+foo (float *output, float *input) -+{ -+ int i = 0; -+ /* Vectorizable. */ -+ for (i = 0; i < N; i++) -+ output[i] = __builtin_floorf (input[i]); -+} ++2013-05-02 Matthew Gretton-Dann + -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_floorf } } } */ -+/* { dg-final { cleanup-tree-dump "vect" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c -+++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c -@@ -0,0 +1,20 @@ -+/* Test the `vcvtf32_f16' ARM Neon intrinsic. */ -+/* This file was autogenerated by neon-testgen. */ ++ Backport from trunk r198424-198425. ++ 2013-04-29 Ian Bolton + -+/* { dg-do assemble } */ -+/* { dg-require-effective-target arm_neon_fp16_ok } */ -+/* { dg-options "-save-temps -O0" } */ -+/* { dg-add-options arm_neon_fp16 } */ ++ * config/aarch64/aarch64.md (movsi_aarch64): Support LDR/STR ++ from/to S register. ++ (movdi_aarch64): Support LDR/STR from/to D register. + -+#include "arm_neon.h" ++ 2013-04-29 Ian Bolton + -+void test_vcvtf32_f16 (void) -+{ -+ float32x4_t out_float32x4_t; -+ float16x4_t arg0_float16x4_t; ++ * common/config/aarch64/aarch64-common.c: Enable REE pass at O2 ++ or higher by default. + -+ out_float32x4_t = vcvt_f32_f16 (arg0_float16x4_t); -+} ++2013-05-02 Matthew Gretton-Dann + -+/* { dg-final { scan-assembler "vcvt\.f32.f16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c -+++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c -@@ -0,0 +1,20 @@ -+/* Test the `vcvtf16_f32' ARM Neon intrinsic. */ -+/* This file was autogenerated by neon-testgen. */ ++ Backport from trunk r198412. ++ 2013-04-29 Kyrylo Tkachov + -+/* { dg-do assemble } */ -+/* { dg-require-effective-target arm_neon_fp16_ok } */ -+/* { dg-options "-save-temps -O0" } */ -+/* { dg-add-options arm_neon_fp16 } */ ++ * config/arm/arm.md (store_minmaxsi): Use only when ++ optimize_insn_for_size_p. + -+#include "arm_neon.h" ++2013-05-02 Matthew Gretton-Dann + -+void test_vcvtf16_f32 (void) -+{ -+ float16x4_t out_float16x4_t; -+ float32x4_t arg0_float32x4_t; ++ Backport from trunk 198394,198396-198400,198402-198404. ++ 2013-04-29 James Greenhalgh + -+ out_float16x4_t = vcvt_f16_f32 (arg0_float32x4_t); -+} ++ * config/aarch64/arm_neon.h ++ (vcvt_f<32,64>_s<32,64>): Rewrite in C. ++ (vcvt_f<32,64>_s<32,64>): Rewrite using builtins. ++ (vcvt__f<32,64>_f<32,64>): Likewise. ++ (vcvt_<32,64>_f<32,64>): Likewise. ++ (vcvta_<32,64>_f<32,64>): Likewise. ++ (vcvtm_<32,64>_f<32,64>): Likewise. ++ (vcvtn_<32,64>_f<32,64>): Likewise. ++ (vcvtp_<32,64>_f<32,64>): Likewise. + -+/* { dg-final { scan-assembler "vcvt\.f16.f32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/arm/anddi3-opt.c -+++ b/src/gcc/testsuite/gcc.target/arm/anddi3-opt.c -@@ -0,0 +1,11 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ ++ 2013-04-29 James Greenhalgh + -+unsigned long long -+muld (unsigned long long X, unsigned long long Y) -+{ -+ unsigned long long mask = 0xffffffffull; -+ return (X & mask) * (Y & mask); -+} ++ * config/aarch64/aarch64-simd.md ++ (2): New, maps to fix, fixuns. ++ (2): New, maps to ++ fix_trunc, fixuns_trunc. ++ (ftrunc2): New. ++ * config/aarch64/iterators.md (optab): Add fix, fixuns. ++ (fix_trunc_optab): New. + -+/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c -+++ b/src/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c -@@ -0,0 +1,11 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_prefer_ldrd_strd } */ -+/* { dg-options "-O2" } */ -+int foo(int a, int b, int* p, int *q) -+{ -+ a = p[2] + p[3]; -+ *q = a; -+ *p = a; -+ return a; -+} -+/* { dg-final { scan-assembler "ldrd" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselgtdf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselgtdf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ 2013-04-29 James Greenhalgh + -+double -+foo (double x, double y) -+{ -+ volatile int i = 0; -+ return i > 0 ? x : y; -+} ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_builtin_vectorized_function): Vectorize over ifloorf, ++ iceilf, lround, iroundf. + -+/* { dg-final { scan-assembler-times "vselgt.f64\td\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++ 2013-04-29 James Greenhalgh + -+#include "../aarch64/atomic-op-relaxed.x" ++ * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi_): New. ++ (float_truncate_hi_): Likewise. ++ (float_extend_lo_): Likewise. ++ (float_truncate_lo_): Likewise. ++ * config/aarch64/aarch64-simd.md (vec_unpacks_lo_v4sf): New. ++ (aarch64_float_extend_lo_v2df): Likewise. ++ (vec_unpacks_hi_v4sf): Likewise. ++ (aarch64_float_truncate_lo_v2sf): Likewise. ++ (aarch64_float_truncate_hi_v4sf): Likewise. ++ (vec_pack_trunc_v2df): Likewise. ++ (vec_pack_trunc_df): Likewise. + -+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselgesf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselgesf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ 2013-04-29 James Greenhalgh + -+float -+foo (float x, float y) -+{ -+ volatile int i = 0; -+ return i >= 0 ? x : y; -+} ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_fold_builtin): Fold float conversions. ++ * config/aarch64/aarch64-simd-builtins.def ++ (floatv2si, floatv4si, floatv2di): New. ++ (floatunsv2si, floatunsv4si, floatunsv2di): Likewise. ++ * config/aarch64/aarch64-simd.md ++ (2): New, expands to float and floatuns. ++ * config/aarch64/iterators.md (FLOATUORS): New. ++ (optab): Add float, floatuns. ++ (su_optab): Likewise. + -+/* { dg-final { scan-assembler-times "vselge.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/peep-strd-1.c -+++ b/src/gcc/testsuite/gcc.target/arm/peep-strd-1.c -@@ -0,0 +1,9 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_prefer_ldrd_strd } */ -+/* { dg-options "-O2" } */ -+void foo(int a, int b, int* p) -+{ -+ p[2] = a; -+ p[3] = b; -+} -+/* { dg-final { scan-assembler "strd" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/negdi-1.c -+++ b/src/gcc/testsuite/gcc.target/arm/negdi-1.c -@@ -0,0 +1,17 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O2" } */ ++ 2013-04-29 James Greenhalgh + -+signed long long extendsidi_negsi (signed int x) -+{ -+ return -x; -+} ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_builtin_vectorized_function): Fold to standard pattern names. ++ * config/aarch64/aarch64-simd-builtins.def (frintn): New. ++ (frintz): Rename to... ++ (btrunc): ...this. ++ (frintp): Rename to... ++ (ceil): ...this. ++ (frintm): Rename to... ++ (floor): ...this. ++ (frinti): Rename to... ++ (nearbyint): ...this. ++ (frintx): Rename to... ++ (rint): ...this. ++ (frinta): Rename to... ++ (round): ...this. ++ * config/aarch64/aarch64-simd.md ++ (aarch64_frint): Delete. ++ (2): Convert to insn. ++ * config/aarch64/aarch64.md (unspec): Add UNSPEC_FRINTN. ++ * config/aarch64/iterators.md (FRINT): Add UNSPEC_FRINTN. ++ (frint_pattern): Likewise. ++ (frint_suffix): Likewise. + -+/* -+Expected output: -+ rsb r0, r0, #0 -+ mov r1, r0, asr #31 -+*/ -+/* { dg-final { scan-assembler-times "rsb" 1 { target { arm_nothumb } } } } */ -+/* { dg-final { scan-assembler-times "negs\\t" 1 { target { ! { arm_nothumb } } } } } */ -+/* { dg-final { scan-assembler-times "asr" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++2013-05-02 Matthew Gretton-Dann + -+#include "../aarch64/atomic-comp-swap-release-acquire.x" ++ Backport from trunk r198302-198306,198316. ++ 2013-04-25 James Greenhalgh + -+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 4 } } */ -+/* { dg-final { scan-assembler-times "stlex" 4 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++ * config/aarch64/aarch64-simd.md ++ (aarch64_simd_bsl_internal): Rewrite RTL to not use UNSPEC_BSL. ++ (aarch64_simd_bsl): Likewise. ++ * config/aarch64/iterators.md (unspec): Remove UNSPEC_BSL. + -+#include "../aarch64/atomic-op-seq_cst.x" ++ 2013-04-25 James Greenhalgh + -+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselgedf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselgedf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ * config/aarch64/aarch64-simd.md (neg2): Use VDQ iterator. + -+double -+foo (double x, double y) -+{ -+ volatile int i = 0; -+ return i >= 0 ? x : y; -+} ++ 2013-04-25 James Greenhalgh + -+/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-consume.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_fold_builtin): New. ++ * config/aarch64/aarch64-protos.h (aarch64_fold_builtin): New. ++ * config/aarch64/aarch64.c (TARGET_FOLD_BUILTIN): Define. ++ * config/aarch64/aarch64-simd-builtins.def (abs): New. ++ * config/aarch64/arm_neon.h ++ (vabs_): Implement using __builtin_aarch64_fabs. + -+#include "../aarch64/atomic-op-consume.x" ++ 2013-04-25 James Greenhalgh ++ Tejas Belagod + -+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-char.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_gimple_fold_builtin): New. ++ * config/aarch64/aarch64-protos.h (aarch64_gimple_fold_builtin): New. ++ * config/aarch64/aarch64-simd-builtins.def (addv): New. ++ * config/aarch64/aarch64-simd.md (addpv4sf): New. ++ (addvv4sf): Update. ++ * config/aarch64/aarch64.c (TARGET_GIMPLE_FOLD_BUILTIN): Define. + -+#include "../aarch64/atomic-op-char.x" ++ 2013-04-25 Naveen H.S + -+/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselnesf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselnesf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ * config/aarch64/aarch64.md ++ (*cmp_swp__shft_): New pattern. + -+float -+foo (float x, float y) -+{ -+ volatile int i = 0; -+ return i != 0 ? x : y; -+} ++ 2013-04-25 Naveen H.S + -+/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/negdi-2.c -+++ b/src/gcc/testsuite/gcc.target/arm/negdi-2.c -@@ -0,0 +1,16 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O2" } */ ++ * config/aarch64/aarch64.md (*ngc): New pattern. ++ (*ngcsi_uxtw): New pattern. + -+signed long long zero_extendsidi_negsi (unsigned int x) -+{ -+ return -x; -+} -+/* -+Expected output: -+ rsb r0, r0, #0 -+ mov r1, #0 -+*/ -+/* { dg-final { scan-assembler-times "rsb\\tr0, r0, #0" 1 { target { arm_nothumb } } } } */ -+/* { dg-final { scan-assembler-times "negs\\tr0, r0" 1 { target { ! arm_nothumb } } } } */ -+/* { dg-final { scan-assembler-times "mov" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselvcsf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselvcsf.c -@@ -0,0 +1,12 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++2013-05-02 Matthew Gretton-Dann + -+float -+foo (float x, float y) -+{ -+ return !__builtin_isunordered (x, y) ? x : y; -+} ++ Backport from trunk 198298. ++ 2013-04-25 Kyrylo Tkachov ++ Julian Brown + -+/* { dg-final { scan-assembler-times "vselvs.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/minmax_minus.c -+++ b/src/gcc/testsuite/gcc.target/arm/minmax_minus.c -@@ -0,0 +1,12 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ ++ * config/arm/arm.c (neon_builtin_type_mode): Add T_V4HF. ++ (TB_DREG): Add T_V4HF. ++ (v4hf_UP): New macro. ++ (neon_itype): Add NEON_FLOAT_WIDEN, NEON_FLOAT_NARROW. ++ (arm_init_neon_builtins): Handle NEON_FLOAT_WIDEN, ++ NEON_FLOAT_NARROW. ++ Handle initialisation of V4HF. Adjust initialisation of reinterpret ++ built-ins. ++ (arm_expand_neon_builtin): Handle NEON_FLOAT_WIDEN, ++ NEON_FLOAT_NARROW. ++ (arm_vector_mode_supported_p): Handle V4HF. ++ (arm_mangle_map): Handle V4HFmode. ++ * config/arm/arm.h (VALID_NEON_DREG_MODE): Add V4HF. ++ * config/arm/arm_neon_builtins.def: Add entries for ++ vcvtv4hfv4sf, vcvtv4sfv4hf. ++ * config/arm/neon.md (neon_vcvtv4sfv4hf): New pattern. ++ (neon_vcvtv4hfv4sf): Likewise. ++ * config/arm/neon-gen.ml: Handle half-precision floating point ++ features. ++ * config/arm/neon-testgen.ml: Handle Requires_FP_bit feature. ++ * config/arm/arm_neon.h: Regenerate. ++ * config/arm/neon.ml (type elts): Add F16. ++ (type vectype): Add T_float16x4, T_floatHF. ++ (type vecmode): Add V4HF. ++ (type features): Add Requires_FP_bit feature. ++ (elt_width): Handle F16. ++ (elt_class): Likewise. ++ (elt_of_class_width): Likewise. ++ (mode_of_elt): Refactor. ++ (type_for_elt): Handle F16, fix error messages. ++ (vectype_size): Handle T_float16x4. ++ (vcvt_sh): New function. ++ (ops): Add entries for vcvt_f16_f32, vcvt_f32_f16. ++ (string_of_vectype): Handle T_floatHF, T_float16, T_float16x4. ++ (string_of_mode): Handle V4HF. ++ * doc/arm-neon-intrinsics.texi: Regenerate. + -+#define MAX(a, b) (a > b ? a : b) -+int -+foo (int a, int b, int c) -+{ -+ return c - MAX (a, b); -+} ++2013-05-02 Matthew Gretton-Dann + -+/* { dg-final { scan-assembler "rsbge" } } */ -+/* { dg-final { scan-assembler "rsblt" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-release.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++ Backport from trunk r198136-198137,198142,198176. ++ 2013-04-23 Andreas Schwab + -+#include "../aarch64/atomic-op-release.x" ++ * coretypes.h (gimple_stmt_iterator): Add struct to make ++ compatible with C. + -+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselvssf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselvssf.c -@@ -0,0 +1,12 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ 2013-04-22 James Greenhalgh + -+float -+foo (float x, float y) -+{ -+ return __builtin_isunordered (x, y) ? x : y; -+} ++ * coretypes.h (gimple_stmt_iterator_d): Forward declare. ++ (gimple_stmt_iterator): New typedef. ++ * gimple.h (gimple_stmt_iterator): Rename to... ++ (gimple_stmt_iterator_d): ... This. ++ * doc/tm.texi.in (TARGET_FOLD_BUILTIN): Detail restriction that ++ trees be valid for GIMPLE and GENERIC. ++ (TARGET_GIMPLE_FOLD_BUILTIN): New. ++ * gimple-fold.c (gimple_fold_call): Call target hook ++ gimple_fold_builtin. ++ * hooks.c (hook_bool_gsiptr_false): New. ++ * hooks.h (hook_bool_gsiptr_false): New. ++ * target.def (fold_stmt): New. ++ * doc/tm.texi: Regenerate. + -+/* { dg-final { scan-assembler-times "vselvs.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c -@@ -0,0 +1,18 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_neon_ok } */ -+/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ -+/* { dg-add-options arm_v8_neon } */ ++ 2013-04-22 James Greenhalgh + -+#define N 32 ++ * config/aarch64/aarch64-builtins.c ++ (CF): Remove. ++ (CF0, CF1, CF2, CF3, CF4, CF10): New. ++ (VAR<1-12>): Add MAP parameter. ++ (BUILTIN_*): Likewise. ++ * config/aarch64/aarch64-simd-builtins.def: Set MAP parameter. ++ * config/aarch64/aarch64-simd.md (aarch64_sshl_n): Remove. ++ (aarch64_ushl_n): Likewise. ++ (aarch64_sshr_n): Likewise. ++ (aarch64_ushr_n): Likewise. ++ (aarch64_): Likewise. ++ (aarch64_sqrt): Likewise. ++ * config/aarch64/arm_neon.h (vshl_n_*): Use new builtin names. ++ (vshr_n_*): Likewise. + -+void -+foo (float *output, float *input) -+{ -+ int i = 0; -+ /* Vectorizable. */ -+ for (i = 0; i < N; i++) -+ output[i] = __builtin_roundf (input[i]); -+} ++ 2013-04-22 James Greenhalgh + -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_roundf } } } */ -+/* { dg-final { cleanup-tree-dump "vect" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c -+++ b/src/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c -@@ -0,0 +1,54 @@ -+/* Check that Neon is *not* used by default to handle 64-bits scalar -+ operations. */ ++ * config/aarch64/aarch64-builtins.c ++ (aarch64_simd_builtin_type_mode): Handle SF types. ++ (sf_UP): Define. ++ (BUILTIN_GPF): Define. ++ (aarch64_init_simd_builtins): Handle SF types. ++ * config/aarch64/aarch64-simd-builtins.def (frecpe): Add support. ++ (frecps): Likewise. ++ (frecpx): Likewise. ++ * config/aarch64/aarch64-simd.md ++ (simd_types): Update simd_frcp to simd_frecp. ++ (aarch64_frecpe): New. ++ (aarch64_frecps): Likewise. ++ * config/aarch64/aarch64.md (unspec): Add UNSPEC_FRECP. ++ (v8type): Add frecp. ++ (aarch64_frecp): New. ++ (aarch64_frecps): Likewise. ++ * config/aarch64/iterators.md (FRECP): New. ++ (frecp_suffix): Likewise. ++ * config/aarch64/arm_neon.h ++ (vrecp_<32, 64>): Convert to using builtins. + -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_neon_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_neon } */ ++2013-05-02 Matthew Gretton-Dann + -+typedef long long i64; -+typedef unsigned long long u64; -+typedef unsigned int u32; -+typedef int i32; ++ Backport from trunk r198030. ++ 2013-04-17 Greta Yorsh + -+/* Unary operators */ -+#define UNARY_OP(name, op) \ -+ void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } ++ * config/arm/arm.md (movsicc_insn): Convert define_insn into ++ define_insn_and_split. ++ (and_scc,ior_scc,negscc): Likewise. ++ (cmpsi2_addneg, subsi3_compare): Convert to named patterns. + -+/* Binary operators */ -+#define BINARY_OP(name, op) \ -+ void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } ++2013-05-02 Matthew Gretton-Dann + -+/* Unsigned shift */ -+#define SHIFT_U(name, op, amount) \ -+ void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } ++ Backport from trunk r198020. ++ 2013-04-16 Naveen H.S + -+/* Signed shift */ -+#define SHIFT_S(name, op, amount) \ -+ void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } ++ * config/aarch64/aarch64.md (*adds__multp2): ++ New pattern. ++ (*subs__multp2): New pattern. ++ (*adds__): New pattern. ++ (*subs__): New pattern. + -+UNARY_OP(not, ~) ++2013-05-02 Matthew Gretton-Dann + -+BINARY_OP(add, +) -+BINARY_OP(sub, -) -+BINARY_OP(and, &) -+BINARY_OP(or, |) -+BINARY_OP(xor, ^) ++ Backport from trunk r198004,198029. ++ 2013-04-17 Greta Yorsh + -+SHIFT_U(right1, >>, 1) -+SHIFT_U(right2, >>, 2) -+SHIFT_U(right5, >>, 5) -+SHIFT_U(rightn, >>, c) ++ * config/arm/arm.c (use_return_insn): Return 0 for targets that ++ can benefit from using a sequence of LDRD instructions in epilogue ++ instead of a single LDM instruction. + -+SHIFT_S(right1, >>, 1) -+SHIFT_S(right2, >>, 2) -+SHIFT_S(right5, >>, 5) -+SHIFT_S(rightn, >>, c) ++ 2013-04-16 Greta Yorsh + -+/* { dg-final {scan-assembler-times "vmvn" 0} } */ -+/* { dg-final {scan-assembler-times "vadd" 0} } */ -+/* { dg-final {scan-assembler-times "vsub" 0} } */ -+/* { dg-final {scan-assembler-times "vand" 0} } */ -+/* { dg-final {scan-assembler-times "vorr" 0} } */ -+/* { dg-final {scan-assembler-times "veor" 0} } */ -+/* { dg-final {scan-assembler-times "vshr" 0} } */ ---- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c -+++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c -@@ -4,7 +4,7 @@ - - #include - --char dest[16]; -+char dest[16] = { 0 }; - - void aligned_dest (char *src) - { -@@ -14,7 +14,10 @@ - /* Expect a multi-word store for the main part of the copy, but subword - loads/stores for the remainder. */ - --/* { dg-final { scan-assembler-times "stmia" 1 } } */ -+/* { dg-final { scan-assembler-times "ldmia" 0 } } */ -+/* { dg-final { scan-assembler-times "ldrd" 0 } } */ -+/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ -+/* { dg-final { scan-assembler-times "strd" 1 { target { arm_prefer_ldrd_strd } } } } */ - /* { dg-final { scan-assembler-times "ldrh" 1 } } */ - /* { dg-final { scan-assembler-times "strh" 1 } } */ - /* { dg-final { scan-assembler-times "ldrb" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/negdi-3.c -+++ b/src/gcc/testsuite/gcc.target/arm/negdi-3.c -@@ -0,0 +1,17 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O2" } */ ++ * config/arm/arm.c (emit_multi_reg_push): New declaration ++ for an existing function. ++ (arm_emit_strd_push): New function. ++ (arm_expand_prologue): Used here. ++ (arm_emit_ldrd_pop): New function. ++ (arm_expand_epilogue): Used here. ++ (arm_get_frame_offsets): Update condition. ++ (arm_emit_multi_reg_pop): Add a special case for load of a single ++ register with writeback. + -+signed long long negdi_zero_extendsidi (unsigned int x) -+{ -+ return -((signed long long) x); -+} -+/* -+Expected output: -+ rsbs r0, r0, #0 -+ sbc r1, r1, r1 -+*/ -+/* { dg-final { scan-assembler-times "rsb" 1 } } */ -+/* { dg-final { scan-assembler-times "sbc" 1 } } */ -+/* { dg-final { scan-assembler-times "mov" 0 } } */ -+/* { dg-final { scan-assembler-times "rsc" 0 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++2013-05-02 Matthew Gretton-Dann + -+#include "../aarch64/atomic-op-acq_rel.x" ++ Backport from trunk r197965. ++ 2013-04-15 Kyrylo Tkachov + -+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselltsf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselltsf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ * config/arm/arm.c (const_ok_for_dimode_op): Handle AND case. ++ * config/arm/arm.md (*anddi3_insn): Change to insn_and_split. ++ * config/arm/constraints.md (De): New constraint. ++ * config/arm/neon.md (anddi3_neon): Delete. ++ (neon_vand): Expand to standard anddi3 pattern. ++ * config/arm/predicates.md (imm_for_neon_inv_logic_operand): ++ Move earlier in the file. ++ (neon_inv_logic_op2): Likewise. ++ (arm_anddi_operand_neon): New predicate. + -+float -+foo (float x, float y) -+{ -+ volatile int i = 0; -+ return i < 0 ? x : y; -+} ++2013-05-02 Matthew Gretton-Dann + -+/* { dg-final { scan-assembler-times "vselge.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselnedf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselnedf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ Backport from trunk r197925. ++ 2013-04-12 Greta Yorsh + -+double -+foo (double x, double y) -+{ -+ volatile int i = 0; -+ return i != 0 ? x : y; -+} ++ * config/arm/arm.md (mov_scc,mov_negscc,mov_notscc): Convert ++ define_insn into define_insn_and_split and emit movsicc patterns. + -+/* { dg-final { scan-assembler-times "vseleq.f64\td\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselvcdf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselvcdf.c -@@ -0,0 +1,12 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++2013-05-02 Matthew Gretton-Dann + -+double -+foo (double x, double y) -+{ -+ return !__builtin_isunordered (x, y) ? x : y; -+} ++ Backport from trunk r197807. ++ 2013-04-11 Naveen H.S + -+/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c -@@ -0,0 +1,18 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_neon_ok } */ -+/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ -+/* { dg-add-options arm_v8_neon } */ ++ * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Define. + -+#define N 32 ++2013-05-02 Matthew Gretton-Dann + -+void -+foo (float *output, float *input) -+{ -+ int i = 0; -+ /* Vectorizable. */ -+ for (i = 0; i < N; i++) -+ output[i] = __builtin_truncf (input[i]); -+} ++ Backport from trunk r197642. ++ 2013-04-09 Kyrylo Tkachov + -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_btruncf } } } */ -+/* { dg-final { cleanup-tree-dump "vect" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vseleqsf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vseleqsf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ * config/arm/arm.md (minmax_arithsi_non_canon): New pattern. + -+float -+foo (float x, float y) -+{ -+ volatile int i = 0; -+ return i == 0 ? x : y; -+} ++2013-05-02 Matthew Gretton-Dann + -+/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c -+++ b/src/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c -@@ -0,0 +1,57 @@ -+/* Check that Neon is used to handle 64-bits scalar operations. */ ++ Backport from trunk r197530,197921. ++ 2013-04-12 Greta Yorsh + -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_neon_ok } */ -+/* { dg-options "-O2 -mneon-for-64bits" } */ -+/* { dg-add-options arm_neon } */ ++ * config/arm/arm.c (gen_operands_ldrd_strd): Initialize "base". + -+typedef long long i64; -+typedef unsigned long long u64; -+typedef unsigned int u32; -+typedef int i32; ++ 2013-04-05 Greta Yorsh + -+/* Unary operators */ -+#define UNARY_OP(name, op) \ -+ void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } ++ * config/arm/constraints.md (q): New constraint. ++ * config/arm/ldrdstrd.md: New file. ++ * config/arm/arm.md (ldrdstrd.md) New include. ++ (arm_movdi): Use "q" instead of "r" constraint ++ for double-word memory access. ++ (movdf_soft_insn): Likewise. ++ * config/arm/vfp.md (movdi_vfp): Likewise. ++ * config/arm/t-arm (MD_INCLUDES): Add ldrdstrd.md. ++ * config/arm/arm-protos.h (gen_operands_ldrd_strd): New declaration. ++ * config/arm/arm.c (gen_operands_ldrd_strd): New function. ++ (mem_ok_for_ldrd_strd): Likewise. ++ (output_move_double): Update assertion. + -+/* Binary operators */ -+#define BINARY_OP(name, op) \ -+ void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } ++2013-05-02 Matthew Gretton-Dann + -+/* Unsigned shift */ -+#define SHIFT_U(name, op, amount) \ -+ void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } ++ Backport of trunk r197518-197522,197526-197528. ++ 2013-04-05 Greta Yorsh + -+/* Signed shift */ -+#define SHIFT_S(name, op, amount) \ -+ void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } ++ * config/arm/arm.md (arm_smax_insn): Convert define_insn into ++ define_insn_and_split. ++ (arm_smin_insn,arm_umaxsi3,arm_uminsi3): Likewise. + -+UNARY_OP(not, ~) ++ 2013-04-05 Greta Yorsh + -+BINARY_OP(add, +) -+BINARY_OP(sub, -) -+BINARY_OP(and, &) -+BINARY_OP(or, |) -+BINARY_OP(xor, ^) ++ * config/arm/arm.md (arm_ashldi3_1bit): Convert define_insn into ++ define_insn_and_split. ++ (arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise. ++ (shiftsi3_compare): New pattern. ++ (rrx): New pattern. ++ * config/arm/unspecs.md (UNSPEC_RRX): New. + -+SHIFT_U(right1, >>, 1) -+SHIFT_U(right2, >>, 2) -+SHIFT_U(right5, >>, 5) -+SHIFT_U(rightn, >>, c) ++ 2013-04-05 Greta Yorsh + -+SHIFT_S(right1, >>, 1) -+SHIFT_S(right2, >>, 2) -+SHIFT_S(right5, >>, 5) -+SHIFT_S(rightn, >>, c) ++ * config/arm/arm.md (negdi_extendsidi): New pattern. ++ (negdi_zero_extendsidi): Likewise. + -+/* { dg-final {scan-assembler-times "vmvn" 1} } */ -+/* Two vadd: 1 in unary_not, 1 in binary_add */ -+/* { dg-final {scan-assembler-times "vadd" 2} } */ -+/* { dg-final {scan-assembler-times "vsub" 1} } */ -+/* { dg-final {scan-assembler-times "vand" 1} } */ -+/* { dg-final {scan-assembler-times "vorr" 1} } */ -+/* { dg-final {scan-assembler-times "veor" 1} } */ -+/* 6 vshr for right shifts by constant, and variable right shift uses -+ vshl with a negative amount in register. */ -+/* { dg-final {scan-assembler-times "vshr" 6} } */ -+/* { dg-final {scan-assembler-times "vshl" 2} } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselvsdf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselvsdf.c -@@ -0,0 +1,12 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ 2013-04-05 Greta Yorsh + -+double -+foo (double x, double y) -+{ -+ return __builtin_isunordered (x, y) ? x : y; -+} ++ * config/arm/arm.md (andsi_iorsi3_notsi): Convert define_insn into ++ define_insn_and_split. ++ (arm_negdi2,arm_abssi2,arm_neg_abssi2): Likewise. ++ (arm_cmpdi_insn,arm_cmpdi_unsigned): Likewise. + -+/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c -+++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c -@@ -4,7 +4,7 @@ - - #include - --char src[16]; -+char src[16] = {0}; - - void aligned_src (char *dest) - { -@@ -14,8 +14,11 @@ - /* Expect a multi-word load for the main part of the copy, but subword - loads/stores for the remainder. */ - --/* { dg-final { scan-assembler-times "ldmia" 1 } } */ --/* { dg-final { scan-assembler-times "ldrh" 1 } } */ -+/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ -+/* { dg-final { scan-assembler-times "ldrd" 1 { target { arm_prefer_ldrd_strd } } } } */ -+/* { dg-final { scan-assembler-times "strd" 0 } } */ -+/* { dg-final { scan-assembler-times "stm" 0 } } */ -+/* { dg-final { scan-assembler-times "ldrh" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ - /* { dg-final { scan-assembler-times "strh" 1 } } */ --/* { dg-final { scan-assembler-times "ldrb" 1 } } */ -+/* { dg-final { scan-assembler-times "ldrb" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ - /* { dg-final { scan-assembler-times "strb" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/anddi3-opt2.c -+++ b/src/gcc/testsuite/gcc.target/arm/anddi3-opt2.c -@@ -0,0 +1,9 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O1" } */ ++ 2013-04-05 Greta Yorsh + -+long long muld(long long X, long long Y) -+{ -+ return X & ~1; -+} ++ * config/arm/arm.md (arm_subdi3): Convert define_insn into ++ define_insn_and_split. ++ (subdi_di_zesidi,subdi_di_sesidi): Likewise. ++ (subdi_zesidi_di,subdi_sesidi_di,subdi_zesidi_zesidi): Likewise. + -+/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/negdi-4.c -+++ b/src/gcc/testsuite/gcc.target/arm/negdi-4.c -@@ -0,0 +1,16 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm32 } */ -+/* { dg-options "-O2" } */ ++ 2013-04-05 Greta Yorsh + -+signed long long negdi_extendsidi (signed int x) -+{ -+ return -((signed long long) x); -+} -+/* -+Expected output: -+ rsbs r0, r0, #0 -+ mov r1, r0, asr #31 -+*/ -+/* { dg-final { scan-assembler-times "rsb" 1 } } */ -+/* { dg-final { scan-assembler-times "asr" 1 } } */ -+/* { dg-final { scan-assembler-times "rsc" 0 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselltdf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselltdf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ * config/arm/arm.md (subsi3_carryin): New pattern. ++ (subsi3_carryin_const): Likewise. ++ (subsi3_carryin_compare,subsi3_carryin_compare_const): Likewise. ++ (subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise. + -+double -+foo (double x, double y) -+{ -+ volatile int i = 0; -+ return i < 0 ? x : y; -+} ++ 2013-04-05 Greta Yorsh + -+/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c -+++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c -@@ -4,8 +4,8 @@ - - #include - --char src[16]; --char dest[16]; -+char src[16] = { 0 }; -+char dest[16] = { 0 }; - - void aligned_both (void) - { -@@ -14,5 +14,9 @@ - - /* We know both src and dest to be aligned: expect multiword loads/stores. */ - --/* { dg-final { scan-assembler-times "ldmia" 1 } } */ --/* { dg-final { scan-assembler-times "stmia" 1 } } */ -+/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ -+/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ -+/* { dg-final { scan-assembler "ldrd" { target { arm_prefer_ldrd_strd } } } } */ -+/* { dg-final { scan-assembler-times "ldm" 0 { target { arm_prefer_ldrd_strd } } } } */ -+/* { dg-final { scan-assembler "strd" { target { arm_prefer_ldrd_strd } } } } */ -+/* { dg-final { scan-assembler-times "stm" 0 { target { arm_prefer_ldrd_strd } } } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vseleqdf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vseleqdf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ * config/arm/arm.md (incscc,arm_incscc,decscc,arm_decscc): Delete. + -+double -+foo (double x, double y) -+{ -+ volatile int i = 0; -+ return i == 0 ? x : y; -+} ++ 2013-04-05 Greta Yorsh + -+/* { dg-final { scan-assembler-times "vseleq.f64\td\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++ * config/arm/arm.md (addsi3_carryin_): Set attribute predicable. ++ (addsi3_carryin_alt2_,addsi3_carryin_shift_): Likewise. + -+#include "../aarch64/atomic-op-acquire.x" ++2013-05-02 Matthew Gretton-Dann + -+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vsellesf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vsellesf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ Backport of trunk r197517. ++ 2013-04-05 Kyrylo Tkachov + -+float -+foo (float x, float y) -+{ -+ volatile int i = 0; -+ return i <= 0 ? x : y; -+} ++ * config/arm/arm.c (arm_expand_builtin): Change fcode ++ type to unsigned int. + -+/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++2013-05-02 Matthew Gretton-Dann + -+#include "../aarch64/atomic-op-int.x" ++ Backport of trunk r197513. ++ 2013-04-05 Ramana Radhakrishnan + -+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/atomic-op-short.c -+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short.c -@@ -0,0 +1,10 @@ -+/* { dg-require-effective-target arm_arch_v8a_ok } */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_arch_v8a } */ ++ * doc/invoke.texi (ARM Options): Document cortex-a53 support. + -+#include "../aarch64/atomic-op-short.x" ++2013-05-02 Matthew Gretton-Dann + -+/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ -+/* { dg-final { scan-assembler-not "dmb" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c -@@ -0,0 +1,18 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_neon_ok } */ -+/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ -+/* { dg-add-options arm_v8_neon } */ -+ -+#define N 32 -+ -+void -+foo (float *output, float *input) -+{ -+ int i = 0; -+ /* Vectorizable. */ -+ for (i = 0; i < N; i++) -+ output[i] = __builtin_ceilf (input[i]); -+} ++ Backport of trunk r197489-197491. ++ 2013-04-04 Kyrylo Tkachov + -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_ceilf } } } */ -+/* { dg-final { cleanup-tree-dump "vect" } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselledf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselledf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ * config/arm/arm-protos.h (arm_builtin_vectorized_function): ++ New function prototype. ++ * config/arm/arm.c (TARGET_VECTORIZE_BUILTINS): Define. ++ (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Likewise. ++ (arm_builtin_vectorized_function): New function. + -+double -+foo (double x, double y) -+{ -+ volatile int i = 0; -+ return i <= 0 ? x : y; -+} ++ 2013-04-04 Kyrylo Tkachov + -+/* { dg-final { scan-assembler-times "vselgt.f64\td\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/arm/vselgtsf.c -+++ b/src/gcc/testsuite/gcc.target/arm/vselgtsf.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_v8_vfp_ok } */ -+/* { dg-options "-O2" } */ -+/* { dg-add-options arm_v8_vfp } */ ++ * config/arm/arm_neon_builtins.def: New file. ++ * config/arm/arm.c (neon_builtin_data): Move contents to ++ arm_neon_builtins.def. ++ (enum arm_builtins): Include neon builtin definitions. ++ (ARM_BUILTIN_NEON_BASE): Move from enum to macro. ++ * config/arm/t-arm (arm.o): Add dependency on ++ arm_neon_builtins.def. + -+float -+foo (float x, float y) -+{ -+ volatile int i = 0; -+ return i > 0 ? x : y; -+} ++2013-05-02 Matthew Gretton-Dann + -+/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vrecps.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vrecps.c -@@ -0,0 +1,144 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 --save-temps" } */ ++ Backport of trunk 196795-196797,196957 ++ 2013-03-19 Ian Bolton + -+#include -+#include -+#include ++ * config/aarch64/aarch64.md (*sub3_carryin): New pattern. ++ (*subsi3_carryin_uxtw): Likewise. + -+int -+test_frecps_float32_t (void) -+{ -+ int i; -+ float32_t value = 0.2; -+ float32_t reciprocal = 5.0; -+ float32_t step = vrecpes_f32 (value); -+ /* 3 steps should give us within ~0.001 accuracy. */ -+ for (i = 0; i < 3; i++) -+ step = step * vrecpss_f32 (step, value); ++ 2013-03-19 Ian Bolton + -+ return fabs (step - reciprocal) < 0.001; -+} ++ * config/aarch64/aarch64.md (*ror3_insn): New pattern. ++ (*rorsi3_insn_uxtw): Likewise. + -+/* { dg-final { scan-assembler "frecpe\\ts\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "frecps\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ ++ 2013-03-19 Ian Bolton + -+int -+test_frecps_float32x2_t (void) -+{ -+ int i; -+ int ret = 1; ++ * config/aarch64/aarch64.md (*extr5_insn): New pattern. ++ (*extrsi5_insn_uxtw): Likewise. + -+ const float32_t value_pool[] = {0.2, 0.4}; -+ const float32_t reciprocal_pool[] = {5.0, 2.5}; -+ float32x2_t value = vld1_f32 (value_pool); -+ float32x2_t reciprocal = vld1_f32 (reciprocal_pool); ++2013-04-10 Matthew Gretton-Dann + -+ float32x2_t step = vrecpe_f32 (value); -+ /* 3 steps should give us within ~0.001 accuracy. */ -+ for (i = 0; i < 3; i++) -+ step = step * vrecps_f32 (step, value); ++ * LINARO-VERSION: Bump version number. + -+ ret &= fabs (vget_lane_f32 (step, 0) -+ - vget_lane_f32 (reciprocal, 0)) < 0.001; -+ ret &= fabs (vget_lane_f32 (step, 1) -+ - vget_lane_f32 (reciprocal, 1)) < 0.001; ++2013-04-09 Matthew Gretton-Dann + -+ return ret; -+} ++ * GCC Linaro 4.8-2013.04 released. ++ ++ * LINARO-VERSION: New file. ++ * configure.ac: Add Linaro version string. ++ * configure: Regenerate. + -+/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.2s, v\[0-9\]+.2s" } } */ -+/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.2s, v\[0-9\]+.2s, v\[0-9\]+.2s" } } */ ++2013-04-08 Matthew Gretton-Dann + -+int -+test_frecps_float32x4_t (void) -+{ -+ int i; -+ int ret = 1; ++ Backport of trunk r197346. ++ 2013-04-02 Ian Caulfield ++ Ramana Radhakrishnan + -+ const float32_t value_pool[] = {0.2, 0.4, 0.5, 0.8}; -+ const float32_t reciprocal_pool[] = {5.0, 2.5, 2.0, 1.25}; -+ float32x4_t value = vld1q_f32 (value_pool); -+ float32x4_t reciprocal = vld1q_f32 (reciprocal_pool); ++ * config/arm/arm-arches.def (armv8-a): Default to cortex-a53. ++ * config/arm/t-arm (MD_INCLUDES): Depend on cortex-a53.md. ++ * config/arm/cortex-a53.md: New file. ++ * config/arm/bpabi.h (BE8_LINK_SPEC): Handle cortex-a53. ++ * config/arm/arm.md (generic_sched, generic_vfp): Handle cortex-a53. ++ * config/arm/arm.c (arm_issue_rate): Likewise. ++ * config/arm/arm-tune.md: Regenerate ++ * config/arm/arm-tables.opt: Regenerate. ++ * config/arm/arm-cores.def: Add cortex-a53. + -+ float32x4_t step = vrecpeq_f32 (value); -+ /* 3 steps should give us within ~0.001 accuracy. */ -+ for (i = 0; i < 3; i++) -+ step = step * vrecpsq_f32 (step, value); ++2013-04-08 Matthew Gretton-Dann + -+ ret &= fabs (vgetq_lane_f32 (step, 0) -+ - vgetq_lane_f32 (reciprocal, 0)) < 0.001; -+ ret &= fabs (vgetq_lane_f32 (step, 1) -+ - vgetq_lane_f32 (reciprocal, 1)) < 0.001; -+ ret &= fabs (vgetq_lane_f32 (step, 2) -+ - vgetq_lane_f32 (reciprocal, 2)) < 0.001; -+ ret &= fabs (vgetq_lane_f32 (step, 3) -+ - vgetq_lane_f32 (reciprocal, 3)) < 0.001; ++ Backport of trunk r197342. ++ 2013-04-02 Sofiane Naci + -+ return ret; -+} ++ * config/aarch64/aarch64.md (*mov_aarch64): Add variants for ++ scalar load/store operations using B/H registers. ++ (*zero_extend2_aarch64): Likewise. + -+/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.4s, v\[0-9\]+.4s" } } */ -+/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.4s, v\[0-9\]+.4s, v\[0-9\]+.4s" } } */ ++2013-04-08 Matthew Gretton-Dann + -+int -+test_frecps_float64_t (void) -+{ -+ int i; -+ float64_t value = 0.2; -+ float64_t reciprocal = 5.0; -+ float64_t step = vrecped_f64 (value); -+ /* 3 steps should give us within ~0.001 accuracy. */ -+ for (i = 0; i < 3; i++) -+ step = step * vrecpsd_f64 (step, value); ++ Backport of trunk r197341. ++ 2013-04-02 Sofiane Naci + -+ return fabs (step - reciprocal) < 0.001; -+} ++ * config/aarch64/aarch64.md (*mov_aarch64): Add alternatives for ++ scalar move. ++ * config/aarch64/aarch64.c ++ (aarch64_simd_scalar_immediate_valid_for_move): New. ++ * config/aarch64/aarch64-protos.h ++ (aarch64_simd_scalar_immediate_valid_for_move): New. ++ * config/aarch64/constraints.md (Dh, Dq): New. ++ * config/aarch64/iterators.md (hq): New. + -+/* { dg-final { scan-assembler "frecpe\\td\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "frecps\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ ++2013-04-08 Matthew Gretton-Dann + -+int -+test_frecps_float64x2_t (void) -+{ -+ int i; -+ int ret = 1; ++ Backport from trunk r197207. ++ 2013-03-28 Naveen H.S + -+ const float64_t value_pool[] = {0.2, 0.4}; -+ const float64_t reciprocal_pool[] = {5.0, 2.5}; -+ float64x2_t value = vld1q_f64 (value_pool); -+ float64x2_t reciprocal = vld1q_f64 (reciprocal_pool); ++ * config/aarch64/aarch64.md (*and3_compare0): New pattern. ++ (*andsi3_compare0_uxtw): New pattern. ++ (*and_3_compare0): New pattern. ++ (*and_si3_compare0_uxtw): New pattern. + -+ float64x2_t step = vrecpeq_f64 (value); -+ /* 3 steps should give us within ~0.001 accuracy. */ -+ for (i = 0; i < 3; i++) -+ step = step * vrecpsq_f64 (step, value); ++2013-04-08 Matthew Gretton-Dann + -+ ret &= fabs (vgetq_lane_f64 (step, 0) -+ - vgetq_lane_f64 (reciprocal, 0)) < 0.001; -+ ret &= fabs (vgetq_lane_f64 (step, 1) -+ - vgetq_lane_f64 (reciprocal, 1)) < 0.001; ++ Backport from trunk r197153. ++ 2013-03-27 Terry Guo + -+ return ret; -+} ++ * config/arm/arm-cores.def: Added core cortex-r7. ++ * config/arm/arm-tune.md: Regenerated. ++ * config/arm/arm-tables.opt: Regenerated. ++ * doc/invoke.texi: Added entry for core cortex-r7. + -+/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.2d, v\[0-9\]+.2d" } } */ -+/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.2d, v\[0-9\]+.2d, v\[0-9\]+.2d" } } */ ++2013-04-08 Matthew Gretton-Dann + -+int -+main (int argc, char **argv) -+{ -+ if (!test_frecps_float32_t ()) -+ abort (); -+ if (!test_frecps_float32x2_t ()) -+ abort (); -+ if (!test_frecps_float32x4_t ()) -+ abort (); -+ if (!test_frecps_float64_t ()) -+ abort (); -+ if (!test_frecps_float64x2_t ()) -+ abort (); ++ Backport from trunk r197052. ++ 2013-03-25 Kyrylo Tkachov + -+ return 0; -+} ++ * config/arm/arm.md (f_sels, f_seld): New types. ++ (*cmov): New pattern. ++ * config/arm/predicates.md (arm_vsel_comparison_operator): New ++ predicate. + -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/scalar-vca.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar-vca.c -@@ -0,0 +1,72 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 --save-temps" } */ ++2013-04-08 Matthew Gretton-Dann + -+#include ++ Backport from trunk r197046. ++ 2013-03-25 Kyrylo Tkachov + -+extern void abort (void); -+extern float fabsf (float); -+extern double fabs (double); ++ * config/arm/arm.c (arm_emit_load_exclusive): Add acq parameter. ++ Emit load-acquire versions when acq is true. ++ (arm_emit_store_exclusive): Add rel parameter. ++ Emit store-release versions when rel is true. ++ (arm_split_compare_and_swap): Use acquire-release instructions ++ instead. ++ of barriers when appropriate. ++ (arm_split_atomic_op): Likewise. ++ * config/arm/arm.h (TARGET_HAVE_LDACQ): New macro. ++ * config/arm/unspecs.md (VUNSPEC_LAX): New unspec. ++ (VUNSPEC_SLX): Likewise. ++ (VUNSPEC_LDA): Likewise. ++ (VUNSPEC_STL): Likewise. ++ * config/arm/sync.md (atomic_load): New pattern. ++ (atomic_store): Likewise. ++ (arm_load_acquire_exclusive): Likewise. ++ (arm_load_acquire_exclusivesi): Likewise. ++ (arm_load_acquire_exclusivedi): Likewise. ++ (arm_store_release_exclusive): Likewise. + -+#define NUM_TESTS 8 ++2013-04-08 Matthew Gretton-Dann + -+float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f}; -+float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f}; -+double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5}; -+double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5}; ++ Backport from trunk r196876. ++ 2013-03-21 Christophe Lyon + -+#define TEST(TEST, CMP, SUFFIX, WIDTH, F) \ -+int \ -+test_fca##TEST##SUFFIX##_float##WIDTH##_t (void) \ -+{ \ -+ int ret = 0; \ -+ int i = 0; \ -+ uint##WIDTH##_t output[NUM_TESTS]; \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ { \ -+ float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]); \ -+ float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]); \ -+ /* Inhibit optimization of our linear test loop. */ \ -+ asm volatile ("" : : : "memory"); \ -+ output[i] = f1 CMP f2 ? -1 : 0; \ -+ } \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ { \ -+ output[i] = vca##TEST##SUFFIX##_f##WIDTH (input_##SUFFIX##1[i], \ -+ input_##SUFFIX##2[i]) \ -+ ^ output[i]; \ -+ /* Inhibit autovectorization of our scalar test loop. */ \ -+ asm volatile ("" : : : "memory"); \ -+ } \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ ret |= output[i]; \ -+ \ -+ return ret; \ -+} ++ * config/arm/arm-protos.h (tune_params): Add ++ prefer_neon_for_64bits field. ++ * config/arm/arm.c (prefer_neon_for_64bits): New variable. ++ (arm_slowmul_tune): Default prefer_neon_for_64bits to false. ++ (arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune): Ditto. ++ (arm_9e_tune, arm_v6t2_tune, arm_cortex_tune): Ditto. ++ (arm_cortex_a15_tune, arm_cortex_a5_tune): Ditto. ++ (arm_cortex_a9_tune, arm_v6m_tune, arm_fa726te_tune): Ditto. ++ (arm_option_override): Handle -mneon-for-64bits new option. ++ * config/arm/arm.h (TARGET_PREFER_NEON_64BITS): New macro. ++ (prefer_neon_for_64bits): Declare new variable. ++ * config/arm/arm.md (arch): Rename neon_onlya8 and neon_nota8 to ++ avoid_neon_for_64bits and neon_for_64bits. Remove onlya8 and ++ nota8. ++ (arch_enabled): Handle new arch types. Remove support for onlya8 ++ and nota8. ++ (one_cmpldi2): Use new arch names. ++ * config/arm/arm.opt (mneon-for-64bits): Add option. ++ * config/arm/neon.md (adddi3_neon, subdi3_neon, iordi3_neon) ++ (anddi3_neon, xordi3_neon, ashldi3_neon, di3_neon): Use ++ neon_for_64bits instead of nota8 and avoid_neon_for_64bits instead ++ of onlya8. ++ * doc/invoke.texi (-mneon-for-64bits): Document. + -+TEST (ge, >=, s, 32, f) -+/* { dg-final { scan-assembler "facge\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ -+TEST (ge, >=, d, 64, ) -+/* { dg-final { scan-assembler "facge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ -+TEST (gt, >, s, 32, f) -+/* { dg-final { scan-assembler "facgt\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ -+TEST (gt, >, d, 64, ) -+/* { dg-final { scan-assembler "facgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ ++2013-04-08 Matthew Gretton-Dann + -+int -+main (int argc, char **argv) -+{ -+ if (test_fcages_float32_t ()) -+ abort (); -+ if (test_fcaged_float64_t ()) -+ abort (); -+ if (test_fcagts_float32_t ()) -+ abort (); -+ if (test_fcagtd_float64_t ()) -+ abort (); -+ return 0; -+} ++ Backport from trunk r196858. ++ 2013-03-21 Naveen H.S + -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x -@@ -0,0 +1,37 @@ -+int v = 0; ++ * config/aarch64/aarch64-simd.md (simd_fabd): New Attribute. ++ (abd_3): New pattern. ++ (aba_3): New pattern. ++ (fabd_3): New pattern. + -+int -+atomic_fetch_add_ACQ_REL (int a) -+{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL); -+} ++2013-04-08 Matthew Gretton-Dann + -+int -+atomic_fetch_sub_ACQ_REL (int a) -+{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL); -+} ++ Backport from trunk r196856. ++ 2013-03-21 Naveen H.S + -+int -+atomic_fetch_and_ACQ_REL (int a) -+{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL); -+} ++ * config/aarch64/aarch64-elf.h (REGISTER_PREFIX): Remove. ++ * config/aarch64/aarch64.c (aarch64_print_operand): Remove all ++ occurrence of REGISTER_PREFIX as its empty string. +--- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_neon_ok } */ ++/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ ++/* { dg-add-options arm_v8_neon } */ + -+int -+atomic_fetch_nand_ACQ_REL (int a) -+{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL); -+} ++#define N 32 + -+int -+atomic_fetch_xor_ACQ_REL (int a) ++void ++foo (float *output, float *input) +{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL); ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = __builtin_floorf (input[i]); +} + -+int -+atomic_fetch_or_ACQ_REL (int a) -+{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); -+} ---- a/src/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c -@@ -0,0 +1,325 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model" } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_floorf } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c +@@ -0,0 +1,20 @@ ++/* Test the `vcvtf32_f16' ARM Neon intrinsic. */ ++/* This file was autogenerated by neon-testgen. */ + -+typedef signed char S8_t; -+typedef signed short S16_t; -+typedef signed int S32_t; -+typedef signed long S64_t; -+typedef signed char *__restrict__ pS8_t; -+typedef signed short *__restrict__ pS16_t; -+typedef signed int *__restrict__ pS32_t; -+typedef signed long *__restrict__ pS64_t; -+typedef unsigned char U8_t; -+typedef unsigned short U16_t; -+typedef unsigned int U32_t; -+typedef unsigned long U64_t; -+typedef unsigned char *__restrict__ pU8_t; -+typedef unsigned short *__restrict__ pU16_t; -+typedef unsigned int *__restrict__ pU32_t; -+typedef unsigned long *__restrict__ pU64_t; ++/* { dg-do assemble } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon_fp16 } */ + -+extern void abort (); ++#include "arm_neon.h" + -+void -+test_addS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c) ++void test_vcvtf32_f16 (void) +{ -+ int i; -+ for (i = 0; i < 4; i++) -+ a[i] += (S64_t) b[i] * (S64_t) c[i]; ++ float32x4_t out_float32x4_t; ++ float16x4_t arg0_float16x4_t; ++ ++ out_float32x4_t = vcvt_f32_f16 (arg0_float16x4_t); +} + -+/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "vcvt\.f32.f16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c +@@ -0,0 +1,20 @@ ++/* Test the `vcvtf16_f32' ARM Neon intrinsic. */ ++/* This file was autogenerated by neon-testgen. */ + -+void -+test_addS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c) ++/* { dg-do assemble } */ ++/* { dg-require-effective-target arm_neon_fp16_ok } */ ++/* { dg-options "-save-temps -O0" } */ ++/* { dg-add-options arm_neon_fp16 } */ ++ ++#include "arm_neon.h" ++ ++void test_vcvtf16_f32 (void) +{ -+ int i; -+ for (i = 0; i < 8; i++) -+ a[i] += (S32_t) b[i] * (S32_t) c[i]; ++ float16x4_t out_float16x4_t; ++ float32x4_t arg0_float32x4_t; ++ ++ out_float16x4_t = vcvt_f16_f32 (arg0_float32x4_t); +} + -+/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "vcvt\.f16.f32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/arm/anddi3-opt.c ++++ b/src/gcc/testsuite/gcc.target/arm/anddi3-opt.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ + -+void -+test_addS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c) ++unsigned long long ++muld (unsigned long long X, unsigned long long Y) +{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] += (S16_t) b[i] * (S16_t) c[i]; ++ unsigned long long mask = 0xffffffffull; ++ return (X & mask) * (Y & mask); +} + -+void -+test_addS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] += (S16_t) -b[i] * (S16_t) -c[i]; -+} -+ -+void -+test_addS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c) ++/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_prefer_ldrd_strd } */ ++/* { dg-options "-O2" } */ ++int foo(int a, int b, int* p, int *q) +{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] -= (S16_t) b[i] * (S16_t) -c[i]; ++ a = p[2] + p[3]; ++ *q = a; ++ *p = a; ++ return a; +} ++/* { dg-final { scan-assembler "ldrd" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselgtdf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselgtdf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+void -+test_addS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c) ++double ++foo (double x, double y) +{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] -= (S16_t) -b[i] * (S16_t) c[i]; ++ volatile int i = 0; ++ return i > 0 ? x : y; +} + -+/* { dg-final { scan-assembler-times "smlal\tv\[0-9\]+\.8h" 4 } } */ -+/* { dg-final { scan-assembler-times "smlal2\tv\[0-9\]+\.8h" 4 } } */ ++/* { dg-final { scan-assembler-times "vselgt.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/iordi3-opt.c ++++ b/src/gcc/testsuite/gcc.target/arm/iordi3-opt.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ + -+void -+test_subS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c) ++unsigned long long or64 (unsigned long long input) +{ -+ int i; -+ for (i = 0; i < 4; i++) -+ a[i] -= (S64_t) b[i] * (S64_t) c[i]; ++ return input | 0x200000004ULL; +} + -+/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+void -+test_subS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c) -+{ -+ int i; -+ for (i = 0; i < 8; i++) -+ a[i] -= (S32_t) b[i] * (S32_t) c[i]; -+} ++#include "../aarch64/atomic-op-relaxed.x" + -+/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselgesf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselgesf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+void -+test_subS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c) ++float ++foo (float x, float y) +{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] -= (S16_t) b[i] * (S16_t) c[i]; ++ volatile int i = 0; ++ return i >= 0 ? x : y; +} + -+void -+test_subS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c) ++/* { dg-final { scan-assembler-times "vselge.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/peep-strd-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/peep-strd-1.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_prefer_ldrd_strd } */ ++/* { dg-options "-O2" } */ ++void foo(int a, int b, int* p) +{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] += (S16_t) -b[i] * (S16_t) c[i]; ++ p[2] = a; ++ p[3] = b; +} ++/* { dg-final { scan-assembler "strd" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/negdi-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/negdi-1.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm32 } */ ++/* { dg-options "-O2" } */ + -+void -+test_subS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c) ++signed long long extendsidi_negsi (signed int x) +{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] += (S16_t) b[i] * (S16_t) -c[i]; ++ return -x; +} + -+void -+test_subS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] += -((S16_t) b[i] * (S16_t) c[i]); -+} ++/* ++Expected output: ++ rsb r0, r0, #0 ++ mov r1, r0, asr #31 ++*/ ++/* { dg-final { scan-assembler-times "rsb" 1 { target { arm_nothumb } } } } */ ++/* { dg-final { scan-assembler-times "negs\\t" 1 { target { ! { arm_nothumb } } } } } */ ++/* { dg-final { scan-assembler-times "asr" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+void -+test_subS16_tS8_t16_neg3 (pS16_t a, pS8_t b, pS8_t c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] -= (S16_t) -b[i] * (S16_t) -c[i]; -+} ++#include "../aarch64/atomic-comp-swap-release-acquire.x" + -+/* { dg-final { scan-assembler-times "smlsl\tv\[0-9\]+\.8h" 5 } } */ -+/* { dg-final { scan-assembler-times "smlsl2\tv\[0-9\]+\.8h" 5 } } */ ++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 4 } } */ ++/* { dg-final { scan-assembler-times "stlex" 4 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr19599.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr19599.c +@@ -0,0 +1,10 @@ ++/* { dg-skip-if "need at least armv5te" { *-*-* } { "-march=armv[234]*" "-mthumb" } { "" } } */ ++/* { dg-options "-O2 -march=armv5te -marm" } */ ++/* { dg-final { scan-assembler "bx" } } */ + -+void -+test_addU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c) ++int (*indirect_func)(); ++ ++int indirect_call() +{ -+ int i; -+ for (i = 0; i < 4; i++) -+ a[i] += (U64_t) b[i] * (U64_t) c[i]; ++ return indirect_func(); +} +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.2d" } } */ ++#include "../aarch64/atomic-op-seq_cst.x" + -+void -+test_addU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c) ++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselgedf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselgedf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ ++ ++double ++foo (double x, double y) +{ -+ int i; -+ for (i = 0; i < 8; i++) -+ a[i] += (U32_t) b[i] * (U32_t) c[i]; ++ volatile int i = 0; ++ return i >= 0 ? x : y; +} + -+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-consume.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+void -+test_addU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] += (U16_t) b[i] * (U16_t) c[i]; -+} ++#include "../aarch64/atomic-op-consume.x" + -+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.8h" } } */ -+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-char.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+void -+test_subU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c) -+{ -+ int i; -+ for (i = 0; i < 4; i++) -+ a[i] -= (U64_t) b[i] * (U64_t) c[i]; -+} ++#include "../aarch64/atomic-op-char.x" + -+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselnesf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselnesf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+void -+test_subU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c) ++float ++foo (float x, float y) +{ -+ int i; -+ for (i = 0; i < 8; i++) -+ a[i] -= (U32_t) b[i] * (U32_t) c[i]; ++ volatile int i = 0; ++ return i != 0 ? x : y; +} + -+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.4s" } } */ -+ -+void -+test_subU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ a[i] -= (U16_t) b[i] * (U16_t) c[i]; ++/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/negdi-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/negdi-2.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm32 } */ ++/* { dg-options "-O2" } */ ++ ++signed long long zero_extendsidi_negsi (unsigned int x) ++{ ++ return -x; +} ++/* ++Expected output: ++ rsb r0, r0, #0 ++ mov r1, #0 ++*/ ++/* { dg-final { scan-assembler-times "rsb\\tr0, r0, #0" 1 { target { arm_nothumb } } } } */ ++/* { dg-final { scan-assembler-times "negs\\tr0, r0" 1 { target { ! arm_nothumb } } } } */ ++/* { dg-final { scan-assembler-times "mov" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselvcsf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselvcsf.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.8h" } } */ -+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.8h" } } */ ++float ++foo (float x, float y) ++{ ++ return !__builtin_isunordered (x, y) ? x : y; ++} + ++/* { dg-final { scan-assembler-times "vselvs.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/minmax_minus.c ++++ b/src/gcc/testsuite/gcc.target/arm/minmax_minus.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ + -+S64_t add_rS64[4] = { 6, 7, -4, -3 }; -+S32_t add_rS32[8] = { 6, 7, -4, -3, 10, 11, 0, 1 }; -+S16_t add_rS16[16] = -+ { 6, 7, -4, -3, 10, 11, 0, 1, 14, 15, 4, 5, 18, 19, 8, 9 }; ++#define MAX(a, b) (a > b ? a : b) ++int ++foo (int a, int b, int c) ++{ ++ return c - MAX (a, b); ++} + -+S64_t sub_rS64[4] = { 0, 1, 2, 3 }; -+S32_t sub_rS32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; -+S16_t sub_rS16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++/* { dg-final { scan-assembler-not "mov" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-release.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+U64_t add_rU64[4] = { 0x6, 0x7, 0x2fffffffc, 0x2fffffffd }; ++#include "../aarch64/atomic-op-release.x" + -+U32_t add_rU32[8] = -+{ -+ 0x6, 0x7, 0x2fffc, 0x2fffd, -+ 0xa, 0xb, 0x30000, 0x30001 -+}; ++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselvssf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselvssf.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+U16_t add_rU16[16] = ++float ++foo (float x, float y) +{ -+ 0x6, 0x7, 0x2fc, 0x2fd, 0xa, 0xb, 0x300, 0x301, -+ 0xe, 0xf, 0x304, 0x305, 0x12, 0x13, 0x308, 0x309 -+}; ++ return __builtin_isunordered (x, y) ? x : y; ++} + -+U64_t sub_rU64[4] = { 0, 1, 2, 3 }; -+U32_t sub_rU32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; -+U16_t sub_rU16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++/* { dg-final { scan-assembler-times "vselvs.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_neon_ok } */ ++/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ ++/* { dg-add-options arm_v8_neon } */ + -+S8_t neg_r[16] = { -6, -5, 8, 9, -2, -1, 12, 13, 2, 3, 16, 17, 6, 7, 20, 21 }; ++#define N 32 + -+S64_t S64_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; -+S32_t S32_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; -+S32_t S32_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++void ++foo (float *output, float *input) ++{ ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = __builtin_roundf (input[i]); ++} + -+S32_t S32_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; -+S16_t S16_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; -+S16_t S16_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_roundf } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c ++++ b/src/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c +@@ -0,0 +1,54 @@ ++/* Check that Neon is *not* used by default to handle 64-bits scalar ++ operations. */ + -+S16_t S16_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; -+S8_t S8_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; -+S8_t S8_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++typedef long long i64; ++typedef unsigned long long u64; ++typedef unsigned int u32; ++typedef int i32; + ++/* Unary operators */ ++#define UNARY_OP(name, op) \ ++ void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } + -+#define CHECK(T,N,AS,US) \ -+do \ -+ { \ -+ for (i = 0; i < N; i++) \ -+ if (S##T##_ta[i] != AS##_r##US##T[i]) \ -+ abort (); \ -+ } \ -+while (0) ++/* Binary operators */ ++#define BINARY_OP(name, op) \ ++ void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } + -+#define SCHECK(T,N,AS) CHECK(T,N,AS,S) -+#define UCHECK(T,N,AS) CHECK(T,N,AS,U) ++/* Unsigned shift */ ++#define SHIFT_U(name, op, amount) \ ++ void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } + -+#define NCHECK(RES) \ -+do \ -+ { \ -+ for (i = 0; i < 16; i++) \ -+ if (S16_ta[i] != RES[i]) \ -+ abort (); \ -+ } \ -+while (0) ++/* Signed shift */ ++#define SHIFT_S(name, op, amount) \ ++ void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } + ++UNARY_OP(not, ~) + -+int -+main () -+{ -+ int i; ++BINARY_OP(add, +) ++BINARY_OP(sub, -) ++BINARY_OP(and, &) ++BINARY_OP(or, |) ++BINARY_OP(xor, ^) + -+ test_addS64_tS32_t4 (S64_ta, S32_tb, S32_tc); -+ SCHECK (64, 4, add); -+ test_addS32_tS16_t8 (S32_ta, S16_tb, S16_tc); -+ SCHECK (32, 8, add); -+ test_addS16_tS8_t16 (S16_ta, S8_tb, S8_tc); -+ SCHECK (16, 16, add); -+ test_subS64_tS32_t4 (S64_ta, S32_tb, S32_tc); -+ SCHECK (64, 4, sub); -+ test_subS32_tS16_t8 (S32_ta, S16_tb, S16_tc); -+ SCHECK (32, 8, sub); -+ test_subS16_tS8_t16 (S16_ta, S8_tb, S8_tc); -+ SCHECK (16, 16, sub); ++SHIFT_U(right1, >>, 1) ++SHIFT_U(right2, >>, 2) ++SHIFT_U(right5, >>, 5) ++SHIFT_U(rightn, >>, c) + -+ test_addU64_tU32_t4 (S64_ta, S32_tb, S32_tc); -+ UCHECK (64, 4, add); -+ test_addU32_tU16_t8 (S32_ta, S16_tb, S16_tc); -+ UCHECK (32, 8, add); -+ test_addU16_tU8_t16 (S16_ta, S8_tb, S8_tc); -+ UCHECK (16, 16, add); -+ test_subU64_tU32_t4 (S64_ta, S32_tb, S32_tc); -+ UCHECK (64, 4, sub); -+ test_subU32_tU16_t8 (S32_ta, S16_tb, S16_tc); -+ UCHECK (32, 8, sub); -+ test_subU16_tU8_t16 (S16_ta, S8_tb, S8_tc); -+ UCHECK (16, 16, sub); ++SHIFT_S(right1, >>, 1) ++SHIFT_S(right2, >>, 2) ++SHIFT_S(right5, >>, 5) ++SHIFT_S(rightn, >>, c) + -+ test_addS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc); -+ NCHECK (add_rS16); -+ test_subS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc); -+ NCHECK (sub_rS16); -+ test_addS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc); -+ NCHECK (add_rS16); -+ test_subS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc); -+ NCHECK (sub_rS16); -+ test_addS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc); -+ NCHECK (add_rS16); -+ test_subS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc); -+ NCHECK (sub_rS16); -+ test_subS16_tS8_t16_neg3 (S16_ta, S8_tb, S8_tc); -+ NCHECK (neg_r); ++/* { dg-final {scan-assembler-times "vmvn" 0} } */ ++/* { dg-final {scan-assembler-times "vadd" 0} } */ ++/* { dg-final {scan-assembler-times "vsub" 0} } */ ++/* { dg-final {scan-assembler-times "vand" 0} } */ ++/* { dg-final {scan-assembler-times "vorr" 0} } */ ++/* { dg-final {scan-assembler-times "veor" 0} } */ ++/* { dg-final {scan-assembler-times "vshr" 0} } */ +--- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c +@@ -4,7 +4,7 @@ + + #include + +-char dest[16]; ++char dest[16] = { 0 }; + + void aligned_dest (char *src) + { +@@ -14,7 +14,10 @@ + /* Expect a multi-word store for the main part of the copy, but subword + loads/stores for the remainder. */ + +-/* { dg-final { scan-assembler-times "stmia" 1 } } */ ++/* { dg-final { scan-assembler-times "ldmia" 0 } } */ ++/* { dg-final { scan-assembler-times "ldrd" 0 } } */ ++/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ ++/* { dg-final { scan-assembler-times "strd" 1 { target { arm_prefer_ldrd_strd } } } } */ + /* { dg-final { scan-assembler-times "ldrh" 1 } } */ + /* { dg-final { scan-assembler-times "strh" 1 } } */ + /* { dg-final { scan-assembler-times "ldrb" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/xordi3-opt.c ++++ b/src/gcc/testsuite/gcc.target/arm/xordi3-opt.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ + -+ return 0; ++unsigned long long xor64 (unsigned long long input) ++{ ++ return input ^ 0x200000004ULL; +} + -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/extr.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/extr.c -@@ -0,0 +1,34 @@ -+/* { dg-options "-O2 --save-temps" } */ -+/* { dg-do run } */ -+ -+extern void abort (void); ++/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/negdi-3.c ++++ b/src/gcc/testsuite/gcc.target/arm/negdi-3.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm32 } */ ++/* { dg-options "-O2" } */ + -+int -+test_si (int a, int b) ++signed long long negdi_zero_extendsidi (unsigned int x) +{ -+ /* { dg-final { scan-assembler "extr\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, 27\n" } } */ -+ return (a << 5) | ((unsigned int) b >> 27); ++ return -((signed long long) x); +} ++/* ++Expected output: ++ rsbs r0, r0, #0 ++ sbc r1, r1, r1 ++*/ ++/* { dg-final { scan-assembler-times "rsb" 1 } } */ ++/* { dg-final { scan-assembler-times "sbc" 1 } } */ ++/* { dg-final { scan-assembler-times "mov" 0 } } */ ++/* { dg-final { scan-assembler-times "rsc" 0 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+long long -+test_di (long long a, long long b) -+{ -+ /* { dg-final { scan-assembler "extr\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, 45\n" } } */ -+ return (a << 19) | ((unsigned long long) b >> 45); -+} ++#include "../aarch64/atomic-op-acq_rel.x" + -+int -+main () ++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselltsf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselltsf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ ++ ++float ++foo (float x, float y) +{ -+ int v; -+ long long w; -+ v = test_si (0x00000004, 0x30000000); -+ if (v != 0x00000086) -+ abort(); -+ w = test_di (0x0001040040040004ll, 0x0070050066666666ll); -+ if (w != 0x2002002000200380ll) -+ abort(); -+ return 0; ++ volatile int i = 0; ++ return i < 0 ? x : y; +} + -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-compile.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-compile.c -@@ -16,5 +16,7 @@ - /* { dg-final { scan-assembler "uminv" } } */ - /* { dg-final { scan-assembler "smaxv" } } */ - /* { dg-final { scan-assembler "sminv" } } */ -+/* { dg-final { scan-assembler "sabd" } } */ -+/* { dg-final { scan-assembler "saba" } } */ - /* { dg-final { scan-assembler-times "addv" 2} } */ - /* { dg-final { scan-assembler-times "addp" 2} } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c -@@ -2,12 +2,13 @@ - /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ - - #define FTYPE double -+#define ITYPE long - #define OP == - #define INV_OP != - - #include "vect-fcm.x" - --/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ - /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ - /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ - /* { dg-final { cleanup-tree-dump "vect" } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/adds3.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/adds3.c -@@ -0,0 +1,61 @@ -+/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps -fno-inline" } */ -+ -+extern void abort (void); -+typedef long long s64; ++/* { dg-final { scan-assembler-times "vselge.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselnedf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselnedf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+int -+adds_ext (s64 a, int b, int c) ++double ++foo (double x, double y) +{ -+ s64 d = a + b; -+ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; ++ volatile int i = 0; ++ return i != 0 ? x : y; +} + -+int -+adds_shift_ext (s64 a, int b, int c) -+{ -+ s64 d = (a + ((s64)b << 3)); -+ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; -+} ++/* { dg-final { scan-assembler-times "vseleq.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselvcdf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselvcdf.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+int main () ++double ++foo (double x, double y) +{ -+ int x; -+ s64 y; -+ -+ x = adds_ext (0x13000002ll, 41, 15); -+ if (x != 318767203) -+ abort (); -+ -+ x = adds_ext (0x50505050ll, 29, 4); -+ if (x != 1347440782) -+ abort (); -+ -+ x = adds_ext (0x12121212121ll, 2, 14); -+ if (x != 555819315) -+ abort (); -+ -+ x = adds_shift_ext (0x123456789ll, 4, 12); -+ if (x != 591751097) -+ abort (); ++ return !__builtin_isunordered (x, y) ? x : y; ++} + -+ x = adds_shift_ext (0x02020202ll, 9, 8); -+ if (x != 33686107) -+ abort (); ++/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_neon_ok } */ ++/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ ++/* { dg-add-options arm_v8_neon } */ + -+ x = adds_shift_ext (0x987987987987ll, 23, 41); -+ if (x != -2020050305) -+ abort (); ++#define N 32 + -+ return 0; ++void ++foo (float *output, float *input) ++{ ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = __builtin_truncf (input[i]); +} + -+/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/subs2.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/subs2.c -@@ -0,0 +1,155 @@ -+/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps -fno-inline" } */ -+ -+extern void abort (void); ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_btruncf } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vseleqsf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vseleqsf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+int -+subs_si_test1 (int a, int b, int c) ++float ++foo (float x, float y) +{ -+ int d = a - b; -+ -+ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ -+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ -+ if (d <= 0) -+ return a + c; -+ else -+ return b + d + c; ++ volatile int i = 0; ++ return i == 0 ? x : y; +} + -+int -+subs_si_test2 (int a, int b, int c) -+{ -+ int d = a - 0xfff; ++/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c ++++ b/src/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -fdump-tree-ivopts-details" } */ ++/* { dg-skip-if "" { arm_thumb1 } } */ + -+ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, #4095" } } */ -+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, #4095" } } */ -+ if (d <= 0) -+ return a + c; -+ else -+ return b + d + c; -+} ++extern char *__ctype_ptr__; + -+int -+subs_si_test3 (int a, int b, int c) ++unsigned char * foo(unsigned char *ReadPtr) +{ -+ int d = a - (b << 3); + -+ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ -+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ -+ if (d <= 0) -+ return a + c; -+ else -+ return b + d + c; ++ unsigned char c; ++ ++ while (!(((__ctype_ptr__+sizeof(""[*ReadPtr]))[(int)(*ReadPtr)])&04) == (!(0))) ++ ReadPtr++; ++ ++ return ReadPtr; +} + -+typedef long long s64; ++/* { dg-final { scan-tree-dump-times "original biv" 2 "ivopts"} } */ ++/* { dg-final { cleanup-tree-dump "ivopts" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselvsdf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselvsdf.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+s64 -+subs_di_test1 (s64 a, s64 b, s64 c) ++double ++foo (double x, double y) +{ -+ s64 d = a - b; ++ return __builtin_isunordered (x, y) ? x : y; ++} + -+ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ -+ if (d <= 0) -+ return a + c; -+ else -+ return b + d + c; -+} ++/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c ++++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c +@@ -4,7 +4,7 @@ + + #include + +-char src[16]; ++char src[16] = {0}; + + void aligned_src (char *dest) + { +@@ -14,8 +14,11 @@ + /* Expect a multi-word load for the main part of the copy, but subword + loads/stores for the remainder. */ + +-/* { dg-final { scan-assembler-times "ldmia" 1 } } */ +-/* { dg-final { scan-assembler-times "ldrh" 1 } } */ ++/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ ++/* { dg-final { scan-assembler-times "ldrd" 1 { target { arm_prefer_ldrd_strd } } } } */ ++/* { dg-final { scan-assembler-times "strd" 0 } } */ ++/* { dg-final { scan-assembler-times "stm" 0 } } */ ++/* { dg-final { scan-assembler-times "ldrh" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ + /* { dg-final { scan-assembler-times "strh" 1 } } */ +-/* { dg-final { scan-assembler-times "ldrb" 1 } } */ ++/* { dg-final { scan-assembler-times "ldrb" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ + /* { dg-final { scan-assembler-times "strb" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr46975-2.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr46975-2.c +@@ -0,0 +1,10 @@ ++/* { dg-options "-mthumb -O2" } */ ++/* { dg-require-effective-target arm_thumb2_ok } */ ++/* { dg-final { scan-assembler "sub" } } */ ++/* { dg-final { scan-assembler "clz" } } */ ++/* { dg-final { scan-assembler "lsr.*#5" } } */ + -+s64 -+subs_di_test2 (s64 a, s64 b, s64 c) ++int foo (int s) +{ -+ s64 d = a - 0x1000ll; -+ -+ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, #4096" } } */ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, #4096" } } */ -+ if (d <= 0) -+ return a + c; -+ else -+ return b + d + c; ++ return s == 1; +} +--- a/src/gcc/testsuite/gcc.target/arm/anddi3-opt2.c ++++ b/src/gcc/testsuite/gcc.target/arm/anddi3-opt2.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O1" } */ + -+s64 -+subs_di_test3 (s64 a, s64 b, s64 c) ++long long muld(long long X, long long Y) +{ -+ s64 d = a - (b << 3); -+ -+ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ -+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ -+ if (d <= 0) -+ return a + c; -+ else -+ return b + d + c; ++ return X & ~1; +} + -+int main () ++/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/negdi-4.c ++++ b/src/gcc/testsuite/gcc.target/arm/negdi-4.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm32 } */ ++/* { dg-options "-O2" } */ ++ ++signed long long negdi_extendsidi (signed int x) +{ -+ int x; -+ s64 y; ++ return -((signed long long) x); ++} ++/* ++Expected output: ++ rsbs r0, r0, #0 ++ mov r1, r0, asr #31 ++*/ ++/* { dg-final { scan-assembler-times "rsb" 1 } } */ ++/* { dg-final { scan-assembler-times "asr" 1 } } */ ++/* { dg-final { scan-assembler-times "rsc" 0 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselltdf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselltdf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+ x = subs_si_test1 (29, 4, 5); -+ if (x != 34) -+ abort (); ++double ++foo (double x, double y) ++{ ++ volatile int i = 0; ++ return i < 0 ? x : y; ++} + -+ x = subs_si_test1 (5, 2, 20); -+ if (x != 25) -+ abort (); ++/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c ++++ b/src/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c +@@ -4,8 +4,8 @@ + + #include + +-char src[16]; +-char dest[16]; ++char src[16] = { 0 }; ++char dest[16] = { 0 }; + + void aligned_both (void) + { +@@ -14,5 +14,9 @@ + + /* We know both src and dest to be aligned: expect multiword loads/stores. */ + +-/* { dg-final { scan-assembler-times "ldmia" 1 } } */ +-/* { dg-final { scan-assembler-times "stmia" 1 } } */ ++/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ ++/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */ ++/* { dg-final { scan-assembler "ldrd" { target { arm_prefer_ldrd_strd } } } } */ ++/* { dg-final { scan-assembler-times "ldm" 0 { target { arm_prefer_ldrd_strd } } } } */ ++/* { dg-final { scan-assembler "strd" { target { arm_prefer_ldrd_strd } } } } */ ++/* { dg-final { scan-assembler-times "stm" 0 { target { arm_prefer_ldrd_strd } } } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vseleqdf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vseleqdf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+ x = subs_si_test2 (29, 4, 5); -+ if (x != 34) -+ abort (); ++double ++foo (double x, double y) ++{ ++ volatile int i = 0; ++ return i == 0 ? x : y; ++} + -+ x = subs_si_test2 (1024, 2, 20); -+ if (x != 1044) -+ abort (); ++/* { dg-final { scan-assembler-times "vseleq.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+ x = subs_si_test3 (35, 4, 5); -+ if (x != 12) -+ abort (); ++#include "../aarch64/atomic-op-acquire.x" + -+ x = subs_si_test3 (5, 2, 20); -+ if (x != 25) -+ abort (); ++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vsellesf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vsellesf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+ y = subs_di_test1 (0x130000029ll, -+ 0x320000004ll, -+ 0x505050505ll); ++float ++foo (float x, float y) ++{ ++ volatile int i = 0; ++ return i <= 0 ? x : y; ++} + -+ if (y != 0x63505052e) -+ abort (); ++/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+ y = subs_di_test1 (0x5000500050005ll, -+ 0x2111211121112ll, -+ 0x0000000002020ll); -+ if (y != 0x5000500052025) -+ abort (); ++#include "../aarch64/atomic-op-int.x" + -+ y = subs_di_test2 (0x130000029ll, -+ 0x320000004ll, -+ 0x505050505ll); -+ if (y != 0x95504f532) -+ abort (); ++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-short.c ++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_arch_v8a_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_arch_v8a } */ + -+ y = subs_di_test2 (0x540004100ll, -+ 0x320000004ll, -+ 0x805050205ll); -+ if (y != 0x1065053309) -+ abort (); ++#include "../aarch64/atomic-op-short.x" + -+ y = subs_di_test3 (0x130000029ll, -+ 0x064000008ll, -+ 0x505050505ll); -+ if (y != 0x63505052e) -+ abort (); ++/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ ++/* { dg-final { scan-assembler-not "dmb" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr40887.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr40887.c +@@ -2,9 +2,9 @@ + /* { dg-options "-O2 -march=armv5te" } */ + /* { dg-final { scan-assembler "blx" } } */ + +-int (*indirect_func)(); ++int (*indirect_func)(int x); + + int indirect_call() + { +- return indirect_func(); ++ return indirect_func(20) + indirect_func (40); + } +--- a/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_neon_ok } */ ++/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */ ++/* { dg-add-options arm_v8_neon } */ + -+ y = subs_di_test3 (0x130002900ll, -+ 0x088000008ll, -+ 0x505050505ll); -+ if (y != 0x635052e05) -+ abort (); ++#define N 32 + -+ return 0; ++void ++foo (float *output, float *input) ++{ ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = __builtin_ceilf (input[i]); +} + -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c -@@ -0,0 +1,117 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 --save-temps -ffast-math" } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_ceilf } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselledf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselledf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+#include ++double ++foo (double x, double y) ++{ ++ volatile int i = 0; ++ return i <= 0 ? x : y; ++} + -+extern void abort (void); ++/* { dg-final { scan-assembler-times "vselgt.f64\td\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/vselgtsf.c ++++ b/src/gcc/testsuite/gcc.target/arm/vselgtsf.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_v8_vfp_ok } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_v8_vfp } */ + -+#define NUM_TESTS 16 -+#define DELTA 0.000001 ++float ++foo (float x, float y) ++{ ++ volatile int i = 0; ++ return i > 0 ? x : y; ++} + -+int8_t input_int8[] = {1, 56, 2, -9, -90, 23, 54, 76, -+ -4, 34, 110, -110, 6, 4, 75, -34}; -+int16_t input_int16[] = {1, 56, 2, -9, -90, 23, 54, 76, -+ -4, 34, 110, -110, 6, 4, 75, -34}; -+int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76, -+ -4, 34, 110, -110, 6, 4, 75, -34}; ++/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */ +--- a/src/gcc/testsuite/gcc.target/arm/pr58578.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr58578.c +@@ -0,0 +1,54 @@ + -+uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76, -+ 4, 34, 110, 110, 6, 4, 75, 34}; -+uint16_t input_uint16[] = {1, 56, 2, 9, 90, 23, 54, 76, -+ 4, 34, 110, 110, 6, 4, 75, 34}; -+uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76, -+ 4, 34, 110, 110, 6, 4, 75, 34}; ++/* PR target/58578 */ ++/* { dg-do run } */ ++/* { dg-options "-O1" } */ + -+#define EQUAL(a, b) (a == b) ++#include + -+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES) \ -+int \ -+test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \ -+{ \ -+ int i, j; \ -+ int moves = (NUM_TESTS - LANES) + 1; \ -+ TYPE##_t out_l[NUM_TESTS]; \ -+ TYPE##_t out_v[NUM_TESTS]; \ -+ \ -+ /* Calculate linearly. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ out_l[i] = input_##TYPE[i]; \ -+ for (j = 0; j < LANES; j++) \ -+ out_l[i] = input_##TYPE[i + j] CMP_OP out_l[i] ? \ -+ input_##TYPE[i + j] : out_l[i]; \ -+ } \ -+ \ -+ /* Calculate using vector reduction intrinsics. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ -+ out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1); \ -+ } \ -+ \ -+ /* Compare. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ if (!EQUAL (out_v[i], out_l[i])) \ -+ return 0; \ -+ } \ -+ return 1; \ -+} ++typedef struct { ++ long _prec; ++ int _flag; ++ long _exp; ++} __my_st_t; + -+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64) \ -+TEST (max, >, STYPE, , TYPE, W32) \ -+TEST (max, >, STYPE, q, TYPE, W64) \ -+TEST (min, <, STYPE, , TYPE, W32) \ -+TEST (min, <, STYPE, q, TYPE, W64) ++typedef __my_st_t *__my_st_ptr; + -+BUILD_VARIANTS (int8, s8, 8, 16) -+/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ -+/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ -+/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ -+/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ -+BUILD_VARIANTS (uint8, u8, 8, 16) -+/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ -+/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ -+/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ -+/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ -+BUILD_VARIANTS (int16, s16, 4, 8) -+/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ -+/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ -+/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ -+/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ -+BUILD_VARIANTS (uint16, u16, 4, 8) -+/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ -+/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ -+/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ -+/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ -+BUILD_VARIANTS (int32, s32, 2, 4) -+/* { dg-final { scan-assembler "smaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "sminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "smaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "sminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ -+BUILD_VARIANTS (uint32, u32, 2, 4) -+/* { dg-final { scan-assembler "umaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "uminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "umaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "uminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++int ++_test_fn (__my_st_ptr y, const __my_st_ptr xt) ++{ ++ int inexact; ++ if (xt->_exp != -2147483647L) ++ { ++ (y->_flag = xt->_flag); ++ } + -+#undef TEST -+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES) \ -+{ \ -+ if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ()) \ -+ abort (); \ ++ do { ++ __my_st_ptr _y = y; ++ long _err1 = -2 * xt->_exp; ++ long _err2 = 2; ++ if (0 < _err1) ++ { ++ unsigned long _err = (unsigned long) _err1 + _err2; ++ if (__builtin_expect(!!(_err > _y->_prec + 1), 0)) ++ return 2; ++ return 3; ++ } ++ } while (0); ++ ++ return 0; +} + -+int -+main (int argc, char **argv) ++int main () +{ -+ BUILD_VARIANTS (int8, s8, 8, 16) -+ BUILD_VARIANTS (uint8, u8, 8, 16) -+ BUILD_VARIANTS (int16, s16, 4, 8) -+ BUILD_VARIANTS (uint16, u16, 4, 8) -+ BUILD_VARIANTS (int32, s32, 2, 4) -+ BUILD_VARIANTS (uint32, u32, 2, 4) ++ __my_st_t x, y; ++ long pz; ++ int inex; ++ ++ x._prec = 914; ++ y._exp = 18; ++ if (_test_fn (&x, &y)) ++ { ++ abort(); ++ } + return 0; +} -+ -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vrecpx.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vrecpx.c -@@ -0,0 +1,54 @@ +--- a/src/gcc/testsuite/gcc.target/arm/pr57637.c ++++ b/src/gcc/testsuite/gcc.target/arm/pr57637.c +@@ -0,0 +1,206 @@ +/* { dg-do run } */ -+/* { dg-options "-O3 --save-temps" } */ ++/* { dg-options "-O2 -fno-inline" } */ + -+#include -+#include -+#include ++typedef struct _GtkCssStyleProperty GtkCssStyleProperty; + -+float32_t in_f[] = -+{2.0, 4.0, 8.0, 16.0, 1.0, 0.5, 0.25, 0.125}; -+float32_t rec_f[] = -+{1.0, 0.5, 0.25, 0.125, 2.0, 4.0, 8.0, 16.0}; -+float64_t in_d[] = -+{2.0, 4.0, 8.0, 16.0, 1.0, 0.5, 0.25, 0.125}; -+float32_t rec_d[] = -+{1.0, 0.5, 0.25, 0.125, 2.0, 4.0, 8.0, 16.0}; ++struct _GtkCssStyleProperty ++{ ++ int *initial_value; ++ unsigned int id; ++ unsigned int inherit :1; ++ unsigned int animated :1; ++ unsigned int affects_size :1; ++ unsigned int affects_font :1; ++ ++ int * parse_value; ++ int * query_value; ++ int * assign_value; ++}; ++ ++void ++g_assertion_message_expr (const char *domain, ++ const char *file, ++ int line, ++ const char *func, ++ const char *expr) __attribute__((__noreturn__)); + ++void ++g_assertion_message_expr (const char *domain, ++ const char *file, ++ int line, ++ const char *func, ++ const char *expr) ++{ ++ __builtin_abort (); ++} +int -+test_frecpx_float32_t (void) ++get_id (GtkCssStyleProperty *property) +{ -+ int i = 0; -+ int ret = 1; -+ for (i = 0; i < 8; i++) -+ ret &= fabs (vrecpxs_f32 (in_f[i]) - rec_f[i]) < 0.001; ++ return 1; ++} ++int ++_gtk_css_style_property_get_type () ++{ ++ return 1; ++} + -+ return ret; ++GtkCssStyleProperty * ++g_object_new (int object_type, ++ const char *first_property_name, ++ ...) ++{ ++ return (GtkCssStyleProperty *) __builtin_malloc (sizeof (GtkCssStyleProperty)); +} + -+/* { dg-final { scan-assembler "frecpx\\ts\[0-9\]+, s\[0-9\]+" } } */ ++typedef enum { ++ INHERIT = (1 << 0), ++ ANIMATED = (1 << 1), ++ RESIZE = (1 << 2), ++ FONT = (1 << 3) ++} GtkStylePropertyFlags; + -+int -+test_frecpx_float64_t (void) ++int t = 0; ++void ++gtk_css_style_property_register (const char * name, ++ int expected_id, ++ int value_type, ++ int flags, ++ int *parse_value, ++ int *query_value, ++ int *assign_value, ++ int *initial_value) +{ -+ int i = 0; -+ int ret = 1; -+ for (i = 0; i < 8; i++) -+ ret &= fabs (vrecpxd_f64 (in_d[i]) - rec_d[i]) < 0.001; ++ GtkCssStyleProperty *node; + -+ return ret; -+} ++ do ++ { ++ if (__builtin_expect (__extension__ ( ++ { ++ int _g_boolean_var_; ++ if (initial_value != ((void *)0)) ++ _g_boolean_var_ = 1; ++ else ++ _g_boolean_var_ = 0; ++ _g_boolean_var_; ++ }), ++ 1)) ++ ; ++ else ++ g_assertion_message_expr ("Gtk", ++ "gtkcssstylepropertyimpl.c", ++ 85, ++ ((const char*) (__PRETTY_FUNCTION__)), ++ "initial_value != NULL"); ++ } while (0); + -+/* { dg-final { scan-assembler "frecpx\\td\[0-9\]+, d\[0-9\]+" } } */ ++ do ++ { ++ if (__builtin_expect (__extension__ ( ++ { ++ int _g_boolean_var_; ++ if (parse_value != ((void *)0)) ++ _g_boolean_var_ = 1; ++ else ++ _g_boolean_var_ = 0; ++ _g_boolean_var_; ++ }), ++ 1)) ++ ; ++ else ++ g_assertion_message_expr ("Gtk", ++ "gtkcssstylepropertyimpl.c", ++ 86, ++ ((const char*) (__PRETTY_FUNCTION__)), ++ "parse_value != NULL"); ++ } while (0); + -+int -+main (int argc, char **argv) ++ do ++ { ++ if (__builtin_expect (__extension__ ( ++ { ++ int _g_boolean_var_; ++ if (value_type == ((int) ((1) << (2))) ++ || query_value != ((void *)0)) ++ _g_boolean_var_ = 1; ++ else ++ _g_boolean_var_ = 0; ++ _g_boolean_var_; ++ }), ++ 1)) ++ ; ++ else ++ g_assertion_message_expr ("Gtk", ++ "gtkcssstylepropertyimpl.c", ++ 87, ((const char*) (__PRETTY_FUNCTION__)), ++ "value_type == NONE || query_value != NULL"); ++ } while (0); ++ ++ /* FLAGS is changed in a cond_exec instruction with pr57637. */ ++ if (flags == 15) ++ t = 15; ++ ++ do ++ { ++ if (__builtin_expect (__extension__ ( ++ { ++ int _g_boolean_var_; ++ if (value_type == ((1) << (2)) ++ || assign_value != ((void *)0)) ++ _g_boolean_var_ = 1; ++ else ++ _g_boolean_var_ = 0; ++ _g_boolean_var_; ++ }), ++ 1)) ++ ; ++ else ++ g_assertion_message_expr ("Gtk", ++ "gtkcssstylepropertyimpl.c", ++ 88, ((const char*) (__PRETTY_FUNCTION__)), ++ "value_type == NONE || assign_value != NULL"); ++ } while (0); ++ ++ node = g_object_new ((_gtk_css_style_property_get_type ()), ++ "value-type", value_type, ++ "affects-size", (flags & RESIZE) ? (0) : (!(0)), ++ "affects-font", (flags & FONT) ? (!(0)) : (0), ++ "animated", (flags & ANIMATED) ? (!(0)) : (0), ++ "inherit", (flags & INHERIT) ? (!(0)) : (0), ++ "initial-value", initial_value, ++ "name", name, ++ ((void *)0)); ++ ++ node->parse_value = parse_value; ++ node->query_value = query_value; ++ node->assign_value = assign_value; ++ ++ do ++ { ++ if (__builtin_expect (__extension__ ( ++ { ++ int _g_boolean_var_; ++ if (get_id (node) == expected_id) ++ _g_boolean_var_ = 1; ++ else ++ _g_boolean_var_ = 0; ++ _g_boolean_var_; ++ }), ++ 1)) ++ ; ++ else ++ g_assertion_message_expr ("Gtk", ++ "gtkcssstylepropertyimpl.c", ++ 106, ++ ((const char*) (__PRETTY_FUNCTION__)), ++ "get_id (node) == expected_id"); ++ } while (0); ++} ++ ++int main () +{ -+ if (!test_frecpx_float32_t ()) -+ abort (); -+ if (!test_frecpx_float64_t ()) -+ abort (); ++ gtk_css_style_property_register ("test", 1, 4, 15, &t, &t, &t, &t); + ++ if (t != 15) ++ __builtin_abort (); + return 0; +} +--- a/src/gcc/testsuite/gcc.target/aarch64/insv_2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/insv_2.c +@@ -0,0 +1,85 @@ ++/* { dg-do run { target aarch64*-*-* } } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-require-effective-target aarch64_big_endian } */ + -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-vca.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vca.c -@@ -0,0 +1,89 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 --save-temps" } */ ++extern void abort (void); + -+#include ++typedef struct bitfield ++{ ++ unsigned short eight: 8; ++ unsigned short four: 4; ++ unsigned short five: 5; ++ unsigned short seven: 7; ++ unsigned int sixteen: 16; ++} bitfield; + -+extern void abort (void); -+extern float fabsf (float); -+extern double fabs (double); ++bitfield ++bfi1 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 56, 8" } } */ ++ a.eight = 3; ++ return a; ++} + -+#define NUM_TESTS 8 ++bitfield ++bfi2 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 43, 5" } } */ ++ a.five = 7; ++ return a; ++} + -+float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f}; -+float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f}; -+double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5}; -+double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5}; ++bitfield ++movk (bitfield a) ++{ ++ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 16" } } */ ++ a.sixteen = 7531; ++ return a; ++} + -+#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F) \ -+int \ -+test_vca##T##_float##WIDTH##x##LANES##_t (void) \ -+{ \ -+ int ret = 0; \ -+ int i = 0; \ -+ uint##WIDTH##_t output[NUM_TESTS]; \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ { \ -+ float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]); \ -+ float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]); \ -+ /* Inhibit optimization of our linear test loop. */ \ -+ asm volatile ("" : : : "memory"); \ -+ output[i] = f1 CMP f2 ? -1 : 0; \ -+ } \ -+ \ -+ for (i = 0; i < NUM_TESTS; i += LANES) \ -+ { \ -+ float##WIDTH##x##LANES##_t in1 = \ -+ vld1##Q##_f##WIDTH (input_##SUFFIX##1 + i); \ -+ float##WIDTH##x##LANES##_t in2 = \ -+ vld1##Q##_f##WIDTH (input_##SUFFIX##2 + i); \ -+ uint##WIDTH##x##LANES##_t expected_out = \ -+ vld1##Q##_u##WIDTH (output + i); \ -+ uint##WIDTH##x##LANES##_t out = \ -+ veor##Q##_u##WIDTH (vca##T##Q##_f##WIDTH (in1, in2), \ -+ expected_out); \ -+ vst1##Q##_u##WIDTH (output + i, out); \ -+ } \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ ret |= output[i]; \ -+ \ -+ return ret; \ ++bitfield ++set1 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 272678883688448" } } */ ++ a.five = 0x1f; ++ return a; +} + -+#define BUILD_VARIANTS(T, CMP) \ -+TEST (T, CMP, s, 32, 2, , f) \ -+TEST (T, CMP, s, 32, 4, q, f) \ -+TEST (T, CMP, d, 64, 2, q, ) ++bitfield ++set0 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -272678883688449" } } */ ++ a.five = 0; ++ return a; ++} + -+BUILD_VARIANTS (ge, >=) -+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ + -+BUILD_VARIANTS (gt, >) -+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++int ++main (int argc, char** argv) ++{ ++ static bitfield a; ++ bitfield b = bfi1 (a); ++ bitfield c = bfi2 (b); ++ bitfield d = movk (c); + -+/* No need for another scan-assembler as these tests -+ also generate facge, facgt instructions. */ -+BUILD_VARIANTS (le, <=) -+BUILD_VARIANTS (lt, <) ++ if (d.eight != 3) ++ abort (); + -+#undef TEST -+#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F) \ -+if (test_vca##T##_float##WIDTH##x##LANES##_t ()) \ -+ abort (); ++ if (d.five != 7) ++ abort (); ++ ++ if (d.sixteen != 7531) ++ abort (); ++ ++ d = set1 (d); ++ if (d.five != 0x1f) ++ abort (); ++ ++ d = set0 (d); ++ if (d.five != 0) ++ abort (); + -+int -+main (int argc, char **argv) -+{ -+BUILD_VARIANTS (ge, >=) -+BUILD_VARIANTS (gt, >) -+BUILD_VARIANTS (le, <=) -+BUILD_VARIANTS (lt, <) + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c -@@ -0,0 +1,117 @@ +--- a/src/gcc/testsuite/gcc.target/aarch64/vrecps.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vrecps.c +@@ -0,0 +1,144 @@ +/* { dg-do run } */ +/* { dg-options "-O3 --save-temps" } */ + +#include ++#include ++#include + -+extern void abort (void); -+extern float fabsf (float); -+extern double fabs (double); ++int ++test_frecps_float32_t (void) ++{ ++ int i; ++ float32_t value = 0.2; ++ float32_t reciprocal = 5.0; ++ float32_t step = vrecpes_f32 (value); ++ /* 3 steps should give us within ~0.001 accuracy. */ ++ for (i = 0; i < 3; i++) ++ step = step * vrecpss_f32 (step, value); + -+extern double trunc (double); -+extern double round (double); -+extern double nearbyint (double); -+extern double floor (double); -+extern double ceil (double); -+extern double rint (double); ++ return fabs (step - reciprocal) < 0.001; ++} + -+extern float truncf (float); -+extern float roundf (float); -+extern float nearbyintf (float); -+extern float floorf (float); -+extern float ceilf (float); -+extern float rintf (float); ++/* { dg-final { scan-assembler "frecpe\\ts\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "frecps\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ + -+#define NUM_TESTS 8 -+#define DELTA 0.000001 ++int ++test_frecps_float32x2_t (void) ++{ ++ int i; ++ int ret = 1; + -+float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f, -+ 200.0f, -800.0f, -13.0f, -0.5f}; -+double input_f64[] = {0.1, -0.1, 0.4, 10.3, -+ 200.0, -800.0, -13.0, -0.5}; ++ const float32_t value_pool[] = {0.2, 0.4}; ++ const float32_t reciprocal_pool[] = {5.0, 2.5}; ++ float32x2_t value = vld1_f32 (value_pool); ++ float32x2_t reciprocal = vld1_f32 (reciprocal_pool); + -+#define TEST(SUFFIX, Q, WIDTH, LANES, C_FN, F) \ -+int \ -+test_vrnd##SUFFIX##_float##WIDTH##x##LANES##_t (void) \ -+{ \ -+ int ret = 1; \ -+ int i = 0; \ -+ int nlanes = LANES; \ -+ float##WIDTH##_t expected_out[NUM_TESTS]; \ -+ float##WIDTH##_t actual_out[NUM_TESTS]; \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ { \ -+ expected_out[i] = C_FN##F (input_f##WIDTH[i]); \ -+ /* Don't vectorize this. */ \ -+ asm volatile ("" : : : "memory"); \ -+ } \ -+ \ -+ /* Prevent the compiler from noticing these two loops do the same \ -+ thing and optimizing away the comparison. */ \ -+ asm volatile ("" : : : "memory"); \ -+ \ -+ for (i = 0; i < NUM_TESTS; i+=nlanes) \ -+ { \ -+ float##WIDTH##x##LANES##_t out = \ -+ vrnd##SUFFIX##Q##_f##WIDTH \ -+ (vld1##Q##_f##WIDTH (input_f##WIDTH + i)); \ -+ vst1##Q##_f##WIDTH (actual_out + i, out); \ -+ } \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ ret &= fabs##F (expected_out[i] - actual_out[i]) < DELTA; \ -+ \ -+ return ret; \ -+} \ ++ float32x2_t step = vrecpe_f32 (value); ++ /* 3 steps should give us within ~0.001 accuracy. */ ++ for (i = 0; i < 3; i++) ++ step = step * vrecps_f32 (step, value); + ++ ret &= fabs (vget_lane_f32 (step, 0) ++ - vget_lane_f32 (reciprocal, 0)) < 0.001; ++ ret &= fabs (vget_lane_f32 (step, 1) ++ - vget_lane_f32 (reciprocal, 1)) < 0.001; + -+#define BUILD_VARIANTS(SUFFIX, C_FN) \ -+TEST (SUFFIX, , 32, 2, C_FN, f) \ -+TEST (SUFFIX, q, 32, 4, C_FN, f) \ -+TEST (SUFFIX, q, 64, 2, C_FN, ) \ ++ return ret; ++} + -+BUILD_VARIANTS ( , trunc) -+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (a, round) -+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (i, nearbyint) -+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (m, floor) -+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (p, ceil) -+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (x, rint) -+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.2s, v\[0-9\]+.2s" } } */ ++/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.2s, v\[0-9\]+.2s, v\[0-9\]+.2s" } } */ + -+#undef TEST -+#define TEST(SUFFIX, Q, WIDTH, LANES, C_FN, F) \ -+{ \ -+ if (!test_vrnd##SUFFIX##_float##WIDTH##x##LANES##_t ()) \ -+ abort (); \ ++int ++test_frecps_float32x4_t (void) ++{ ++ int i; ++ int ret = 1; ++ ++ const float32_t value_pool[] = {0.2, 0.4, 0.5, 0.8}; ++ const float32_t reciprocal_pool[] = {5.0, 2.5, 2.0, 1.25}; ++ float32x4_t value = vld1q_f32 (value_pool); ++ float32x4_t reciprocal = vld1q_f32 (reciprocal_pool); ++ ++ float32x4_t step = vrecpeq_f32 (value); ++ /* 3 steps should give us within ~0.001 accuracy. */ ++ for (i = 0; i < 3; i++) ++ step = step * vrecpsq_f32 (step, value); ++ ++ ret &= fabs (vgetq_lane_f32 (step, 0) ++ - vgetq_lane_f32 (reciprocal, 0)) < 0.001; ++ ret &= fabs (vgetq_lane_f32 (step, 1) ++ - vgetq_lane_f32 (reciprocal, 1)) < 0.001; ++ ret &= fabs (vgetq_lane_f32 (step, 2) ++ - vgetq_lane_f32 (reciprocal, 2)) < 0.001; ++ ret &= fabs (vgetq_lane_f32 (step, 3) ++ - vgetq_lane_f32 (reciprocal, 3)) < 0.001; ++ ++ return ret; +} + ++/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.4s, v\[0-9\]+.4s" } } */ ++/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.4s, v\[0-9\]+.4s, v\[0-9\]+.4s" } } */ ++ +int -+main (int argc, char **argv) ++test_frecps_float64_t (void) +{ -+ BUILD_VARIANTS ( , trunc) -+ BUILD_VARIANTS (a, round) -+ BUILD_VARIANTS (i, nearbyint) -+ BUILD_VARIANTS (m, floor) -+ BUILD_VARIANTS (p, ceil) -+ BUILD_VARIANTS (x, rint) -+ return 0; -+} -+ -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c -@@ -1,43 +1,7 @@ - /* { dg-do compile } */ - /* { dg-options "-O2" } */ - --int v = 0; -+#include "atomic-op-relaxed.x" - --int --atomic_fetch_add_RELAXED (int a) --{ -- return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_sub_RELAXED (int a) --{ -- return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_and_RELAXED (int a) --{ -- return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_nand_RELAXED (int a) --{ -- return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_xor_RELAXED (int a) --{ -- return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_or_RELAXED (int a) --{ -- return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); --} -- - /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm.x -@@ -13,6 +13,8 @@ - 2.0, -4.0, 8.0, -16.0, - -2.125, 4.25, -8.5, 17.0}; - -+/* Float comparisons, float results. */ -+ - void - foo (FTYPE *in1, FTYPE *in2, FTYPE *output) - { -@@ -49,11 +51,52 @@ - output[i] = (in1[i] INV_OP 0.0) ? 4.0 : 2.0; - } - -+/* Float comparisons, int results. */ ++ int i; ++ float64_t value = 0.2; ++ float64_t reciprocal = 5.0; ++ float64_t step = vrecped_f64 (value); ++ /* 3 steps should give us within ~0.001 accuracy. */ ++ for (i = 0; i < 3; i++) ++ step = step * vrecpsd_f64 (step, value); + -+void -+foo_int (FTYPE *in1, FTYPE *in2, ITYPE *output) -+{ -+ int i = 0; -+ /* Vectorizable. */ -+ for (i = 0; i < N; i++) -+ output[i] = (in1[i] OP in2[i]) ? 2 : 4; ++ return fabs (step - reciprocal) < 0.001; +} + -+void -+bar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) -+{ -+ int i = 0; -+ /* Vectorizable. */ -+ for (i = 0; i < N; i++) -+ output[i] = (in1[i] INV_OP in2[i]) ? 4 : 2; -+} ++/* { dg-final { scan-assembler "frecpe\\td\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "frecps\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ + -+void -+foobar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) ++int ++test_frecps_float64x2_t (void) +{ -+ int i = 0; -+ /* Vectorizable. */ -+ for (i = 0; i < N; i++) -+ output[i] = (in1[i] OP 0.0) ? 4 : 2; -+} ++ int i; ++ int ret = 1; + -+void -+foobarbar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) -+{ -+ int i = 0; -+ /* Vectorizable. */ -+ for (i = 0; i < N; i++) -+ output[i] = (in1[i] INV_OP 0.0) ? 4 : 2; -+} ++ const float64_t value_pool[] = {0.2, 0.4}; ++ const float64_t reciprocal_pool[] = {5.0, 2.5}; ++ float64x2_t value = vld1q_f64 (value_pool); ++ float64x2_t reciprocal = vld1q_f64 (reciprocal_pool); + - int - main (int argc, char **argv) - { - FTYPE out1[N]; - FTYPE out2[N]; -+ ITYPE outi1[N]; -+ ITYPE outi2[N]; ++ float64x2_t step = vrecpeq_f64 (value); ++ /* 3 steps should give us within ~0.001 accuracy. */ ++ for (i = 0; i < 3; i++) ++ step = step * vrecpsq_f64 (step, value); + - int i = 0; - foo (input1, input2, out1); - bar (input1, input2, out2); -@@ -65,6 +108,17 @@ - for (i = 0; i < N; i++) - if (out1[i] == out2[i]) - abort (); ++ ret &= fabs (vgetq_lane_f64 (step, 0) ++ - vgetq_lane_f64 (reciprocal, 0)) < 0.001; ++ ret &= fabs (vgetq_lane_f64 (step, 1) ++ - vgetq_lane_f64 (reciprocal, 1)) < 0.001; + -+ foo_int (input1, input2, outi1); -+ bar_int (input1, input2, outi2); -+ for (i = 0; i < N; i++) -+ if (outi1[i] != outi2[i]) -+ abort (); -+ foobar_int (input1, input2, outi1); -+ foobarbar_int (input1, input2, outi2); -+ for (i = 0; i < N; i++) -+ if (outi1[i] == outi2[i]) -+ abort (); - return 0; - } - ---- a/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c -@@ -0,0 +1,11 @@ ++ return ret; ++} + -+/* { dg-do compile } */ -+/* { dg-options "-O3" } */ ++/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.2d, v\[0-9\]+.2d" } } */ ++/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.2d, v\[0-9\]+.2d, v\[0-9\]+.2d" } } */ + -+#include "arm_neon.h" ++int ++main (int argc, char **argv) ++{ ++ if (!test_frecps_float32_t ()) ++ abort (); ++ if (!test_frecps_float32x2_t ()) ++ abort (); ++ if (!test_frecps_float32x4_t ()) ++ abort (); ++ if (!test_frecps_float64_t ()) ++ abort (); ++ if (!test_frecps_float64x2_t ()) ++ abort (); + -+#include "vaddv-intrinsic.x" ++ return 0; ++} + -+/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+"} } */ -+/* { dg-final { scan-assembler-times "faddp\\tv\[0-9\]+\.4s" 2} } */ -+/* { dg-final { scan-assembler "faddp\\td\[0-9\]+"} } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/movi_1.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/movi_1.c -@@ -0,0 +1,13 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/ands_2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/ands_2.c +@@ -0,0 +1,157 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + -+void -+dummy (short* b) ++extern void abort (void); ++ ++int ++ands_si_test1 (int a, int b, int c) +{ -+ /* { dg-final { scan-assembler "movi\tv\[0-9\]+\.4h, 0x4, lsl 8" } } */ -+ /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 0x400" } } */ -+ /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 1024" } } */ -+ register short x asm ("h8") = 1024; -+ asm volatile ("" : : "w" (x)); -+ *b = x; ++ int d = a & b; ++ ++ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x -@@ -0,0 +1,37 @@ -+int v = 0; + +int -+atomic_fetch_add_RELAXED (int a) ++ands_si_test2 (int a, int b, int c) +{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); ++ int d = a & 0x99999999; ++ ++ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */ ++ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} + +int -+atomic_fetch_sub_RELAXED (int a) ++ands_si_test3 (int a, int b, int c) +{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); ++ int d = a & (b << 3); ++ ++ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} + -+int -+atomic_fetch_and_RELAXED (int a) ++typedef long long s64; ++ ++s64 ++ands_di_test1 (s64 a, s64 b, s64 c) +{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); ++ s64 d = a & b; ++ ++ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} + -+int -+atomic_fetch_nand_RELAXED (int a) ++s64 ++ands_di_test2 (s64 a, s64 b, s64 c) +{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); ++ s64 d = a & 0xaaaaaaaaaaaaaaaall; ++ ++ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */ ++ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} + -+int -+atomic_fetch_xor_RELAXED (int a) ++s64 ++ands_di_test3 (s64 a, s64 b, s64 c) +{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); ++ s64 d = a & (b << 3); ++ ++ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} + +int -+atomic_fetch_or_RELAXED (int a) ++main () +{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -+} ---- a/src/gcc/testsuite/gcc.target/aarch64/vect.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect.c -@@ -55,6 +55,8 @@ - int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15}; - unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; - unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; -+ int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -+ int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - int reduce_smax_value = 0; - int reduce_smin_value = -15; - unsigned int reduce_umax_value = 15; -@@ -81,6 +83,8 @@ - TEST (smin, s); - TEST (umax, u); - TEST (umin, u); -+ TEST (sabd, s); -+ TEST (saba, s); - TESTV (reduce_smax, s); - TESTV (reduce_smin, s); - TESTV (reduce_umax, u); ---- a/src/gcc/testsuite/gcc.target/aarch64/scalar-mov.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar-mov.c -@@ -0,0 +1,9 @@ -+/* { dg-do compile } */ -+/* { dg-options "-g -mgeneral-regs-only" } */ ++ int x; ++ s64 y; + -+void -+foo (const char *c, ...) -+{ -+ char buf[256]; -+ buf[256 - 1] = '\0'; -+} ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c -@@ -2,12 +2,13 @@ - /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ - - #define FTYPE double -+#define ITYPE long - #define OP >= - #define INV_OP < - - #include "vect-fcm.x" - --/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ - /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ - /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ - /* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c -@@ -1,43 +1,7 @@ - /* { dg-do compile } */ - /* { dg-options "-O2" } */ - --int v = 0; -+#include "atomic-op-acquire.x" - --int --atomic_fetch_add_ACQUIRE (int a) --{ -- return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE); --} -- --int --atomic_fetch_sub_ACQUIRE (int a) --{ -- return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE); --} -- --int --atomic_fetch_and_ACQUIRE (int a) --{ -- return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE); --} -- --int --atomic_fetch_nand_ACQUIRE (int a) --{ -- return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE); --} -- --int --atomic_fetch_xor_ACQUIRE (int a) --{ -- return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE); --} -- --int --atomic_fetch_or_ACQUIRE (int a) --{ -- return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE); --} -- - /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c -@@ -1,41 +1,7 @@ - /* { dg-do compile } */ - /* { dg-options "-O2" } */ - --#define STRONG 0 --#define WEAK 1 --int v = 0; -+#include "atomic-comp-swap-release-acquire.x" - --int --atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b) --{ -- return __atomic_compare_exchange (&v, &a, &b, -- STRONG, __ATOMIC_RELEASE, -- __ATOMIC_ACQUIRE); --} -- --int --atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b) --{ -- return __atomic_compare_exchange (&v, &a, &b, -- WEAK, __ATOMIC_RELEASE, -- __ATOMIC_ACQUIRE); --} -- --int --atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b) --{ -- return __atomic_compare_exchange_n (&v, &a, b, -- STRONG, __ATOMIC_RELEASE, -- __ATOMIC_ACQUIRE); --} -- --int --atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b) --{ -- return __atomic_compare_exchange_n (&v, &a, b, -- WEAK, __ATOMIC_RELEASE, -- __ATOMIC_ACQUIRE); --} -- - /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */ - /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect.x -@@ -138,3 +138,17 @@ - - return s; - } ++ x = ands_si_test1 (29, 4, 5); ++ if (x != 13) ++ abort (); + -+void sabd (pRINT a, pRINT b, pRINT c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ c[i] = abs (a[i] - b[i]); -+} ++ x = ands_si_test1 (5, 2, 20); ++ if (x != 25) ++ abort (); + -+void saba (pRINT a, pRINT b, pRINT c) -+{ -+ int i; -+ for (i = 0; i < 16; i++) -+ c[i] += abs (a[i] - b[i]); -+} ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c -@@ -0,0 +1,35 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 -save-temps -fno-inline" } */ ++ x = ands_si_test2 (29, 4, 5); ++ if (x != 34) ++ abort (); + -+extern void abort (); ++ x = ands_si_test2 (1024, 2, 20); ++ if (x != 1044) ++ abort (); + -+void -+count_lz_v4si (unsigned *__restrict a, int *__restrict b) -+{ -+ int i; ++ x = ands_si_test3 (35, 4, 5); ++ if (x != 41) ++ abort (); + -+ for (i = 0; i < 4; i++) -+ b[i] = __builtin_clz (a[i]); -+} ++ x = ands_si_test3 (5, 2, 20); ++ if (x != 25) ++ abort (); + -+/* { dg-final { scan-assembler "clz\tv\[0-9\]+\.4s" } } */ ++ y = ands_di_test1 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); + -+int -+main () -+{ -+ unsigned int x[4] = { 0x0, 0xFFFF, 0x1FFFF, 0xFFFFFFFF }; -+ int r[4] = { 32, 16, 15, 0 }; -+ int d[4], i; ++ if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll)) ++ abort (); + -+ count_lz_v4si (x, d); ++ y = ands_di_test1 (0x5000500050005ll, ++ 0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x5000500052025ll) ++ abort (); + -+ for (i = 0; i < 4; i++) -+ { -+ if (d[i] != r[i]) -+ abort (); -+ } ++ y = ands_di_test2 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != ((0x130000029ll & 0xaaaaaaaaaaaaaaaall) + 0x320000004ll + 0x505050505ll)) ++ abort (); ++ ++ y = ands_di_test2 (0x540004100ll, ++ 0x320000004ll, ++ 0x805050205ll); ++ if (y != (0x540004100ll + 0x805050205ll)) ++ abort (); ++ ++ y = ands_di_test3 (0x130000029ll, ++ 0x064000008ll, ++ 0x505050505ll); ++ if (y != ((0x130000029ll & (0x064000008ll << 3)) ++ + 0x064000008ll + 0x505050505ll)) ++ abort (); ++ ++ y = ands_di_test3 (0x130002900ll, ++ 0x088000008ll, ++ 0x505050505ll); ++ if (y != (0x130002900ll + 0x505050505ll)) ++ abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c -@@ -2,12 +2,13 @@ - /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ - - #define FTYPE float -+#define ITYPE int - #define OP > - #define INV_OP <= - - #include "vect-fcm.x" - --/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ - /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ - /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ - /* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/subs3.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/subs3.c -@@ -0,0 +1,61 @@ +--- a/src/gcc/testsuite/gcc.target/aarch64/scalar-vca.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/scalar-vca.c +@@ -0,0 +1,72 @@ +/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-options "-O3 --save-temps" } */ ++ ++#include + +extern void abort (void); -+typedef long long s64; ++extern float fabsf (float); ++extern double fabs (double); + -+int -+subs_ext (s64 a, int b, int c) -+{ -+ s64 d = a - b; ++#define NUM_TESTS 8 + -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; -+} ++float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f}; ++float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f}; ++double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5}; ++double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5}; + -+int -+subs_shift_ext (s64 a, int b, int c) -+{ -+ s64 d = (a - ((s64)b << 3)); -+ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; ++#define TEST(TEST, CMP, SUFFIX, WIDTH, F) \ ++int \ ++test_fca##TEST##SUFFIX##_float##WIDTH##_t (void) \ ++{ \ ++ int ret = 0; \ ++ int i = 0; \ ++ uint##WIDTH##_t output[NUM_TESTS]; \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ { \ ++ float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]); \ ++ float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]); \ ++ /* Inhibit optimization of our linear test loop. */ \ ++ asm volatile ("" : : : "memory"); \ ++ output[i] = f1 CMP f2 ? -1 : 0; \ ++ } \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ { \ ++ output[i] = vca##TEST##SUFFIX##_f##WIDTH (input_##SUFFIX##1[i], \ ++ input_##SUFFIX##2[i]) \ ++ ^ output[i]; \ ++ /* Inhibit autovectorization of our scalar test loop. */ \ ++ asm volatile ("" : : : "memory"); \ ++ } \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ ret |= output[i]; \ ++ \ ++ return ret; \ +} + -+int main () -+{ -+ int x; -+ s64 y; -+ -+ x = subs_ext (0x13000002ll, 41, 15); -+ if (x != 318767121) -+ abort (); -+ -+ x = subs_ext (0x50505050ll, 29, 4); -+ if (x != 1347440724) -+ abort (); ++TEST (ge, >=, s, 32, f) ++/* { dg-final { scan-assembler "facge\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ ++TEST (ge, >=, d, 64, ) ++/* { dg-final { scan-assembler "facge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ ++TEST (gt, >, s, 32, f) ++/* { dg-final { scan-assembler "facgt\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */ ++TEST (gt, >, d, 64, ) ++/* { dg-final { scan-assembler "facgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */ + -+ x = subs_ext (0x12121212121ll, 2, 14); -+ if (x != 555819311) ++int ++main (int argc, char **argv) ++{ ++ if (test_fcages_float32_t ()) + abort (); -+ -+ x = subs_shift_ext (0x123456789ll, 4, 12); -+ if (x != 591751033) ++ if (test_fcaged_float64_t ()) + abort (); -+ -+ x = subs_shift_ext (0x02020202ll, 9, 8); -+ if (x != 33685963) ++ if (test_fcagts_float32_t ()) + abort (); -+ -+ x = subs_shift_ext (0x987987987987ll, 23, 41); -+ if (x != -2020050673) ++ if (test_fcagtd_float64_t ()) + abort (); -+ + return 0; +} + -+/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x @@ -0,0 +1,37 @@ +int v = 0; + +int -+atomic_fetch_add_ACQUIRE (int a) ++atomic_fetch_add_ACQ_REL (int a) +{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE); ++ return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL); +} + +int -+atomic_fetch_sub_ACQUIRE (int a) ++atomic_fetch_sub_ACQ_REL (int a) +{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE); ++ return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL); +} + +int -+atomic_fetch_and_ACQUIRE (int a) ++atomic_fetch_and_ACQ_REL (int a) +{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE); ++ return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL); +} + +int -+atomic_fetch_nand_ACQUIRE (int a) ++atomic_fetch_nand_ACQ_REL (int a) +{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE); ++ return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL); +} + +int -+atomic_fetch_xor_ACQUIRE (int a) ++atomic_fetch_xor_ACQ_REL (int a) +{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE); ++ return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL); +} + +int -+atomic_fetch_or_ACQUIRE (int a) ++atomic_fetch_or_ACQ_REL (int a) +{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE); ++ return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); +} ---- a/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c -@@ -0,0 +1,28 @@ -+ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c +@@ -0,0 +1,325 @@ +/* { dg-do run } */ -+/* { dg-options "-O3" } */ -+ -+#include "arm_neon.h" ++/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model" } */ + -+extern void abort (void); ++typedef signed char S8_t; ++typedef signed short S16_t; ++typedef signed int S32_t; ++typedef signed long S64_t; ++typedef signed char *__restrict__ pS8_t; ++typedef signed short *__restrict__ pS16_t; ++typedef signed int *__restrict__ pS32_t; ++typedef signed long *__restrict__ pS64_t; ++typedef unsigned char U8_t; ++typedef unsigned short U16_t; ++typedef unsigned int U32_t; ++typedef unsigned long U64_t; ++typedef unsigned char *__restrict__ pU8_t; ++typedef unsigned short *__restrict__ pU16_t; ++typedef unsigned int *__restrict__ pU32_t; ++typedef unsigned long *__restrict__ pU64_t; + -+#include "vaddv-intrinsic.x" ++extern void abort (); + -+int -+main (void) ++void ++test_addS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c) +{ -+ const float32_t pool_v2sf[] = {4.0f, 9.0f}; -+ const float32_t pool_v4sf[] = {4.0f, 9.0f, 16.0f, 25.0f}; -+ const float64_t pool_v2df[] = {4.0, 9.0}; -+ -+ if (test_vaddv_v2sf (pool_v2sf) != 13.0f) -+ abort (); -+ -+ if (test_vaddv_v4sf (pool_v4sf) != 54.0f) -+ abort (); ++ int i; ++ for (i = 0; i < 4; i++) ++ a[i] += (S64_t) b[i] * (S64_t) c[i]; ++} + -+ if (test_vaddv_v2df (pool_v2df) != 13.0) -+ abort (); ++/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.2d" } } */ + -+ return 0; ++void ++test_addS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c) ++{ ++ int i; ++ for (i = 0; i < 8; i++) ++ a[i] += (S32_t) b[i] * (S32_t) c[i]; +} ---- a/src/gcc/testsuite/gcc.target/aarch64/sbc.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/sbc.c -@@ -0,0 +1,41 @@ -+/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps" } */ -+ -+extern void abort (void); + -+typedef unsigned int u32int; -+typedef unsigned long long u64int; ++/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.4s" } } */ + -+u32int -+test_si (u32int w1, u32int w2, u32int w3, u32int w4) ++void ++test_addS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c) +{ -+ u32int w0; -+ /* { dg-final { scan-assembler "sbc\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+\n" } } */ -+ w0 = w1 - w2 - (w3 < w4); -+ return w0; ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (S16_t) b[i] * (S16_t) c[i]; +} + -+u64int -+test_di (u64int x1, u64int x2, u64int x3, u64int x4) ++void ++test_addS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c) +{ -+ u64int x0; -+ /* { dg-final { scan-assembler "sbc\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+\n" } } */ -+ x0 = x1 - x2 - (x3 < x4); -+ return x0; ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (S16_t) -b[i] * (S16_t) -c[i]; +} + -+int -+main () ++void ++test_addS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c) +{ -+ u32int x; -+ u64int y; -+ x = test_si (7, 8, 12, 15); -+ if (x != -2) -+ abort(); -+ y = test_di (0x987654321ll, 0x123456789ll, 0x345345345ll, 0x123123123ll); -+ if (y != 0x8641fdb98ll) -+ abort(); -+ return 0; ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (S16_t) b[i] * (S16_t) -c[i]; +} + -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x -@@ -0,0 +1,36 @@ -+ -+#define STRONG 0 -+#define WEAK 1 -+int v = 0; -+ -+int -+atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b) ++void ++test_addS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c) +{ -+ return __atomic_compare_exchange (&v, &a, &b, -+ STRONG, __ATOMIC_RELEASE, -+ __ATOMIC_ACQUIRE); ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (S16_t) -b[i] * (S16_t) c[i]; +} + -+int -+atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b) ++/* { dg-final { scan-assembler-times "smlal\tv\[0-9\]+\.8h" 4 } } */ ++/* { dg-final { scan-assembler-times "smlal2\tv\[0-9\]+\.8h" 4 } } */ ++ ++void ++test_subS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c) +{ -+ return __atomic_compare_exchange (&v, &a, &b, -+ WEAK, __ATOMIC_RELEASE, -+ __ATOMIC_ACQUIRE); ++ int i; ++ for (i = 0; i < 4; i++) ++ a[i] -= (S64_t) b[i] * (S64_t) c[i]; +} + -+int -+atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b) ++/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.2d" } } */ ++ ++void ++test_subS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c) +{ -+ return __atomic_compare_exchange_n (&v, &a, b, -+ STRONG, __ATOMIC_RELEASE, -+ __ATOMIC_ACQUIRE); ++ int i; ++ for (i = 0; i < 8; i++) ++ a[i] -= (S32_t) b[i] * (S32_t) c[i]; +} + ++/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.4s" } } */ ++ ++void ++test_subS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (S16_t) b[i] * (S16_t) c[i]; ++} ++ ++void ++test_subS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (S16_t) -b[i] * (S16_t) c[i]; ++} ++ ++void ++test_subS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (S16_t) b[i] * (S16_t) -c[i]; ++} ++ ++void ++test_subS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += -((S16_t) b[i] * (S16_t) c[i]); ++} ++ ++void ++test_subS16_tS8_t16_neg3 (pS16_t a, pS8_t b, pS8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (S16_t) -b[i] * (S16_t) -c[i]; ++} ++ ++/* { dg-final { scan-assembler-times "smlsl\tv\[0-9\]+\.8h" 5 } } */ ++/* { dg-final { scan-assembler-times "smlsl2\tv\[0-9\]+\.8h" 5 } } */ ++ ++void ++test_addU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c) ++{ ++ int i; ++ for (i = 0; i < 4; i++) ++ a[i] += (U64_t) b[i] * (U64_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.2d" } } */ ++ ++void ++test_addU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c) ++{ ++ int i; ++ for (i = 0; i < 8; i++) ++ a[i] += (U32_t) b[i] * (U32_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.4s" } } */ ++ ++void ++test_addU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] += (U16_t) b[i] * (U16_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.8h" } } */ ++ ++void ++test_subU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c) ++{ ++ int i; ++ for (i = 0; i < 4; i++) ++ a[i] -= (U64_t) b[i] * (U64_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.2d" } } */ ++ ++void ++test_subU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c) ++{ ++ int i; ++ for (i = 0; i < 8; i++) ++ a[i] -= (U32_t) b[i] * (U32_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.4s" } } */ ++ ++void ++test_subU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ a[i] -= (U16_t) b[i] * (U16_t) c[i]; ++} ++ ++/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.8h" } } */ ++ ++ ++S64_t add_rS64[4] = { 6, 7, -4, -3 }; ++S32_t add_rS32[8] = { 6, 7, -4, -3, 10, 11, 0, 1 }; ++S16_t add_rS16[16] = ++ { 6, 7, -4, -3, 10, 11, 0, 1, 14, 15, 4, 5, 18, 19, 8, 9 }; ++ ++S64_t sub_rS64[4] = { 0, 1, 2, 3 }; ++S32_t sub_rS32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; ++S16_t sub_rS16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++ ++U64_t add_rU64[4] = { 0x6, 0x7, 0x2fffffffc, 0x2fffffffd }; ++ ++U32_t add_rU32[8] = ++{ ++ 0x6, 0x7, 0x2fffc, 0x2fffd, ++ 0xa, 0xb, 0x30000, 0x30001 ++}; ++ ++U16_t add_rU16[16] = ++{ ++ 0x6, 0x7, 0x2fc, 0x2fd, 0xa, 0xb, 0x300, 0x301, ++ 0xe, 0xf, 0x304, 0x305, 0x12, 0x13, 0x308, 0x309 ++}; ++ ++U64_t sub_rU64[4] = { 0, 1, 2, 3 }; ++U32_t sub_rU32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; ++U16_t sub_rU16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++ ++S8_t neg_r[16] = { -6, -5, 8, 9, -2, -1, 12, 13, 2, 3, 16, 17, 6, 7, 20, 21 }; ++ ++S64_t S64_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++S32_t S32_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; ++S32_t S32_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++ ++S32_t S32_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++S16_t S16_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; ++S16_t S16_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++ ++S16_t S16_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; ++S8_t S8_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 }; ++S8_t S8_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }; ++ ++ ++#define CHECK(T,N,AS,US) \ ++do \ ++ { \ ++ for (i = 0; i < N; i++) \ ++ if (S##T##_ta[i] != AS##_r##US##T[i]) \ ++ abort (); \ ++ } \ ++while (0) ++ ++#define SCHECK(T,N,AS) CHECK(T,N,AS,S) ++#define UCHECK(T,N,AS) CHECK(T,N,AS,U) ++ ++#define NCHECK(RES) \ ++do \ ++ { \ ++ for (i = 0; i < 16; i++) \ ++ if (S16_ta[i] != RES[i]) \ ++ abort (); \ ++ } \ ++while (0) ++ ++ +int -+atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b) ++main () +{ -+ return __atomic_compare_exchange_n (&v, &a, b, -+ WEAK, __ATOMIC_RELEASE, -+ __ATOMIC_ACQUIRE); ++ int i; ++ ++ test_addS64_tS32_t4 (S64_ta, S32_tb, S32_tc); ++ SCHECK (64, 4, add); ++ test_addS32_tS16_t8 (S32_ta, S16_tb, S16_tc); ++ SCHECK (32, 8, add); ++ test_addS16_tS8_t16 (S16_ta, S8_tb, S8_tc); ++ SCHECK (16, 16, add); ++ test_subS64_tS32_t4 (S64_ta, S32_tb, S32_tc); ++ SCHECK (64, 4, sub); ++ test_subS32_tS16_t8 (S32_ta, S16_tb, S16_tc); ++ SCHECK (32, 8, sub); ++ test_subS16_tS8_t16 (S16_ta, S8_tb, S8_tc); ++ SCHECK (16, 16, sub); ++ ++ test_addU64_tU32_t4 (S64_ta, S32_tb, S32_tc); ++ UCHECK (64, 4, add); ++ test_addU32_tU16_t8 (S32_ta, S16_tb, S16_tc); ++ UCHECK (32, 8, add); ++ test_addU16_tU8_t16 (S16_ta, S8_tb, S8_tc); ++ UCHECK (16, 16, add); ++ test_subU64_tU32_t4 (S64_ta, S32_tb, S32_tc); ++ UCHECK (64, 4, sub); ++ test_subU32_tU16_t8 (S32_ta, S16_tb, S16_tc); ++ UCHECK (32, 8, sub); ++ test_subU16_tU8_t16 (S16_ta, S8_tb, S8_tc); ++ UCHECK (16, 16, sub); ++ ++ test_addS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc); ++ NCHECK (add_rS16); ++ test_subS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc); ++ NCHECK (sub_rS16); ++ test_addS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc); ++ NCHECK (add_rS16); ++ test_subS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc); ++ NCHECK (sub_rS16); ++ test_addS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc); ++ NCHECK (add_rS16); ++ test_subS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc); ++ NCHECK (sub_rS16); ++ test_subS16_tS8_t16_neg3 (S16_ta, S8_tb, S8_tc); ++ NCHECK (neg_r); ++ ++ return 0; +} ---- a/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c -@@ -1,8 +1,14 @@ - /* { dg-do compile } */ --/* { dg-options "-O2" } */ -+/* { dg-options "-O2 -dp" } */ - --#include "../../../config/aarch64/arm_neon.h" -+#include - -+/* Used to force a variable to a SIMD register. */ -+#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \ -+ : "=w"(V1) \ -+ : "w"(V1) \ -+ : /* No clobbers */); + - /* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */ - - uint64x1_t -@@ -31,7 +37,12 @@ - uint64x1_t - test_vceqd_s64 (int64x1_t a, int64x1_t b) - { -- return vceqd_s64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vceqd_s64 (a, b); -+ force_simd (res); -+ return res; - } - - /* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -@@ -39,7 +50,11 @@ - uint64x1_t - test_vceqzd_s64 (int64x1_t a) - { -- return vceqzd_s64 (a); -+ uint64x1_t res; -+ force_simd (a); -+ res = vceqzd_s64 (a); -+ force_simd (res); -+ return res; - } - - /* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ -@@ -47,21 +62,36 @@ - uint64x1_t - test_vcged_s64 (int64x1_t a, int64x1_t b) - { -- return vcged_s64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vcged_s64 (a, b); -+ force_simd (res); -+ return res; - } - - uint64x1_t - test_vcled_s64 (int64x1_t a, int64x1_t b) - { -- return vcled_s64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vcled_s64 (a, b); -+ force_simd (res); -+ return res; - } - --/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -+/* Idiom recognition will cause this testcase not to generate -+ the expected cmge instruction, so do not check for it. */ - - uint64x1_t - test_vcgezd_s64 (int64x1_t a) - { -- return vcgezd_s64 (a); -+ uint64x1_t res; -+ force_simd (a); -+ res = vcgezd_s64 (a); -+ force_simd (res); -+ return res; - } - - /* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -@@ -69,7 +99,12 @@ - uint64x1_t - test_vcged_u64 (uint64x1_t a, uint64x1_t b) - { -- return vcged_u64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vcged_u64 (a, b); -+ force_simd (res); -+ return res; - } - - /* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ -@@ -77,13 +112,23 @@ - uint64x1_t - test_vcgtd_s64 (int64x1_t a, int64x1_t b) - { -- return vcgtd_s64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vcgtd_s64 (a, b); -+ force_simd (res); -+ return res; - } - - uint64x1_t - test_vcltd_s64 (int64x1_t a, int64x1_t b) - { -- return vcltd_s64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vcltd_s64 (a, b); -+ force_simd (res); -+ return res; - } - - /* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -@@ -91,7 +136,11 @@ - uint64x1_t - test_vcgtzd_s64 (int64x1_t a) - { -- return vcgtzd_s64 (a); -+ uint64x1_t res; -+ force_simd (a); -+ res = vcgtzd_s64 (a); -+ force_simd (res); -+ return res; - } - - /* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -@@ -99,7 +148,12 @@ - uint64x1_t - test_vcgtd_u64 (uint64x1_t a, uint64x1_t b) - { -- return vcgtd_u64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vcgtd_u64 (a, b); -+ force_simd (res); -+ return res; - } - - /* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -@@ -107,18 +161,27 @@ - uint64x1_t - test_vclezd_s64 (int64x1_t a) - { -- return vclezd_s64 (a); -+ uint64x1_t res; -+ force_simd (a); -+ res = vclezd_s64 (a); -+ force_simd (res); -+ return res; - } - --/* { dg-final { scan-assembler-times "\\tcmlt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ -+/* Idiom recognition will cause this testcase not to generate -+ the expected cmlt instruction, so do not check for it. */ - - uint64x1_t - test_vcltzd_s64 (int64x1_t a) - { -- return vcltzd_s64 (a); -+ uint64x1_t res; -+ force_simd (a); -+ res = vcltzd_s64 (a); -+ force_simd (res); -+ return res; - } - --/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */ -+/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv16qi" 2 } } */ - - int8x1_t - test_vdupb_lane_s8 (int8x16_t a) -@@ -132,7 +195,7 @@ - return vdupb_lane_u8 (a, 2); - } - --/* { dg-final { scan-assembler-times "\\tdup\\th\[0-9\]+, v\[0-9\]+\.h" 2 } } */ -+/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv8hi" 2 } } */ - - int16x1_t - test_vduph_lane_s16 (int16x8_t a) -@@ -146,7 +209,7 @@ - return vduph_lane_u16 (a, 2); - } - --/* { dg-final { scan-assembler-times "\\tdup\\ts\[0-9\]+, v\[0-9\]+\.s" 2 } } */ -+/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv4si" 2 } } */ - - int32x1_t - test_vdups_lane_s32 (int32x4_t a) -@@ -160,18 +223,18 @@ - return vdups_lane_u32 (a, 2); - } - --/* { dg-final { scan-assembler-times "\\tdup\\td\[0-9\]+, v\[0-9\]+\.d" 2 } } */ -+/* { dg-final { scan-assembler-times "aarch64_dup_lane_scalarv2di" 2 } } */ - - int64x1_t - test_vdupd_lane_s64 (int64x2_t a) - { -- return vdupd_lane_s64 (a, 2); -+ return vdupd_lane_s64 (a, 1); - } ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/extr.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/extr.c +@@ -0,0 +1,34 @@ ++/* { dg-options "-O2 --save-temps" } */ ++/* { dg-do run } */ ++ ++extern void abort (void); ++ ++int ++test_si (int a, int b) ++{ ++ /* { dg-final { scan-assembler "extr\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, 27\n" } } */ ++ return (a << 5) | ((unsigned int) b >> 27); ++} ++ ++long long ++test_di (long long a, long long b) ++{ ++ /* { dg-final { scan-assembler "extr\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, 45\n" } } */ ++ return (a << 19) | ((unsigned long long) b >> 45); ++} ++ ++int ++main () ++{ ++ int v; ++ long long w; ++ v = test_si (0x00000004, 0x30000000); ++ if (v != 0x00000086) ++ abort(); ++ w = test_di (0x0001040040040004ll, 0x0070050066666666ll); ++ if (w != 0x2002002000200380ll) ++ abort(); ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-compile.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-compile.c +@@ -16,5 +16,7 @@ + /* { dg-final { scan-assembler "uminv" } } */ + /* { dg-final { scan-assembler "smaxv" } } */ + /* { dg-final { scan-assembler "sminv" } } */ ++/* { dg-final { scan-assembler "sabd" } } */ ++/* { dg-final { scan-assembler "saba" } } */ + /* { dg-final { scan-assembler-times "addv" 2} } */ + /* { dg-final { scan-assembler-times "addp" 2} } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ - uint64x1_t - test_vdupd_lane_u64 (uint64x2_t a) - { -- return vdupd_lane_u64 (a, 2); -+ return vdupd_lane_u64 (a, 1); - } + #define FTYPE double ++#define ITYPE long + #define OP == + #define INV_OP != - /* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ -@@ -179,13 +242,23 @@ - int64x1_t - test_vtst_s64 (int64x1_t a, int64x1_t b) - { -- return vtstd_s64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vtstd_s64 (a, b); -+ force_simd (res); -+ return res; - } + #include "vect-fcm.x" - uint64x1_t - test_vtst_u64 (uint64x1_t a, uint64x1_t b) - { -- return vtstd_u64 (a, b); -+ uint64x1_t res; -+ force_simd (a); -+ force_simd (b); -+ res = vtstd_s64 (a, b); -+ force_simd (res); -+ return res; - } - - /* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */ -@@ -722,8 +795,11 @@ - return vrshld_u64 (a, b); - } - --/* { dg-final { scan-assembler-times "\\tasr\\tx\[0-9\]+" 1 } } */ -+/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd), -+ so we cannot check scan-assembler-times. */ - -+/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ + /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/adds3.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/adds3.c +@@ -0,0 +1,61 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + - int64x1_t - test_vshrd_n_s64 (int64x1_t a) - { ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c -@@ -1,43 +1,7 @@ - /* { dg-do compile } */ - /* { dg-options "-O2" } */ - --int v = 0; -+#include "atomic-op-int.x" - --int --atomic_fetch_add_RELAXED (int a) --{ -- return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_sub_RELAXED (int a) --{ -- return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_and_RELAXED (int a) --{ -- return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_nand_RELAXED (int a) --{ -- return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_xor_RELAXED (int a) --{ -- return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); --} -- --int --atomic_fetch_or_RELAXED (int a) --{ -- return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); --} -- - /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c -@@ -1,43 +1,7 @@ - /* { dg-do compile } */ - /* { dg-options "-O2" } */ - --int v = 0; -+#include "atomic-op-seq_cst.x" - --int --atomic_fetch_add_SEQ_CST (int a) --{ -- return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST); --} -- --int --atomic_fetch_sub_SEQ_CST (int a) --{ -- return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST); --} -- --int --atomic_fetch_and_SEQ_CST (int a) --{ -- return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST); --} -- --int --atomic_fetch_nand_SEQ_CST (int a) --{ -- return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST); --} -- --int --atomic_fetch_xor_SEQ_CST (int a) --{ -- return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST); --} -- --int --atomic_fetch_or_SEQ_CST (int a) --{ -- return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); --} -- - /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x -@@ -0,0 +1,27 @@ ++extern void abort (void); ++typedef long long s64; + -+float32_t -+test_vaddv_v2sf (const float32_t *pool) ++int ++adds_ext (s64 a, int b, int c) +{ -+ float32x2_t val; ++ s64 d = a + b; + -+ val = vld1_f32 (pool); -+ return vaddv_f32 (val); ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; +} + -+float32_t -+test_vaddv_v4sf (const float32_t *pool) ++int ++adds_shift_ext (s64 a, int b, int c) +{ -+ float32x4_t val; ++ s64 d = (a + ((s64)b << 3)); + -+ val = vld1q_f32 (pool); -+ return vaddvq_f32 (val); ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; +} + -+float64_t -+test_vaddv_v2df (const float64_t *pool) ++int main () +{ -+ float64x2_t val; ++ int x; ++ s64 y; + -+ val = vld1q_f64 (pool); -+ return vaddvq_f64 (val); ++ x = adds_ext (0x13000002ll, 41, 15); ++ if (x != 318767203) ++ abort (); ++ ++ x = adds_ext (0x50505050ll, 29, 4); ++ if (x != 1347440782) ++ abort (); ++ ++ x = adds_ext (0x12121212121ll, 2, 14); ++ if (x != 555819315) ++ abort (); ++ ++ x = adds_shift_ext (0x123456789ll, 4, 12); ++ if (x != 591751097) ++ abort (); ++ ++ x = adds_shift_ext (0x02020202ll, 9, 8); ++ if (x != 33686107) ++ abort (); ++ ++ x = adds_shift_ext (0x987987987987ll, 23, 41); ++ if (x != -2020050305) ++ abort (); ++ ++ return 0; +} ---- a/src/gcc/testsuite/gcc.target/aarch64/negs.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/negs.c -@@ -0,0 +1,108 @@ ++ ++/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/subs2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/subs2.c +@@ -0,0 +1,155 @@ +/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps" } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); -+int z; + +int -+negs_si_test1 (int a, int b, int c) ++subs_si_test1 (int a, int b, int c) +{ -+ int d = -b; ++ int d = a - b; + -+ /* { dg-final { scan-assembler "negs\tw\[0-9\]+, w\[0-9\]+" } } */ -+ if (d < 0) ++ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ if (d <= 0) + return a + c; -+ -+ z = d; -+ return b + c + d; ++ else ++ return b + d + c; +} + +int -+negs_si_test3 (int a, int b, int c) ++subs_si_test2 (int a, int b, int c) +{ -+ int d = -(b) << 3; ++ int d = a - 0xfff; + -+ /* { dg-final { scan-assembler "negs\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */ -+ if (d == 0) ++ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, #4095" } } */ ++ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, #4095" } } */ ++ if (d <= 0) + return a + c; ++ else ++ return b + d + c; ++} + -+ z = d; -+ return b + c + d; ++int ++subs_si_test3 (int a, int b, int c) ++{ ++ int d = a - (b << 3); ++ ++ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} + +typedef long long s64; -+s64 zz; + +s64 -+negs_di_test1 (s64 a, s64 b, s64 c) ++subs_di_test1 (s64 a, s64 b, s64 c) +{ -+ s64 d = -b; ++ s64 d = a - b; + -+ /* { dg-final { scan-assembler "negs\tx\[0-9\]+, x\[0-9\]+" } } */ -+ if (d < 0) ++ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ if (d <= 0) + return a + c; -+ -+ zz = d; -+ return b + c + d; ++ else ++ return b + d + c; +} + +s64 -+negs_di_test3 (s64 a, s64 b, s64 c) ++subs_di_test2 (s64 a, s64 b, s64 c) +{ -+ s64 d = -(b) << 3; ++ s64 d = a - 0x1000ll; + -+ /* { dg-final { scan-assembler "negs\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */ -+ if (d == 0) ++ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, #4096" } } */ ++ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, #4096" } } */ ++ if (d <= 0) + return a + c; -+ -+ zz = d; -+ return b + c + d; ++ else ++ return b + d + c; ++} ++ ++s64 ++subs_di_test3 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a - (b << 3); ++ ++ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} + +int main () @@ -5196,106 +6102,190 @@ + int x; + s64 y; + -+ x = negs_si_test1 (2, 12, 5); -+ if (x != 7) ++ x = subs_si_test1 (29, 4, 5); ++ if (x != 34) + abort (); + -+ x = negs_si_test1 (1, 2, 32); -+ if (x != 33) ++ x = subs_si_test1 (5, 2, 20); ++ if (x != 25) + abort (); + -+ x = negs_si_test3 (13, 14, 5); -+ if (x != -93) ++ x = subs_si_test2 (29, 4, 5); ++ if (x != 34) + abort (); + -+ x = negs_si_test3 (15, 21, 2); -+ if (x != -145) ++ x = subs_si_test2 (1024, 2, 20); ++ if (x != 1044) + abort (); + -+ y = negs_di_test1 (0x20202020ll, -+ 0x65161611ll, -+ 0x42434243ll); -+ if (y != 0x62636263ll) ++ x = subs_si_test3 (35, 4, 5); ++ if (x != 12) + abort (); + -+ y = negs_di_test1 (0x1010101010101ll, -+ 0x123456789abcdll, -+ 0x5555555555555ll); -+ if (y != 0x6565656565656ll) ++ x = subs_si_test3 (5, 2, 20); ++ if (x != 25) + abort (); + -+ y = negs_di_test3 (0x62523781ll, -+ 0x64234978ll, -+ 0x12345123ll); -+ if (y != 0xfffffffd553d4edbll) ++ y = subs_di_test1 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ ++ if (y != 0x63505052e) + abort (); + -+ y = negs_di_test3 (0x763526268ll, -+ 0x101010101ll, -+ 0x222222222ll); -+ if (y != 0xfffffffb1b1b1b1bll) ++ y = subs_di_test1 (0x5000500050005ll, ++ 0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x5000500052025) ++ abort (); ++ ++ y = subs_di_test2 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != 0x95504f532) ++ abort (); ++ ++ y = subs_di_test2 (0x540004100ll, ++ 0x320000004ll, ++ 0x805050205ll); ++ if (y != 0x1065053309) ++ abort (); ++ ++ y = subs_di_test3 (0x130000029ll, ++ 0x064000008ll, ++ 0x505050505ll); ++ if (y != 0x63505052e) ++ abort (); ++ ++ y = subs_di_test3 (0x130002900ll, ++ 0x088000008ll, ++ 0x505050505ll); ++ if (y != 0x635052e05) + abort (); + + return 0; +} ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c -@@ -1,43 +1,7 @@ - /* { dg-do compile } */ - /* { dg-options "-O2" } */ - --int v = 0; -+#include "atomic-op-consume.x" - --int --atomic_fetch_add_CONSUME (int a) --{ -- return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME); --} -- --int --atomic_fetch_sub_CONSUME (int a) --{ -- return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME); --} -- --int --atomic_fetch_and_CONSUME (int a) --{ -- return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME); --} -- --int --atomic_fetch_nand_CONSUME (int a) --{ -- return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME); --} -- --int --atomic_fetch_xor_CONSUME (int a) --{ -- return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME); --} -- --int --atomic_fetch_or_CONSUME (int a) --{ -- return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME); --} -- - /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c -@@ -0,0 +1,128 @@ ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/bics_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/bics_1.c +@@ -0,0 +1,107 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++ ++extern void abort (void); ++ ++int ++bics_si_test1 (int a, int b, int c) ++{ ++ int d = a & ~b; ++ ++ /* { dg-final { scan-assembler-times "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int ++bics_si_test2 (int a, int b, int c) ++{ ++ int d = a & ~(b << 3); ++ ++ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++typedef long long s64; ++ ++s64 ++bics_di_test1 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & ~b; ++ ++ /* { dg-final { scan-assembler-times "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++s64 ++bics_di_test2 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & ~(b << 3); ++ ++ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int ++main () ++{ ++ int x; ++ s64 y; ++ ++ x = bics_si_test1 (29, ~4, 5); ++ if (x != ((29 & 4) + ~4 + 5)) ++ abort (); ++ ++ x = bics_si_test1 (5, ~2, 20); ++ if (x != 25) ++ abort (); ++ ++ x = bics_si_test2 (35, ~4, 5); ++ if (x != ((35 & ~(~4 << 3)) + ~4 + 5)) ++ abort (); ++ ++ x = bics_si_test2 (96, ~2, 20); ++ if (x != 116) ++ abort (); ++ ++ y = bics_di_test1 (0x130000029ll, ++ ~0x320000004ll, ++ 0x505050505ll); ++ ++ if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll)) ++ abort (); ++ ++ y = bics_di_test1 (0x5000500050005ll, ++ ~0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x5000500052025ll) ++ abort (); ++ ++ y = bics_di_test2 (0x130000029ll, ++ ~0x064000008ll, ++ 0x505050505ll); ++ if (y != ((0x130000029ll & ~(~0x064000008ll << 3)) ++ + ~0x064000008ll + 0x505050505ll)) ++ abort (); ++ ++ y = bics_di_test2 (0x130002900ll, ++ ~0x088000008ll, ++ 0x505050505ll); ++ if (y != (0x130002900ll + 0x505050505ll)) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c +@@ -0,0 +1,117 @@ +/* { dg-do run } */ +/* { dg-options "-O3 --save-temps -ffast-math" } */ + +#include + +extern void abort (void); -+extern float fabsf (float); -+extern double fabs (double); + +#define NUM_TESTS 16 +#define DELTA 0.000001 @@ -5306,8 +6296,6 @@ + -4, 34, 110, -110, 6, 4, 75, -34}; +int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76, + -4, 34, 110, -110, 6, 4, 75, -34}; -+int64_t input_int64[] = {1, 56, 2, -9, -90, 23, 54, 76, -+ -4, 34, 110, -110, 6, 4, 75, -34}; + +uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76, + 4, 34, 110, 110, 6, 4, 75, 34}; @@ -5316,26 +6304,11 @@ +uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76, + 4, 34, 110, 110, 6, 4, 75, 34}; + -+uint64_t input_uint64[] = {1, 56, 2, 9, 90, 23, 54, 76, -+ 4, 34, 110, 110, 6, 4, 75, 34}; -+ -+float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f, -+ 200.0f, -800.0f, -13.0f, -0.5f, -+ 7.9f, -870.0f, 10.4f, 310.11f, -+ 0.0f, -865.0f, -2213.0f, -1.5f}; -+ -+double input_float64[] = {0.1, -0.1, 0.4, 10.3, -+ 200.0, -800.0, -13.0, -0.5, -+ 7.9, -870.0, 10.4, 310.11, -+ 0.0, -865.0, -2213.0, -1.5}; -+ -+#define EQUALF(a, b) (fabsf (a - b) < DELTA) -+#define EQUALD(a, b) (fabs (a - b) < DELTA) -+#define EQUALL(a, b) (a == b) ++#define EQUAL(a, b) (a == b) + -+#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT) \ ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES) \ +int \ -+test_vaddv##SUFFIX##_##TYPE##x##LANES##_t (void) \ ++test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \ +{ \ + int i, j; \ + int moves = (NUM_TESTS - LANES) + 1; \ @@ -5346,1617 +6319,1841 @@ + for (i = 0; i < moves; i++) \ + { \ + out_l[i] = input_##TYPE[i]; \ -+ for (j = 1; j < LANES; j++) \ -+ out_l[i] += input_##TYPE[i + j]; \ ++ for (j = 0; j < LANES; j++) \ ++ out_l[i] = input_##TYPE[i + j] CMP_OP out_l[i] ? \ ++ input_##TYPE[i + j] : out_l[i]; \ + } \ + \ + /* Calculate using vector reduction intrinsics. */ \ + for (i = 0; i < moves; i++) \ + { \ + TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ -+ out_v[i] = vaddv##Q##_##SUFFIX (t1); \ ++ out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1); \ + } \ + \ + /* Compare. */ \ + for (i = 0; i < moves; i++) \ + { \ -+ if (!EQUAL##FLOAT (out_v[i], out_l[i])) \ ++ if (!EQUAL (out_v[i], out_l[i])) \ + return 0; \ + } \ + return 1; \ +} + -+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F) \ -+TEST (STYPE, , TYPE, W32, F) \ -+TEST (STYPE, q, TYPE, W64, F) \ ++#define BUILD_VARIANTS(TYPE, STYPE, W32, W64) \ ++TEST (max, >, STYPE, , TYPE, W32) \ ++TEST (max, >, STYPE, q, TYPE, W64) \ ++TEST (min, <, STYPE, , TYPE, W32) \ ++TEST (min, <, STYPE, q, TYPE, W64) + -+BUILD_VARIANTS (int8, s8, 8, 16, L) -+BUILD_VARIANTS (uint8, u8, 8, 16, L) -+/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ -+/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ -+BUILD_VARIANTS (int16, s16, 4, 8, L) -+BUILD_VARIANTS (uint16, u16, 4, 8, L) -+/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ -+/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ -+BUILD_VARIANTS (int32, s32, 2, 4, L) -+BUILD_VARIANTS (uint32, u32, 2, 4, L) -+/* { dg-final { scan-assembler "addp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "addv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ -+TEST (s64, q, int64, 2, D) -+TEST (u64, q, uint64, 2, D) -+/* { dg-final { scan-assembler "addp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */ -+ -+BUILD_VARIANTS (float32, f32, 2, 4, F) -+/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "faddp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+TEST (f64, q, float64, 2, D) -+/* { dg-final { scan-assembler "faddp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (int8, s8, 8, 16) ++/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++BUILD_VARIANTS (uint8, u8, 8, 16) ++/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++BUILD_VARIANTS (int16, s16, 4, 8) ++/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++BUILD_VARIANTS (uint16, u16, 4, 8) ++/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++BUILD_VARIANTS (int32, s32, 2, 4) ++/* { dg-final { scan-assembler "smaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "sminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "smaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "sminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++BUILD_VARIANTS (uint32, u32, 2, 4) ++/* { dg-final { scan-assembler "umaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "uminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "umaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "uminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ + +#undef TEST -+#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT) \ -+{ \ -+ if (!test_vaddv##SUFFIX##_##TYPE##x##LANES##_t ()) \ -+ abort (); \ ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES) \ ++{ \ ++ if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ()) \ ++ abort (); \ +} + +int +main (int argc, char **argv) +{ -+BUILD_VARIANTS (int8, s8, 8, 16, L) -+BUILD_VARIANTS (uint8, u8, 8, 16, L) -+BUILD_VARIANTS (int16, s16, 4, 8, L) -+BUILD_VARIANTS (uint16, u16, 4, 8, L) -+BUILD_VARIANTS (int32, s32, 2, 4, L) -+BUILD_VARIANTS (uint32, u32, 2, 4, L) -+ -+BUILD_VARIANTS (float32, f32, 2, 4, F) -+TEST (f64, q, float64, 2, D) -+ ++ BUILD_VARIANTS (int8, s8, 8, 16) ++ BUILD_VARIANTS (uint8, u8, 8, 16) ++ BUILD_VARIANTS (int16, s16, 4, 8) ++ BUILD_VARIANTS (uint16, u16, 4, 8) ++ BUILD_VARIANTS (int32, s32, 2, 4) ++ BUILD_VARIANTS (uint32, u32, 2, 4) + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c -@@ -1,43 +1,7 @@ - /* { dg-do compile } */ - /* { dg-options "-O2" } */ - --char v = 0; -+#include "atomic-op-char.x" - --char --atomic_fetch_add_RELAXED (char a) --{ -- return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); --} -- --char --atomic_fetch_sub_RELAXED (char a) --{ -- return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); --} -- --char --atomic_fetch_and_RELAXED (char a) --{ -- return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); --} -- --char --atomic_fetch_nand_RELAXED (char a) --{ -- return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); --} -- --char --atomic_fetch_xor_RELAXED (char a) --{ -- return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); --} -- --char --atomic_fetch_or_RELAXED (char a) --{ -- return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); --} -- - /* { dg-final { scan-assembler-times "ldxrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stxrb\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x -@@ -0,0 +1,37 @@ -+int v = 0; -+ -+int -+atomic_fetch_add_RELAXED (int a) -+{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -+} +--- a/src/gcc/testsuite/gcc.target/aarch64/vrecpx.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vrecpx.c +@@ -0,0 +1,54 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps" } */ + -+int -+atomic_fetch_sub_RELAXED (int a) -+{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -+} ++#include ++#include ++#include + -+int -+atomic_fetch_and_RELAXED (int a) -+{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -+} ++float32_t in_f[] = ++{2.0, 4.0, 8.0, 16.0, 1.0, 0.5, 0.25, 0.125}; ++float32_t rec_f[] = ++{1.0, 0.5, 0.25, 0.125, 2.0, 4.0, 8.0, 16.0}; ++float64_t in_d[] = ++{2.0, 4.0, 8.0, 16.0, 1.0, 0.5, 0.25, 0.125}; ++float32_t rec_d[] = ++{1.0, 0.5, 0.25, 0.125, 2.0, 4.0, 8.0, 16.0}; + +int -+atomic_fetch_nand_RELAXED (int a) ++test_frecpx_float32_t (void) +{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -+} ++ int i = 0; ++ int ret = 1; ++ for (i = 0; i < 8; i++) ++ ret &= fabs (vrecpxs_f32 (in_f[i]) - rec_f[i]) < 0.001; + -+int -+atomic_fetch_xor_RELAXED (int a) -+{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); ++ return ret; +} + -+int -+atomic_fetch_or_RELAXED (int a) -+{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -+} ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x -@@ -0,0 +1,37 @@ -+int v = 0; ++/* { dg-final { scan-assembler "frecpx\\ts\[0-9\]+, s\[0-9\]+" } } */ + +int -+atomic_fetch_add_SEQ_CST (int a) ++test_frecpx_float64_t (void) +{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST); -+} ++ int i = 0; ++ int ret = 1; ++ for (i = 0; i < 8; i++) ++ ret &= fabs (vrecpxd_f64 (in_d[i]) - rec_d[i]) < 0.001; + -+int -+atomic_fetch_sub_SEQ_CST (int a) -+{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST); ++ return ret; +} + -+int -+atomic_fetch_and_SEQ_CST (int a) -+{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST); -+} ++/* { dg-final { scan-assembler "frecpx\\td\[0-9\]+, d\[0-9\]+" } } */ + +int -+atomic_fetch_nand_SEQ_CST (int a) ++main (int argc, char **argv) +{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST); -+} ++ if (!test_frecpx_float32_t ()) ++ abort (); ++ if (!test_frecpx_float64_t ()) ++ abort (); + -+int -+atomic_fetch_xor_SEQ_CST (int a) -+{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST); ++ return 0; +} + -+int -+atomic_fetch_or_SEQ_CST (int a) -+{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); -+} ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x -@@ -0,0 +1,37 @@ -+int v = 0; ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vca.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vca.c +@@ -0,0 +1,89 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps" } */ + -+int -+atomic_fetch_add_CONSUME (int a) -+{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME); -+} ++#include + -+int -+atomic_fetch_sub_CONSUME (int a) -+{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME); -+} ++extern void abort (void); ++extern float fabsf (float); ++extern double fabs (double); + -+int -+atomic_fetch_and_CONSUME (int a) -+{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME); -+} ++#define NUM_TESTS 8 + -+int -+atomic_fetch_nand_CONSUME (int a) -+{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME); -+} ++float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f}; ++float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f}; ++double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5}; ++double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5}; + -+int -+atomic_fetch_xor_CONSUME (int a) ++#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F) \ ++int \ ++test_vca##T##_float##WIDTH##x##LANES##_t (void) \ ++{ \ ++ int ret = 0; \ ++ int i = 0; \ ++ uint##WIDTH##_t output[NUM_TESTS]; \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ { \ ++ float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]); \ ++ float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]); \ ++ /* Inhibit optimization of our linear test loop. */ \ ++ asm volatile ("" : : : "memory"); \ ++ output[i] = f1 CMP f2 ? -1 : 0; \ ++ } \ ++ \ ++ for (i = 0; i < NUM_TESTS; i += LANES) \ ++ { \ ++ float##WIDTH##x##LANES##_t in1 = \ ++ vld1##Q##_f##WIDTH (input_##SUFFIX##1 + i); \ ++ float##WIDTH##x##LANES##_t in2 = \ ++ vld1##Q##_f##WIDTH (input_##SUFFIX##2 + i); \ ++ uint##WIDTH##x##LANES##_t expected_out = \ ++ vld1##Q##_u##WIDTH (output + i); \ ++ uint##WIDTH##x##LANES##_t out = \ ++ veor##Q##_u##WIDTH (vca##T##Q##_f##WIDTH (in1, in2), \ ++ expected_out); \ ++ vst1##Q##_u##WIDTH (output + i, out); \ ++ } \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ ret |= output[i]; \ ++ \ ++ return ret; \ ++} ++ ++#define BUILD_VARIANTS(T, CMP) \ ++TEST (T, CMP, s, 32, 2, , f) \ ++TEST (T, CMP, s, 32, 4, q, f) \ ++TEST (T, CMP, d, 64, 2, q, ) ++ ++BUILD_VARIANTS (ge, >=) ++/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++ ++BUILD_VARIANTS (gt, >) ++/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++ ++/* No need for another scan-assembler as these tests ++ also generate facge, facgt instructions. */ ++BUILD_VARIANTS (le, <=) ++BUILD_VARIANTS (lt, <) ++ ++#undef TEST ++#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F) \ ++if (test_vca##T##_float##WIDTH##x##LANES##_t ()) \ ++ abort (); ++ ++int ++main (int argc, char **argv) +{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME); ++BUILD_VARIANTS (ge, >=) ++BUILD_VARIANTS (gt, >) ++BUILD_VARIANTS (le, <=) ++BUILD_VARIANTS (lt, <) ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c +@@ -0,0 +1,117 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps" } */ ++ ++#include ++ ++extern void abort (void); ++extern float fabsf (float); ++extern double fabs (double); ++ ++extern double trunc (double); ++extern double round (double); ++extern double nearbyint (double); ++extern double floor (double); ++extern double ceil (double); ++extern double rint (double); ++ ++extern float truncf (float); ++extern float roundf (float); ++extern float nearbyintf (float); ++extern float floorf (float); ++extern float ceilf (float); ++extern float rintf (float); ++ ++#define NUM_TESTS 8 ++#define DELTA 0.000001 ++ ++float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f, ++ 200.0f, -800.0f, -13.0f, -0.5f}; ++double input_f64[] = {0.1, -0.1, 0.4, 10.3, ++ 200.0, -800.0, -13.0, -0.5}; ++ ++#define TEST(SUFFIX, Q, WIDTH, LANES, C_FN, F) \ ++int \ ++test_vrnd##SUFFIX##_float##WIDTH##x##LANES##_t (void) \ ++{ \ ++ int ret = 1; \ ++ int i = 0; \ ++ int nlanes = LANES; \ ++ float##WIDTH##_t expected_out[NUM_TESTS]; \ ++ float##WIDTH##_t actual_out[NUM_TESTS]; \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ { \ ++ expected_out[i] = C_FN##F (input_f##WIDTH[i]); \ ++ /* Don't vectorize this. */ \ ++ asm volatile ("" : : : "memory"); \ ++ } \ ++ \ ++ /* Prevent the compiler from noticing these two loops do the same \ ++ thing and optimizing away the comparison. */ \ ++ asm volatile ("" : : : "memory"); \ ++ \ ++ for (i = 0; i < NUM_TESTS; i+=nlanes) \ ++ { \ ++ float##WIDTH##x##LANES##_t out = \ ++ vrnd##SUFFIX##Q##_f##WIDTH \ ++ (vld1##Q##_f##WIDTH (input_f##WIDTH + i)); \ ++ vst1##Q##_f##WIDTH (actual_out + i, out); \ ++ } \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ ret &= fabs##F (expected_out[i] - actual_out[i]) < DELTA; \ ++ \ ++ return ret; \ ++} \ ++ ++ ++#define BUILD_VARIANTS(SUFFIX, C_FN) \ ++TEST (SUFFIX, , 32, 2, C_FN, f) \ ++TEST (SUFFIX, q, 32, 4, C_FN, f) \ ++TEST (SUFFIX, q, 64, 2, C_FN, ) \ ++ ++BUILD_VARIANTS ( , trunc) ++/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (a, round) ++/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (i, nearbyint) ++/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (m, floor) ++/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (p, ceil) ++/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (x, rint) ++/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++ ++#undef TEST ++#define TEST(SUFFIX, Q, WIDTH, LANES, C_FN, F) \ ++{ \ ++ if (!test_vrnd##SUFFIX##_float##WIDTH##x##LANES##_t ()) \ ++ abort (); \ +} + +int -+atomic_fetch_or_CONSUME (int a) ++main (int argc, char **argv) +{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME); ++ BUILD_VARIANTS ( , trunc) ++ BUILD_VARIANTS (a, round) ++ BUILD_VARIANTS (i, nearbyint) ++ BUILD_VARIANTS (m, floor) ++ BUILD_VARIANTS (p, ceil) ++ BUILD_VARIANTS (x, rint) ++ return 0; +} ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ --short v = 0; -+#include "atomic-op-short.x" +-int v = 0; ++#include "atomic-op-relaxed.x" --short --atomic_fetch_add_RELAXED (short a) +-int +-atomic_fetch_add_RELAXED (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - --short --atomic_fetch_sub_RELAXED (short a) +-int +-atomic_fetch_sub_RELAXED (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - --short --atomic_fetch_and_RELAXED (short a) +-int +-atomic_fetch_and_RELAXED (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - --short --atomic_fetch_nand_RELAXED (short a) +-int +-atomic_fetch_nand_RELAXED (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - --short --atomic_fetch_xor_RELAXED (short a) +-int +-atomic_fetch_xor_RELAXED (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - --short --atomic_fetch_or_RELAXED (short a) +-int +-atomic_fetch_or_RELAXED (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} - - /* { dg-final { scan-assembler-times "ldxrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stxrh\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x -@@ -0,0 +1,37 @@ -+char v = 0; + /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm.x +@@ -13,6 +13,8 @@ + 2.0, -4.0, 8.0, -16.0, + -2.125, 4.25, -8.5, 17.0}; + ++/* Float comparisons, float results. */ + -+char -+atomic_fetch_add_RELAXED (char a) + void + foo (FTYPE *in1, FTYPE *in2, FTYPE *output) + { +@@ -49,11 +51,52 @@ + output[i] = (in1[i] INV_OP 0.0) ? 4.0 : 2.0; + } + ++/* Float comparisons, int results. */ ++ ++void ++foo_int (FTYPE *in1, FTYPE *in2, ITYPE *output) +{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = (in1[i] OP in2[i]) ? 2 : 4; +} + -+char -+atomic_fetch_sub_RELAXED (char a) ++void ++bar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) +{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = (in1[i] INV_OP in2[i]) ? 4 : 2; +} + -+char -+atomic_fetch_and_RELAXED (char a) ++void ++foobar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) +{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = (in1[i] OP 0.0) ? 4 : 2; +} + -+char -+atomic_fetch_nand_RELAXED (char a) ++void ++foobarbar_int (FTYPE *in1, FTYPE *in2, ITYPE *output) +{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); ++ int i = 0; ++ /* Vectorizable. */ ++ for (i = 0; i < N; i++) ++ output[i] = (in1[i] INV_OP 0.0) ? 4 : 2; +} + -+char -+atomic_fetch_xor_RELAXED (char a) -+{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -+} + int + main (int argc, char **argv) + { + FTYPE out1[N]; + FTYPE out2[N]; ++ ITYPE outi1[N]; ++ ITYPE outi2[N]; + -+char -+atomic_fetch_or_RELAXED (char a) + int i = 0; + foo (input1, input2, out1); + bar (input1, input2, out2); +@@ -65,6 +108,17 @@ + for (i = 0; i < N; i++) + if (out1[i] == out2[i]) + abort (); ++ ++ foo_int (input1, input2, outi1); ++ bar_int (input1, input2, outi2); ++ for (i = 0; i < N; i++) ++ if (outi1[i] != outi2[i]) ++ abort (); ++ foobar_int (input1, input2, outi1); ++ foobarbar_int (input1, input2, outi2); ++ for (i = 0; i < N; i++) ++ if (outi1[i] == outi2[i]) ++ abort (); + return 0; + } + +--- a/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c +@@ -0,0 +1,11 @@ ++ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++ ++#include "arm_neon.h" ++ ++#include "vaddv-intrinsic.x" ++ ++/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+"} } */ ++/* { dg-final { scan-assembler-times "faddp\\tv\[0-9\]+\.4s" 2} } */ ++/* { dg-final { scan-assembler "faddp\\td\[0-9\]+"} } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/movi_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/movi_1.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++void ++dummy (short* b) +{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); ++ /* { dg-final { scan-assembler "movi\tv\[0-9\]+\.4h, 0x4, lsl 8" } } */ ++ /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 0x400" } } */ ++ /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 1024" } } */ ++ register short x asm ("h8") = 1024; ++ asm volatile ("" : : "w" (x)); ++ *b = x; +} ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c -@@ -11,3 +11,4 @@ - /* { dg-final { scan-assembler "fdiv\\tv" } } */ - /* { dg-final { scan-assembler "fneg\\tv" } } */ - /* { dg-final { scan-assembler "fabs\\tv" } } */ -+/* { dg-final { scan-assembler "fabd\\tv" } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c -@@ -2,12 +2,13 @@ - /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ - - #define FTYPE float -+#define ITYPE int - #define OP == - #define INV_OP != - - #include "vect-fcm.x" - --/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ - /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ - /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ - /* { dg-final { cleanup-tree-dump "vect" } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/adds1.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/adds1.c -@@ -0,0 +1,149 @@ +--- a/src/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c +@@ -0,0 +1,101 @@ +/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-options "-O3 --save-temps" } */ ++ ++#include + +extern void abort (void); + ++#define ETYPE(size) int##size##_t ++#define VTYPE(size, lanes) int##size##x##lanes##_t ++ ++#define TEST_VABS(q, size, lanes) \ ++static void \ ++test_vabs##q##_##size (ETYPE (size) * res, \ ++ const ETYPE (size) *in1) \ ++{ \ ++ VTYPE (size, lanes) a = vld1##q##_s##size (res); \ ++ VTYPE (size, lanes) b = vld1##q##_s##size (in1); \ ++ a = vabs##q##_s##size (b); \ ++ vst1##q##_s##size (res, a); \ ++} ++ ++#define BUILD_VARS(width, n_lanes, n_half_lanes) \ ++TEST_VABS (, width, n_half_lanes) \ ++TEST_VABS (q, width, n_lanes) \ ++ ++BUILD_VARS (64, 2, 1) ++BUILD_VARS (32, 4, 2) ++BUILD_VARS (16, 8, 4) ++BUILD_VARS (8, 16, 8) ++ ++#define POOL1 {-10} ++#define POOL2 {2, -10} ++#define POOL4 {0, -10, 2, -3} ++#define POOL8 {0, -10, 2, -3, 4, -50, 6, -70} ++#define POOL16 {0, -10, 2, -3, 4, -50, 6, -70, \ ++ -5, 10, -2, 3, -4, 50, -6, 70} ++ ++#define EXPECTED1 {10} ++#define EXPECTED2 {2, 10} ++#define EXPECTED4 {0, 10, 2, 3} ++#define EXPECTED8 {0, 10, 2, 3, 4, 50, 6, 70} ++#define EXPECTED16 {0, 10, 2, 3, 4, 50, 6, 70, \ ++ 5, 10, 2, 3, 4, 50, 6, 70} ++ ++#define BUILD_TEST(size, lanes_64, lanes_128) \ ++static void \ ++test_##size (void) \ ++{ \ ++ int i; \ ++ ETYPE (size) pool1[lanes_64] = POOL##lanes_64; \ ++ ETYPE (size) res1[lanes_64] = {0}; \ ++ ETYPE (size) expected1[lanes_64] = EXPECTED##lanes_64; \ ++ ETYPE (size) pool2[lanes_128] = POOL##lanes_128; \ ++ ETYPE (size) res2[lanes_128] = {0}; \ ++ ETYPE (size) expected2[lanes_128] = EXPECTED##lanes_128; \ ++ \ ++ /* Forcefully avoid optimization. */ \ ++ asm volatile ("" : : : "memory"); \ ++ test_vabs_##size (res1, pool1); \ ++ for (i = 0; i < lanes_64; i++) \ ++ if (res1[i] != expected1[i]) \ ++ abort (); \ ++ \ ++ /* Forcefully avoid optimization. */ \ ++ asm volatile ("" : : : "memory"); \ ++ test_vabsq_##size (res2, pool2); \ ++ for (i = 0; i < lanes_128; i++) \ ++ if (res2[i] != expected2[i]) \ ++ abort (); \ ++} ++ ++/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */ ++/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ ++BUILD_TEST (8 , 8, 16) ++ ++/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */ ++/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */ ++BUILD_TEST (16, 4, 8) ++ ++/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */ ++/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */ ++BUILD_TEST (32, 2, 4) ++ ++/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */ ++BUILD_TEST (64, 1, 2) ++ ++#undef BUILD_TEST ++ ++#define BUILD_TEST(size) test_##size () ++ +int -+adds_si_test1 (int a, int b, int c) ++main (int argc, char **argv) +{ -+ int d = a + b; -+ -+ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; ++ BUILD_TEST (8); ++ BUILD_TEST (16); ++ BUILD_TEST (32); ++ BUILD_TEST (64); ++ return 0; +} + ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x +@@ -0,0 +1,37 @@ ++int v = 0; ++ +int -+adds_si_test2 (int a, int b, int c) ++atomic_fetch_add_RELAXED (int a) +{ -+ int d = a + 0xff; ++ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); ++} + -+ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, 255" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; ++int ++atomic_fetch_sub_RELAXED (int a) ++{ ++ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +int -+adds_si_test3 (int a, int b, int c) ++atomic_fetch_and_RELAXED (int a) +{ -+ int d = a + (b << 3); ++ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); ++} + -+ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; ++int ++atomic_fetch_nand_RELAXED (int a) ++{ ++ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + -+typedef long long s64; ++int ++atomic_fetch_xor_RELAXED (int a) ++{ ++ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); ++} + -+s64 -+adds_di_test1 (s64 a, s64 b, s64 c) ++int ++atomic_fetch_or_RELAXED (int a) +{ -+ s64 d = a + b; ++ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/vect.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect.c +@@ -55,6 +55,8 @@ + int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15}; + unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; + unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; ++ int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; ++ int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int reduce_smax_value = 0; + int reduce_smin_value = -15; + unsigned int reduce_umax_value = 15; +@@ -81,6 +83,8 @@ + TEST (smin, s); + TEST (umax, u); + TEST (umin, u); ++ TEST (sabd, s); ++ TEST (saba, s); + TESTV (reduce_smax, s); + TESTV (reduce_smin, s); + TESTV (reduce_umax, u); +--- a/src/gcc/testsuite/gcc.target/aarch64/scalar-mov.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/scalar-mov.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-g -mgeneral-regs-only" } */ + -+ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; ++void ++foo (const char *c, ...) ++{ ++ char buf[256]; ++ buf[256 - 1] = '\0'; +} +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-movi.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-movi.c +@@ -0,0 +1,74 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps -fno-inline" } */ + -+s64 -+adds_di_test2 (s64 a, s64 b, s64 c) ++extern void abort (void); ++ ++#define N 16 ++ ++static void ++movi_msl8 (int *__restrict a) +{ -+ s64 d = a + 0xff; ++ int i; + -+ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, 255" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; ++ /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */ ++ for (i = 0; i < N; i++) ++ a[i] = 0xabff; +} + -+s64 -+adds_di_test3 (s64 a, s64 b, s64 c) ++static void ++movi_msl16 (int *__restrict a) +{ -+ s64 d = a + (b << 3); ++ int i; + -+ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; ++ /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */ ++ for (i = 0; i < N; i++) ++ a[i] = 0xabffff; +} + -+int main () ++static void ++mvni_msl8 (int *__restrict a) +{ -+ int x; -+ s64 y; ++ int i; + -+ x = adds_si_test1 (29, 4, 5); -+ if (x != 42) -+ abort (); ++ /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */ ++ for (i = 0; i < N; i++) ++ a[i] = 0xffff5400; ++} + -+ x = adds_si_test1 (5, 2, 20); -+ if (x != 29) -+ abort (); -+ -+ x = adds_si_test2 (29, 4, 5); -+ if (x != 293) -+ abort (); -+ -+ x = adds_si_test2 (1024, 2, 20); -+ if (x != 1301) -+ abort (); -+ -+ x = adds_si_test3 (35, 4, 5); -+ if (x != 76) -+ abort (); -+ -+ x = adds_si_test3 (5, 2, 20); -+ if (x != 43) -+ abort (); ++static void ++mvni_msl16 (int *__restrict a) ++{ ++ int i; + -+ y = adds_di_test1 (0x130000029ll, -+ 0x320000004ll, -+ 0x505050505ll); ++ /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */ ++ for (i = 0; i < N; i++) ++ a[i] = 0xff540000; ++} + -+ if (y != 0xc75050536) -+ abort (); ++int ++main (void) ++{ ++ int a[N] = { 0 }; ++ int i; + -+ y = adds_di_test1 (0x5000500050005ll, -+ 0x2111211121112ll, -+ 0x0000000002020ll); -+ if (y != 0x9222922294249) -+ abort (); ++#define CHECK_ARRAY(a, val) \ ++ for (i = 0; i < N; i++) \ ++ if (a[i] != val) \ ++ abort (); + -+ y = adds_di_test2 (0x130000029ll, -+ 0x320000004ll, -+ 0x505050505ll); -+ if (y != 0x955050631) -+ abort (); ++ movi_msl8 (a); ++ CHECK_ARRAY (a, 0xabff); + -+ y = adds_di_test2 (0x130002900ll, -+ 0x320000004ll, -+ 0x505050505ll); -+ if (y != 0x955052f08) -+ abort (); ++ movi_msl16 (a); ++ CHECK_ARRAY (a, 0xabffff); + -+ y = adds_di_test3 (0x130000029ll, -+ 0x064000008ll, -+ 0x505050505ll); -+ if (y != 0x9b9050576) -+ abort (); ++ mvni_msl8 (a); ++ CHECK_ARRAY (a, 0xffff5400); + -+ y = adds_di_test3 (0x130002900ll, -+ 0x088000008ll, -+ 0x505050505ll); -+ if (y != 0xafd052e4d) -+ abort (); ++ mvni_msl16 (a); ++ CHECK_ARRAY (a, 0xff540000); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/insv_1.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/insv_1.c -@@ -0,0 +1,84 @@ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE double ++#define ITYPE long + #define OP >= + #define INV_OP < + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ + /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ + /* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c +@@ -1,43 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2" } */ + +-int v = 0; ++#include "atomic-op-acquire.x" + +-int +-atomic_fetch_add_ACQUIRE (int a) +-{ +- return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE); +-} +- +-int +-atomic_fetch_sub_ACQUIRE (int a) +-{ +- return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE); +-} +- +-int +-atomic_fetch_and_ACQUIRE (int a) +-{ +- return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE); +-} +- +-int +-atomic_fetch_nand_ACQUIRE (int a) +-{ +- return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE); +-} +- +-int +-atomic_fetch_xor_ACQUIRE (int a) +-{ +- return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE); +-} +- +-int +-atomic_fetch_or_ACQUIRE (int a) +-{ +- return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE); +-} +- + /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/abs_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/abs_1.c +@@ -0,0 +1,53 @@ +/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-options "-O2 -fno-inline --save-temps" } */ + ++extern long long llabs (long long); +extern void abort (void); + -+typedef struct bitfield -+{ -+ unsigned short eight: 8; -+ unsigned short four: 4; -+ unsigned short five: 5; -+ unsigned short seven: 7; -+ unsigned int sixteen: 16; -+} bitfield; -+ -+bitfield -+bfi1 (bitfield a) -+{ -+ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 0, 8" } } */ -+ a.eight = 3; -+ return a; -+} -+ -+bitfield -+bfi2 (bitfield a) -+{ -+ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 16, 5" } } */ -+ a.five = 7; -+ return a; -+} -+ -+bitfield -+movk (bitfield a) -+{ -+ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 32" } } */ -+ a.sixteen = 7531; -+ return a; -+} -+ -+bitfield -+set1 (bitfield a) ++long long ++abs64 (long long a) +{ -+ /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 2031616" } } */ -+ a.five = 0x1f; -+ return a; ++ /* { dg-final { scan-assembler "eor\t" } } */ ++ /* { dg-final { scan-assembler "sub\t" } } */ ++ return llabs (a); +} + -+bitfield -+set0 (bitfield a) ++long long ++abs64_in_dreg (long long a) +{ -+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -2031617" } } */ -+ a.five = 0; -+ return a; ++ /* { dg-final { scan-assembler "abs\td\[0-9\]+, d\[0-9\]+" } } */ ++ register long long x asm ("d8") = a; ++ register long long y asm ("d9"); ++ asm volatile ("" : : "w" (x)); ++ y = llabs (x); ++ asm volatile ("" : : "w" (y)); ++ return y; +} + -+ +int -+main (int argc, char** argv) ++main (void) +{ -+ static bitfield a; -+ bitfield b = bfi1 (a); -+ bitfield c = bfi2 (b); -+ bitfield d = movk (c); ++ volatile long long ll0 = 0LL, ll1 = 1LL, llm1 = -1LL; + -+ if (d.eight != 3) ++ if (abs64 (ll0) != 0LL) + abort (); + -+ if (d.five != 7) ++ if (abs64 (ll1) != 1LL) + abort (); + -+ if (d.sixteen != 7531) ++ if (abs64 (llm1) != 1LL) + abort (); + -+ d = set1 (d); -+ if (d.five != 0x1f) ++ if (abs64_in_dreg (ll0) != 0LL) + abort (); + -+ d = set0 (d); -+ if (d.five != 0) ++ if (abs64_in_dreg (ll1) != 1LL) + abort (); + -+ return 0; -+} -+ -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/ror.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/ror.c -@@ -0,0 +1,34 @@ -+/* { dg-options "-O2 --save-temps" } */ -+/* { dg-do run } */ -+ -+extern void abort (void); -+ -+int -+test_si (int a) -+{ -+ /* { dg-final { scan-assembler "ror\tw\[0-9\]+, w\[0-9\]+, 27\n" } } */ -+ return (a << 5) | ((unsigned int) a >> 27); -+} -+ -+long long -+test_di (long long a) -+{ -+ /* { dg-final { scan-assembler "ror\tx\[0-9\]+, x\[0-9\]+, 45\n" } } */ -+ return (a << 19) | ((unsigned long long) a >> 45); -+} ++ if (abs64_in_dreg (llm1) != 1LL) ++ abort (); + -+int -+main () -+{ -+ int v; -+ long long w; -+ v = test_si (0x0203050); -+ if (v != 0x4060a00) -+ abort(); -+ w = test_di (0x0000020506010304ll); -+ if (w != 0x1028300818200000ll) -+ abort(); + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c -@@ -1,43 +1,7 @@ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c +@@ -1,41 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ +-#define STRONG 0 +-#define WEAK 1 -int v = 0; -+#include "atomic-op-release.x" ++#include "atomic-comp-swap-release-acquire.x" -int --atomic_fetch_add_RELEASE (int a) +-atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b) -{ -- return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE); +- return __atomic_compare_exchange (&v, &a, &b, +- STRONG, __ATOMIC_RELEASE, +- __ATOMIC_ACQUIRE); -} - -int --atomic_fetch_sub_RELEASE (int a) +-atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b) -{ -- return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE); +- return __atomic_compare_exchange (&v, &a, &b, +- WEAK, __ATOMIC_RELEASE, +- __ATOMIC_ACQUIRE); -} - -int --atomic_fetch_and_RELEASE (int a) +-atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b) -{ -- return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE); +- return __atomic_compare_exchange_n (&v, &a, b, +- STRONG, __ATOMIC_RELEASE, +- __ATOMIC_ACQUIRE); -} - -int --atomic_fetch_nand_RELEASE (int a) +-atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b) -{ -- return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE); --} -- --int --atomic_fetch_xor_RELEASE (int a) --{ -- return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE); --} -- --int --atomic_fetch_or_RELEASE (int a) --{ -- return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE); +- return __atomic_compare_exchange_n (&v, &a, b, +- WEAK, __ATOMIC_RELEASE, +- __ATOMIC_ACQUIRE); -} - - /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c -@@ -0,0 +1,169 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 --save-temps -ffast-math" } */ -+ -+#include -+ -+extern void abort (void); -+ -+extern float fabsf (float); -+extern double fabs (double); -+extern int isnan (double); -+extern float fmaxf (float, float); -+extern float fminf (float, float); -+extern double fmax (double, double); -+extern double fmin (double, double); -+ -+#define NUM_TESTS 16 -+#define DELTA 0.000001 -+#define NAN (0.0 / 0.0) -+ -+float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f, -+ 200.0f, -800.0f, -13.0f, -0.5f, -+ NAN, -870.0f, 10.4f, 310.11f, -+ 0.0f, -865.0f, -2213.0f, -1.5f}; -+ -+double input_float64[] = {0.1, -0.1, 0.4, 10.3, -+ 200.0, -800.0, -13.0, -0.5, -+ NAN, -870.0, 10.4, 310.11, -+ 0.0, -865.0, -2213.0, -1.5}; -+ -+#define EQUALF(a, b) (fabsf (a - b) < DELTA) -+#define EQUALD(a, b) (fabs (a - b) < DELTA) -+ -+/* Floating point 'unordered' variants. */ + /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */ + /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect.x +@@ -138,3 +138,17 @@ + + return s; + } + -+#undef TEST -+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ -+int \ -+test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \ -+{ \ -+ int i, j; \ -+ int moves = (NUM_TESTS - LANES) + 1; \ -+ TYPE##_t out_l[NUM_TESTS]; \ -+ TYPE##_t out_v[NUM_TESTS]; \ -+ \ -+ /* Calculate linearly. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ out_l[i] = input_##TYPE[i]; \ -+ for (j = 0; j < LANES; j++) \ -+ { \ -+ if (isnan (out_l[i])) \ -+ continue; \ -+ if (isnan (input_##TYPE[i + j]) \ -+ || input_##TYPE[i + j] CMP_OP out_l[i]) \ -+ out_l[i] = input_##TYPE[i + j]; \ -+ } \ -+ } \ -+ \ -+ /* Calculate using vector reduction intrinsics. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ -+ out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1); \ -+ } \ -+ \ -+ /* Compare. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ if (!EQUAL##FLOAT (out_v[i], out_l[i]) \ -+ && !(isnan (out_v[i]) && isnan (out_l[i]))) \ -+ return 0; \ -+ } \ -+ return 1; \ ++void sabd (pRINT a, pRINT b, pRINT c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ c[i] = abs (a[i] - b[i]); +} + -+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F) \ -+TEST (max, >, STYPE, , TYPE, W32, F) \ -+TEST (max, >, STYPE, q, TYPE, W64, F) \ -+TEST (min, <, STYPE, , TYPE, W32, F) \ -+TEST (min, <, STYPE, q, TYPE, W64, F) ++void saba (pRINT a, pRINT b, pRINT c) ++{ ++ int i; ++ for (i = 0; i < 16; i++) ++ c[i] += abs (a[i] - b[i]); ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-clz.c +@@ -0,0 +1,35 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 -save-temps -fno-inline" } */ + -+BUILD_VARIANTS (float32, f32, 2, 4, F) -+/* { dg-final { scan-assembler "fmaxp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fminp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fmaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ -+TEST (max, >, f64, q, float64, 2, D) -+/* { dg-final { scan-assembler "fmaxp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ -+TEST (min, <, f64, q, float64, 2, D) -+/* { dg-final { scan-assembler "fminp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ ++extern void abort (); + -+/* Floating point 'nm' variants. */ ++void ++count_lz_v4si (unsigned *__restrict a, int *__restrict b) ++{ ++ int i; + -+#undef TEST -+#define TEST(MAXMIN, F, SUFFIX, Q, TYPE, LANES, FLOAT) \ -+int \ -+test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t (void) \ -+{ \ -+ int i, j; \ -+ int moves = (NUM_TESTS - LANES) + 1; \ -+ TYPE##_t out_l[NUM_TESTS]; \ -+ TYPE##_t out_v[NUM_TESTS]; \ -+ \ -+ /* Calculate linearly. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ out_l[i] = input_##TYPE[i]; \ -+ for (j = 0; j < LANES; j++) \ -+ out_l[i] = f##MAXMIN##F (input_##TYPE[i + j], out_l[i]); \ -+ } \ -+ \ -+ /* Calculate using vector reduction intrinsics. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ -+ out_v[i] = v##MAXMIN##nmv##Q##_##SUFFIX (t1); \ -+ } \ -+ \ -+ /* Compare. */ \ -+ for (i = 0; i < moves; i++) \ -+ { \ -+ if (!EQUAL##FLOAT (out_v[i], out_l[i])) \ -+ return 0; \ -+ } \ -+ return 1; \ ++ for (i = 0; i < 4; i++) ++ b[i] = __builtin_clz (a[i]); +} + -+TEST (max, f, f32, , float32, 2, D) -+/* { dg-final { scan-assembler "fmaxnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ -+TEST (min, f, f32, , float32, 2, D) -+/* { dg-final { scan-assembler "fminnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ -+TEST (max, f, f32, q, float32, 4, D) -+/* { dg-final { scan-assembler "fmaxnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ -+TEST (min, f, f32, q, float32, 4, D) -+/* { dg-final { scan-assembler "fminnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ -+TEST (max, , f64, q, float64, 2, D) -+/* { dg-final { scan-assembler "fmaxnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ -+TEST (min, , f64, q, float64, 2, D) -+/* { dg-final { scan-assembler "fminnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ -+ -+#undef TEST -+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ -+{ \ -+ if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ()) \ -+ abort (); \ -+} ++/* { dg-final { scan-assembler "clz\tv\[0-9\]+\.4s" } } */ + +int -+main (int argc, char **argv) ++main () +{ -+ BUILD_VARIANTS (float32, f32, 2, 4, F) -+ TEST (max, >, f64, q, float64, 2, D) -+ TEST (min, <, f64, q, float64, 2, D) ++ unsigned int x[4] = { 0x0, 0xFFFF, 0x1FFFF, 0xFFFFFFFF }; ++ int r[4] = { 32, 16, 15, 0 }; ++ int d[4], i; + -+#undef TEST -+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ -+{ \ -+ if (!test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t ()) \ -+ abort (); \ -+} ++ count_lz_v4si (x, d); + -+ BUILD_VARIANTS (float32, f32, 2, 4, F) -+ TEST (max, >, f64, q, float64, 2, D) -+ TEST (min, <, f64, q, float64, 2, D) ++ for (i = 0; i < 4; i++) ++ { ++ if (d[i] != r[i]) ++ abort (); ++ } + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x -@@ -0,0 +1,37 @@ -+short v = 0; +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE float ++#define ITYPE int + #define OP > + #define INV_OP <= + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ + /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ + /* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/subs3.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/subs3.c +@@ -0,0 +1,61 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + -+short -+atomic_fetch_add_RELAXED (short a) -+{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -+} ++extern void abort (void); ++typedef long long s64; + -+short -+atomic_fetch_sub_RELAXED (short a) ++int ++subs_ext (s64 a, int b, int c) +{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); ++ s64 d = a - b; ++ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; +} + -+short -+atomic_fetch_and_RELAXED (short a) ++int ++subs_shift_ext (s64 a, int b, int c) +{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -+} ++ s64 d = (a - ((s64)b << 3)); + -+short -+atomic_fetch_nand_RELAXED (short a) -+{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; +} + -+short -+atomic_fetch_xor_RELAXED (short a) ++int main () +{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -+} ++ int x; ++ s64 y; + -+short -+atomic_fetch_or_RELAXED (short a) -+{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); ++ x = subs_ext (0x13000002ll, 41, 15); ++ if (x != 318767121) ++ abort (); ++ ++ x = subs_ext (0x50505050ll, 29, 4); ++ if (x != 1347440724) ++ abort (); ++ ++ x = subs_ext (0x12121212121ll, 2, 14); ++ if (x != 555819311) ++ abort (); ++ ++ x = subs_shift_ext (0x123456789ll, 4, 12); ++ if (x != 591751033) ++ abort (); ++ ++ x = subs_shift_ext (0x02020202ll, 9, 8); ++ if (x != 33685963) ++ abort (); ++ ++ x = subs_shift_ext (0x987987987987ll, 23, 41); ++ if (x != -2020050673) ++ abort (); ++ ++ return 0; +} ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c -@@ -0,0 +1,132 @@ -+/* { dg-do run } */ -+/* { dg-options "-O3 --save-temps -ffast-math" } */ + -+#include ++/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/bics_2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/bics_2.c +@@ -0,0 +1,111 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); -+extern double fabs (double); + -+#define NUM_TESTS 8 -+#define DELTA 0.000001 ++int ++bics_si_test1 (int a, int b, int c) ++{ ++ int d = a & ~b; + -+float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f, -+ 200.0f, -800.0f, -13.0f, -0.5f}; -+double input_f64[] = {0.1, -0.1, 0.4, 10.3, -+ 200.0, -800.0, -13.0, -0.5}; ++ /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+#define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D) \ -+int \ -+test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t (void) \ -+{ \ -+ int ret = 1; \ -+ int i = 0; \ -+ int nlanes = LANES; \ -+ U##int##WIDTH##_t expected_out[NUM_TESTS]; \ -+ U##int##WIDTH##_t actual_out[NUM_TESTS]; \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ { \ -+ expected_out[i] \ -+ = vcvt##SUFFIX##D##_##S##WIDTH##_f##WIDTH (input_f##WIDTH[i]); \ -+ /* Don't vectorize this. */ \ -+ asm volatile ("" : : : "memory"); \ -+ } \ -+ \ -+ for (i = 0; i < NUM_TESTS; i+=nlanes) \ -+ { \ -+ U##int##WIDTH##x##LANES##_t out = \ -+ vcvt##SUFFIX##Q##_##S##WIDTH##_f##WIDTH \ -+ (vld1##Q##_f##WIDTH (input_f##WIDTH + i)); \ -+ vst1##Q##_##S##WIDTH (actual_out + i, out); \ -+ } \ -+ \ -+ for (i = 0; i < NUM_TESTS; i++) \ -+ ret &= fabs (expected_out[i] - actual_out[i]) < DELTA; \ -+ \ -+ return ret; \ -+} \ ++int ++bics_si_test2 (int a, int b, int c) ++{ ++ int d = a & ~(b << 3); + ++ /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+#define BUILD_VARIANTS(SUFFIX) \ -+TEST (SUFFIX, , 32, 2, s, ,s) \ -+TEST (SUFFIX, q, 32, 4, s, ,s) \ -+TEST (SUFFIX, q, 64, 2, s, ,d) \ -+TEST (SUFFIX, , 32, 2, u,u,s) \ -+TEST (SUFFIX, q, 32, 4, u,u,s) \ -+TEST (SUFFIX, q, 64, 2, u,u,d) \ ++typedef long long s64; + -+BUILD_VARIANTS ( ) -+/* { dg-final { scan-assembler "fcvtzs\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtzs\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtzu\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (a) -+/* { dg-final { scan-assembler "fcvtas\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtas\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "fcvtau\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtau\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (m) -+/* { dg-final { scan-assembler "fcvtms\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtms\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "fcvtmu\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtmu\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (n) -+/* { dg-final { scan-assembler "fcvtns\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtns\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "fcvtnu\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtnu\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+BUILD_VARIANTS (p) -+/* { dg-final { scan-assembler "fcvtps\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtps\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -+/* { dg-final { scan-assembler "fcvtpu\\tw\[0-9\]+, s\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtpu\\tx\[0-9\]+, d\[0-9\]+" } } */ -+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ -+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ -+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++s64 ++bics_di_test1 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & ~b; + -+#undef TEST -+#define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D) \ -+{ \ -+ if (!test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t ()) \ -+ abort (); \ ++ /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++s64 ++bics_di_test2 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & ~(b << 3); ++ ++ /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; +} + +int -+main (int argc, char **argv) ++main () +{ -+ BUILD_VARIANTS ( ) -+ BUILD_VARIANTS (a) -+ BUILD_VARIANTS (m) -+ BUILD_VARIANTS (n) -+ BUILD_VARIANTS (p) ++ int x; ++ s64 y; ++ ++ x = bics_si_test1 (29, ~4, 5); ++ if (x != ((29 & 4) + ~4 + 5)) ++ abort (); ++ ++ x = bics_si_test1 (5, ~2, 20); ++ if (x != 25) ++ abort (); ++ ++ x = bics_si_test2 (35, ~4, 5); ++ if (x != ((35 & ~(~4 << 3)) + ~4 + 5)) ++ abort (); ++ ++ x = bics_si_test2 (96, ~2, 20); ++ if (x != 116) ++ abort (); ++ ++ y = bics_di_test1 (0x130000029ll, ++ ~0x320000004ll, ++ 0x505050505ll); ++ ++ if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll)) ++ abort (); ++ ++ y = bics_di_test1 (0x5000500050005ll, ++ ~0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x5000500052025ll) ++ abort (); ++ ++ y = bics_di_test2 (0x130000029ll, ++ ~0x064000008ll, ++ 0x505050505ll); ++ if (y != ((0x130000029ll & ~(~0x064000008ll << 3)) ++ + ~0x064000008ll + 0x505050505ll)) ++ abort (); ++ ++ y = bics_di_test2 (0x130002900ll, ++ ~0x088000008ll, ++ 0x505050505ll); ++ if (y != (0x130002900ll + 0x505050505ll)) ++ abort (); ++ + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x @@ -0,0 +1,37 @@ +int v = 0; + +int -+atomic_fetch_add_RELEASE (int a) ++atomic_fetch_add_ACQUIRE (int a) +{ -+ return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE); ++ return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE); +} + +int -+atomic_fetch_sub_RELEASE (int a) ++atomic_fetch_sub_ACQUIRE (int a) +{ -+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE); ++ return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE); +} + +int -+atomic_fetch_and_RELEASE (int a) ++atomic_fetch_and_ACQUIRE (int a) +{ -+ return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE); ++ return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE); +} + +int -+atomic_fetch_nand_RELEASE (int a) ++atomic_fetch_nand_ACQUIRE (int a) +{ -+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE); ++ return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE); +} + +int -+atomic_fetch_xor_RELEASE (int a) ++atomic_fetch_xor_ACQUIRE (int a) +{ -+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE); ++ return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE); +} + +int -+atomic_fetch_or_RELEASE (int a) ++atomic_fetch_or_ACQUIRE (int a) +{ -+ return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE); ++ return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE); +} ---- a/src/gcc/testsuite/gcc.target/aarch64/fabd.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/fabd.c -@@ -0,0 +1,38 @@ -+/* { dg-do run } */ -+/* { dg-options "-O1 -fno-inline --save-temps" } */ -+ -+extern double fabs (double); -+extern float fabsf (float); -+extern void abort (); -+extern void exit (int); +--- a/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c +@@ -0,0 +1,28 @@ + -+void -+fabd_d (double x, double y, double d) -+{ -+ if ((fabs (x - y) - d) > 0.00001) -+ abort (); -+} ++/* { dg-do run } */ ++/* { dg-options "-O3" } */ + -+/* { dg-final { scan-assembler "fabd\td\[0-9\]+" } } */ ++#include "arm_neon.h" + -+void -+fabd_f (float x, float y, float d) -+{ -+ if ((fabsf (x - y) - d) > 0.00001) -+ abort (); -+} ++extern void abort (void); + -+/* { dg-final { scan-assembler "fabd\ts\[0-9\]+" } } */ ++#include "vaddv-intrinsic.x" + +int -+main () ++main (void) +{ -+ fabd_d (10.0, 5.0, 5.0); -+ fabd_d (5.0, 10.0, 5.0); -+ fabd_f (10.0, 5.0, 5.0); -+ fabd_f (5.0, 10.0, 5.0); ++ const float32_t pool_v2sf[] = {4.0f, 9.0f}; ++ const float32_t pool_v4sf[] = {4.0f, 9.0f, 16.0f, 25.0f}; ++ const float64_t pool_v2df[] = {4.0, 9.0}; + -+ return 0; -+} ++ if (test_vaddv_v2sf (pool_v2sf) != 13.0f) ++ abort (); + -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp.c -@@ -117,6 +117,16 @@ - 9.0, 10.0, 11.0, 12.0, - 13.0, 14.0, 15.0, 16.0 }; - -+ F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f, -+ 1.0f, 1.0f, 1.0f, 1.0f, -+ 1.0f, 1.0f, 1.0f, 1.0f, -+ 1.0f, 1.0f, 1.0f, 1.0f }; ++ if (test_vaddv_v4sf (pool_v4sf) != 54.0f) ++ abort (); + -+ F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0, -+ 1.0, 1.0, 1.0, 1.0, -+ 1.0, 1.0, 1.0, 1.0, -+ 1.0, 1.0, 1.0, 1.0 }; ++ if (test_vaddv_v2df (pool_v2df) != 13.0) ++ abort (); + - /* Setup input vectors. */ - for (i=1; i<=16; i++) - { -@@ -132,6 +142,7 @@ - TEST (div, 3); - TEST (neg, 2); - TEST (abs, 2); -+ TEST (fabd, 3); - - return 0; - } ---- a/src/gcc/testsuite/gcc.target/aarch64/ngc.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/ngc.c -@@ -0,0 +1,66 @@ ++ return 0; ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/sbc.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/sbc.c +@@ -0,0 +1,41 @@ +/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); -+typedef unsigned int u32; + -+u32 -+ngc_si (u32 a, u32 b, u32 c, u32 d) -+{ -+ a = -b - (c < d); -+ return a; -+} -+ -+typedef unsigned long long u64; ++typedef unsigned int u32int; ++typedef unsigned long long u64int; + -+u64 -+ngc_si_tst (u64 a, u32 b, u32 c, u32 d) ++u32int ++test_si (u32int w1, u32int w2, u32int w3, u32int w4) +{ -+ a = -b - (c < d); -+ return a; ++ u32int w0; ++ /* { dg-final { scan-assembler "sbc\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+\n" } } */ ++ w0 = w1 - w2 - (w3 < w4); ++ return w0; +} + -+u64 -+ngc_di (u64 a, u64 b, u64 c, u64 d) ++u64int ++test_di (u64int x1, u64int x2, u64int x3, u64int x4) +{ -+ a = -b - (c < d); -+ return a; ++ u64int x0; ++ /* { dg-final { scan-assembler "sbc\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+\n" } } */ ++ x0 = x1 - x2 - (x3 < x4); ++ return x0; +} + +int +main () +{ -+ int x; -+ u64 y; -+ -+ x = ngc_si (29, 4, 5, 4); -+ if (x != -4) -+ abort (); -+ -+ x = ngc_si (1024, 2, 20, 13); ++ u32int x; ++ u64int y; ++ x = test_si (7, 8, 12, 15); + if (x != -2) -+ abort (); -+ -+ y = ngc_si_tst (0x130000029ll, 32, 50, 12); -+ if (y != 0xffffffe0) -+ abort (); -+ -+ y = ngc_si_tst (0x5000500050005ll, 21, 2, 14); -+ if (y != 0xffffffea) -+ abort (); -+ -+ y = ngc_di (0x130000029ll, 0x320000004ll, 0x505050505ll, 0x123123123ll); -+ if (y != 0xfffffffcdffffffc) -+ abort (); -+ -+ y = ngc_di (0x5000500050005ll, -+ 0x2111211121112ll, 0x0000000002020ll, 0x1414575046477ll); -+ if (y != 0xfffdeeedeeedeeed) -+ abort (); -+ ++ abort(); ++ y = test_di (0x987654321ll, 0x123456789ll, 0x345345345ll, 0x123123123ll); ++ if (y != 0x8641fdb98ll) ++ abort(); + return 0; +} + -+/* { dg-final { scan-assembler-times "ngc\tw\[0-9\]+, w\[0-9\]+" 2 } } */ -+/* { dg-final { scan-assembler-times "ngc\tx\[0-9\]+, x\[0-9\]+" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/cmp.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/cmp.c -@@ -0,0 +1,61 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x +@@ -0,0 +1,36 @@ + -+int -+cmp_si_test1 (int a, int b, int c) -+{ -+ if (a > b) -+ return a + c; -+ else -+ return a + b + c; -+} ++#define STRONG 0 ++#define WEAK 1 ++int v = 0; + +int -+cmp_si_test2 (int a, int b, int c) -+{ -+ if ((a >> 3) > b) -+ return a + c; -+ else -+ return a + b + c; -+} -+ -+typedef long long s64; -+ -+s64 -+cmp_di_test1 (s64 a, s64 b, s64 c) ++atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b) +{ -+ if (a > b) -+ return a + c; -+ else -+ return a + b + c; ++ return __atomic_compare_exchange (&v, &a, &b, ++ STRONG, __ATOMIC_RELEASE, ++ __ATOMIC_ACQUIRE); +} + -+s64 -+cmp_di_test2 (s64 a, s64 b, s64 c) ++int ++atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b) +{ -+ if ((a >> 3) > b) -+ return a + c; -+ else -+ return a + b + c; ++ return __atomic_compare_exchange (&v, &a, &b, ++ WEAK, __ATOMIC_RELEASE, ++ __ATOMIC_ACQUIRE); +} + +int -+cmp_di_test3 (int a, s64 b, s64 c) ++atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b) +{ -+ if (a > b) -+ return a + c; -+ else -+ return a + b + c; ++ return __atomic_compare_exchange_n (&v, &a, b, ++ STRONG, __ATOMIC_RELEASE, ++ __ATOMIC_ACQUIRE); +} + +int -+cmp_di_test4 (int a, s64 b, s64 c) ++atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b) +{ -+ if (((s64)a << 3) > b) -+ return a + c; -+ else -+ return a + b + c; ++ return __atomic_compare_exchange_n (&v, &a, b, ++ WEAK, __ATOMIC_RELEASE, ++ __ATOMIC_ACQUIRE); +} -+ -+/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */ -+/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c -@@ -2,12 +2,13 @@ - /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c +@@ -1,8 +1,14 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2" } */ ++/* { dg-options "-O2 -dp" } */ - #define FTYPE float -+#define ITYPE int - #define OP >= - #define INV_OP < +-#include "../../../config/aarch64/arm_neon.h" ++#include - #include "vect-fcm.x" ++/* Used to force a variable to a SIMD register. */ ++#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \ ++ : "=w"(V1) \ ++ : "w"(V1) \ ++ : /* No clobbers */); ++ + /* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */ --/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ - /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ - /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ - /* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x -@@ -7,13 +7,23 @@ - extern float fabsf (float); - extern double fabs (double); + uint64x1_t +@@ -26,12 +32,29 @@ + vqaddd_s64 (a, d)); + } -+#define DEF3a(fname, type, op) \ -+ void fname##_##type (pR##type a, \ -+ pR##type b, \ -+ pR##type c) \ -+ { \ -+ int i; \ -+ for (i = 0; i < 16; i++) \ -+ a[i] = op (b[i] - c[i]); \ -+ } ++/* { dg-final { scan-assembler-times "\\tabs\\td\[0-9\]+, d\[0-9\]+" 1 } } */ + - #define DEF3(fname, type, op) \ - void fname##_##type (pR##type a, \ - pR##type b, \ - pR##type c) \ - { \ - int i; \ -- for (i=0; i<16; i++) \ -+ for (i = 0; i < 16; i++) \ - a[i] = b[i] op c[i]; \ - } ++int64x1_t ++test_vabs_s64 (int64x1_t a) ++{ ++ uint64x1_t res; ++ force_simd (a); ++ res = vabs_s64 (a); ++ force_simd (res); ++ return res; ++} ++ + /* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ -@@ -22,11 +32,15 @@ - pR##type b) \ - { \ - int i; \ -- for (i=0; i<16; i++) \ -+ for (i = 0; i < 16; i++) \ - a[i] = op(b[i]); \ - } + uint64x1_t + test_vceqd_s64 (int64x1_t a, int64x1_t b) + { +- return vceqd_s64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vceqd_s64 (a, b); ++ force_simd (res); ++ return res; + } + /* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ +@@ -39,7 +62,11 @@ + uint64x1_t + test_vceqzd_s64 (int64x1_t a) + { +- return vceqzd_s64 (a); ++ uint64x1_t res; ++ force_simd (a); ++ res = vceqzd_s64 (a); ++ force_simd (res); ++ return res; + } -+#define DEFN3a(fname, op) \ -+ DEF3a (fname, F32, op) \ -+ DEF3a (fname, F64, op) -+ - #define DEFN3(fname, op) \ - DEF3 (fname, F32, op) \ - DEF3 (fname, F64, op) -@@ -42,3 +56,5 @@ - DEFN2 (neg, -) - DEF2 (abs, F32, fabsf) - DEF2 (abs, F64, fabs) -+DEF3a (fabd, F32, fabsf) -+DEF3a (fabd, F64, fabs) ---- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c -@@ -1,43 +1,7 @@ - /* { dg-do compile } */ - /* { dg-options "-O2" } */ + /* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ +@@ -47,21 +74,36 @@ + uint64x1_t + test_vcged_s64 (int64x1_t a, int64x1_t b) + { +- return vcged_s64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vcged_s64 (a, b); ++ force_simd (res); ++ return res; + } --int v = 0; -+#include "atomic-op-acq_rel.x" + uint64x1_t + test_vcled_s64 (int64x1_t a, int64x1_t b) + { +- return vcled_s64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vcled_s64 (a, b); ++ force_simd (res); ++ return res; + } --int --atomic_fetch_add_ACQ_REL (int a) --{ -- return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL); --} -- --int --atomic_fetch_sub_ACQ_REL (int a) --{ -- return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL); --} -- --int --atomic_fetch_and_ACQ_REL (int a) --{ -- return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL); --} -- --int --atomic_fetch_nand_ACQ_REL (int a) --{ -- return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL); --} -- --int --atomic_fetch_xor_ACQ_REL (int a) --{ -- return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL); --} -- --int --atomic_fetch_or_ACQ_REL (int a) --{ -- return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); --} -- - /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ - /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/subs1.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/subs1.c -@@ -0,0 +1,149 @@ -+/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps -fno-inline" } */ -+ -+extern void abort (void); -+ -+int -+subs_si_test1 (int a, int b, int c) -+{ -+ int d = a - c; -+ -+ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; -+} -+ -+int -+subs_si_test2 (int a, int b, int c) -+{ -+ int d = a - 0xff; -+ -+ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, #255" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; -+} -+ -+int -+subs_si_test3 (int a, int b, int c) -+{ -+ int d = a - (b << 3); -+ -+ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; -+} -+ -+typedef long long s64; -+ -+s64 -+subs_di_test1 (s64 a, s64 b, s64 c) -+{ -+ s64 d = a - c; -+ -+ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; -+} -+ -+s64 -+subs_di_test2 (s64 a, s64 b, s64 c) -+{ -+ s64 d = a - 0xff; -+ -+ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, #255" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; -+} -+ -+s64 -+subs_di_test3 (s64 a, s64 b, s64 c) -+{ -+ s64 d = a - (b << 3); -+ -+ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ -+ if (d == 0) -+ return a + c; -+ else -+ return b + d + c; -+} -+ -+int main () -+{ -+ int x; -+ s64 y; -+ -+ x = subs_si_test1 (29, 4, 5); -+ if (x != 33) -+ abort (); -+ -+ x = subs_si_test1 (5, 2, 20); -+ if (x != 7) -+ abort (); -+ -+ x = subs_si_test2 (29, 4, 5); -+ if (x != -217) -+ abort (); -+ -+ x = subs_si_test2 (1024, 2, 20); -+ if (x != 791) -+ abort (); -+ -+ x = subs_si_test3 (35, 4, 5); -+ if (x != 12) -+ abort (); -+ -+ x = subs_si_test3 (5, 2, 20); -+ if (x != 11) -+ abort (); -+ -+ y = subs_di_test1 (0x130000029ll, -+ 0x320000004ll, -+ 0x505050505ll); -+ -+ if (y != 0x45000002d) -+ abort (); -+ -+ y = subs_di_test1 (0x5000500050005ll, -+ 0x2111211121112ll, -+ 0x0000000002020ll); -+ if (y != 0x7111711171117) -+ abort (); +-/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ ++/* Idiom recognition will cause this testcase not to generate ++ the expected cmge instruction, so do not check for it. */ + + uint64x1_t + test_vcgezd_s64 (int64x1_t a) + { +- return vcgezd_s64 (a); ++ uint64x1_t res; ++ force_simd (a); ++ res = vcgezd_s64 (a); ++ force_simd (res); ++ return res; + } + + /* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ +@@ -69,7 +111,12 @@ + uint64x1_t + test_vcged_u64 (uint64x1_t a, uint64x1_t b) + { +- return vcged_u64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vcged_u64 (a, b); ++ force_simd (res); ++ return res; + } + + /* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ +@@ -77,13 +124,23 @@ + uint64x1_t + test_vcgtd_s64 (int64x1_t a, int64x1_t b) + { +- return vcgtd_s64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vcgtd_s64 (a, b); ++ force_simd (res); ++ return res; + } + + uint64x1_t + test_vcltd_s64 (int64x1_t a, int64x1_t b) + { +- return vcltd_s64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vcltd_s64 (a, b); ++ force_simd (res); ++ return res; + } + + /* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ +@@ -91,7 +148,11 @@ + uint64x1_t + test_vcgtzd_s64 (int64x1_t a) + { +- return vcgtzd_s64 (a); ++ uint64x1_t res; ++ force_simd (a); ++ res = vcgtzd_s64 (a); ++ force_simd (res); ++ return res; + } + + /* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ +@@ -99,7 +160,12 @@ + uint64x1_t + test_vcgtd_u64 (uint64x1_t a, uint64x1_t b) + { +- return vcgtd_u64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vcgtd_u64 (a, b); ++ force_simd (res); ++ return res; + } + + /* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ +@@ -107,18 +173,27 @@ + uint64x1_t + test_vclezd_s64 (int64x1_t a) + { +- return vclezd_s64 (a); ++ uint64x1_t res; ++ force_simd (a); ++ res = vclezd_s64 (a); ++ force_simd (res); ++ return res; + } + +-/* { dg-final { scan-assembler-times "\\tcmlt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ ++/* Idiom recognition will cause this testcase not to generate ++ the expected cmlt instruction, so do not check for it. */ + + uint64x1_t + test_vcltzd_s64 (int64x1_t a) + { +- return vcltzd_s64 (a); ++ uint64x1_t res; ++ force_simd (a); ++ res = vcltzd_s64 (a); ++ force_simd (res); ++ return res; + } + +-/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */ ++/* { dg-final { scan-assembler-times "aarch64_get_lanev16qi" 2 } } */ + + int8x1_t + test_vdupb_lane_s8 (int8x16_t a) +@@ -132,7 +207,7 @@ + return vdupb_lane_u8 (a, 2); + } + +-/* { dg-final { scan-assembler-times "\\tdup\\th\[0-9\]+, v\[0-9\]+\.h" 2 } } */ ++/* { dg-final { scan-assembler-times "aarch64_get_lanev8hi" 2 } } */ + + int16x1_t + test_vduph_lane_s16 (int16x8_t a) +@@ -146,7 +221,7 @@ + return vduph_lane_u16 (a, 2); + } + +-/* { dg-final { scan-assembler-times "\\tdup\\ts\[0-9\]+, v\[0-9\]+\.s" 2 } } */ ++/* { dg-final { scan-assembler-times "aarch64_get_lanev4si" 2 } } */ + + int32x1_t + test_vdups_lane_s32 (int32x4_t a) +@@ -160,18 +235,18 @@ + return vdups_lane_u32 (a, 2); + } + +-/* { dg-final { scan-assembler-times "\\tdup\\td\[0-9\]+, v\[0-9\]+\.d" 2 } } */ ++/* { dg-final { scan-assembler-times "aarch64_get_lanev2di" 2 } } */ + + int64x1_t + test_vdupd_lane_s64 (int64x2_t a) + { +- return vdupd_lane_s64 (a, 2); ++ return vdupd_lane_s64 (a, 1); + } + + uint64x1_t + test_vdupd_lane_u64 (uint64x2_t a) + { +- return vdupd_lane_u64 (a, 2); ++ return vdupd_lane_u64 (a, 1); + } + + /* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ +@@ -179,13 +254,23 @@ + int64x1_t + test_vtst_s64 (int64x1_t a, int64x1_t b) + { +- return vtstd_s64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vtstd_s64 (a, b); ++ force_simd (res); ++ return res; + } + + uint64x1_t + test_vtst_u64 (uint64x1_t a, uint64x1_t b) + { +- return vtstd_u64 (a, b); ++ uint64x1_t res; ++ force_simd (a); ++ force_simd (b); ++ res = vtstd_s64 (a, b); ++ force_simd (res); ++ return res; + } + + /* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */ +@@ -722,8 +807,11 @@ + return vrshld_u64 (a, b); + } + +-/* { dg-final { scan-assembler-times "\\tasr\\tx\[0-9\]+" 1 } } */ ++/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd), ++ so we cannot check scan-assembler-times. */ + ++/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */ + -+ y = subs_di_test2 (0x130000029ll, -+ 0x320000004ll, -+ 0x505050505ll); -+ if (y != 0x955050433) -+ abort (); + int64x1_t + test_vshrd_n_s64 (int64x1_t a) + { +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c +@@ -1,43 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2" } */ + +-int v = 0; ++#include "atomic-op-int.x" + +-int +-atomic_fetch_add_RELAXED (int a) +-{ +- return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +-} +- +-int +-atomic_fetch_sub_RELAXED (int a) +-{ +- return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +-} +- +-int +-atomic_fetch_and_RELAXED (int a) +-{ +- return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +-} +- +-int +-atomic_fetch_nand_RELAXED (int a) +-{ +- return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +-} +- +-int +-atomic_fetch_xor_RELAXED (int a) +-{ +- return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +-} +- +-int +-atomic_fetch_or_RELAXED (int a) +-{ +- return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +-} +- + /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/cmn-neg.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/cmn-neg.c +@@ -0,0 +1,33 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps" } */ + -+ y = subs_di_test2 (0x130002900ll, -+ 0x320000004ll, -+ 0x505050505ll); -+ if (y != 0x955052d0a) -+ abort (); ++extern void abort (void); + -+ y = subs_di_test3 (0x130000029ll, -+ 0x064000008ll, -+ 0x505050505ll); -+ if (y != 0x3790504f6) ++void __attribute__ ((noinline)) ++foo_s32 (int a, int b) ++{ ++ if (a < -b) + abort (); ++} ++/* { dg-final { scan-assembler "cmn\tw\[0-9\]" } } */ + -+ y = subs_di_test3 (0x130002900ll, -+ 0x088000008ll, -+ 0x505050505ll); -+ if (y != 0x27d052dcd) ++void __attribute__ ((noinline)) ++foo_s64 (long long a, long long b) ++{ ++ if (a < -b) + abort (); ++} ++/* { dg-final { scan-assembler "cmn\tx\[0-9\]" } } */ + ++ ++int ++main (void) ++{ ++ int a = 30; ++ int b = 42; ++ foo_s32 (a, b); ++ foo_s64 (a, b); + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/adds2.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/adds2.c -@@ -0,0 +1,155 @@ -+/* { dg-do run } */ -+/* { dg-options "-O2 --save-temps -fno-inline" } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c +@@ -1,43 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2" } */ + +-int v = 0; ++#include "atomic-op-seq_cst.x" + +-int +-atomic_fetch_add_SEQ_CST (int a) +-{ +- return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST); +-} +- +-int +-atomic_fetch_sub_SEQ_CST (int a) +-{ +- return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST); +-} +- +-int +-atomic_fetch_and_SEQ_CST (int a) +-{ +- return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST); +-} +- +-int +-atomic_fetch_nand_SEQ_CST (int a) +-{ +- return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST); +-} +- +-int +-atomic_fetch_xor_SEQ_CST (int a) +-{ +- return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST); +-} +- +-int +-atomic_fetch_or_SEQ_CST (int a) +-{ +- return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); +-} +- + /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x +@@ -0,0 +1,27 @@ + -+extern void abort (void); ++float32_t ++test_vaddv_v2sf (const float32_t *pool) ++{ ++ float32x2_t val; + -+int -+adds_si_test1 (int a, int b, int c) ++ val = vld1_f32 (pool); ++ return vaddv_f32 (val); ++} ++ ++float32_t ++test_vaddv_v4sf (const float32_t *pool) +{ -+ int d = a + b; ++ float32x4_t val; + -+ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ -+ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ -+ if (d <= 0) -+ return a + c; -+ else -+ return b + d + c; ++ val = vld1q_f32 (pool); ++ return vaddvq_f32 (val); +} + -+int -+adds_si_test2 (int a, int b, int c) ++float64_t ++test_vaddv_v2df (const float64_t *pool) +{ -+ int d = a + 0xfff; ++ float64x2_t val; + -+ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, 4095" } } */ -+ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, 4095" } } */ -+ if (d <= 0) -+ return a + c; -+ else -+ return b + d + c; ++ val = vld1q_f64 (pool); ++ return vaddvq_f64 (val); +} +--- a/src/gcc/testsuite/gcc.target/aarch64/negs.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/negs.c +@@ -0,0 +1,108 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps" } */ ++ ++extern void abort (void); ++int z; + +int -+adds_si_test3 (int a, int b, int c) ++negs_si_test1 (int a, int b, int c) +{ -+ int d = a + (b << 3); ++ int d = -b; + -+ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ -+ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ -+ if (d <= 0) ++ /* { dg-final { scan-assembler "negs\tw\[0-9\]+, w\[0-9\]+" } } */ ++ if (d < 0) + return a + c; -+ else -+ return b + d + c; -+} + -+typedef long long s64; ++ z = d; ++ return b + c + d; ++} + -+s64 -+adds_di_test1 (s64 a, s64 b, s64 c) ++int ++negs_si_test3 (int a, int b, int c) +{ -+ s64 d = a + b; ++ int d = -(b) << 3; + -+ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ -+ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ -+ if (d <= 0) ++ /* { dg-final { scan-assembler "negs\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d == 0) + return a + c; -+ else -+ return b + d + c; ++ ++ z = d; ++ return b + c + d; +} + ++typedef long long s64; ++s64 zz; ++ +s64 -+adds_di_test2 (s64 a, s64 b, s64 c) ++negs_di_test1 (s64 a, s64 b, s64 c) +{ -+ s64 d = a + 0x1000ll; ++ s64 d = -b; + -+ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, 4096" } } */ -+ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, 4096" } } */ -+ if (d <= 0) ++ /* { dg-final { scan-assembler "negs\tx\[0-9\]+, x\[0-9\]+" } } */ ++ if (d < 0) + return a + c; -+ else -+ return b + d + c; ++ ++ zz = d; ++ return b + c + d; +} + +s64 -+adds_di_test3 (s64 a, s64 b, s64 c) ++negs_di_test3 (s64 a, s64 b, s64 c) +{ -+ s64 d = a + (b << 3); ++ s64 d = -(b) << 3; + -+ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ -+ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ -+ if (d <= 0) ++ /* { dg-final { scan-assembler "negs\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d == 0) + return a + c; -+ else -+ return b + d + c; ++ ++ zz = d; ++ return b + c + d; +} + +int main () @@ -6964,1762 +8161,4489 @@ + int x; + s64 y; + -+ x = adds_si_test1 (29, 4, 5); -+ if (x != 42) -+ abort (); -+ -+ x = adds_si_test1 (5, 2, 20); -+ if (x != 29) -+ abort (); -+ -+ x = adds_si_test2 (29, 4, 5); -+ if (x != 4133) -+ abort (); -+ -+ x = adds_si_test2 (1024, 2, 20); -+ if (x != 5141) -+ abort (); -+ -+ x = adds_si_test3 (35, 4, 5); -+ if (x != 76) ++ x = negs_si_test1 (2, 12, 5); ++ if (x != 7) + abort (); + -+ x = adds_si_test3 (5, 2, 20); -+ if (x != 43) ++ x = negs_si_test1 (1, 2, 32); ++ if (x != 33) + abort (); + -+ y = adds_di_test1 (0x130000029ll, -+ 0x320000004ll, -+ 0x505050505ll); -+ -+ if (y != 0xc75050536) ++ x = negs_si_test3 (13, 14, 5); ++ if (x != -93) + abort (); + -+ y = adds_di_test1 (0x5000500050005ll, -+ 0x2111211121112ll, -+ 0x0000000002020ll); -+ if (y != 0x9222922294249) ++ x = negs_si_test3 (15, 21, 2); ++ if (x != -145) + abort (); + -+ y = adds_di_test2 (0x130000029ll, -+ 0x320000004ll, -+ 0x505050505ll); -+ if (y != 0x955051532) ++ y = negs_di_test1 (0x20202020ll, ++ 0x65161611ll, ++ 0x42434243ll); ++ if (y != 0x62636263ll) + abort (); + -+ y = adds_di_test2 (0x540004100ll, -+ 0x320000004ll, -+ 0x805050205ll); -+ if (y != 0x1065055309) ++ y = negs_di_test1 (0x1010101010101ll, ++ 0x123456789abcdll, ++ 0x5555555555555ll); ++ if (y != 0x6565656565656ll) + abort (); + -+ y = adds_di_test3 (0x130000029ll, -+ 0x064000008ll, -+ 0x505050505ll); -+ if (y != 0x9b9050576) ++ y = negs_di_test3 (0x62523781ll, ++ 0x64234978ll, ++ 0x12345123ll); ++ if (y != 0xfffffffd553d4edbll) + abort (); + -+ y = adds_di_test3 (0x130002900ll, -+ 0x088000008ll, -+ 0x505050505ll); -+ if (y != 0xafd052e4d) ++ y = negs_di_test3 (0x763526268ll, ++ 0x101010101ll, ++ 0x222222222ll); ++ if (y != 0xfffffffb1b1b1b1bll) + abort (); + + return 0; +} -+ -+/* { dg-final { cleanup-saved-temps } } */ ---- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c -+++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c -@@ -2,12 +2,13 @@ - /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ - - #define FTYPE double -+#define ITYPE long - #define OP > - #define INV_OP <= +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c +@@ -1,43 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2" } */ - #include "vect-fcm.x" +-int v = 0; ++#include "atomic-op-consume.x" --/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ -+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ - /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ - /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ - /* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ ---- a/src/gcc/testsuite/lib/target-supports.exp -+++ b/src/gcc/testsuite/lib/target-supports.exp -@@ -2012,6 +2012,7 @@ - || ([istarget powerpc*-*-*] - && ![istarget powerpc-*-linux*paired*]) - || [istarget x86_64-*-*] -+ || [istarget aarch64*-*-*] - || ([istarget arm*-*-*] - && [check_effective_target_arm_neon_ok])} { - set et_vect_uintfloat_cvt_saved 1 -@@ -2147,22 +2148,6 @@ - } - } - --# Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8 --# -mfloat-abi=softfp --proc check_effective_target_arm_v8_neon_ok {} { -- if { [check_effective_target_arm32] } { -- return [check_no_compiler_messages arm_v8_neon_ok object { -- int foo (void) -- { -- __asm__ volatile ("vrintn.f32 q0, q0"); -- return 0; -- } -- } "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"] -- } else { -- return 0 -- } +-int +-atomic_fetch_add_CONSUME (int a) +-{ +- return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME); -} - - # Return 1 if this is an ARM target supporting -mfpu=vfp - # -mfloat-abi=hard. Some multilibs may be incompatible with these - # options. -@@ -2226,7 +2211,8 @@ - if { ! [check_effective_target_arm_v8_neon_ok] } { - return "$flags" - } -- return "$flags -march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=softfp" -+ global et_arm_v8_neon_flags -+ return "$flags $et_arm_v8_neon_flags -march=armv8-a" - } - - # Add the options needed for NEON. We need either -mfloat-abi=softfp -@@ -2270,6 +2256,79 @@ - check_effective_target_arm_neon_ok_nocache] - } - -+# Return 1 if this is an ARM target supporting -mfpu=neon-fp16 -+# -mfloat-abi=softfp or equivalent options. Some multilibs may be -+# incompatible with these options. Also set et_arm_neon_flags to the -+# best options to add. +-int +-atomic_fetch_sub_CONSUME (int a) +-{ +- return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME); +-} +- +-int +-atomic_fetch_and_CONSUME (int a) +-{ +- return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME); +-} +- +-int +-atomic_fetch_nand_CONSUME (int a) +-{ +- return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME); +-} +- +-int +-atomic_fetch_xor_CONSUME (int a) +-{ +- return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME); +-} +- +-int +-atomic_fetch_or_CONSUME (int a) +-{ +- return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME); +-} +- + /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c +@@ -0,0 +1,128 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps -ffast-math" } */ + -+proc check_effective_target_arm_neon_fp16_ok_nocache { } { -+ global et_arm_neon_fp16_flags -+ set et_arm_neon_fp16_flags "" -+ if { [check_effective_target_arm32] } { -+ foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16" -+ "-mfpu=neon-fp16 -mfloat-abi=softfp"} { -+ if { [check_no_compiler_messages_nocache arm_neon_fp_16_ok object { -+ #include "arm_neon.h" -+ float16x4_t -+ foo (float32x4_t arg) -+ { -+ return vcvt_f16_f32 (arg); -+ } -+ } "$flags"] } { -+ set et_arm_neon_fp16_flags $flags -+ return 1 -+ } -+ } -+ } ++#include + -+ return 0 -+} ++extern void abort (void); ++extern float fabsf (float); ++extern double fabs (double); + -+proc check_effective_target_arm_neon_fp16_ok { } { -+ return [check_cached_effective_target arm_neon_fp16_ok \ -+ check_effective_target_arm_neon_fp16_ok_nocache] -+} ++#define NUM_TESTS 16 ++#define DELTA 0.000001 + -+proc add_options_for_arm_neon_fp16 { flags } { -+ if { ! [check_effective_target_arm_neon_fp16_ok] } { -+ return "$flags" -+ } -+ global et_arm_neon_fp16_flags -+ return "$flags $et_arm_neon_fp16_flags" -+} ++int8_t input_int8[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++int16_t input_int16[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; ++int64_t input_int64[] = {1, 56, 2, -9, -90, 23, 54, 76, ++ -4, 34, 110, -110, 6, 4, 75, -34}; + -+# Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8 -+# -mfloat-abi=softfp or equivalent options. Some multilibs may be -+# incompatible with these options. Also set et_arm_v8_neon_flags to the -+# best options to add. ++uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++uint16_t input_uint16[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; ++uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; + -+proc check_effective_target_arm_v8_neon_ok_nocache { } { -+ global et_arm_v8_neon_flags -+ set et_arm_v8_neon_flags "" -+ if { [check_effective_target_arm32] } { -+ foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} { -+ if { [check_no_compiler_messages_nocache arm_v8_neon_ok object { -+ #include "arm_neon.h" -+ void -+ foo () -+ { -+ __asm__ volatile ("vrintn.f32 q0, q0"); -+ } -+ } "$flags"] } { -+ set et_arm_v8_neon_flags $flags -+ return 1 -+ } -+ } -+ } ++uint64_t input_uint64[] = {1, 56, 2, 9, 90, 23, 54, 76, ++ 4, 34, 110, 110, 6, 4, 75, 34}; + -+ return 0 -+} ++float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f, ++ 200.0f, -800.0f, -13.0f, -0.5f, ++ 7.9f, -870.0f, 10.4f, 310.11f, ++ 0.0f, -865.0f, -2213.0f, -1.5f}; + -+proc check_effective_target_arm_v8_neon_ok { } { -+ return [check_cached_effective_target arm_v8_neon_ok \ -+ check_effective_target_arm_v8_neon_ok_nocache] -+} ++double input_float64[] = {0.1, -0.1, 0.4, 10.3, ++ 200.0, -800.0, -13.0, -0.5, ++ 7.9, -870.0, 10.4, 310.11, ++ 0.0, -865.0, -2213.0, -1.5}; + - # Return 1 if this is an ARM target supporting -mfpu=neon-vfpv4 - # -mfloat-abi=softfp or equivalent options. Some multilibs may be - # incompatible with these options. Also set et_arm_neonv2_flags to the -@@ -2509,6 +2568,24 @@ - } [add_options_for_arm_neonv2 ""]] - } - -+# Return 1 if the target supports executing ARMv8 NEON instructions, 0 -+# otherwise. ++#define EQUALF(a, b) (fabsf (a - b) < DELTA) ++#define EQUALD(a, b) (fabs (a - b) < DELTA) ++#define EQUALL(a, b) (a == b) + -+proc check_effective_target_arm_v8_neon_hw { } { -+ return [check_runtime arm_v8_neon_hw_available { -+ #include "arm_neon.h" -+ int -+ main (void) -+ { -+ float32x2_t a; -+ asm ("vrinta.f32 %P0, %P1" -+ : "=w" (a) -+ : "0" (a)); -+ return 0; -+ } -+ } [add_options_for_arm_v8_neon ""]] ++#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT) \ ++int \ ++test_vaddv##SUFFIX##_##TYPE##x##LANES##_t (void) \ ++{ \ ++ int i, j; \ ++ int moves = (NUM_TESTS - LANES) + 1; \ ++ TYPE##_t out_l[NUM_TESTS]; \ ++ TYPE##_t out_v[NUM_TESTS]; \ ++ \ ++ /* Calculate linearly. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ out_l[i] = input_##TYPE[i]; \ ++ for (j = 1; j < LANES; j++) \ ++ out_l[i] += input_##TYPE[i + j]; \ ++ } \ ++ \ ++ /* Calculate using vector reduction intrinsics. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ ++ out_v[i] = vaddv##Q##_##SUFFIX (t1); \ ++ } \ ++ \ ++ /* Compare. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ if (!EQUAL##FLOAT (out_v[i], out_l[i])) \ ++ return 0; \ ++ } \ ++ return 1; \ +} + - # Return 1 if this is a ARM target with NEON enabled. - - proc check_effective_target_arm_neon { } { -@@ -4591,6 +4668,33 @@ - return 0 - } - -+# Return 1 if programs are intended to be run on hardware rather than -+# on a simulator -+ -+proc check_effective_target_hw { } { -+ -+ # All "src/sim" simulators set this one. -+ if [board_info target exists is_simulator] { -+ if [board_info target is_simulator] { -+ return 0 -+ } else { -+ return 1 -+ } -+ } ++#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F) \ ++TEST (STYPE, , TYPE, W32, F) \ ++TEST (STYPE, q, TYPE, W64, F) \ + -+ # The "sid" simulators don't set that one, but at least they set -+ # this one. -+ if [board_info target exists slow_simulator] { -+ if [board_info target slow_simulator] { -+ return 0 -+ } else { -+ return 1 -+ } -+ } ++BUILD_VARIANTS (int8, s8, 8, 16, L) ++BUILD_VARIANTS (uint8, u8, 8, 16, L) ++/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */ ++/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */ ++BUILD_VARIANTS (int16, s16, 4, 8, L) ++BUILD_VARIANTS (uint16, u16, 4, 8, L) ++/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */ ++/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */ ++BUILD_VARIANTS (int32, s32, 2, 4, L) ++BUILD_VARIANTS (uint32, u32, 2, 4, L) ++/* { dg-final { scan-assembler "addp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "addv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++TEST (s64, q, int64, 2, D) ++TEST (u64, q, uint64, 2, D) ++/* { dg-final { scan-assembler "addp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */ + -+ return 1 -+} ++BUILD_VARIANTS (float32, f32, 2, 4, F) ++/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "faddp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++TEST (f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "faddp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */ + - # Return 1 if the target is a VxWorks kernel. - - proc check_effective_target_vxworks_kernel { } { ---- a/src/gcc/testsuite/ChangeLog.linaro -+++ b/src/gcc/testsuite/ChangeLog.linaro -@@ -0,0 +1,467 @@ -+2013-07-03 Christophe Lyon ++#undef TEST ++#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT) \ ++{ \ ++ if (!test_vaddv##SUFFIX##_##TYPE##x##LANES##_t ()) \ ++ abort (); \ ++} + -+ Revert backport from trunk r198928. -+ 2013-05-15 Ramana Radhakrishnan ++int ++main (int argc, char **argv) ++{ ++BUILD_VARIANTS (int8, s8, 8, 16, L) ++BUILD_VARIANTS (uint8, u8, 8, 16, L) ++BUILD_VARIANTS (int16, s16, 4, 8, L) ++BUILD_VARIANTS (uint16, u16, 4, 8, L) ++BUILD_VARIANTS (int32, s32, 2, 4, L) ++BUILD_VARIANTS (uint32, u32, 2, 4, L) + -+ PR target/19599 -+ * gcc.target/arm/pr40887.c: Adjust testcase. -+ * gcc.target/arm/pr19599.c: New test. ++BUILD_VARIANTS (float32, f32, 2, 4, F) ++TEST (f64, q, float64, 2, D) + -+2013-07-03 Christophe Lyon ++ return 0; ++} + -+ Revert backport from trunk 199439, 199533 -+ 2013-05-31 Rainer Orth ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c +@@ -1,43 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2" } */ + +-char v = 0; ++#include "atomic-op-char.x" + +-char +-atomic_fetch_add_RELAXED (char a) +-{ +- return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +-} +- +-char +-atomic_fetch_sub_RELAXED (char a) +-{ +- return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +-} +- +-char +-atomic_fetch_and_RELAXED (char a) +-{ +- return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +-} +- +-char +-atomic_fetch_nand_RELAXED (char a) +-{ +- return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +-} +- +-char +-atomic_fetch_xor_RELAXED (char a) +-{ +- return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +-} +- +-char +-atomic_fetch_or_RELAXED (char a) +-{ +- return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +-} +- + /* { dg-final { scan-assembler-times "ldxrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stxrb\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x +@@ -0,0 +1,37 @@ ++int v = 0; + -+ * gcc.dg/shrink-wrap-alloca.c: Use __builtin_alloca. ++int ++atomic_fetch_add_RELAXED (int a) ++{ ++ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); ++} + -+ 2013-05-30 Zhenqiang Chen ++int ++atomic_fetch_sub_RELAXED (int a) ++{ ++ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); ++} + -+ * gcc.dg/shrink-wrap-alloca.c: New added. -+ * gcc.dg/shrink-wrap-pretend.c: New added. -+ * gcc.dg/shrink-wrap-sibcall.c: New added. ++int ++atomic_fetch_and_RELAXED (int a) ++{ ++ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); ++} + -+2013-07-02 Rob Savoye ++int ++atomic_fetch_nand_RELAXED (int a) ++{ ++ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); ++} + -+ Backport from trunk 200096 ++int ++atomic_fetch_xor_RELAXED (int a) ++{ ++ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); ++} + -+ 2013-06-14 Vidya Praveen ++int ++atomic_fetch_or_RELAXED (int a) ++{ ++ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x +@@ -0,0 +1,37 @@ ++int v = 0; + -+ * gcc.target/aarch64/vect_smlal_1.c: New file. ++int ++atomic_fetch_add_SEQ_CST (int a) ++{ ++ return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST); ++} + -+2013-07-02 Rob Savoye ++int ++atomic_fetch_sub_SEQ_CST (int a) ++{ ++ return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST); ++} + -+ Backport from trunk 200019 -+ 2013-06-12 Ramana Radhakrishnan ++int ++atomic_fetch_and_SEQ_CST (int a) ++{ ++ return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST); ++} + -+ * gcc.target/arm/unaligned-memcpy-4.c (src, dst): Initialize -+ to ensure alignment. -+ * gcc.target/arm/unaligned-memcpy-3.c (src): Likewise. ++int ++atomic_fetch_nand_SEQ_CST (int a) ++{ ++ return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST); ++} + -+2013-06-20 Rob Savoye ++int ++atomic_fetch_xor_SEQ_CST (int a) ++{ ++ return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST); ++} + -+ Backport from trunk 200152 -+ 2013-06-17 Sofiane Naci ++int ++atomic_fetch_or_SEQ_CST (int a) ++{ ++ return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/bfxil_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/bfxil_1.c +@@ -0,0 +1,40 @@ ++/* { dg-do run { target aarch64*-*-* } } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-require-effective-target aarch64_little_endian } */ + -+ * gcc.target/aarch64/scalar_intrinsics.c: Update. ++extern void abort (void); + -+2013-06-20 Rob Savoye ++typedef struct bitfield ++{ ++ unsigned short eight1: 8; ++ unsigned short four: 4; ++ unsigned short eight2: 8; ++ unsigned short seven: 7; ++ unsigned int sixteen: 16; ++} bitfield; + -+ Backport from trunk 200148 -+ 2013-06-17 Kyrylo Tkachov ++bitfield ++bfxil (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfxil\tx\[0-9\]+, x\[0-9\]+, 16, 8" } } */ ++ a.eight1 = a.eight2; ++ return a; ++} + -+ * gcc.target/arm/unaligned-memcpy-2.c (dest): Initialize to -+ ensure alignment. ++int ++main (void) ++{ ++ static bitfield a; ++ bitfield b; + -+2013-06-20 Rob Savoye ++ a.eight1 = 9; ++ a.eight2 = 57; ++ b = bfxil (a); + -+ Backport from trunk 199533 -+ 2013-05-31 Rainer Orth ++ if (b.eight1 != a.eight2) ++ abort (); + -+ * gcc.dg/shrink-wrap-alloca.c: Use __builtin_alloca. ++ return 0; ++} + -+2013-06-20 Christophe Lyon ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x +@@ -0,0 +1,37 @@ ++int v = 0; + -+ Backport from trunk r198683. -+ 2013-05-07 Christophe Lyon ++int ++atomic_fetch_add_CONSUME (int a) ++{ ++ return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME); ++} + -+ * lib/target-supports.exp (check_effective_target_hw): New -+ function. -+ * c-c++-common/asan/clone-test-1.c: Call -+ check_effective_target_hw. -+ * c-c++-common/asan/rlimit-mmap-test-1.c: Likewise. -+ * c-c++-common/asan/heap-overflow-1.c: Update regexps to accept -+ possible decorations. -+ * c-c++-common/asan/null-deref-1.c: Likewise. -+ * c-c++-common/asan/stack-overflow-1.c: Likewise. -+ * c-c++-common/asan/strncpy-overflow-1.c: Likewise. -+ * c-c++-common/asan/use-after-free-1.c: Likewise. -+ * g++.dg/asan/deep-thread-stack-1.C: Likewise. -+ * g++.dg/asan/large-func-test-1.C: Likewise. ++int ++atomic_fetch_sub_CONSUME (int a) ++{ ++ return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME); ++} + -+2013-06-11 Rob Savoye ++int ++atomic_fetch_and_CONSUME (int a) ++{ ++ return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME); ++} + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++int ++atomic_fetch_nand_CONSUME (int a) ++{ ++ return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME); ++} + -+2013-06-06 Zhenqiang Chen ++int ++atomic_fetch_xor_CONSUME (int a) ++{ ++ return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME); ++} + -+ Backport from mainline r199439. -+ 2013-05-30 Zhenqiang Chen ++int ++atomic_fetch_or_CONSUME (int a) ++{ ++ return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME); ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c +@@ -1,43 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2" } */ + +-short v = 0; ++#include "atomic-op-short.x" + +-short +-atomic_fetch_add_RELAXED (short a) +-{ +- return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +-} +- +-short +-atomic_fetch_sub_RELAXED (short a) +-{ +- return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +-} +- +-short +-atomic_fetch_and_RELAXED (short a) +-{ +- return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +-} +- +-short +-atomic_fetch_nand_RELAXED (short a) +-{ +- return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +-} +- +-short +-atomic_fetch_xor_RELAXED (short a) +-{ +- return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +-} +- +-short +-atomic_fetch_or_RELAXED (short a) +-{ +- return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +-} +- + /* { dg-final { scan-assembler-times "ldxrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stxrh\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x +@@ -0,0 +1,37 @@ ++char v = 0; + -+ * gcc.dg/shrink-wrap-alloca.c: New added. -+ * gcc.dg/shrink-wrap-pretend.c: New added. -+ * gcc.dg/shrink-wrap-sibcall.c: New added. ++char ++atomic_fetch_add_RELAXED (char a) ++{ ++ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); ++} + -+2013-06-05 Christophe Lyon ++char ++atomic_fetch_sub_RELAXED (char a) ++{ ++ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); ++} + -+ Backport from trunk r199658. -+ 2013-06-04 Ian Bolton ++char ++atomic_fetch_and_RELAXED (char a) ++{ ++ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); ++} + -+ * gcc.target/aarch64/movi_1.c: New test. ++char ++atomic_fetch_nand_RELAXED (char a) ++{ ++ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); ++} + -+2013-06-04 Christophe Lyon ++char ++atomic_fetch_xor_RELAXED (char a) ++{ ++ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); ++} + -+ Backport from trunk r199261. -+ 2013-05-23 Christian Bruel ++char ++atomic_fetch_or_RELAXED (char a) ++{ ++ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE float ++#define ITYPE int + #define OP == + #define INV_OP != + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ + /* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c +@@ -11,3 +11,4 @@ + /* { dg-final { scan-assembler "fdiv\\tv" } } */ + /* { dg-final { scan-assembler "fneg\\tv" } } */ + /* { dg-final { scan-assembler "fabs\\tv" } } */ ++/* { dg-final { scan-assembler "fabd\\tv" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/adds1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/adds1.c +@@ -0,0 +1,149 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + -+ PR debug/57351 -+ * gcc.dg/debug/pr57351.c: New test ++extern void abort (void); + -+2013-06-03 Christophe Lyon -+ Backport from trunk r198890,199254,199294,199454. ++int ++adds_si_test1 (int a, int b, int c) ++{ ++ int d = a + b; + -+ 2013-05-30 Ian Bolton ++ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ * gcc.target/aarch64/insv_1.c: New test. ++int ++adds_si_test2 (int a, int b, int c) ++{ ++ int d = a + 0xff; + -+ 2013-05-24 Ian Bolton ++ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, 255" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ * gcc.target/aarch64/scalar_intrinsics.c -+ (force_simd): Use a valid instruction. -+ (test_vdupd_lane_s64): Pass a valid lane argument. -+ (test_vdupd_lane_u64): Likewise. ++int ++adds_si_test3 (int a, int b, int c) ++{ ++ int d = a + (b << 3); + -+ 2013-05-23 Vidya Praveen ++ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ * gcc.target/aarch64/vect-clz.c: New file. ++typedef long long s64; + -+ 2013-05-14 James Greenhalgh ++s64 ++adds_di_test1 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a + b; + -+ * gcc.target/aarch64/vect-fcm.x: Add cases testing -+ FLOAT cmp FLOAT ? INT : INT. -+ * gcc.target/aarch64/vect-fcm-eq-d.c: Define IMODE. -+ * gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. -+ * gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. -+ * gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. -+ * gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. -+ * gcc.target/aarch64/vect-fcm-gt-f.c: Likewise. ++ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+2013-05-29 Christophe Lyon ++s64 ++adds_di_test2 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a + 0xff; + -+ Backport from trunk r198928. -+ 2013-05-15 Ramana Radhakrishnan ++ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, 255" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ PR target/19599 -+ * gcc.target/arm/pr40887.c: Adjust testcase. -+ * gcc.target/arm/pr19599.c: New test. ++s64 ++adds_di_test3 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a + (b << 3); + -+2013-05-28 Christophe Lyon ++ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ Backport from trunk r198680. -+ 2013-05-07 Sofiane Naci ++int main () ++{ ++ int x; ++ s64 y; + -+ * gcc.target/aarch64/scalar_intrinsics.c: Update. ++ x = adds_si_test1 (29, 4, 5); ++ if (x != 42) ++ abort (); + -+2013-05-28 Christophe Lyon ++ x = adds_si_test1 (5, 2, 20); ++ if (x != 29) ++ abort (); + -+ Backport from trunk r198499-198500. -+ 2013-05-01 James Greenhalgh -+ * gcc.target/aarch64/vect-vaddv.c: New. ++ x = adds_si_test2 (29, 4, 5); ++ if (x != 293) ++ abort (); + -+ 2013-05-01 James Greenhalgh ++ x = adds_si_test2 (1024, 2, 20); ++ if (x != 1301) ++ abort (); + -+ * gcc.target/aarch64/vect-vmaxv.c: New. -+ * gcc.target/aarch64/vect-vfmaxv.c: Likewise. ++ x = adds_si_test3 (35, 4, 5); ++ if (x != 76) ++ abort (); + -+2013-05-23 Christophe Lyon ++ x = adds_si_test3 (5, 2, 20); ++ if (x != 43) ++ abort (); + -+ Backport from trunk r198970. -+ 2013-05-16 Greta Yorsh ++ y = adds_di_test1 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); + -+ * gcc.target/arm/unaligned-memcpy-2.c: Adjust expected output. -+ * gcc.target/arm/unaligned-memcpy-3.c: Likewise. -+ * gcc.target/arm/unaligned-memcpy-4.c: Likewise. ++ if (y != 0xc75050536) ++ abort (); + -+2013-05-14 Matthew Gretton-Dann ++ y = adds_di_test1 (0x5000500050005ll, ++ 0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x9222922294249) ++ abort (); + -+ GCC Linaro 4.8-2013.05 released. ++ y = adds_di_test2 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != 0x955050631) ++ abort (); + -+2013-05-14 Matthew Gretton-Dann ++ y = adds_di_test2 (0x130002900ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != 0x955052f08) ++ abort (); + -+ Backport from trunk r198574-198575. -+ 2013-05-03 Vidya Praveen ++ y = adds_di_test3 (0x130000029ll, ++ 0x064000008ll, ++ 0x505050505ll); ++ if (y != 0x9b9050576) ++ abort (); + -+ * gcc.target/aarch64/fabd.c: New file. ++ y = adds_di_test3 (0x130002900ll, ++ 0x088000008ll, ++ 0x505050505ll); ++ if (y != 0xafd052e4d) ++ abort (); + -+2013-05-14 Matthew Gretton-Dann ++ return 0; ++} + -+ Backport from trunk r198490-198496. -+ 2013-05-01 James Greenhalgh ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/insv_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/insv_1.c +@@ -0,0 +1,85 @@ ++/* { dg-do run { target aarch64*-*-* } } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-require-effective-target aarch64_little_endian } */ + -+ * gcc.target/aarch64/scalar-vca.c: New. -+ * gcc.target/aarch64/vect-vca.c: Likewise. ++extern void abort (void); + -+ 2013-05-01 James Greenhalgh ++typedef struct bitfield ++{ ++ unsigned short eight: 8; ++ unsigned short four: 4; ++ unsigned short five: 5; ++ unsigned short seven: 7; ++ unsigned int sixteen: 16; ++} bitfield; + -+ * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New. -+ (test_vceqd_s64): Force arguments to SIMD registers. -+ (test_vceqzd_s64): Likewise. -+ (test_vcged_s64): Likewise. -+ (test_vcled_s64): Likewise. -+ (test_vcgezd_s64): Likewise. -+ (test_vcged_u64): Likewise. -+ (test_vcgtd_s64): Likewise. -+ (test_vcltd_s64): Likewise. -+ (test_vcgtzd_s64): Likewise. -+ (test_vcgtd_u64): Likewise. -+ (test_vclezd_s64): Likewise. -+ (test_vcltzd_s64): Likewise. -+ (test_vtst_s64): Likewise. -+ (test_vtst_u64): Likewise. ++bitfield ++bfi1 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 0, 8" } } */ ++ a.eight = 3; ++ return a; ++} + -+2013-05-14 Matthew Gretton-Dann ++bitfield ++bfi2 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 16, 5" } } */ ++ a.five = 7; ++ return a; ++} + -+ Backport from trunk r198191. -+ 2013-04-23 Sofiane Naci ++bitfield ++movk (bitfield a) ++{ ++ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 32" } } */ ++ a.sixteen = 7531; ++ return a; ++} + -+ * gcc.target/aarch64/scalar-mov.c: New testcase. ++bitfield ++set1 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 2031616" } } */ ++ a.five = 0x1f; ++ return a; ++} + -+2013-05-14 Matthew Gretton-Dann ++bitfield ++set0 (bitfield a) ++{ ++ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -2031617" } } */ ++ a.five = 0; ++ return a; ++} + -+ Backport from trunk r197838. -+ 2013-04-11 Naveen H.S + -+ * gcc.target/aarch64/negs.c: New. ++int ++main (int argc, char** argv) ++{ ++ static bitfield a; ++ bitfield b = bfi1 (a); ++ bitfield c = bfi2 (b); ++ bitfield d = movk (c); + -+2013-05-02 Matthew Gretton-Dann ++ if (d.eight != 3) ++ abort (); + -+ Backport from trunk r198019. -+ 2013-04-16 Naveen H.S ++ if (d.five != 7) ++ abort (); + -+ * gcc.target/aarch64/adds1.c: New. -+ * gcc.target/aarch64/adds2.c: New. -+ * gcc.target/aarch64/subs1.c: New. -+ * gcc.target/aarch64/subs2.c: New. ++ if (d.sixteen != 7531) ++ abort (); + -+2013-05-02 Matthew Gretton-Dann ++ d = set1 (d); ++ if (d.five != 0x1f) ++ abort (); + -+ Backport from trunk r198394,198396-198400,198402-198404,198406. -+ 2013-04-29 James Greenhalgh ++ d = set0 (d); ++ if (d.five != 0) ++ abort (); + -+ * lib/target-supports.exp (vect_uintfloat_cvt): Enable for AArch64. ++ return 0; ++} + -+ 2013-04-29 James Greenhalgh ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/ror.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/ror.c +@@ -0,0 +1,34 @@ ++/* { dg-options "-O2 --save-temps" } */ ++/* { dg-do run } */ + -+ * gcc.target/aarch64/vect-vcvt.c: New. ++extern void abort (void); + -+ 2013-04-29 James Greenhalgh ++int ++test_si (int a) ++{ ++ /* { dg-final { scan-assembler "ror\tw\[0-9\]+, w\[0-9\]+, 27\n" } } */ ++ return (a << 5) | ((unsigned int) a >> 27); ++} + -+ * gcc.target/aarch64/vect-vrnd.c: New. ++long long ++test_di (long long a) ++{ ++ /* { dg-final { scan-assembler "ror\tx\[0-9\]+, x\[0-9\]+, 45\n" } } */ ++ return (a << 19) | ((unsigned long long) a >> 45); ++} + -+2013-05-02 Matthew Gretton-Dann ++int ++main () ++{ ++ int v; ++ long long w; ++ v = test_si (0x0203050); ++ if (v != 0x4060a00) ++ abort(); ++ w = test_di (0x0000020506010304ll); ++ if (w != 0x1028300818200000ll) ++ abort(); ++ return 0; ++} + -+ Backport from trunk r198302-198306,198316. -+ 2013-04-25 James Greenhalgh -+ Tejas Belagod ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/ands_1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/ands_1.c +@@ -0,0 +1,151 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + -+ * gcc.target/aarch64/vaddv-intrinsic.c: New. -+ * gcc.target/aarch64/vaddv-intrinsic-compile.c: Likewise. -+ * gcc.target/aarch64/vaddv-intrinsic.x: Likewise. ++extern void abort (void); + -+ 2013-04-25 Naveen H.S ++int ++ands_si_test1 (int a, int b, int c) ++{ ++ int d = a & b; + -+ * gcc.target/aarch64/cmp.c: New. ++ /* { dg-final { scan-assembler-times "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ 2013-04-25 Naveen H.S ++int ++ands_si_test2 (int a, int b, int c) ++{ ++ int d = a & 0xff; + -+ * gcc.target/aarch64/ngc.c: New. ++ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, 255" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+2013-05-02 Matthew Gretton-Dann ++int ++ands_si_test3 (int a, int b, int c) ++{ ++ int d = a & (b << 3); + -+ Backport from trunk r198298. -+ 2013-04-25 Kyrylo Tkachov ++ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ * lib/target-supports.exp -+ (check_effective_target_arm_neon_fp16_ok_nocache): New procedure. -+ (check_effective_target_arm_neon_fp16_ok): Likewise. -+ (add_options_for_arm_neon_fp16): Likewise. -+ * gcc.target/arm/neon/vcvtf16_f32.c: New test. Generated. -+ * gcc.target/arm/neon/vcvtf32_f16.c: Likewise. ++typedef long long s64; + -+2013-05-02 Matthew Gretton-Dann ++s64 ++ands_di_test1 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & b; + -+ Backport from trunk r198136-198137,198142,198176 -+ 2013-04-22 James Greenhalgh ++ /* { dg-final { scan-assembler-times "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ * gcc.target/aarch64/vrecps.c: New. -+ * gcc.target/aarch64/vrecpx.c: Likewise. -+ -+2013-05-02 Matthew Gretton-Dann ++s64 ++ands_di_test2 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & 0xff; + -+ Backport from trunk r198020. -+ 2013-04-16 Naveen H.S ++ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, 255" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ * gcc.target/aarch64/adds3.c: New. -+ * gcc.target/aarch64/subs3.c: New. ++s64 ++ands_di_test3 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a & (b << 3); + -+2013-05-02 Matthew Gretton-Dann ++ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+ Backport from trunk r197965. -+ 2013-04-15 Kyrylo Tkachov ++int ++main () ++{ ++ int x; ++ s64 y; + -+ * gcc.target/arm/anddi3-opt.c: New test. -+ * gcc.target/arm/anddi3-opt2.c: Likewise. ++ x = ands_si_test1 (29, 4, 5); ++ if (x != 13) ++ abort (); + -+2013-05-02 Matthew Gretton-Dann ++ x = ands_si_test1 (5, 2, 20); ++ if (x != 25) ++ abort (); + -+ Backport from trunk r197642. -+ 2013-04-09 Kyrylo Tkachov ++ x = ands_si_test2 (29, 4, 5); ++ if (x != 38) ++ abort (); + -+ * gcc.target/arm/minmax_minus.c: New test. ++ x = ands_si_test2 (1024, 2, 20); ++ if (x != 1044) ++ abort (); + -+2013-05-02 Matthew Gretton-Dann ++ x = ands_si_test3 (35, 4, 5); ++ if (x != 41) ++ abort (); + -+ Backport from trunk r197530,197921. -+ 2013-04-05 Greta Yorsh ++ x = ands_si_test3 (5, 2, 20); ++ if (x != 25) ++ abort (); + -+ * gcc.target/arm/peep-ldrd-1.c: New test. -+ * gcc.target/arm/peep-strd-1.c: Likewise. ++ y = ands_di_test1 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); + -+2013-05-02 Matthew Gretton-Dann ++ if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll)) ++ abort (); + -+ Backport from trunk r197523. -+ 2013-04-05 Kyrylo Tkachov ++ y = ands_di_test1 (0x5000500050005ll, ++ 0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x5000500052025ll) ++ abort (); + -+ * lib/target-supports.exp (add_options_for_arm_v8_neon): -+ Add -march=armv8-a when we use v8 NEON. -+ (check_effective_target_vect_call_btruncf): Remove arm-*-*-*. -+ (check_effective_target_vect_call_ceilf): Likewise. -+ (check_effective_target_vect_call_floorf): Likewise. -+ (check_effective_target_vect_call_roundf): Likewise. -+ (check_vect_support_and_set_flags): Remove check for arm_v8_neon. -+ * gcc.target/arm/vect-rounding-btruncf.c: New testcase. -+ * gcc.target/arm/vect-rounding-ceilf.c: Likewise. -+ * gcc.target/arm/vect-rounding-floorf.c: Likewise. -+ * gcc.target/arm/vect-rounding-roundf.c: Likewise. ++ y = ands_di_test2 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != ((0x130000029ll & 0xff) + 0x320000004ll + 0x505050505ll)) ++ abort (); + -+2013-05-02 Matthew Gretton-Dann ++ y = ands_di_test2 (0x130002900ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != (0x130002900ll + 0x505050505ll)) ++ abort (); + -+ Backport from trunk r197518-197522,197516-197528. -+ 2013-04-05 Greta Yorsh ++ y = ands_di_test3 (0x130000029ll, ++ 0x064000008ll, ++ 0x505050505ll); ++ if (y != ((0x130000029ll & (0x064000008ll << 3)) ++ + 0x064000008ll + 0x505050505ll)) ++ abort (); + -+ * gcc.target/arm/negdi-1.c: New test. -+ * gcc.target/arm/negdi-2.c: Likewise. -+ * gcc.target/arm/negdi-3.c: Likewise. -+ * gcc.target/arm/negdi-4.c: Likewise. ++ y = ands_di_test3 (0x130002900ll, ++ 0x088000008ll, ++ 0x505050505ll); ++ if (y != (0x130002900ll + 0x505050505ll)) ++ abort (); + -+2013-05-02 Matthew Gretton-Dann ++ return 0; ++} + -+ Backport from trunk r197489-197491. -+ 2013-04-04 Kyrylo Tkachov ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c +@@ -1,43 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2" } */ + +-int v = 0; ++#include "atomic-op-release.x" + +-int +-atomic_fetch_add_RELEASE (int a) +-{ +- return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE); +-} +- +-int +-atomic_fetch_sub_RELEASE (int a) +-{ +- return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE); +-} +- +-int +-atomic_fetch_and_RELEASE (int a) +-{ +- return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE); +-} +- +-int +-atomic_fetch_nand_RELEASE (int a) +-{ +- return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE); +-} +- +-int +-atomic_fetch_xor_RELEASE (int a) +-{ +- return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE); +-} +- +-int +-atomic_fetch_or_RELEASE (int a) +-{ +- return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE); +-} +- + /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c +@@ -0,0 +1,169 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps -ffast-math" } */ + -+ * lib/target-supports.exp (check_effective_target_arm_v8_neon_hw): -+ New procedure. -+ (check_effective_target_arm_v8_neon_ok_nocache): -+ Likewise. -+ (check_effective_target_arm_v8_neon_ok): Change to use -+ check_effective_target_arm_v8_neon_ok_nocache. -+ (add_options_for_arm_v8_neon): Use et_arm_v8_neon_flags to set ARMv8 -+ NEON flags. -+ (check_effective_target_vect_call_btruncf): -+ Enable for arm and ARMv8 NEON. -+ (check_effective_target_vect_call_ceilf): Likewise. -+ (check_effective_target_vect_call_floorf): Likewise. -+ (check_effective_target_vect_call_roundf): Likewise. -+ (check_vect_support_and_set_flags): Handle ARMv8 NEON effective -+ target. ++#include + -+2013-05-02 Matthew Gretton-Dann ++extern void abort (void); + -+ Backport from trunk r196795-196797,196957. -+ 2013-03-19 Ian Bolton ++extern float fabsf (float); ++extern double fabs (double); ++extern int isnan (double); ++extern float fmaxf (float, float); ++extern float fminf (float, float); ++extern double fmax (double, double); ++extern double fmin (double, double); + -+ * gcc.target/aarch64/sbc.c: New test. ++#define NUM_TESTS 16 ++#define DELTA 0.000001 ++#define NAN (0.0 / 0.0) + -+ 2013-03-19 Ian Bolton ++float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f, ++ 200.0f, -800.0f, -13.0f, -0.5f, ++ NAN, -870.0f, 10.4f, 310.11f, ++ 0.0f, -865.0f, -2213.0f, -1.5f}; + -+ * gcc.target/aarch64/ror.c: New test. ++double input_float64[] = {0.1, -0.1, 0.4, 10.3, ++ 200.0, -800.0, -13.0, -0.5, ++ NAN, -870.0, 10.4, 310.11, ++ 0.0, -865.0, -2213.0, -1.5}; + -+ 2013-03-19 Ian Bolton ++#define EQUALF(a, b) (fabsf (a - b) < DELTA) ++#define EQUALD(a, b) (fabs (a - b) < DELTA) + -+ * gcc.target/aarch64/extr.c: New test. ++/* Floating point 'unordered' variants. */ + -+2013-04-09 Matthew Gretton-Dann ++#undef TEST ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ ++int \ ++test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \ ++{ \ ++ int i, j; \ ++ int moves = (NUM_TESTS - LANES) + 1; \ ++ TYPE##_t out_l[NUM_TESTS]; \ ++ TYPE##_t out_v[NUM_TESTS]; \ ++ \ ++ /* Calculate linearly. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ out_l[i] = input_##TYPE[i]; \ ++ for (j = 0; j < LANES; j++) \ ++ { \ ++ if (isnan (out_l[i])) \ ++ continue; \ ++ if (isnan (input_##TYPE[i + j]) \ ++ || input_##TYPE[i + j] CMP_OP out_l[i]) \ ++ out_l[i] = input_##TYPE[i + j]; \ ++ } \ ++ } \ ++ \ ++ /* Calculate using vector reduction intrinsics. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ ++ out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1); \ ++ } \ ++ \ ++ /* Compare. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ if (!EQUAL##FLOAT (out_v[i], out_l[i]) \ ++ && !(isnan (out_v[i]) && isnan (out_l[i]))) \ ++ return 0; \ ++ } \ ++ return 1; \ ++} + -+ * GCC Linaro 4.8-2013.04 released. ++#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F) \ ++TEST (max, >, STYPE, , TYPE, W32, F) \ ++TEST (max, >, STYPE, q, TYPE, W64, F) \ ++TEST (min, <, STYPE, , TYPE, W32, F) \ ++TEST (min, <, STYPE, q, TYPE, W64, F) + -+2013-04-08 Matthew Gretton-Dann ++BUILD_VARIANTS (float32, f32, 2, 4, F) ++/* { dg-final { scan-assembler "fmaxp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fminp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fmaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++TEST (max, >, f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "fmaxp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ ++TEST (min, <, f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "fminp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ + -+ Backport from trunk r197052. -+ 2013-03-25 Kyrylo Tkachov ++/* Floating point 'nm' variants. */ + -+ * gcc.target/arm/vseleqdf.c: New test. -+ * gcc.target/arm/vseleqsf.c: Likewise. -+ * gcc.target/arm/vselgedf.c: Likewise. -+ * gcc.target/arm/vselgesf.c: Likewise. -+ * gcc.target/arm/vselgtdf.c: Likewise. -+ * gcc.target/arm/vselgtsf.c: Likewise. -+ * gcc.target/arm/vselledf.c: Likewise. -+ * gcc.target/arm/vsellesf.c: Likewise. -+ * gcc.target/arm/vselltdf.c: Likewise. -+ * gcc.target/arm/vselltsf.c: Likewise. -+ * gcc.target/arm/vselnedf.c: Likewise. -+ * gcc.target/arm/vselnesf.c: Likewise. -+ * gcc.target/arm/vselvcdf.c: Likewise. -+ * gcc.target/arm/vselvcsf.c: Likewise. -+ * gcc.target/arm/vselvsdf.c: Likewise. -+ * gcc.target/arm/vselvssf.c: Likewise. ++#undef TEST ++#define TEST(MAXMIN, F, SUFFIX, Q, TYPE, LANES, FLOAT) \ ++int \ ++test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t (void) \ ++{ \ ++ int i, j; \ ++ int moves = (NUM_TESTS - LANES) + 1; \ ++ TYPE##_t out_l[NUM_TESTS]; \ ++ TYPE##_t out_v[NUM_TESTS]; \ ++ \ ++ /* Calculate linearly. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ out_l[i] = input_##TYPE[i]; \ ++ for (j = 0; j < LANES; j++) \ ++ out_l[i] = f##MAXMIN##F (input_##TYPE[i + j], out_l[i]); \ ++ } \ ++ \ ++ /* Calculate using vector reduction intrinsics. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \ ++ out_v[i] = v##MAXMIN##nmv##Q##_##SUFFIX (t1); \ ++ } \ ++ \ ++ /* Compare. */ \ ++ for (i = 0; i < moves; i++) \ ++ { \ ++ if (!EQUAL##FLOAT (out_v[i], out_l[i])) \ ++ return 0; \ ++ } \ ++ return 1; \ ++} + -+2013-04-08 Matthew Gretton-Dann ++TEST (max, f, f32, , float32, 2, D) ++/* { dg-final { scan-assembler "fmaxnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++TEST (min, f, f32, , float32, 2, D) ++/* { dg-final { scan-assembler "fminnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */ ++TEST (max, f, f32, q, float32, 4, D) ++/* { dg-final { scan-assembler "fmaxnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++TEST (min, f, f32, q, float32, 4, D) ++/* { dg-final { scan-assembler "fminnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */ ++TEST (max, , f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "fmaxnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ ++TEST (min, , f64, q, float64, 2, D) ++/* { dg-final { scan-assembler "fminnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */ + -+ Backport from trunk r197051. -+ 2013-03-25 Kyrylo Tkachov ++#undef TEST ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ ++{ \ ++ if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ()) \ ++ abort (); \ ++} + -+ * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move test -+ body from here... -+ * gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to here. -+ * gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-acq_rel.x: ... to here. -+ * gcc.target/aarch64/atomic-op-acquire.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-acquire.x: ... to here. -+ * gcc.target/aarch64/atomic-op-char.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-char.x: ... to here. -+ * gcc.target/aarch64/atomic-op-consume.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-consume.x: ... to here. -+ * gcc.target/aarch64/atomic-op-int.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-int.x: ... to here. -+ * gcc.target/aarch64/atomic-op-relaxed.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-relaxed.x: ... to here. -+ * gcc.target/aarch64/atomic-op-release.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-release.x: ... to here. -+ * gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-seq_cst.x: ... to here. -+ * gcc.target/aarch64/atomic-op-short.c: Move test body from here... -+ * gcc.target/aarch64/atomic-op-short.x: ... to here. -+ * gcc.target/arm/atomic-comp-swap-release-acquire.c: New test. -+ * gcc.target/arm/atomic-op-acq_rel.c: Likewise. -+ * gcc.target/arm/atomic-op-acquire.c: Likewise. -+ * gcc.target/arm/atomic-op-char.c: Likewise. -+ * gcc.target/arm/atomic-op-consume.c: Likewise. -+ * gcc.target/arm/atomic-op-int.c: Likewise. -+ * gcc.target/arm/atomic-op-relaxed.c: Likewise. -+ * gcc.target/arm/atomic-op-release.c: Likewise. -+ * gcc.target/arm/atomic-op-seq_cst.c: Likewise. -+ * gcc.target/arm/atomic-op-short.c: Likewise. ++int ++main (int argc, char **argv) ++{ ++ BUILD_VARIANTS (float32, f32, 2, 4, F) ++ TEST (max, >, f64, q, float64, 2, D) ++ TEST (min, <, f64, q, float64, 2, D) + -+2013-04-08 Matthew Gretton-Dann ++#undef TEST ++#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \ ++{ \ ++ if (!test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t ()) \ ++ abort (); \ ++} + -+ Backport from trunk r196876. -+ 2013-03-21 Christophe Lyon ++ BUILD_VARIANTS (float32, f32, 2, 4, F) ++ TEST (max, >, f64, q, float64, 2, D) ++ TEST (min, <, f64, q, float64, 2, D) + -+ * gcc.target/arm/neon-for-64bits-1.c: New tests. -+ * gcc.target/arm/neon-for-64bits-2.c: Likewise. ++ return 0; ++} + -+2013-04-08 Matthew Gretton-Dann ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x +@@ -0,0 +1,37 @@ ++short v = 0; + -+ Backport from trunk r196858. -+ 2013-03-21 Naveen H.S ++short ++atomic_fetch_add_RELAXED (short a) ++{ ++ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); ++} + -+ * gcc.target/aarch64/vect.c: Test and result vector added -+ for sabd and saba instructions. -+ * gcc.target/aarch64/vect-compile.c: Check for sabd and saba -+ instructions in assembly. -+ * gcc.target/aarch64/vect.x: Add sabd and saba test functions. -+ * gcc.target/aarch64/vect-fp.c: Test and result vector added -+ for fabd instruction. -+ * gcc.target/aarch64/vect-fp-compile.c: Check for fabd -+ instruction in assembly. -+ * gcc.target/aarch64/vect-fp.x: Add fabd test function. ---- a/src/gcc/testsuite/gcc.dg/debug/pr57351.c -+++ b/src/gcc/testsuite/gcc.dg/debug/pr57351.c -@@ -0,0 +1,54 @@ -+/* { dg-do compile } */ -+/* { dg-require-effective-target arm_neon } */ -+/* { dg-options "-std=c99 -Os -g -march=armv7-a" } */ -+/* { dg-add-options arm_neon } */ ++short ++atomic_fetch_sub_RELAXED (short a) ++{ ++ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); ++} + -+typedef unsigned int size_t; -+typedef int ptrdiff_t; -+typedef signed char int8_t ; -+typedef signed long long int64_t; -+typedef int8_t GFC_INTEGER_1; -+typedef GFC_INTEGER_1 GFC_LOGICAL_1; -+typedef int64_t GFC_INTEGER_8; -+typedef GFC_INTEGER_8 GFC_LOGICAL_8; -+typedef ptrdiff_t index_type; -+typedef struct descriptor_dimension ++short ++atomic_fetch_and_RELAXED (short a) +{ -+ index_type lower_bound; -+ index_type _ubound; ++ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} -+descriptor_dimension; -+typedef struct { GFC_LOGICAL_1 *base_addr; size_t offset; index_type dtype; descriptor_dimension dim[7];} gfc_array_l1; -+typedef struct { GFC_LOGICAL_8 *base_addr; size_t offset; index_type dtype; descriptor_dimension dim[7];} gfc_array_l8; -+void -+all_l8 (gfc_array_l8 * const restrict retarray, -+ gfc_array_l1 * const restrict array, -+ const index_type * const restrict pdim) ++ ++short ++atomic_fetch_nand_RELAXED (short a) +{ -+ GFC_LOGICAL_8 * restrict dest; -+ index_type n; -+ index_type len; -+ index_type delta; -+ index_type dim; -+ dim = (*pdim) - 1; -+ len = ((array)->dim[dim]._ubound + 1 - (array)->dim[dim].lower_bound); -+ for (n = 0; n < dim; n++) -+ { -+ const GFC_LOGICAL_1 * restrict src; -+ GFC_LOGICAL_8 result; -+ { -+ result = 1; -+ { -+ for (n = 0; n < len; n++, src += delta) -+ { -+ if (! *src) -+ { -+ result = 0; -+ break; -+ } -+ } -+ *dest = result; -+ } -+ } -+ } ++ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} ---- a/src/gcc/testsuite/g++.dg/asan/large-func-test-1.C -+++ b/src/gcc/testsuite/g++.dg/asan/large-func-test-1.C -@@ -37,9 +37,9 @@ - - // { dg-output "ERROR: AddressSanitizer:? heap-buffer-overflow on address\[^\n\r]*" } - // { dg-output "0x\[0-9a-f\]+ at pc 0x\[0-9a-f\]+ bp 0x\[0-9a-f\]+ sp 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } --// { dg-output "READ of size 4 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } -+// { dg-output "\[^\n\r]*READ of size 4 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } - // { dg-output " #0 0x\[0-9a-f\]+ (in \[^\n\r]*LargeFunction\[^\n\r]*(large-func-test-1.C:18|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } --// { dg-output "0x\[0-9a-f\]+ is located 44 bytes to the right of 400-byte region.*(\n|\r\n|\r)" } --// { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } -+// { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 44 bytes to the right of 400-byte region.*(\n|\r\n|\r)" } -+// { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } - // { dg-output " #0( 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } - // { dg-output " #1|) 0x\[0-9a-f\]+ (in (operator new|_*_Zn\[aw\]\[mj\])|\[(\])\[^\n\r]*(\n|\r\n|\r)" } ---- a/src/gcc/testsuite/g++.dg/asan/deep-thread-stack-1.C -+++ b/src/gcc/testsuite/g++.dg/asan/deep-thread-stack-1.C -@@ -45,9 +45,9 @@ - } - - // { dg-output "ERROR: AddressSanitizer: heap-use-after-free.*(\n|\r\n|\r)" } --// { dg-output "WRITE of size 4 at 0x\[0-9a-f\]+ thread T(\[0-9\]+).*(\n|\r\n|\r)" } --// { dg-output "freed by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } --// { dg-output "previously allocated by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } -+// { dg-output "\[^\n\r]*WRITE of size 4 at 0x\[0-9a-f\]+ thread T(\[0-9\]+).*(\n|\r\n|\r)" } -+// { dg-output "\[^\n\r]*freed by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } -+// { dg-output "\[^\n\r]*previously allocated by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } - // { dg-output "Thread T\\2 created by T(\[0-9\]+) here:.*(\n|\r\n|\r)" } - // { dg-output "Thread T\\8 created by T0 here:.*(\n|\r\n|\r)" } - // { dg-output "Thread T\\4 created by T(\[0-9\]+) here:.*(\n|\r\n|\r)" } ---- a/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c -+++ b/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c -@@ -15,7 +15,7 @@ - /* { dg-output "WRITE of size \[0-9\]* at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)strncpy|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*strncpy-overflow-1.c:11|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ --/* { dg-output "0x\[0-9a-f\]+ is located 0 bytes to the right of 9-byte region\[^\n\r]*(\n|\r\n|\r)" } */ --/* { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 0 bytes to the right of 9-byte region\[^\n\r]*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*strncpy-overflow-1.c:10|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ ---- a/src/gcc/testsuite/c-c++-common/asan/rlimit-mmap-test-1.c -+++ b/src/gcc/testsuite/c-c++-common/asan/rlimit-mmap-test-1.c -@@ -2,6 +2,7 @@ - - /* { dg-do run { target setrlimit } } */ - /* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */ -+/* { dg-require-effective-target hw } */ - /* { dg-shouldfail "asan" } */ - - #include ---- a/src/gcc/testsuite/c-c++-common/asan/stack-overflow-1.c -+++ b/src/gcc/testsuite/c-c++-common/asan/stack-overflow-1.c -@@ -19,4 +19,4 @@ - - /* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*stack-overflow-1.c:16|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ --/* { dg-output "Address 0x\[0-9a-f\]+ is\[^\n\r]*frame
" } */ -+/* { dg-output "\[^\n\r]*Address 0x\[0-9a-f\]+ is\[^\n\r]*frame
" } */ ---- a/src/gcc/testsuite/c-c++-common/asan/use-after-free-1.c -+++ b/src/gcc/testsuite/c-c++-common/asan/use-after-free-1.c -@@ -11,12 +11,12 @@ - - /* { dg-output "ERROR: AddressSanitizer:? heap-use-after-free on address\[^\n\r]*" } */ - /* { dg-output "0x\[0-9a-f\]+ at pc 0x\[0-9a-f\]+ bp 0x\[0-9a-f\]+ sp 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ --/* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:9|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ --/* { dg-output "0x\[0-9a-f\]+ is located 5 bytes inside of 10-byte region .0x\[0-9a-f\]+,0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ --/* { dg-output "freed by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 5 bytes inside of 10-byte region .0x\[0-9a-f\]+,0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*freed by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)free|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:8|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ --/* { dg-output "previously allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*previously allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:7|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ ---- a/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c -+++ b/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c -@@ -3,6 +3,7 @@ - - /* { dg-do run { target { *-*-linux* } } } */ - /* { dg-require-effective-target clone } */ -+/* { dg-require-effective-target hw } */ - /* { dg-options "-D_GNU_SOURCE" } */ - - #include ---- a/src/gcc/testsuite/c-c++-common/asan/heap-overflow-1.c -+++ b/src/gcc/testsuite/c-c++-common/asan/heap-overflow-1.c -@@ -25,7 +25,7 @@ - - /* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0.*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*heap-overflow-1.c:21|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ --/* { dg-output "0x\[0-9a-f\]+ is located 0 bytes to the right of 10-byte region\[^\n\r]*(\n|\r\n|\r)" } */ --/* { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 0 bytes to the right of 10-byte region\[^\n\r]*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*heap-overflow-1.c:19|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ ---- a/src/gcc/testsuite/c-c++-common/asan/null-deref-1.c -+++ b/src/gcc/testsuite/c-c++-common/asan/null-deref-1.c -@@ -18,6 +18,6 @@ - - /* { dg-output "ERROR: AddressSanitizer:? SEGV on unknown address\[^\n\r]*" } */ - /* { dg-output "0x\[0-9a-f\]+ \[^\n\r]*pc 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ --/* { dg-output "AddressSanitizer can not provide additional info.*(\n|\r\n|\r)" } */ -+/* { dg-output "\[^\n\r]*AddressSanitizer can not provide additional info.*(\n|\r\n|\r)" } */ - /* { dg-output " #0 0x\[0-9a-f\]+ (in \[^\n\r]*NullDeref\[^\n\r]* (\[^\n\r]*null-deref-1.c:10|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ - /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*null-deref-1.c:15|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ ---- a/src/gcc/objcp/ChangeLog.linaro -+++ b/src/gcc/objcp/ChangeLog.linaro -@@ -0,0 +1,11 @@ -+2013-06-11 Rob Savoye + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++short ++atomic_fetch_xor_RELAXED (short a) ++{ ++ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); ++} + -+2013-05-14 Matthew Gretton-Dann ++short ++atomic_fetch_or_RELAXED (short a) ++{ ++ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c +@@ -0,0 +1,132 @@ ++/* { dg-do run } */ ++/* { dg-options "-O3 --save-temps -ffast-math" } */ + -+ GCC Linaro 4.8-2013.05 released. ++#include + -+2013-04-09 Matthew Gretton-Dann ++extern void abort (void); ++extern double fabs (double); + -+ * GCC Linaro 4.8-2013.04 released. ---- a/src/gcc/cp/ChangeLog.linaro -+++ b/src/gcc/cp/ChangeLog.linaro -@@ -0,0 +1,11 @@ -+2013-06-11 Rob Savoye ++#define NUM_TESTS 8 ++#define DELTA 0.000001 + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f, ++ 200.0f, -800.0f, -13.0f, -0.5f}; ++double input_f64[] = {0.1, -0.1, 0.4, 10.3, ++ 200.0, -800.0, -13.0, -0.5}; + -+2013-05-14 Matthew Gretton-Dann ++#define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D) \ ++int \ ++test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t (void) \ ++{ \ ++ int ret = 1; \ ++ int i = 0; \ ++ int nlanes = LANES; \ ++ U##int##WIDTH##_t expected_out[NUM_TESTS]; \ ++ U##int##WIDTH##_t actual_out[NUM_TESTS]; \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ { \ ++ expected_out[i] \ ++ = vcvt##SUFFIX##D##_##S##WIDTH##_f##WIDTH (input_f##WIDTH[i]); \ ++ /* Don't vectorize this. */ \ ++ asm volatile ("" : : : "memory"); \ ++ } \ ++ \ ++ for (i = 0; i < NUM_TESTS; i+=nlanes) \ ++ { \ ++ U##int##WIDTH##x##LANES##_t out = \ ++ vcvt##SUFFIX##Q##_##S##WIDTH##_f##WIDTH \ ++ (vld1##Q##_f##WIDTH (input_f##WIDTH + i)); \ ++ vst1##Q##_##S##WIDTH (actual_out + i, out); \ ++ } \ ++ \ ++ for (i = 0; i < NUM_TESTS; i++) \ ++ ret &= fabs (expected_out[i] - actual_out[i]) < DELTA; \ ++ \ ++ return ret; \ ++} \ + -+ GCC Linaro 4.8-2013.05 released. + -+2013-04-09 Matthew Gretton-Dann ++#define BUILD_VARIANTS(SUFFIX) \ ++TEST (SUFFIX, , 32, 2, s, ,s) \ ++TEST (SUFFIX, q, 32, 4, s, ,s) \ ++TEST (SUFFIX, q, 64, 2, s, ,d) \ ++TEST (SUFFIX, , 32, 2, u,u,s) \ ++TEST (SUFFIX, q, 32, 4, u,u,s) \ ++TEST (SUFFIX, q, 64, 2, u,u,d) \ + -+ * GCC Linaro 4.8-2013.04 released. ---- a/src/gcc/rtl.def -+++ b/src/gcc/rtl.def -@@ -937,8 +937,9 @@ - relational operator. Operands should have only one alternative. - 1: A C expression giving an additional condition for recognizing - the generated pattern. -- 2: A template or C code to produce assembler output. */ --DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) -+ 2: A template or C code to produce assembler output. -+ 3: A vector of attributes to append to the resulting cond_exec insn. */ -+DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA) - - /* Definition of an operand predicate. The difference between - DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will ---- a/src/gcc/go/ChangeLog.linaro -+++ b/src/gcc/go/ChangeLog.linaro -@@ -0,0 +1,11 @@ -+2013-06-11 Rob Savoye ++BUILD_VARIANTS ( ) ++/* { dg-final { scan-assembler "fcvtzs\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtzs\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtzu\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (a) ++/* { dg-final { scan-assembler "fcvtas\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtas\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "fcvtau\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtau\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (m) ++/* { dg-final { scan-assembler "fcvtms\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtms\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "fcvtmu\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtmu\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (n) ++/* { dg-final { scan-assembler "fcvtns\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtns\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "fcvtnu\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtnu\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++BUILD_VARIANTS (p) ++/* { dg-final { scan-assembler "fcvtps\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtps\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ ++/* { dg-final { scan-assembler "fcvtpu\\tw\[0-9\]+, s\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtpu\\tx\[0-9\]+, d\[0-9\]+" } } */ ++/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ ++/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ ++/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++#undef TEST ++#define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D) \ ++{ \ ++ if (!test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t ()) \ ++ abort (); \ ++} + -+2013-05-14 Matthew Gretton-Dann ++int ++main (int argc, char **argv) ++{ ++ BUILD_VARIANTS ( ) ++ BUILD_VARIANTS (a) ++ BUILD_VARIANTS (m) ++ BUILD_VARIANTS (n) ++ BUILD_VARIANTS (p) ++ return 0; ++} + -+ GCC Linaro 4.8-2013.05 released. ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x +@@ -0,0 +1,37 @@ ++int v = 0; + -+2013-04-09 Matthew Gretton-Dann ++int ++atomic_fetch_add_RELEASE (int a) ++{ ++ return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE); ++} + -+ * GCC Linaro 4.8-2013.04 released. ---- a/src/gcc/ada/ChangeLog.linaro -+++ b/src/gcc/ada/ChangeLog.linaro -@@ -0,0 +1,11 @@ -+2013-06-11 Rob Savoye ++int ++atomic_fetch_sub_RELEASE (int a) ++{ ++ return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE); ++} + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++int ++atomic_fetch_and_RELEASE (int a) ++{ ++ return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE); ++} + -+2013-05-14 Matthew Gretton-Dann ++int ++atomic_fetch_nand_RELEASE (int a) ++{ ++ return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE); ++} + -+ GCC Linaro 4.8-2013.05 released. ++int ++atomic_fetch_xor_RELEASE (int a) ++{ ++ return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE); ++} + -+2013-04-09 Matthew Gretton-Dann ++int ++atomic_fetch_or_RELEASE (int a) ++{ ++ return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE); ++} +--- a/src/gcc/testsuite/gcc.target/aarch64/fabd.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/fabd.c +@@ -0,0 +1,38 @@ ++/* { dg-do run } */ ++/* { dg-options "-O1 -fno-inline --save-temps" } */ + -+ * GCC Linaro 4.8-2013.04 released. ---- a/src/gcc/common/config/aarch64/aarch64-common.c -+++ b/src/gcc/common/config/aarch64/aarch64-common.c -@@ -44,6 +44,8 @@ - { - /* Enable section anchors by default at -O1 or higher. */ - { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, -+ /* Enable redundant extension instructions removal at -O2 and higher. */ -+ { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, - { OPT_LEVELS_NONE, 0, NULL, 0 } - }; - ---- a/src/gcc/fortran/ChangeLog.linaro -+++ b/src/gcc/fortran/ChangeLog.linaro -@@ -0,0 +1,11 @@ -+2013-06-11 Rob Savoye ++extern double fabs (double); ++extern float fabsf (float); ++extern void abort (); ++extern void exit (int); + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++void ++fabd_d (double x, double y, double d) ++{ ++ if ((fabs (x - y) - d) > 0.00001) ++ abort (); ++} + -+2013-05-14 Matthew Gretton-Dann ++/* { dg-final { scan-assembler "fabd\td\[0-9\]+" } } */ + -+ GCC Linaro 4.8-2013.05 released. ++void ++fabd_f (float x, float y, float d) ++{ ++ if ((fabsf (x - y) - d) > 0.00001) ++ abort (); ++} + -+2013-04-09 Matthew Gretton-Dann ++/* { dg-final { scan-assembler "fabd\ts\[0-9\]+" } } */ + -+ * GCC Linaro 4.8-2013.04 released. ---- a/src/gcc/configure.ac -+++ b/src/gcc/configure.ac -@@ -813,7 +813,7 @@ - ) - AC_SUBST(CONFIGURE_SPECS) - --ACX_PKGVERSION([GCC]) -+ACX_PKGVERSION([Linaro GCC `cat $srcdir/LINARO-VERSION`]) - ACX_BUGURL([http://gcc.gnu.org/bugs.html]) ++int ++main () ++{ ++ fabd_d (10.0, 5.0, 5.0); ++ fabd_d (5.0, 10.0, 5.0); ++ fabd_f (10.0, 5.0, 5.0); ++ fabd_f (5.0, 10.0, 5.0); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp.c +@@ -117,6 +117,16 @@ + 9.0, 10.0, 11.0, 12.0, + 13.0, 14.0, 15.0, 16.0 }; - # Sanity check enable_languages in case someone does not run the toplevel ---- a/src/gcc/coretypes.h -+++ b/src/gcc/coretypes.h -@@ -62,6 +62,8 @@ - typedef union gimple_statement_d *gimple; - typedef const union gimple_statement_d *const_gimple; - typedef gimple gimple_seq; -+struct gimple_stmt_iterator_d; -+typedef struct gimple_stmt_iterator_d gimple_stmt_iterator; - union section; - typedef union section section; - struct gcc_options; ---- a/src/gcc/gimple-fold.c -+++ b/src/gcc/gimple-fold.c -@@ -1143,6 +1143,8 @@ - gimplify_and_update_call_from_tree (gsi, result); - changed = true; - } -+ else if (DECL_BUILT_IN_CLASS (callee) == BUILT_IN_MD) -+ changed |= targetm.gimple_fold_builtin (gsi); - } ++ F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f, ++ 1.0f, 1.0f, 1.0f, 1.0f, ++ 1.0f, 1.0f, 1.0f, 1.0f, ++ 1.0f, 1.0f, 1.0f, 1.0f }; ++ ++ F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0, ++ 1.0, 1.0, 1.0, 1.0, ++ 1.0, 1.0, 1.0, 1.0, ++ 1.0, 1.0, 1.0, 1.0 }; ++ + /* Setup input vectors. */ + for (i=1; i<=16; i++) + { +@@ -132,6 +142,7 @@ + TEST (div, 3); + TEST (neg, 2); + TEST (abs, 2); ++ TEST (fabd, 3); - return changed; ---- a/src/gcc/lto/ChangeLog.linaro -+++ b/src/gcc/lto/ChangeLog.linaro -@@ -0,0 +1,11 @@ -+2013-06-11 Rob Savoye + return 0; + } +--- a/src/gcc/testsuite/gcc.target/aarch64/ngc.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/ngc.c +@@ -0,0 +1,66 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++extern void abort (void); ++typedef unsigned int u32; + -+2013-05-14 Matthew Gretton-Dann ++u32 ++ngc_si (u32 a, u32 b, u32 c, u32 d) ++{ ++ a = -b - (c < d); ++ return a; ++} + -+ GCC Linaro 4.8-2013.05 released. ++typedef unsigned long long u64; + -+2013-04-09 Matthew Gretton-Dann ++u64 ++ngc_si_tst (u64 a, u32 b, u32 c, u32 d) ++{ ++ a = -b - (c < d); ++ return a; ++} + -+ * GCC Linaro 4.8-2013.04 released. ---- a/src/gcc/po/ChangeLog.linaro -+++ b/src/gcc/po/ChangeLog.linaro -@@ -0,0 +1,11 @@ -+2013-06-11 Rob Savoye ++u64 ++ngc_di (u64 a, u64 b, u64 c, u64 d) ++{ ++ a = -b - (c < d); ++ return a; ++} + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++int ++main () ++{ ++ int x; ++ u64 y; + -+2013-05-14 Matthew Gretton-Dann ++ x = ngc_si (29, 4, 5, 4); ++ if (x != -4) ++ abort (); + -+ GCC Linaro 4.8-2013.05 released. ++ x = ngc_si (1024, 2, 20, 13); ++ if (x != -2) ++ abort (); + -+2013-04-09 Matthew Gretton-Dann ++ y = ngc_si_tst (0x130000029ll, 32, 50, 12); ++ if (y != 0xffffffe0) ++ abort (); + -+ * GCC Linaro 4.8-2013.04 released. ---- a/src/gcc/gimple.h -+++ b/src/gcc/gimple.h -@@ -130,7 +130,7 @@ - - /* Iterator object for GIMPLE statement sequences. */ - --typedef struct -+struct gimple_stmt_iterator_d - { - /* Sequence node holding the current statement. */ - gimple_seq_node ptr; -@@ -141,9 +141,8 @@ - block/sequence is removed. */ - gimple_seq *seq; - basic_block bb; --} gimple_stmt_iterator; -+}; - -- - /* Data structure definitions for GIMPLE tuples. NOTE: word markers - are for 64 bit hosts. */ - ---- a/src/gcc/config/aarch64/aarch64-simd.md -+++ b/src/gcc/config/aarch64/aarch64-simd.md -@@ -21,7 +21,7 @@ - - ; Main data types used by the insntructions - --(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI" -+(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI" - (const_string "unknown")) - - -@@ -44,6 +44,7 @@ - ; simd_dup duplicate element. - ; simd_dupgp duplicate general purpose register. - ; simd_ext bitwise extract from pair. -+; simd_fabd floating point absolute difference. - ; simd_fadd floating point add/sub. - ; simd_fcmp floating point compare. - ; simd_fcvti floating point convert to integer. -@@ -58,9 +59,9 @@ - ; simd_fmul floating point multiply. - ; simd_fmul_elt floating point multiply (by element). - ; simd_fnegabs floating point neg/abs. --; simd_frcpe floating point reciprocal estimate. --; simd_frcps floating point reciprocal step. --; simd_frecx floating point reciprocal exponent. -+; simd_frecpe floating point reciprocal estimate. -+; simd_frecps floating point reciprocal step. -+; simd_frecpx floating point reciprocal exponent. - ; simd_frint floating point round to integer. - ; simd_fsqrt floating point square root. - ; simd_icvtf integer convert to floating point. -@@ -147,6 +148,7 @@ - simd_dup,\ - simd_dupgp,\ - simd_ext,\ -+ simd_fabd,\ - simd_fadd,\ - simd_fcmp,\ - simd_fcvti,\ -@@ -161,9 +163,9 @@ - simd_fmul,\ - simd_fmul_elt,\ - simd_fnegabs,\ -- simd_frcpe,\ -- simd_frcps,\ -- simd_frecx,\ -+ simd_frecpe,\ -+ simd_frecps,\ -+ simd_frecpx,\ - simd_frint,\ - simd_fsqrt,\ - simd_icvtf,\ -@@ -303,8 +305,8 @@ - (eq_attr "simd_type" "simd_store3,simd_store4") (const_string "neon_vst1_3_4_regs") - (eq_attr "simd_type" "simd_store1s,simd_store2s") (const_string "neon_vst1_vst2_lane") - (eq_attr "simd_type" "simd_store3s,simd_store4s") (const_string "neon_vst3_vst4_lane") -- (and (eq_attr "simd_type" "simd_frcpe,simd_frcps") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vrecps_vrsqrts_ddd") -- (and (eq_attr "simd_type" "simd_frcpe,simd_frcps") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vrecps_vrsqrts_qqq") -+ (and (eq_attr "simd_type" "simd_frecpe,simd_frecps") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vrecps_vrsqrts_ddd") -+ (and (eq_attr "simd_type" "simd_frecpe,simd_frecps") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vrecps_vrsqrts_qqq") - (eq_attr "simd_type" "none") (const_string "none") - ] - (const_string "unknown"))) -@@ -355,15 +357,17 @@ - (set_attr "simd_mode" "")] - ) - --(define_insn "aarch64_dup_lane" -- [(set (match_operand:SDQ_I 0 "register_operand" "=w") -+(define_insn "aarch64_dup_lane_scalar" -+ [(set (match_operand: 0 "register_operand" "=w, r") - (vec_select: -- (match_operand: 1 "register_operand" "w") -- (parallel [(match_operand:SI 2 "immediate_operand" "i")]) -+ (match_operand:VDQ 1 "register_operand" "w, w") -+ (parallel [(match_operand:SI 2 "immediate_operand" "i, i")]) - ))] - "TARGET_SIMD" -- "dup\\t%0, %1.[%2]" -- [(set_attr "simd_type" "simd_dup") -+ "@ -+ dup\\t%0, %1.[%2] -+ umov\\t%0, %1.[%2]" -+ [(set_attr "simd_type" "simd_dup, simd_movgp") - (set_attr "simd_mode" "")] - ) - -@@ -394,7 +398,7 @@ - case 4: return "ins\t%0.d[0], %1"; - case 5: return "mov\t%0, %1"; - case 6: -- return aarch64_output_simd_mov_immediate (&operands[1], -+ return aarch64_output_simd_mov_immediate (operands[1], - mode, 64); - default: gcc_unreachable (); - } -@@ -417,13 +421,13 @@ - case 0: return "ld1\t{%0.}, %1"; - case 1: return "st1\t{%1.}, %0"; - case 2: return "orr\t%0., %1., %1."; -- case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]"; -- case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1"; -+ case 3: return "#"; -+ case 4: return "#"; - case 5: return "#"; - case 6: -- return aarch64_output_simd_mov_immediate (&operands[1], -- mode, 128); -- default: gcc_unreachable (); -+ return aarch64_output_simd_mov_immediate (operands[1], mode, 128); -+ default: -+ gcc_unreachable (); - } - } - [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") -@@ -452,6 +456,105 @@ - aarch64_simd_disambiguate_copy (operands, dest, src, 2); - }) - -+(define_split -+ [(set (match_operand:VQ 0 "register_operand" "") -+ (match_operand:VQ 1 "register_operand" ""))] -+ "TARGET_SIMD && reload_completed -+ && ((FP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) -+ || (GP_REGNUM_P (REGNO (operands[0])) && FP_REGNUM_P (REGNO (operands[1]))))" -+ [(const_int 0)] -+{ -+ aarch64_split_simd_move (operands[0], operands[1]); -+ DONE; -+}) ++ y = ngc_si_tst (0x5000500050005ll, 21, 2, 14); ++ if (y != 0xffffffea) ++ abort (); + -+(define_expand "aarch64_simd_mov" -+ [(set (match_operand:VQ 0) -+ (match_operand:VQ 1))] -+ "TARGET_SIMD" -+ { -+ rtx dst = operands[0]; -+ rtx src = operands[1]; ++ y = ngc_di (0x130000029ll, 0x320000004ll, 0x505050505ll, 0x123123123ll); ++ if (y != 0xfffffffcdffffffc) ++ abort (); + -+ if (GP_REGNUM_P (REGNO (src))) -+ { -+ rtx low_part = gen_lowpart (mode, src); -+ rtx high_part = gen_highpart (mode, src); ++ y = ngc_di (0x5000500050005ll, ++ 0x2111211121112ll, 0x0000000002020ll, 0x1414575046477ll); ++ if (y != 0xfffdeeedeeedeeed) ++ abort (); + -+ emit_insn -+ (gen_aarch64_simd_mov_to_low (dst, low_part)); -+ emit_insn -+ (gen_aarch64_simd_mov_to_high (dst, high_part)); -+ } ++ return 0; ++} + -+ else -+ { -+ rtx low_half = aarch64_simd_vect_par_cnst_half (mode, false); -+ rtx high_half = aarch64_simd_vect_par_cnst_half (mode, true); -+ rtx low_part = gen_lowpart (mode, dst); -+ rtx high_part = gen_highpart (mode, dst); ++/* { dg-final { scan-assembler-times "ngc\tw\[0-9\]+, w\[0-9\]+" 2 } } */ ++/* { dg-final { scan-assembler-times "ngc\tx\[0-9\]+, x\[0-9\]+" 1 } } */ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/cmp.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/cmp.c +@@ -0,0 +1,61 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ + -+ emit_insn -+ (gen_aarch64_simd_mov_from_low (low_part, src, low_half)); -+ emit_insn -+ (gen_aarch64_simd_mov_from_high (high_part, src, high_half)); -+ } -+ DONE; -+ } -+) ++int ++cmp_si_test1 (int a, int b, int c) ++{ ++ if (a > b) ++ return a + c; ++ else ++ return a + b + c; ++} + -+(define_insn "aarch64_simd_mov_to_low" -+ [(set (zero_extract:VQ -+ (match_operand:VQ 0 "register_operand" "+w") -+ (const_int 64) (const_int 0)) -+ (vec_concat:VQ -+ (match_operand: 1 "register_operand" "r") -+ (vec_duplicate: (const_int 0))))] -+ "TARGET_SIMD && reload_completed" -+ "ins\t%0.d[0], %1" -+ [(set_attr "simd_type" "simd_move") -+ (set_attr "simd_mode" "") -+ (set_attr "length" "4") -+ ]) ++int ++cmp_si_test2 (int a, int b, int c) ++{ ++ if ((a >> 3) > b) ++ return a + c; ++ else ++ return a + b + c; ++} + -+(define_insn "aarch64_simd_mov_to_high" -+ [(set (zero_extract:VQ -+ (match_operand:VQ 0 "register_operand" "+w") -+ (const_int 64) (const_int 64)) -+ (vec_concat:VQ -+ (match_operand: 1 "register_operand" "r") -+ (vec_duplicate: (const_int 0))))] -+ "TARGET_SIMD && reload_completed" -+ "ins\t%0.d[1], %1" -+ [(set_attr "simd_type" "simd_move") -+ (set_attr "simd_mode" "") -+ (set_attr "length" "4") -+ ]) ++typedef long long s64; + -+(define_insn "aarch64_simd_mov_from_low" -+ [(set (match_operand: 0 "register_operand" "=r") -+ (vec_select: -+ (match_operand:VQ 1 "register_operand" "w") -+ (match_operand:VQ 2 "vect_par_cnst_lo_half" "")))] -+ "TARGET_SIMD && reload_completed" -+ "umov\t%0, %1.d[0]" -+ [(set_attr "simd_type" "simd_move") -+ (set_attr "simd_mode" "") -+ (set_attr "length" "4") -+ ]) ++s64 ++cmp_di_test1 (s64 a, s64 b, s64 c) ++{ ++ if (a > b) ++ return a + c; ++ else ++ return a + b + c; ++} + -+(define_insn "aarch64_simd_mov_from_high" -+ [(set (match_operand: 0 "register_operand" "=r") -+ (vec_select: -+ (match_operand:VQ 1 "register_operand" "w") -+ (match_operand:VQ 2 "vect_par_cnst_hi_half" "")))] -+ "TARGET_SIMD && reload_completed" -+ "umov\t%0, %1.d[1]" -+ [(set_attr "simd_type" "simd_move") -+ (set_attr "simd_mode" "") -+ (set_attr "length" "4") -+ ]) ++s64 ++cmp_di_test2 (s64 a, s64 b, s64 c) ++{ ++ if ((a >> 3) > b) ++ return a + c; ++ else ++ return a + b + c; ++} + - (define_insn "orn3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")) -@@ -503,8 +606,8 @@ - ) ++int ++cmp_di_test3 (int a, s64 b, s64 c) ++{ ++ if (a > b) ++ return a + c; ++ else ++ return a + b + c; ++} ++ ++int ++cmp_di_test4 (int a, s64 b, s64 c) ++{ ++ if (((s64)a << 3) > b) ++ return a + c; ++ else ++ return a + b + c; ++} ++ ++/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */ ++/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ - (define_insn "neg2" -- [(set (match_operand:VDQM 0 "register_operand" "=w") -- (neg:VDQM (match_operand:VDQM 1 "register_operand" "w")))] -+ [(set (match_operand:VDQ 0 "register_operand" "=w") -+ (neg:VDQ (match_operand:VDQ 1 "register_operand" "w")))] - "TARGET_SIMD" - "neg\t%0., %1." - [(set_attr "simd_type" "simd_negabs") -@@ -520,6 +623,51 @@ - (set_attr "simd_mode" "")] - ) + #define FTYPE float ++#define ITYPE int + #define OP >= + #define INV_OP < -+(define_insn "abd_3" -+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") -+ (abs:VDQ_BHSI (minus:VDQ_BHSI -+ (match_operand:VDQ_BHSI 1 "register_operand" "w") -+ (match_operand:VDQ_BHSI 2 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "sabd\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_abd") -+ (set_attr "simd_mode" "")] -+) + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */ + /* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ + /* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/bfxil_2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/bfxil_2.c +@@ -0,0 +1,42 @@ ++/* { dg-do run { target aarch64*-*-* } } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++/* { dg-require-effective-target aarch64_big_endian } */ + -+(define_insn "aba_3" -+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") -+ (plus:VDQ_BHSI (abs:VDQ_BHSI (minus:VDQ_BHSI -+ (match_operand:VDQ_BHSI 1 "register_operand" "w") -+ (match_operand:VDQ_BHSI 2 "register_operand" "w"))) -+ (match_operand:VDQ_BHSI 3 "register_operand" "0")))] -+ "TARGET_SIMD" -+ "saba\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_abd") -+ (set_attr "simd_mode" "")] -+) ++extern void abort (void); + -+(define_insn "fabd_3" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (abs:VDQF (minus:VDQF -+ (match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "fabd\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_fabd") -+ (set_attr "simd_mode" "")] -+) ++typedef struct bitfield ++{ ++ unsigned short eight1: 8; ++ unsigned short four: 4; ++ unsigned short eight2: 8; ++ unsigned short seven: 7; ++ unsigned int sixteen: 16; ++ unsigned short eight3: 8; ++ unsigned short eight4: 8; ++} bitfield; + -+(define_insn "*fabd_scalar3" -+ [(set (match_operand:GPF 0 "register_operand" "=w") -+ (abs:GPF (minus:GPF -+ (match_operand:GPF 1 "register_operand" "w") -+ (match_operand:GPF 2 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "fabd\t%0, %1, %2" -+ [(set_attr "simd_type" "simd_fabd") -+ (set_attr "mode" "")] -+) -+ - (define_insn "and3" - [(set (match_operand:VDQ 0 "register_operand" "=w") - (and:VDQ (match_operand:VDQ 1 "register_operand" "w") -@@ -904,12 +1052,12 @@ - ) - - ;; Max/Min operations. --(define_insn "3" -+(define_insn "3" - [(set (match_operand:VQ_S 0 "register_operand" "=w") - (MAXMIN:VQ_S (match_operand:VQ_S 1 "register_operand" "w") - (match_operand:VQ_S 2 "register_operand" "w")))] - "TARGET_SIMD" -- "\t%0., %1., %2." -+ "\t%0., %1., %2." - [(set_attr "simd_type" "simd_minmax") - (set_attr "simd_mode" "")] - ) -@@ -1045,6 +1193,104 @@ - - ;; Widening arithmetic. - -+(define_insn "*aarch64_mlal_lo" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (plus: -+ (mult: -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 2 "register_operand" "w") -+ (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 4 "register_operand" "w") -+ (match_dup 3)))) -+ (match_operand: 1 "register_operand" "0")))] -+ "TARGET_SIMD" -+ "mlal\t%0., %2., %4." -+ [(set_attr "simd_type" "simd_mlal") -+ (set_attr "simd_mode" "")] -+) -+ -+(define_insn "*aarch64_mlal_hi" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (plus: -+ (mult: -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 2 "register_operand" "w") -+ (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 4 "register_operand" "w") -+ (match_dup 3)))) -+ (match_operand: 1 "register_operand" "0")))] -+ "TARGET_SIMD" -+ "mlal2\t%0., %2., %4." -+ [(set_attr "simd_type" "simd_mlal") -+ (set_attr "simd_mode" "")] -+) ++bitfield ++bfxil (bitfield a) ++{ ++ /* { dg-final { scan-assembler "bfxil\tx\[0-9\]+, x\[0-9\]+, 40, 8" } } */ ++ a.eight4 = a.eight2; ++ return a; ++} + -+(define_insn "*aarch64_mlsl_lo" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (minus: -+ (match_operand: 1 "register_operand" "0") -+ (mult: -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 2 "register_operand" "w") -+ (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 4 "register_operand" "w") -+ (match_dup 3))))))] -+ "TARGET_SIMD" -+ "mlsl\t%0., %2., %4." -+ [(set_attr "simd_type" "simd_mlal") -+ (set_attr "simd_mode" "")] -+) ++int ++main (void) ++{ ++ static bitfield a; ++ bitfield b; + -+(define_insn "*aarch64_mlsl_hi" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (minus: -+ (match_operand: 1 "register_operand" "0") -+ (mult: -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 2 "register_operand" "w") -+ (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) -+ (ANY_EXTEND: (vec_select: -+ (match_operand:VQW 4 "register_operand" "w") -+ (match_dup 3))))))] -+ "TARGET_SIMD" -+ "mlsl2\t%0., %2., %4." -+ [(set_attr "simd_type" "simd_mlal") -+ (set_attr "simd_mode" "")] -+) ++ a.eight4 = 9; ++ a.eight2 = 57; ++ b = bfxil (a); + -+(define_insn "*aarch64_mlal" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (plus: -+ (mult: -+ (ANY_EXTEND: -+ (match_operand:VDW 1 "register_operand" "w")) -+ (ANY_EXTEND: -+ (match_operand:VDW 2 "register_operand" "w"))) -+ (match_operand: 3 "register_operand" "0")))] -+ "TARGET_SIMD" -+ "mlal\t%0., %1., %2." -+ [(set_attr "simd_type" "simd_mlal") -+ (set_attr "simd_mode" "")] -+) ++ if (b.eight4 != a.eight2) ++ abort (); + -+(define_insn "*aarch64_mlsl" -+ [(set (match_operand: 0 "register_operand" "=w") -+ (minus: -+ (match_operand: 1 "register_operand" "0") -+ (mult: -+ (ANY_EXTEND: -+ (match_operand:VDW 2 "register_operand" "w")) -+ (ANY_EXTEND: -+ (match_operand:VDW 3 "register_operand" "w")))))] -+ "TARGET_SIMD" -+ "mlsl\t%0., %2., %3." -+ [(set_attr "simd_type" "simd_mlal") -+ (set_attr "simd_mode" "")] -+) ++ return 0; ++} + - (define_insn "aarch64_simd_vec_mult_lo_" - [(set (match_operand: 0 "register_operand" "=w") - (mult: (ANY_EXTEND: (vec_select: -@@ -1196,7 +1442,9 @@ - (set_attr "simd_mode" "")] - ) ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fp.x +@@ -7,13 +7,23 @@ + extern float fabsf (float); + extern double fabs (double); --(define_insn "aarch64_frint" -+;; Vector versions of the floating-point frint patterns. -+;; Expands to btrunc, ceil, floor, nearbyint, rint, round. -+(define_insn "2" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")] - FRINT))] -@@ -1206,16 +1454,9 @@ - (set_attr "simd_mode" "")] - ) ++#define DEF3a(fname, type, op) \ ++ void fname##_##type (pR##type a, \ ++ pR##type b, \ ++ pR##type c) \ ++ { \ ++ int i; \ ++ for (i = 0; i < 16; i++) \ ++ a[i] = op (b[i] - c[i]); \ ++ } ++ + #define DEF3(fname, type, op) \ + void fname##_##type (pR##type a, \ + pR##type b, \ + pR##type c) \ + { \ + int i; \ +- for (i=0; i<16; i++) \ ++ for (i = 0; i < 16; i++) \ + a[i] = b[i] op c[i]; \ + } --;; Vector versions of the floating-point frint patterns. --;; Expands to btrunc, ceil, floor, nearbyint, rint, round. --(define_expand "2" -- [(set (match_operand:VDQF 0 "register_operand") -- (unspec:VDQF [(match_operand:VDQF 1 "register_operand")] -- FRINT))] -- "TARGET_SIMD" -- {}) -- --(define_insn "aarch64_fcvt" -+;; Vector versions of the fcvt standard patterns. -+;; Expands to lbtrunc, lround, lceil, lfloor -+(define_insn "l2" - [(set (match_operand: 0 "register_operand" "=w") - (FIXUORS: (unspec: - [(match_operand:VDQF 1 "register_operand" "w")] -@@ -1226,16 +1467,141 @@ - (set_attr "simd_mode" "")] - ) +@@ -22,11 +32,15 @@ + pR##type b) \ + { \ + int i; \ +- for (i=0; i<16; i++) \ ++ for (i = 0; i < 16; i++) \ + a[i] = op(b[i]); \ + } --;; Vector versions of the fcvt standard patterns. --;; Expands to lbtrunc, lround, lceil, lfloor --(define_expand "l2" -+(define_expand "2" - [(set (match_operand: 0 "register_operand") - (FIXUORS: (unspec: - [(match_operand:VDQF 1 "register_operand")] -- FCVT)))] -+ UNSPEC_FRINTZ)))] - "TARGET_SIMD" - {}) -+(define_expand "2" -+ [(set (match_operand: 0 "register_operand") -+ (FIXUORS: (unspec: -+ [(match_operand:VDQF 1 "register_operand")] -+ UNSPEC_FRINTZ)))] -+ "TARGET_SIMD" -+ {}) -+ -+(define_expand "ftrunc2" -+ [(set (match_operand:VDQF 0 "register_operand") -+ (unspec:VDQF [(match_operand:VDQF 1 "register_operand")] -+ UNSPEC_FRINTZ))] -+ "TARGET_SIMD" -+ {}) -+ -+(define_insn "2" -+ [(set (match_operand:VDQF 0 "register_operand" "=w") -+ (FLOATUORS:VDQF -+ (match_operand: 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "cvtf\\t%0., %1." -+ [(set_attr "simd_type" "simd_icvtf") -+ (set_attr "simd_mode" "")] -+) -+ -+;; Conversions between vectors of floats and doubles. -+;; Contains a mix of patterns to match standard pattern names -+;; and those for intrinsics. -+ -+;; Float widening operations. -+ -+(define_insn "vec_unpacks_lo_v4sf" -+ [(set (match_operand:V2DF 0 "register_operand" "=w") -+ (float_extend:V2DF -+ (vec_select:V2SF -+ (match_operand:V4SF 1 "register_operand" "w") -+ (parallel [(const_int 0) (const_int 1)]) -+ )))] -+ "TARGET_SIMD" -+ "fcvtl\\t%0.2d, %1.2s" -+ [(set_attr "simd_type" "simd_fcvtl") -+ (set_attr "simd_mode" "V2DF")] -+) ++#define DEFN3a(fname, op) \ ++ DEF3a (fname, F32, op) \ ++ DEF3a (fname, F64, op) + -+(define_insn "aarch64_float_extend_lo_v2df" -+ [(set (match_operand:V2DF 0 "register_operand" "=w") -+ (float_extend:V2DF -+ (match_operand:V2SF 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fcvtl\\t%0.2d, %1.2s" -+ [(set_attr "simd_type" "simd_fcvtl") -+ (set_attr "simd_mode" "V2DF")] -+) + #define DEFN3(fname, op) \ + DEF3 (fname, F32, op) \ + DEF3 (fname, F64, op) +@@ -42,3 +56,5 @@ + DEFN2 (neg, -) + DEF2 (abs, F32, fabsf) + DEF2 (abs, F64, fabs) ++DEF3a (fabd, F32, fabsf) ++DEF3a (fabd, F64, fabs) +--- a/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c +@@ -1,43 +1,7 @@ + /* { dg-do compile } */ + /* { dg-options "-O2" } */ + +-int v = 0; ++#include "atomic-op-acq_rel.x" + +-int +-atomic_fetch_add_ACQ_REL (int a) +-{ +- return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL); +-} +- +-int +-atomic_fetch_sub_ACQ_REL (int a) +-{ +- return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL); +-} +- +-int +-atomic_fetch_and_ACQ_REL (int a) +-{ +- return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL); +-} +- +-int +-atomic_fetch_nand_ACQ_REL (int a) +-{ +- return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL); +-} +- +-int +-atomic_fetch_xor_ACQ_REL (int a) +-{ +- return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL); +-} +- +-int +-atomic_fetch_or_ACQ_REL (int a) +-{ +- return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); +-} +- + /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ + /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/subs1.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/subs1.c +@@ -0,0 +1,149 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ + -+(define_insn "vec_unpacks_hi_v4sf" -+ [(set (match_operand:V2DF 0 "register_operand" "=w") -+ (float_extend:V2DF -+ (vec_select:V2SF -+ (match_operand:V4SF 1 "register_operand" "w") -+ (parallel [(const_int 2) (const_int 3)]) -+ )))] -+ "TARGET_SIMD" -+ "fcvtl2\\t%0.2d, %1.4s" -+ [(set_attr "simd_type" "simd_fcvtl") -+ (set_attr "simd_mode" "V2DF")] -+) ++extern void abort (void); + -+;; Float narrowing operations. ++int ++subs_si_test1 (int a, int b, int c) ++{ ++ int d = a - c; + -+(define_insn "aarch64_float_truncate_lo_v2sf" -+ [(set (match_operand:V2SF 0 "register_operand" "=w") -+ (float_truncate:V2SF -+ (match_operand:V2DF 1 "register_operand" "w")))] -+ "TARGET_SIMD" -+ "fcvtn\\t%0.2s, %1.2d" -+ [(set_attr "simd_type" "simd_fcvtl") -+ (set_attr "simd_mode" "V2SF")] -+) ++ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+(define_insn "aarch64_float_truncate_hi_v4sf" -+ [(set (match_operand:V4SF 0 "register_operand" "=w") -+ (vec_concat:V4SF -+ (match_operand:V2SF 1 "register_operand" "0") -+ (float_truncate:V2SF -+ (match_operand:V2DF 2 "register_operand" "w"))))] -+ "TARGET_SIMD" -+ "fcvtn2\\t%0.4s, %2.2d" -+ [(set_attr "simd_type" "simd_fcvtl") -+ (set_attr "simd_mode" "V4SF")] -+) ++int ++subs_si_test2 (int a, int b, int c) ++{ ++ int d = a - 0xff; + -+(define_expand "vec_pack_trunc_v2df" -+ [(set (match_operand:V4SF 0 "register_operand") -+ (vec_concat:V4SF -+ (float_truncate:V2SF -+ (match_operand:V2DF 1 "register_operand")) -+ (float_truncate:V2SF -+ (match_operand:V2DF 2 "register_operand")) -+ ))] -+ "TARGET_SIMD" -+ { -+ rtx tmp = gen_reg_rtx (V2SFmode); -+ emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[1])); -+ emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0], -+ tmp, operands[2])); -+ DONE; -+ } -+) ++ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, #255" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+(define_expand "vec_pack_trunc_df" -+ [(set (match_operand:V2SF 0 "register_operand") -+ (vec_concat:V2SF -+ (float_truncate:SF -+ (match_operand:DF 1 "register_operand")) -+ (float_truncate:SF -+ (match_operand:DF 2 "register_operand")) -+ ))] -+ "TARGET_SIMD" -+ { -+ rtx tmp = gen_reg_rtx (V2SFmode); -+ emit_insn (gen_move_lo_quad_v2df (tmp, operands[1])); -+ emit_insn (gen_move_hi_quad_v2df (tmp, operands[2])); -+ emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp)); -+ DONE; -+ } -+) ++int ++subs_si_test3 (int a, int b, int c) ++{ ++ int d = a - (b << 3); + - (define_insn "aarch64_vmls" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") -@@ -1261,51 +1627,70 @@ - ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring - ;; NaNs. - --(define_insn "smax3" -+(define_insn "3" - [(set (match_operand:VDQF 0 "register_operand" "=w") -- (smax:VDQF (match_operand:VDQF 1 "register_operand" "w") -+ (FMAXMIN:VDQF (match_operand:VDQF 1 "register_operand" "w") - (match_operand:VDQF 2 "register_operand" "w")))] - "TARGET_SIMD" -- "fmaxnm\\t%0., %1., %2." -+ "fnm\\t%0., %1., %2." - [(set_attr "simd_type" "simd_fminmax") - (set_attr "simd_mode" "")] - ) - --(define_insn "smin3" -+(define_insn "3" - [(set (match_operand:VDQF 0 "register_operand" "=w") -- (smin:VDQF (match_operand:VDQF 1 "register_operand" "w") -- (match_operand:VDQF 2 "register_operand" "w")))] -+ (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") -+ (match_operand:VDQF 2 "register_operand" "w")] -+ FMAXMIN_UNS))] - "TARGET_SIMD" -- "fminnm\\t%0., %1., %2." -+ "\\t%0., %1., %2." - [(set_attr "simd_type" "simd_fminmax") - (set_attr "simd_mode" "")] - ) - --;; FP 'across lanes' max and min ops. -+;; 'across lanes' add. - --(define_insn "reduc_s_v4sf" -- [(set (match_operand:V4SF 0 "register_operand" "=w") -- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] -- FMAXMINV))] -+(define_insn "reduc_plus_" -+ [(set (match_operand:VDQV 0 "register_operand" "=w") -+ (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] -+ SUADDV))] - "TARGET_SIMD" -- "fnmv\\t%s0, %1.4s"; -- [(set_attr "simd_type" "simd_fminmaxv") -- (set_attr "simd_mode" "V4SF")] -+ "addv\\t%0, %1." -+ [(set_attr "simd_type" "simd_addv") -+ (set_attr "simd_mode" "")] - ) - --(define_insn "reduc_s_" -+(define_insn "reduc_plus_v2di" -+ [(set (match_operand:V2DI 0 "register_operand" "=w") -+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] -+ SUADDV))] -+ "TARGET_SIMD" -+ "addp\\t%d0, %1.2d" -+ [(set_attr "simd_type" "simd_addv") -+ (set_attr "simd_mode" "V2DI")] -+) ++ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} + -+(define_insn "reduc_plus_v2si" -+ [(set (match_operand:V2SI 0 "register_operand" "=w") -+ (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] -+ SUADDV))] -+ "TARGET_SIMD" -+ "addp\\t%0.2s, %1.2s, %1.2s" -+ [(set_attr "simd_type" "simd_addv") -+ (set_attr "simd_mode" "V2SI")] -+) ++typedef long long s64; + -+(define_insn "reduc_plus_" - [(set (match_operand:V2F 0 "register_operand" "=w") - (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] -- FMAXMINV))] -+ SUADDV))] - "TARGET_SIMD" -- "fnmp\\t%0., %1., %1."; -- [(set_attr "simd_type" "simd_fminmax") -+ "faddp\\t%0, %1." -+ [(set_attr "simd_type" "simd_fadd") - (set_attr "simd_mode" "")] - ) - --;; FP 'across lanes' add. -- --(define_insn "aarch64_addvv4sf" -+(define_insn "aarch64_addpv4sf" - [(set (match_operand:V4SF 0 "register_operand" "=w") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] - UNSPEC_FADDV))] -@@ -1315,169 +1700,106 @@ ++s64 ++subs_di_test1 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a - c; ++ ++ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++s64 ++subs_di_test2 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a - 0xff; ++ ++ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, #255" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++s64 ++subs_di_test3 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a - (b << 3); ++ ++ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d == 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int main () ++{ ++ int x; ++ s64 y; ++ ++ x = subs_si_test1 (29, 4, 5); ++ if (x != 33) ++ abort (); ++ ++ x = subs_si_test1 (5, 2, 20); ++ if (x != 7) ++ abort (); ++ ++ x = subs_si_test2 (29, 4, 5); ++ if (x != -217) ++ abort (); ++ ++ x = subs_si_test2 (1024, 2, 20); ++ if (x != 791) ++ abort (); ++ ++ x = subs_si_test3 (35, 4, 5); ++ if (x != 12) ++ abort (); ++ ++ x = subs_si_test3 (5, 2, 20); ++ if (x != 11) ++ abort (); ++ ++ y = subs_di_test1 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ ++ if (y != 0x45000002d) ++ abort (); ++ ++ y = subs_di_test1 (0x5000500050005ll, ++ 0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x7111711171117) ++ abort (); ++ ++ y = subs_di_test2 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != 0x955050433) ++ abort (); ++ ++ y = subs_di_test2 (0x130002900ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != 0x955052d0a) ++ abort (); ++ ++ y = subs_di_test3 (0x130000029ll, ++ 0x064000008ll, ++ 0x505050505ll); ++ if (y != 0x3790504f6) ++ abort (); ++ ++ y = subs_di_test3 (0x130002900ll, ++ 0x088000008ll, ++ 0x505050505ll); ++ if (y != 0x27d052dcd) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/adds2.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/adds2.c +@@ -0,0 +1,155 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2 --save-temps -fno-inline" } */ ++ ++extern void abort (void); ++ ++int ++adds_si_test1 (int a, int b, int c) ++{ ++ int d = a + b; ++ ++ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int ++adds_si_test2 (int a, int b, int c) ++{ ++ int d = a + 0xfff; ++ ++ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, 4095" } } */ ++ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, 4095" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int ++adds_si_test3 (int a, int b, int c) ++{ ++ int d = a + (b << 3); ++ ++ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++typedef long long s64; ++ ++s64 ++adds_di_test1 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a + b; ++ ++ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++s64 ++adds_di_test2 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a + 0x1000ll; ++ ++ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, 4096" } } */ ++ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, 4096" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++s64 ++adds_di_test3 (s64 a, s64 b, s64 c) ++{ ++ s64 d = a + (b << 3); ++ ++ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ ++ if (d <= 0) ++ return a + c; ++ else ++ return b + d + c; ++} ++ ++int main () ++{ ++ int x; ++ s64 y; ++ ++ x = adds_si_test1 (29, 4, 5); ++ if (x != 42) ++ abort (); ++ ++ x = adds_si_test1 (5, 2, 20); ++ if (x != 29) ++ abort (); ++ ++ x = adds_si_test2 (29, 4, 5); ++ if (x != 4133) ++ abort (); ++ ++ x = adds_si_test2 (1024, 2, 20); ++ if (x != 5141) ++ abort (); ++ ++ x = adds_si_test3 (35, 4, 5); ++ if (x != 76) ++ abort (); ++ ++ x = adds_si_test3 (5, 2, 20); ++ if (x != 43) ++ abort (); ++ ++ y = adds_di_test1 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ ++ if (y != 0xc75050536) ++ abort (); ++ ++ y = adds_di_test1 (0x5000500050005ll, ++ 0x2111211121112ll, ++ 0x0000000002020ll); ++ if (y != 0x9222922294249) ++ abort (); ++ ++ y = adds_di_test2 (0x130000029ll, ++ 0x320000004ll, ++ 0x505050505ll); ++ if (y != 0x955051532) ++ abort (); ++ ++ y = adds_di_test2 (0x540004100ll, ++ 0x320000004ll, ++ 0x805050205ll); ++ if (y != 0x1065055309) ++ abort (); ++ ++ y = adds_di_test3 (0x130000029ll, ++ 0x064000008ll, ++ 0x505050505ll); ++ if (y != 0x9b9050576) ++ abort (); ++ ++ y = adds_di_test3 (0x130002900ll, ++ 0x088000008ll, ++ 0x505050505ll); ++ if (y != 0xafd052e4d) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { cleanup-saved-temps } } */ +--- a/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c ++++ b/src/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c +@@ -2,12 +2,13 @@ + /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */ + + #define FTYPE double ++#define ITYPE long + #define OP > + #define INV_OP <= + + #include "vect-fcm.x" + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */ + /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ + /* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ + /* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */ +--- a/src/gcc/testsuite/lib/target-supports.exp ++++ b/src/gcc/testsuite/lib/target-supports.exp +@@ -487,13 +487,6 @@ + return 0 + } + +- # We don't yet support profiling for AArch64. +- if { [istarget aarch64*-*-*] +- && ([lindex $test_what 1] == "-p" +- || [lindex $test_what 1] == "-pg") } { +- return 0 +- } +- + # cygwin does not support -p. + if { [istarget *-*-cygwin*] && $test_what == "-p" } { + return 0 +@@ -2012,6 +2005,7 @@ + || ([istarget powerpc*-*-*] + && ![istarget powerpc-*-linux*paired*]) + || [istarget x86_64-*-*] ++ || [istarget aarch64*-*-*] + || ([istarget arm*-*-*] + && [check_effective_target_arm_neon_ok])} { + set et_vect_uintfloat_cvt_saved 1 +@@ -2078,6 +2072,15 @@ + }] + } + ++# Return 1 if this is a AArch64 target supporting little endian ++proc check_effective_target_aarch64_little_endian { } { ++ return [check_no_compiler_messages aarch64_little_endian assembly { ++ #if !defined(__aarch64__) || defined(__AARCH64EB__) ++ #error FOO ++ #endif ++ }] ++} ++ + # Return 1 is this is an arm target using 32-bit instructions + proc check_effective_target_arm32 { } { + return [check_no_compiler_messages arm32 assembly { +@@ -2147,22 +2150,6 @@ + } + } + +-# Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8 +-# -mfloat-abi=softfp +-proc check_effective_target_arm_v8_neon_ok {} { +- if { [check_effective_target_arm32] } { +- return [check_no_compiler_messages arm_v8_neon_ok object { +- int foo (void) +- { +- __asm__ volatile ("vrintn.f32 q0, q0"); +- return 0; +- } +- } "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"] +- } else { +- return 0 +- } +-} +- + # Return 1 if this is an ARM target supporting -mfpu=vfp + # -mfloat-abi=hard. Some multilibs may be incompatible with these + # options. +@@ -2226,7 +2213,8 @@ + if { ! [check_effective_target_arm_v8_neon_ok] } { + return "$flags" + } +- return "$flags -march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=softfp" ++ global et_arm_v8_neon_flags ++ return "$flags $et_arm_v8_neon_flags -march=armv8-a" + } + + # Add the options needed for NEON. We need either -mfloat-abi=softfp +@@ -2270,6 +2258,79 @@ + check_effective_target_arm_neon_ok_nocache] + } + ++# Return 1 if this is an ARM target supporting -mfpu=neon-fp16 ++# -mfloat-abi=softfp or equivalent options. Some multilibs may be ++# incompatible with these options. Also set et_arm_neon_flags to the ++# best options to add. ++ ++proc check_effective_target_arm_neon_fp16_ok_nocache { } { ++ global et_arm_neon_fp16_flags ++ set et_arm_neon_fp16_flags "" ++ if { [check_effective_target_arm32] } { ++ foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16" ++ "-mfpu=neon-fp16 -mfloat-abi=softfp"} { ++ if { [check_no_compiler_messages_nocache arm_neon_fp_16_ok object { ++ #include "arm_neon.h" ++ float16x4_t ++ foo (float32x4_t arg) ++ { ++ return vcvt_f16_f32 (arg); ++ } ++ } "$flags"] } { ++ set et_arm_neon_fp16_flags $flags ++ return 1 ++ } ++ } ++ } ++ ++ return 0 ++} ++ ++proc check_effective_target_arm_neon_fp16_ok { } { ++ return [check_cached_effective_target arm_neon_fp16_ok \ ++ check_effective_target_arm_neon_fp16_ok_nocache] ++} ++ ++proc add_options_for_arm_neon_fp16 { flags } { ++ if { ! [check_effective_target_arm_neon_fp16_ok] } { ++ return "$flags" ++ } ++ global et_arm_neon_fp16_flags ++ return "$flags $et_arm_neon_fp16_flags" ++} ++ ++# Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8 ++# -mfloat-abi=softfp or equivalent options. Some multilibs may be ++# incompatible with these options. Also set et_arm_v8_neon_flags to the ++# best options to add. ++ ++proc check_effective_target_arm_v8_neon_ok_nocache { } { ++ global et_arm_v8_neon_flags ++ set et_arm_v8_neon_flags "" ++ if { [check_effective_target_arm32] } { ++ foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} { ++ if { [check_no_compiler_messages_nocache arm_v8_neon_ok object { ++ #include "arm_neon.h" ++ void ++ foo () ++ { ++ __asm__ volatile ("vrintn.f32 q0, q0"); ++ } ++ } "$flags"] } { ++ set et_arm_v8_neon_flags $flags ++ return 1 ++ } ++ } ++ } ++ ++ return 0 ++} ++ ++proc check_effective_target_arm_v8_neon_ok { } { ++ return [check_cached_effective_target arm_v8_neon_ok \ ++ check_effective_target_arm_v8_neon_ok_nocache] ++} ++ + # Return 1 if this is an ARM target supporting -mfpu=neon-vfpv4 + # -mfloat-abi=softfp or equivalent options. Some multilibs may be + # incompatible with these options. Also set et_arm_neonv2_flags to the +@@ -2509,6 +2570,24 @@ + } [add_options_for_arm_neonv2 ""]] + } + ++# Return 1 if the target supports executing ARMv8 NEON instructions, 0 ++# otherwise. ++ ++proc check_effective_target_arm_v8_neon_hw { } { ++ return [check_runtime arm_v8_neon_hw_available { ++ #include "arm_neon.h" ++ int ++ main (void) ++ { ++ float32x2_t a; ++ asm ("vrinta.f32 %P0, %P1" ++ : "=w" (a) ++ : "0" (a)); ++ return 0; ++ } ++ } [add_options_for_arm_v8_neon ""]] ++} ++ + # Return 1 if this is a ARM target with NEON enabled. + + proc check_effective_target_arm_neon { } { +@@ -4591,6 +4670,33 @@ + return 0 + } + ++# Return 1 if programs are intended to be run on hardware rather than ++# on a simulator ++ ++proc check_effective_target_hw { } { ++ ++ # All "src/sim" simulators set this one. ++ if [board_info target exists is_simulator] { ++ if [board_info target is_simulator] { ++ return 0 ++ } else { ++ return 1 ++ } ++ } ++ ++ # The "sid" simulators don't set that one, but at least they set ++ # this one. ++ if [board_info target exists slow_simulator] { ++ if [board_info target slow_simulator] { ++ return 0 ++ } else { ++ return 1 ++ } ++ } ++ ++ return 1 ++} ++ + # Return 1 if the target is a VxWorks kernel. + + proc check_effective_target_vxworks_kernel { } { +--- a/src/gcc/testsuite/ChangeLog.linaro ++++ b/src/gcc/testsuite/ChangeLog.linaro +@@ -0,0 +1,681 @@ ++2013-10-09 Christophe Lyon ++ ++ Backport from trunk r198526,200595,200597. ++ 2013-05-02 Ian Bolton ++ ++ * gcc.target/aarch64/bics_1.c: New test. ++ * gcc.target/aarch64/bics_2.c: Likewise. ++ ++ 2013-07-02 Ian Bolton ++ ++ * gcc.target/aarch64/bfxil_1.c: New test. ++ * gcc.target/aarch64/bfxil_2.c: Likewise. ++ ++ 2013-07-02 Ian Bolton ++ ++ * gcc.target/config/aarch64/insv_1.c: Update to show it doesn't work ++ on big endian. ++ * gcc.target/config/aarch64/insv_2.c: New test for big endian. ++ * lib/target-supports.exp: Define aarch64_little_endian. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r202400. ++ 2013-09-09 Kyrylo Tkachov ++ ++ * gcc.target/aarch64/cmn-neg.c: New test. ++ ++2013-10-03 Christophe Lyon ++ ++ Backport from trunk r202164. ++ 2013-09-02 Bin Cheng ++ ++ * gcc.target/arm/ivopts-orig_biv-inc.c: New testcase. ++ ++2013-10-01 Kugan Vivekanandarajah ++ ++ Backport from trunk r203059,203116. ++ 2013-10-01 Kugan Vivekanandarajah ++ ++ PR Target/58578 ++ * gcc.target/arm/pr58578.c: New test. ++ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-09-06 Venkataramanan Kumar ++ ++ Backport from trunk r201411. ++ 2013-08-01 Kyrylo Tkachov ++ ++ * gcc.target/arm/pr46972-2.c: New test. ++ ++2013-09-05 Yvan Roux ++ ++ Backport from trunk r201267. ++ 2013-07-26 Kyrylo Tkachov ++ ++ * gcc.target/arm/minmax_minus.c: Scan for absence of mov. ++ ++2013-09-05 Christophe Lyon ++ ++ Backport from trunk r199527,199814,201435. ++ 2013-05-31 Kyrylo Tkachov ++ ++ PR target/56315 ++ * gcc.target/arm/iordi3-opt.c: New test. ++ ++ 2013-06-07 Kyrylo Tkachov ++ ++ PR target/56315 ++ * gcc.target/arm/xordi3-opt.c: New test. ++ ++ 2013-08-02 Kyrylo Tkachov ++ ++ * gcc.target/arm/neon-for-64bits-2.c: Delete. ++ ++2013-09-05 Christophe Lyon ++ ++ Backport from trunk r201730,201731. ++ ++ 2013-08-14 Janis Johnson ++ ++ * gcc.target/arm/atomic-comp-swap-release-acquire.c: Move dg-do ++ to be the first test directive. ++ * gcc.target/arm/atomic-op-acq_rel.c: Likewise. ++ * gcc.target/arm/atomic-op-acquire.c: Likewise. ++ * gcc.target/arm/atomic-op-char.c: Likewise. ++ * gcc.target/arm/atomic-op-consume.c: Likewise. ++ * gcc.target/arm/atomic-op-int.c: Likewise. ++ * gcc.target/arm/atomic-op-relaxed.c: Likewise. ++ * gcc.target/arm/atomic-op-release.c: Likewise. ++ * gcc.target/arm/atomic-op-seq_cst.c: Likewise. ++ * gcc.target/arm/atomic-op-short.c: Likewise. ++ ++ 2013-08-14 Janis Johnson ++ ++ * gcc.target/arm/pr19599.c: Skip for -mthumb. ++ ++2013-09-03 Venkataramanan Kumar ++ ++ Backport from trunk r201624. ++ 2013-08-09 James Greenhalgh ++ ++ * gcc.target/aarch64/scalar_intrinsics.c: Update expected ++ output of vdup intrinsics ++ ++2013-08-26 Kugan Vivekanandarajah ++ ++ Backport from trunk r201636. ++ 2013-08-09 Yufeng Zhang ++ ++ * gcc.dg/lower-subreg-1.c: Skip aarch64*-*-*. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-08-07 Christophe Lyon ++ ++ Backport from trunk r199720 ++ 2013-06-06 Marcus Shawcroft ++ ++ * gcc.dg/vect/no-section-anchors-vect-68.c: ++ Add dg-skip-if aarch64_tiny. ++ ++2013-08-07 Christophe Lyon ++ ++ Backport from trunk r201237. ++ 2013-07-25 Terry Guo ++ ++ * gcc.target/arm/thumb1-Os-mult.c: New test case. ++ ++2013-08-06 Christophe Lyon ++ ++ Backport from trunk r200596,201067,201083. ++ 2013-07-02 Ian Bolton ++ ++ * gcc.target/aarch64/abs_1.c: New test. ++ ++ 2013-07-19 Ian Bolton ++ ++ * gcc.target/aarch64/scalar_intrinsics.c (test_vabs_s64): Added ++ new testcase. ++ ++ 2013-07-20 James Greenhalgh ++ ++ * gcc.target/aarch64/vabs_intrinsic_1.c: New file. ++ ++2013-08-06 Christophe Lyon ++ ++ Backport from trunk r198864. ++ 2013-05-07 Ian Bolton ++ ++ * gcc.target/aarch64/ands_1.c: New test. ++ * gcc.target/aarch64/ands_2.c: Likewise ++ ++2013-08-06 Christophe Lyon ++ ++ Backport from trunk r199439,199533,201326. ++ ++ 2013-05-30 Zhenqiang Chen ++ ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ ++ 2013-05-31 Rainer Orth ++ ++ * gcc.dg/shrink-wrap-alloca.c: Use __builtin_alloca. ++ ++ 2013-07-30 Zhenqiang Chen ++ ++ * gcc.target/arm/pr57637.c: New testcase. ++ ++2013-08-06 Christophe Lyon ++ ++ Backport from trunk r198928,198973,199203,201240,201241. ++ 2013-05-15 Ramana Radhakrishnan ++ ++ PR target/19599 ++ * gcc.target/arm/pr40887.c: Adjust testcase. ++ * gcc.target/arm/pr19599.c: New test. ++ ++2013-08-05 Yvan Roux ++ ++ Backport from trunk r200922. ++ 2013-07-12 Tejas Belagod ++ ++ * gcc.target/aarch64/vect-movi.c: New. ++ ++2013-08-05 Yvan Roux ++ ++ Backport from trunk r200720. ++ 2013-07-05 Marcus Shawcroft ++ ++ * gcc.dg/pr57518.c: Adjust scan-rtl-dump-not pattern. ++ ++2013-07-21 Yvan Roux ++ ++ Backport from trunk r200204. ++ 2013-06-19 Yufeng Zhang ++ ++ * gcc.dg/torture/stackalign/builtin-apply-2.c: set ++ STACK_ARGUMENTS_SIZE with 0 if __aarch64__ is defined. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ ++2013-07-03 Christophe Lyon ++ ++ Revert backport from trunk r198928. ++ 2013-05-15 Ramana Radhakrishnan ++ ++ PR target/19599 ++ * gcc.target/arm/pr40887.c: Adjust testcase. ++ * gcc.target/arm/pr19599.c: New test. ++ ++2013-07-03 Christophe Lyon ++ ++ Revert backport from trunk 199439, 199533 ++ 2013-05-31 Rainer Orth ++ ++ * gcc.dg/shrink-wrap-alloca.c: Use __builtin_alloca. ++ ++ 2013-05-30 Zhenqiang Chen ++ ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ ++2013-07-02 Rob Savoye ++ ++ Backport from trunk 200096 ++ ++ 2013-06-14 Vidya Praveen ++ ++ * gcc.target/aarch64/vect_smlal_1.c: New file. ++ ++2013-07-02 Rob Savoye ++ ++ Backport from trunk 200019 ++ 2013-06-12 Ramana Radhakrishnan ++ ++ * gcc.target/arm/unaligned-memcpy-4.c (src, dst): Initialize ++ to ensure alignment. ++ * gcc.target/arm/unaligned-memcpy-3.c (src): Likewise. ++ ++2013-06-20 Rob Savoye ++ ++ Backport from trunk 200152 ++ 2013-06-17 Sofiane Naci ++ ++ * gcc.target/aarch64/scalar_intrinsics.c: Update. ++ ++2013-06-20 Rob Savoye ++ ++ Backport from trunk 200148 ++ 2013-06-17 Kyrylo Tkachov ++ ++ * gcc.target/arm/unaligned-memcpy-2.c (dest): Initialize to ++ ensure alignment. ++ ++2013-06-20 Rob Savoye ++ ++ Backport from trunk 199533 ++ 2013-05-31 Rainer Orth ++ ++ * gcc.dg/shrink-wrap-alloca.c: Use __builtin_alloca. ++ ++2013-06-20 Christophe Lyon ++ ++ Backport from trunk r198683. ++ 2013-05-07 Christophe Lyon ++ ++ * lib/target-supports.exp (check_effective_target_hw): New ++ function. ++ * c-c++-common/asan/clone-test-1.c: Call ++ check_effective_target_hw. ++ * c-c++-common/asan/rlimit-mmap-test-1.c: Likewise. ++ * c-c++-common/asan/heap-overflow-1.c: Update regexps to accept ++ possible decorations. ++ * c-c++-common/asan/null-deref-1.c: Likewise. ++ * c-c++-common/asan/stack-overflow-1.c: Likewise. ++ * c-c++-common/asan/strncpy-overflow-1.c: Likewise. ++ * c-c++-common/asan/use-after-free-1.c: Likewise. ++ * g++.dg/asan/deep-thread-stack-1.C: Likewise. ++ * g++.dg/asan/large-func-test-1.C: Likewise. ++ ++2013-06-11 Rob Savoye ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-06-06 Zhenqiang Chen ++ ++ Backport from mainline r199439. ++ 2013-05-30 Zhenqiang Chen ++ ++ * gcc.dg/shrink-wrap-alloca.c: New added. ++ * gcc.dg/shrink-wrap-pretend.c: New added. ++ * gcc.dg/shrink-wrap-sibcall.c: New added. ++ ++2013-06-05 Christophe Lyon ++ ++ Backport from trunk r199658. ++ 2013-06-04 Ian Bolton ++ ++ * gcc.target/aarch64/movi_1.c: New test. ++ ++2013-06-04 Christophe Lyon ++ ++ Backport from trunk r199261. ++ 2013-05-23 Christian Bruel ++ ++ PR debug/57351 ++ * gcc.dg/debug/pr57351.c: New test ++ ++2013-06-03 Christophe Lyon ++ Backport from trunk r198890,199254,199294,199454. ++ ++ 2013-05-30 Ian Bolton ++ ++ * gcc.target/aarch64/insv_1.c: New test. ++ ++ 2013-05-24 Ian Bolton ++ ++ * gcc.target/aarch64/scalar_intrinsics.c ++ (force_simd): Use a valid instruction. ++ (test_vdupd_lane_s64): Pass a valid lane argument. ++ (test_vdupd_lane_u64): Likewise. ++ ++ 2013-05-23 Vidya Praveen ++ ++ * gcc.target/aarch64/vect-clz.c: New file. ++ ++ 2013-05-14 James Greenhalgh ++ ++ * gcc.target/aarch64/vect-fcm.x: Add cases testing ++ FLOAT cmp FLOAT ? INT : INT. ++ * gcc.target/aarch64/vect-fcm-eq-d.c: Define IMODE. ++ * gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. ++ * gcc.target/aarch64/vect-fcm-gt-f.c: Likewise. ++ ++2013-05-29 Christophe Lyon ++ ++ Backport from trunk r198928. ++ 2013-05-15 Ramana Radhakrishnan ++ ++ PR target/19599 ++ * gcc.target/arm/pr40887.c: Adjust testcase. ++ * gcc.target/arm/pr19599.c: New test. ++ ++2013-05-28 Christophe Lyon ++ ++ Backport from trunk r198680. ++ 2013-05-07 Sofiane Naci ++ ++ * gcc.target/aarch64/scalar_intrinsics.c: Update. ++ ++2013-05-28 Christophe Lyon ++ ++ Backport from trunk r198499-198500. ++ 2013-05-01 James Greenhalgh ++ * gcc.target/aarch64/vect-vaddv.c: New. ++ ++ 2013-05-01 James Greenhalgh ++ ++ * gcc.target/aarch64/vect-vmaxv.c: New. ++ * gcc.target/aarch64/vect-vfmaxv.c: Likewise. ++ ++2013-05-23 Christophe Lyon ++ ++ Backport from trunk r198970. ++ 2013-05-16 Greta Yorsh ++ ++ * gcc.target/arm/unaligned-memcpy-2.c: Adjust expected output. ++ * gcc.target/arm/unaligned-memcpy-3.c: Likewise. ++ * gcc.target/arm/unaligned-memcpy-4.c: Likewise. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.05 released. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ Backport from trunk r198574-198575. ++ 2013-05-03 Vidya Praveen ++ ++ * gcc.target/aarch64/fabd.c: New file. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ Backport from trunk r198490-198496. ++ 2013-05-01 James Greenhalgh ++ ++ * gcc.target/aarch64/scalar-vca.c: New. ++ * gcc.target/aarch64/vect-vca.c: Likewise. ++ ++ 2013-05-01 James Greenhalgh ++ ++ * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New. ++ (test_vceqd_s64): Force arguments to SIMD registers. ++ (test_vceqzd_s64): Likewise. ++ (test_vcged_s64): Likewise. ++ (test_vcled_s64): Likewise. ++ (test_vcgezd_s64): Likewise. ++ (test_vcged_u64): Likewise. ++ (test_vcgtd_s64): Likewise. ++ (test_vcltd_s64): Likewise. ++ (test_vcgtzd_s64): Likewise. ++ (test_vcgtd_u64): Likewise. ++ (test_vclezd_s64): Likewise. ++ (test_vcltzd_s64): Likewise. ++ (test_vtst_s64): Likewise. ++ (test_vtst_u64): Likewise. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ Backport from trunk r198191. ++ 2013-04-23 Sofiane Naci ++ ++ * gcc.target/aarch64/scalar-mov.c: New testcase. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ Backport from trunk r197838. ++ 2013-04-11 Naveen H.S ++ ++ * gcc.target/aarch64/negs.c: New. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r198019. ++ 2013-04-16 Naveen H.S ++ ++ * gcc.target/aarch64/adds1.c: New. ++ * gcc.target/aarch64/adds2.c: New. ++ * gcc.target/aarch64/subs1.c: New. ++ * gcc.target/aarch64/subs2.c: New. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r198394,198396-198400,198402-198404,198406. ++ 2013-04-29 James Greenhalgh ++ ++ * lib/target-supports.exp (vect_uintfloat_cvt): Enable for AArch64. ++ ++ 2013-04-29 James Greenhalgh ++ ++ * gcc.target/aarch64/vect-vcvt.c: New. ++ ++ 2013-04-29 James Greenhalgh ++ ++ * gcc.target/aarch64/vect-vrnd.c: New. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r198302-198306,198316. ++ 2013-04-25 James Greenhalgh ++ Tejas Belagod ++ ++ * gcc.target/aarch64/vaddv-intrinsic.c: New. ++ * gcc.target/aarch64/vaddv-intrinsic-compile.c: Likewise. ++ * gcc.target/aarch64/vaddv-intrinsic.x: Likewise. ++ ++ 2013-04-25 Naveen H.S ++ ++ * gcc.target/aarch64/cmp.c: New. ++ ++ 2013-04-25 Naveen H.S ++ ++ * gcc.target/aarch64/ngc.c: New. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r198298. ++ 2013-04-25 Kyrylo Tkachov ++ ++ * lib/target-supports.exp ++ (check_effective_target_arm_neon_fp16_ok_nocache): New procedure. ++ (check_effective_target_arm_neon_fp16_ok): Likewise. ++ (add_options_for_arm_neon_fp16): Likewise. ++ * gcc.target/arm/neon/vcvtf16_f32.c: New test. Generated. ++ * gcc.target/arm/neon/vcvtf32_f16.c: Likewise. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r198136-198137,198142,198176 ++ 2013-04-22 James Greenhalgh ++ ++ * gcc.target/aarch64/vrecps.c: New. ++ * gcc.target/aarch64/vrecpx.c: Likewise. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r198020. ++ 2013-04-16 Naveen H.S ++ ++ * gcc.target/aarch64/adds3.c: New. ++ * gcc.target/aarch64/subs3.c: New. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r197965. ++ 2013-04-15 Kyrylo Tkachov ++ ++ * gcc.target/arm/anddi3-opt.c: New test. ++ * gcc.target/arm/anddi3-opt2.c: Likewise. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r197642. ++ 2013-04-09 Kyrylo Tkachov ++ ++ * gcc.target/arm/minmax_minus.c: New test. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r197530,197921. ++ 2013-04-05 Greta Yorsh ++ ++ * gcc.target/arm/peep-ldrd-1.c: New test. ++ * gcc.target/arm/peep-strd-1.c: Likewise. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r197523. ++ 2013-04-05 Kyrylo Tkachov ++ ++ * lib/target-supports.exp (add_options_for_arm_v8_neon): ++ Add -march=armv8-a when we use v8 NEON. ++ (check_effective_target_vect_call_btruncf): Remove arm-*-*-*. ++ (check_effective_target_vect_call_ceilf): Likewise. ++ (check_effective_target_vect_call_floorf): Likewise. ++ (check_effective_target_vect_call_roundf): Likewise. ++ (check_vect_support_and_set_flags): Remove check for arm_v8_neon. ++ * gcc.target/arm/vect-rounding-btruncf.c: New testcase. ++ * gcc.target/arm/vect-rounding-ceilf.c: Likewise. ++ * gcc.target/arm/vect-rounding-floorf.c: Likewise. ++ * gcc.target/arm/vect-rounding-roundf.c: Likewise. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r197518-197522,197516-197528. ++ 2013-04-05 Greta Yorsh ++ ++ * gcc.target/arm/negdi-1.c: New test. ++ * gcc.target/arm/negdi-2.c: Likewise. ++ * gcc.target/arm/negdi-3.c: Likewise. ++ * gcc.target/arm/negdi-4.c: Likewise. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r197489-197491. ++ 2013-04-04 Kyrylo Tkachov ++ ++ * lib/target-supports.exp (check_effective_target_arm_v8_neon_hw): ++ New procedure. ++ (check_effective_target_arm_v8_neon_ok_nocache): ++ Likewise. ++ (check_effective_target_arm_v8_neon_ok): Change to use ++ check_effective_target_arm_v8_neon_ok_nocache. ++ (add_options_for_arm_v8_neon): Use et_arm_v8_neon_flags to set ARMv8 ++ NEON flags. ++ (check_effective_target_vect_call_btruncf): ++ Enable for arm and ARMv8 NEON. ++ (check_effective_target_vect_call_ceilf): Likewise. ++ (check_effective_target_vect_call_floorf): Likewise. ++ (check_effective_target_vect_call_roundf): Likewise. ++ (check_vect_support_and_set_flags): Handle ARMv8 NEON effective ++ target. ++ ++2013-05-02 Matthew Gretton-Dann ++ ++ Backport from trunk r196795-196797,196957. ++ 2013-03-19 Ian Bolton ++ ++ * gcc.target/aarch64/sbc.c: New test. ++ ++ 2013-03-19 Ian Bolton ++ ++ * gcc.target/aarch64/ror.c: New test. ++ ++ 2013-03-19 Ian Bolton ++ ++ * gcc.target/aarch64/extr.c: New test. ++ ++2013-04-09 Matthew Gretton-Dann ++ ++ * GCC Linaro 4.8-2013.04 released. ++ ++2013-04-08 Matthew Gretton-Dann ++ ++ Backport from trunk r197052. ++ 2013-03-25 Kyrylo Tkachov ++ ++ * gcc.target/arm/vseleqdf.c: New test. ++ * gcc.target/arm/vseleqsf.c: Likewise. ++ * gcc.target/arm/vselgedf.c: Likewise. ++ * gcc.target/arm/vselgesf.c: Likewise. ++ * gcc.target/arm/vselgtdf.c: Likewise. ++ * gcc.target/arm/vselgtsf.c: Likewise. ++ * gcc.target/arm/vselledf.c: Likewise. ++ * gcc.target/arm/vsellesf.c: Likewise. ++ * gcc.target/arm/vselltdf.c: Likewise. ++ * gcc.target/arm/vselltsf.c: Likewise. ++ * gcc.target/arm/vselnedf.c: Likewise. ++ * gcc.target/arm/vselnesf.c: Likewise. ++ * gcc.target/arm/vselvcdf.c: Likewise. ++ * gcc.target/arm/vselvcsf.c: Likewise. ++ * gcc.target/arm/vselvsdf.c: Likewise. ++ * gcc.target/arm/vselvssf.c: Likewise. ++ ++2013-04-08 Matthew Gretton-Dann ++ ++ Backport from trunk r197051. ++ 2013-03-25 Kyrylo Tkachov ++ ++ * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move test ++ body from here... ++ * gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to here. ++ * gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-acq_rel.x: ... to here. ++ * gcc.target/aarch64/atomic-op-acquire.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-acquire.x: ... to here. ++ * gcc.target/aarch64/atomic-op-char.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-char.x: ... to here. ++ * gcc.target/aarch64/atomic-op-consume.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-consume.x: ... to here. ++ * gcc.target/aarch64/atomic-op-int.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-int.x: ... to here. ++ * gcc.target/aarch64/atomic-op-relaxed.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-relaxed.x: ... to here. ++ * gcc.target/aarch64/atomic-op-release.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-release.x: ... to here. ++ * gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-seq_cst.x: ... to here. ++ * gcc.target/aarch64/atomic-op-short.c: Move test body from here... ++ * gcc.target/aarch64/atomic-op-short.x: ... to here. ++ * gcc.target/arm/atomic-comp-swap-release-acquire.c: New test. ++ * gcc.target/arm/atomic-op-acq_rel.c: Likewise. ++ * gcc.target/arm/atomic-op-acquire.c: Likewise. ++ * gcc.target/arm/atomic-op-char.c: Likewise. ++ * gcc.target/arm/atomic-op-consume.c: Likewise. ++ * gcc.target/arm/atomic-op-int.c: Likewise. ++ * gcc.target/arm/atomic-op-relaxed.c: Likewise. ++ * gcc.target/arm/atomic-op-release.c: Likewise. ++ * gcc.target/arm/atomic-op-seq_cst.c: Likewise. ++ * gcc.target/arm/atomic-op-short.c: Likewise. ++ ++2013-04-08 Matthew Gretton-Dann ++ ++ Backport from trunk r196876. ++ 2013-03-21 Christophe Lyon ++ ++ * gcc.target/arm/neon-for-64bits-1.c: New tests. ++ * gcc.target/arm/neon-for-64bits-2.c: Likewise. ++ ++2013-04-08 Matthew Gretton-Dann ++ ++ Backport from trunk r196858. ++ 2013-03-21 Naveen H.S ++ ++ * gcc.target/aarch64/vect.c: Test and result vector added ++ for sabd and saba instructions. ++ * gcc.target/aarch64/vect-compile.c: Check for sabd and saba ++ instructions in assembly. ++ * gcc.target/aarch64/vect.x: Add sabd and saba test functions. ++ * gcc.target/aarch64/vect-fp.c: Test and result vector added ++ for fabd instruction. ++ * gcc.target/aarch64/vect-fp-compile.c: Check for fabd ++ instruction in assembly. ++ * gcc.target/aarch64/vect-fp.x: Add fabd test function. +--- a/src/gcc/testsuite/gcc.dg/pr57518.c ++++ b/src/gcc/testsuite/gcc.dg/pr57518.c +@@ -2,7 +2,7 @@ + + /* { dg-do compile } */ + /* { dg-options "-O2 -fdump-rtl-ira" } */ +-/* { dg-final { scan-rtl-dump-not "REG_EQUIV.*mem.*\"ip\"" "ira" } } */ ++/* { dg-final { scan-rtl-dump-not "REG_EQUIV\[^\n\]*mem\[^\n\]*\"ip\"" "ira" } } */ + + char ip[10]; + int total; +--- a/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c ++++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-alloca.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -g" } */ ++ ++int *p; ++ ++void ++test (int a) ++{ ++ if (a > 0) ++ p = __builtin_alloca (4); ++} +--- a/src/gcc/testsuite/gcc.dg/shrink-wrap-pretend.c ++++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-pretend.c +@@ -0,0 +1,36 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -g" } */ ++ ++#include ++#include ++#include ++ ++#define DEBUG_BUFFER_SIZE 80 ++int unifi_debug = 5; ++ ++void ++unifi_trace (void* ospriv, int level, const char *fmt, ...) ++{ ++ static char s[DEBUG_BUFFER_SIZE]; ++ va_list args; ++ unsigned int len; ++ ++ if (!ospriv) ++ return; ++ ++ if (unifi_debug >= level) ++ { ++ va_start (args, fmt); ++ len = vsnprintf (&(s)[0], (DEBUG_BUFFER_SIZE), fmt, args); ++ va_end (args); ++ ++ if (len >= DEBUG_BUFFER_SIZE) ++ { ++ (s)[DEBUG_BUFFER_SIZE - 2] = '\n'; ++ (s)[DEBUG_BUFFER_SIZE - 1] = 0; ++ } ++ ++ printf ("%s", s); ++ } ++} ++ +--- a/src/gcc/testsuite/gcc.dg/debug/pr57351.c ++++ b/src/gcc/testsuite/gcc.dg/debug/pr57351.c +@@ -0,0 +1,54 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon } */ ++/* { dg-options "-std=c99 -Os -g -march=armv7-a" } */ ++/* { dg-add-options arm_neon } */ ++ ++typedef unsigned int size_t; ++typedef int ptrdiff_t; ++typedef signed char int8_t ; ++typedef signed long long int64_t; ++typedef int8_t GFC_INTEGER_1; ++typedef GFC_INTEGER_1 GFC_LOGICAL_1; ++typedef int64_t GFC_INTEGER_8; ++typedef GFC_INTEGER_8 GFC_LOGICAL_8; ++typedef ptrdiff_t index_type; ++typedef struct descriptor_dimension ++{ ++ index_type lower_bound; ++ index_type _ubound; ++} ++descriptor_dimension; ++typedef struct { GFC_LOGICAL_1 *base_addr; size_t offset; index_type dtype; descriptor_dimension dim[7];} gfc_array_l1; ++typedef struct { GFC_LOGICAL_8 *base_addr; size_t offset; index_type dtype; descriptor_dimension dim[7];} gfc_array_l8; ++void ++all_l8 (gfc_array_l8 * const restrict retarray, ++ gfc_array_l1 * const restrict array, ++ const index_type * const restrict pdim) ++{ ++ GFC_LOGICAL_8 * restrict dest; ++ index_type n; ++ index_type len; ++ index_type delta; ++ index_type dim; ++ dim = (*pdim) - 1; ++ len = ((array)->dim[dim]._ubound + 1 - (array)->dim[dim].lower_bound); ++ for (n = 0; n < dim; n++) ++ { ++ const GFC_LOGICAL_1 * restrict src; ++ GFC_LOGICAL_8 result; ++ { ++ result = 1; ++ { ++ for (n = 0; n < len; n++, src += delta) ++ { ++ if (! *src) ++ { ++ result = 0; ++ break; ++ } ++ } ++ *dest = result; ++ } ++ } ++ } ++} +--- a/src/gcc/testsuite/gcc.dg/lower-subreg-1.c ++++ b/src/gcc/testsuite/gcc.dg/lower-subreg-1.c +@@ -1,4 +1,4 @@ +-/* { dg-do compile { target { ! { mips64 || { arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */ ++/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */ + /* { dg-options "-O -fdump-rtl-subreg1" } */ + /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */ + /* { dg-require-effective-target ilp32 } */ +--- a/src/gcc/testsuite/gcc.dg/shrink-wrap-sibcall.c ++++ b/src/gcc/testsuite/gcc.dg/shrink-wrap-sibcall.c +@@ -0,0 +1,26 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -g" } */ ++ ++unsigned char a, b, d, f, g; ++ ++int test (void); ++ ++int ++baz (int c) ++{ ++ if (c == 0) return test (); ++ if (b & 1) ++ { ++ g = 0; ++ int e = (a & 0x0f) - (g & 0x0f); ++ ++ if (!a) b |= 0x80; ++ a = e + test (); ++ f = g/5 + a*3879 + b *2985; ++ } ++ else ++ { ++ f = g + a*39879 + b *25; ++ } ++ return test (); ++} +--- a/src/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c ++++ b/src/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c +@@ -16,7 +16,7 @@ + E, F and G are passed on stack. So the size of the stack argument + data is 20. */ + #define STACK_ARGUMENTS_SIZE 20 +-#elif defined __MMIX__ ++#elif defined __aarch64__ || defined __MMIX__ + /* No parameters on stack for bar. */ + #define STACK_ARGUMENTS_SIZE 0 + #else +--- a/src/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c ++++ b/src/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c +@@ -1,4 +1,6 @@ +-/* { dg-require-effective-target vect_int } */ ++/* { dg-require-effective-target vect_int } ++ { dg-skip-if "AArch64 tiny code model does not support programs larger than 1MiB" {aarch64_tiny} {"*"} {""} } ++ */ + + #include + #include "tree-vect.h" +--- a/src/gcc/testsuite/g++.dg/asan/large-func-test-1.C ++++ b/src/gcc/testsuite/g++.dg/asan/large-func-test-1.C +@@ -37,9 +37,9 @@ + + // { dg-output "ERROR: AddressSanitizer:? heap-buffer-overflow on address\[^\n\r]*" } + // { dg-output "0x\[0-9a-f\]+ at pc 0x\[0-9a-f\]+ bp 0x\[0-9a-f\]+ sp 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } +-// { dg-output "READ of size 4 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*READ of size 4 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } + // { dg-output " #0 0x\[0-9a-f\]+ (in \[^\n\r]*LargeFunction\[^\n\r]*(large-func-test-1.C:18|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } +-// { dg-output "0x\[0-9a-f\]+ is located 44 bytes to the right of 400-byte region.*(\n|\r\n|\r)" } +-// { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 44 bytes to the right of 400-byte region.*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } + // { dg-output " #0( 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } + // { dg-output " #1|) 0x\[0-9a-f\]+ (in (operator new|_*_Zn\[aw\]\[mj\])|\[(\])\[^\n\r]*(\n|\r\n|\r)" } +--- a/src/gcc/testsuite/g++.dg/asan/deep-thread-stack-1.C ++++ b/src/gcc/testsuite/g++.dg/asan/deep-thread-stack-1.C +@@ -45,9 +45,9 @@ + } + + // { dg-output "ERROR: AddressSanitizer: heap-use-after-free.*(\n|\r\n|\r)" } +-// { dg-output "WRITE of size 4 at 0x\[0-9a-f\]+ thread T(\[0-9\]+).*(\n|\r\n|\r)" } +-// { dg-output "freed by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } +-// { dg-output "previously allocated by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*WRITE of size 4 at 0x\[0-9a-f\]+ thread T(\[0-9\]+).*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*freed by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } ++// { dg-output "\[^\n\r]*previously allocated by thread T(\[0-9\]+) here:.*(\n|\r\n|\r)" } + // { dg-output "Thread T\\2 created by T(\[0-9\]+) here:.*(\n|\r\n|\r)" } + // { dg-output "Thread T\\8 created by T0 here:.*(\n|\r\n|\r)" } + // { dg-output "Thread T\\4 created by T(\[0-9\]+) here:.*(\n|\r\n|\r)" } +--- a/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/strncpy-overflow-1.c +@@ -15,7 +15,7 @@ + /* { dg-output "WRITE of size \[0-9\]* at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)strncpy|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*strncpy-overflow-1.c:11|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "0x\[0-9a-f\]+ is located 0 bytes to the right of 9-byte region\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 0 bytes to the right of 9-byte region\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*strncpy-overflow-1.c:10|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +--- a/src/gcc/testsuite/c-c++-common/asan/rlimit-mmap-test-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/rlimit-mmap-test-1.c +@@ -2,6 +2,7 @@ + + /* { dg-do run { target setrlimit } } */ + /* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */ ++/* { dg-require-effective-target hw } */ + /* { dg-shouldfail "asan" } */ + + #include +--- a/src/gcc/testsuite/c-c++-common/asan/stack-overflow-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/stack-overflow-1.c +@@ -19,4 +19,4 @@ + + /* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*stack-overflow-1.c:16|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "Address 0x\[0-9a-f\]+ is\[^\n\r]*frame
" } */ ++/* { dg-output "\[^\n\r]*Address 0x\[0-9a-f\]+ is\[^\n\r]*frame
" } */ +--- a/src/gcc/testsuite/c-c++-common/asan/use-after-free-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/use-after-free-1.c +@@ -11,12 +11,12 @@ + + /* { dg-output "ERROR: AddressSanitizer:? heap-use-after-free on address\[^\n\r]*" } */ + /* { dg-output "0x\[0-9a-f\]+ at pc 0x\[0-9a-f\]+ bp 0x\[0-9a-f\]+ sp 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*READ of size 1 at 0x\[0-9a-f\]+ thread T0\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:9|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "0x\[0-9a-f\]+ is located 5 bytes inside of 10-byte region .0x\[0-9a-f\]+,0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "freed by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 5 bytes inside of 10-byte region .0x\[0-9a-f\]+,0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*freed by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)free|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:8|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "previously allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*previously allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*use-after-free-1.c:7|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +--- a/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/clone-test-1.c +@@ -3,6 +3,7 @@ + + /* { dg-do run { target { *-*-linux* } } } */ + /* { dg-require-effective-target clone } */ ++/* { dg-require-effective-target hw } */ + /* { dg-options "-D_GNU_SOURCE" } */ + + #include +--- a/src/gcc/testsuite/c-c++-common/asan/heap-overflow-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/heap-overflow-1.c +@@ -25,7 +25,7 @@ + + /* { dg-output "READ of size 1 at 0x\[0-9a-f\]+ thread T0.*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*heap-overflow-1.c:21|\[^\n\r]*:0)|\[(\]).*(\n|\r\n|\r)" } */ +-/* { dg-output "0x\[0-9a-f\]+ is located 0 bytes to the right of 10-byte region\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*0x\[0-9a-f\]+ is located 0 bytes to the right of 10-byte region\[^\n\r]*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*allocated by thread T0 here:\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in _*(interceptor_|)malloc|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*heap-overflow-1.c:19|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +--- a/src/gcc/testsuite/c-c++-common/asan/null-deref-1.c ++++ b/src/gcc/testsuite/c-c++-common/asan/null-deref-1.c +@@ -18,6 +18,6 @@ + + /* { dg-output "ERROR: AddressSanitizer:? SEGV on unknown address\[^\n\r]*" } */ + /* { dg-output "0x\[0-9a-f\]+ \[^\n\r]*pc 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */ +-/* { dg-output "AddressSanitizer can not provide additional info.*(\n|\r\n|\r)" } */ ++/* { dg-output "\[^\n\r]*AddressSanitizer can not provide additional info.*(\n|\r\n|\r)" } */ + /* { dg-output " #0 0x\[0-9a-f\]+ (in \[^\n\r]*NullDeref\[^\n\r]* (\[^\n\r]*null-deref-1.c:10|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ + /* { dg-output " #1 0x\[0-9a-f\]+ (in _*main (\[^\n\r]*null-deref-1.c:15|\[^\n\r]*:0)|\[(\])\[^\n\r]*(\n|\r\n|\r)" } */ +--- a/src/gcc/objcp/ChangeLog.linaro ++++ b/src/gcc/objcp/ChangeLog.linaro +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ ++2013-06-11 Rob Savoye ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.05 released. ++ ++2013-04-09 Matthew Gretton-Dann ++ ++ * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/cp/ChangeLog.linaro ++++ b/src/gcc/cp/ChangeLog.linaro +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ ++2013-06-11 Rob Savoye ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.05 released. ++ ++2013-04-09 Matthew Gretton-Dann ++ ++ * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/tree-ssa-loop-ivopts.c ++++ b/src/gcc/tree-ssa-loop-ivopts.c +@@ -4827,22 +4827,36 @@ + for (i = 0; i < n_iv_cands (data); i++) + { + struct iv_cand *cand = iv_cand (data, i); +- struct iv_use *closest = NULL; ++ struct iv_use *closest_before = NULL; ++ struct iv_use *closest_after = NULL; + if (cand->pos != IP_ORIGINAL) + continue; ++ + for (j = 0; j < n_iv_uses (data); j++) + { + struct iv_use *use = iv_use (data, j); + unsigned uid = gimple_uid (use->stmt); +- if (gimple_bb (use->stmt) != gimple_bb (cand->incremented_at) +- || uid > gimple_uid (cand->incremented_at)) ++ ++ if (gimple_bb (use->stmt) != gimple_bb (cand->incremented_at)) + continue; +- if (closest == NULL || uid > gimple_uid (closest->stmt)) +- closest = use; ++ ++ if (uid < gimple_uid (cand->incremented_at) ++ && (closest_before == NULL ++ || uid > gimple_uid (closest_before->stmt))) ++ closest_before = use; ++ ++ if (uid > gimple_uid (cand->incremented_at) ++ && (closest_after == NULL ++ || uid < gimple_uid (closest_after->stmt))) ++ closest_after = use; + } +- if (closest == NULL || !autoinc_possible_for_pair (data, closest, cand)) +- continue; +- cand->ainc_use = closest; ++ ++ if (closest_before != NULL ++ && autoinc_possible_for_pair (data, closest_before, cand)) ++ cand->ainc_use = closest_before; ++ else if (closest_after != NULL ++ && autoinc_possible_for_pair (data, closest_after, cand)) ++ cand->ainc_use = closest_after; + } + } + +--- a/src/gcc/rtl.def ++++ b/src/gcc/rtl.def +@@ -937,8 +937,9 @@ + relational operator. Operands should have only one alternative. + 1: A C expression giving an additional condition for recognizing + the generated pattern. +- 2: A template or C code to produce assembler output. */ +-DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) ++ 2: A template or C code to produce assembler output. ++ 3: A vector of attributes to append to the resulting cond_exec insn. */ ++DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA) + + /* Definition of an operand predicate. The difference between + DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will +--- a/src/gcc/go/ChangeLog.linaro ++++ b/src/gcc/go/ChangeLog.linaro +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ ++2013-06-11 Rob Savoye ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.05 released. ++ ++2013-04-09 Matthew Gretton-Dann ++ ++ * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/ada/ChangeLog.linaro ++++ b/src/gcc/ada/ChangeLog.linaro +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ ++2013-06-11 Rob Savoye ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.05 released. ++ ++2013-04-09 Matthew Gretton-Dann ++ ++ * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/common/config/aarch64/aarch64-common.c ++++ b/src/gcc/common/config/aarch64/aarch64-common.c +@@ -44,6 +44,8 @@ + { + /* Enable section anchors by default at -O1 or higher. */ + { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, ++ /* Enable redundant extension instructions removal at -O2 and higher. */ ++ { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, + { OPT_LEVELS_NONE, 0, NULL, 0 } + }; + +--- a/src/gcc/fortran/ChangeLog.linaro ++++ b/src/gcc/fortran/ChangeLog.linaro +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ ++2013-06-11 Rob Savoye ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.05 released. ++ ++2013-04-09 Matthew Gretton-Dann ++ ++ * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/configure.ac ++++ b/src/gcc/configure.ac +@@ -813,7 +813,7 @@ + ) + AC_SUBST(CONFIGURE_SPECS) + +-ACX_PKGVERSION([GCC]) ++ACX_PKGVERSION([Linaro GCC `cat $srcdir/LINARO-VERSION`]) + ACX_BUGURL([http://gcc.gnu.org/bugs.html]) + + # Sanity check enable_languages in case someone does not run the toplevel +@@ -4179,8 +4179,9 @@ + # ??? Once 2.11 is released, probably need to add first known working + # version to the per-target configury. + case "$cpu_type" in +- alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze | mips \ +- | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 | xtensa) ++ aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \ ++ | mips | pa | rs6000 | score | sparc | spu | tilegx | tilepro | xstormy16 \ ++ | xtensa) + insn="nop" + ;; + ia64 | s390) +--- a/src/gcc/function.c ++++ b/src/gcc/function.c +@@ -5509,22 +5509,45 @@ + except for any part that overlaps SRC (next loop). */ + bb_uses = &DF_LR_BB_INFO (bb)->use; + bb_defs = &DF_LR_BB_INFO (bb)->def; +- for (i = dregno; i < end_dregno; i++) ++ if (df_live) + { +- if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i)) +- next_block = NULL; +- CLEAR_REGNO_REG_SET (live_out, i); +- CLEAR_REGNO_REG_SET (live_in, i); ++ for (i = dregno; i < end_dregno; i++) ++ { ++ if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i) ++ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i)) ++ next_block = NULL; ++ CLEAR_REGNO_REG_SET (live_out, i); ++ CLEAR_REGNO_REG_SET (live_in, i); ++ } ++ ++ /* Check whether BB clobbers SRC. We need to add INSN to BB if so. ++ Either way, SRC is now live on entry. */ ++ for (i = sregno; i < end_sregno; i++) ++ { ++ if (REGNO_REG_SET_P (bb_defs, i) ++ || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i)) ++ next_block = NULL; ++ SET_REGNO_REG_SET (live_out, i); ++ SET_REGNO_REG_SET (live_in, i); ++ } + } ++ else ++ { ++ /* DF_LR_BB_INFO (bb)->def does not comprise the DF_REF_PARTIAL and ++ DF_REF_CONDITIONAL defs. So if DF_LIVE doesn't exist, i.e. ++ at -O1, just give up searching NEXT_BLOCK. */ ++ next_block = NULL; ++ for (i = dregno; i < end_dregno; i++) ++ { ++ CLEAR_REGNO_REG_SET (live_out, i); ++ CLEAR_REGNO_REG_SET (live_in, i); ++ } + +- /* Check whether BB clobbers SRC. We need to add INSN to BB if so. +- Either way, SRC is now live on entry. */ +- for (i = sregno; i < end_sregno; i++) +- { +- if (REGNO_REG_SET_P (bb_defs, i)) +- next_block = NULL; +- SET_REGNO_REG_SET (live_out, i); +- SET_REGNO_REG_SET (live_in, i); ++ for (i = sregno; i < end_sregno; i++) ++ { ++ SET_REGNO_REG_SET (live_out, i); ++ SET_REGNO_REG_SET (live_in, i); ++ } + } + + /* If we don't need to add the move to BB, look for a single +--- a/src/gcc/coretypes.h ++++ b/src/gcc/coretypes.h +@@ -62,6 +62,8 @@ + typedef union gimple_statement_d *gimple; + typedef const union gimple_statement_d *const_gimple; + typedef gimple gimple_seq; ++struct gimple_stmt_iterator_d; ++typedef struct gimple_stmt_iterator_d gimple_stmt_iterator; + union section; + typedef union section section; + struct gcc_options; +--- a/src/gcc/gimple-fold.c ++++ b/src/gcc/gimple-fold.c +@@ -1143,6 +1143,8 @@ + gimplify_and_update_call_from_tree (gsi, result); + changed = true; + } ++ else if (DECL_BUILT_IN_CLASS (callee) == BUILT_IN_MD) ++ changed |= targetm.gimple_fold_builtin (gsi); + } + + return changed; +--- a/src/gcc/lto/ChangeLog.linaro ++++ b/src/gcc/lto/ChangeLog.linaro +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ ++2013-06-11 Rob Savoye ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.05 released. ++ ++2013-04-09 Matthew Gretton-Dann ++ ++ * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/po/ChangeLog.linaro ++++ b/src/gcc/po/ChangeLog.linaro +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ ++2013-06-11 Rob Savoye ++ ++ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ ++2013-05-14 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.05 released. ++ ++2013-04-09 Matthew Gretton-Dann ++ ++ * GCC Linaro 4.8-2013.04 released. +--- a/src/gcc/combine.c ++++ b/src/gcc/combine.c +@@ -11982,6 +11982,13 @@ + } + } + ++ /* We may have changed the comparison operands. Re-canonicalize. */ ++ if (swap_commutative_operands_p (op0, op1)) ++ { ++ tem = op0, op0 = op1, op1 = tem; ++ code = swap_condition (code); ++ } ++ + /* If this machine only supports a subset of valid comparisons, see if we + can convert an unsupported one into a supported one. */ + target_canonicalize_comparison (&code, &op0, &op1, 0); +--- a/src/gcc/config.gcc ++++ b/src/gcc/config.gcc +@@ -329,6 +329,7 @@ + target_type_format_char='%' + c_target_objs="arm-c.o" + cxx_target_objs="arm-c.o" ++ need_64bit_hwint=yes + extra_options="${extra_options} arm/arm-tables.opt" + ;; + avr-*-*) +@@ -885,10 +886,6 @@ + tmake_file="$tmake_file arm/t-linux-androideabi" + ;; + esac +- # The BPABI long long divmod functions return a 128-bit value in +- # registers r0-r3. Correctly modeling that requires the use of +- # TImode. +- need_64bit_hwint=yes + # The EABI requires the use of __cxa_atexit. + default_use_cxa_atexit=yes + with_tls=${with_tls:-gnu} +@@ -897,10 +894,6 @@ + tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/linux-gas.h arm/uclinux-elf.h glibc-stdint.h" + tmake_file="arm/t-arm arm/t-arm-elf arm/t-bpabi" + tm_file="$tm_file arm/bpabi.h arm/uclinux-eabi.h arm/aout.h vxworks-dummy.h arm/arm.h" +- # The BPABI long long divmod functions return a 128-bit value in +- # registers r0-r3. Correctly modeling that requires the use of +- # TImode. +- need_64bit_hwint=yes + # The EABI requires the use of __cxa_atexit. + default_use_cxa_atexit=yes + ;; +@@ -909,10 +902,6 @@ + arm*eb-*-eabi*) + tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" + esac +- # The BPABI long long divmod functions return a 128-bit value in +- # registers r0-r3. Correctly modeling that requires the use of +- # TImode. +- need_64bit_hwint=yes + default_use_cxa_atexit=yes + tm_file="dbxelf.h elfos.h arm/unknown-elf.h arm/elf.h arm/bpabi.h" + tmake_file="arm/t-arm arm/t-arm-elf" +--- a/src/gcc/gimple.h ++++ b/src/gcc/gimple.h +@@ -130,7 +130,7 @@ + + /* Iterator object for GIMPLE statement sequences. */ + +-typedef struct ++struct gimple_stmt_iterator_d + { + /* Sequence node holding the current statement. */ + gimple_seq_node ptr; +@@ -141,9 +141,8 @@ + block/sequence is removed. */ + gimple_seq *seq; + basic_block bb; +-} gimple_stmt_iterator; ++}; + +- + /* Data structure definitions for GIMPLE tuples. NOTE: word markers + are for 64 bit hosts. */ + +--- a/src/gcc/config/i386/linux-common.h ++++ b/src/gcc/config/i386/linux-common.h +@@ -40,7 +40,7 @@ + #undef LIB_SPEC + #define LIB_SPEC \ + LINUX_OR_ANDROID_LD (GNU_USER_TARGET_LIB_SPEC, \ +- GNU_USER_TARGET_LIB_SPEC " " ANDROID_LIB_SPEC) ++ GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC " " ANDROID_LIB_SPEC) + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ +--- a/src/gcc/config/gnu-user.h ++++ b/src/gcc/config/gnu-user.h +@@ -73,10 +73,14 @@ + #undef CPLUSPLUS_CPP_SPEC + #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" + ++#define GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC \ ++ "%{shared:-lc} \ ++ %{!shared:%{mieee-fp:-lieee} %{profile:-lc_p}%{!profile:-lc}}" ++ + #define GNU_USER_TARGET_LIB_SPEC \ +- "%{pthread:-lpthread} \ +- %{shared:-lc} \ +- %{!shared:%{mieee-fp:-lieee} %{profile:-lc_p}%{!profile:-lc}}" ++ "%{pthread:-lpthread} " \ ++ GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC ++ + #undef LIB_SPEC + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC + +--- a/src/gcc/config/aarch64/aarch64-simd.md ++++ b/src/gcc/config/aarch64/aarch64-simd.md +@@ -21,7 +21,7 @@ + + ; Main data types used by the insntructions + +-(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI" ++(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI" + (const_string "unknown")) + + +@@ -44,6 +44,7 @@ + ; simd_dup duplicate element. + ; simd_dupgp duplicate general purpose register. + ; simd_ext bitwise extract from pair. ++; simd_fabd floating point absolute difference. + ; simd_fadd floating point add/sub. + ; simd_fcmp floating point compare. + ; simd_fcvti floating point convert to integer. +@@ -58,9 +59,9 @@ + ; simd_fmul floating point multiply. + ; simd_fmul_elt floating point multiply (by element). + ; simd_fnegabs floating point neg/abs. +-; simd_frcpe floating point reciprocal estimate. +-; simd_frcps floating point reciprocal step. +-; simd_frecx floating point reciprocal exponent. ++; simd_frecpe floating point reciprocal estimate. ++; simd_frecps floating point reciprocal step. ++; simd_frecpx floating point reciprocal exponent. + ; simd_frint floating point round to integer. + ; simd_fsqrt floating point square root. + ; simd_icvtf integer convert to floating point. +@@ -147,6 +148,7 @@ + simd_dup,\ + simd_dupgp,\ + simd_ext,\ ++ simd_fabd,\ + simd_fadd,\ + simd_fcmp,\ + simd_fcvti,\ +@@ -161,9 +163,9 @@ + simd_fmul,\ + simd_fmul_elt,\ + simd_fnegabs,\ +- simd_frcpe,\ +- simd_frcps,\ +- simd_frecx,\ ++ simd_frecpe,\ ++ simd_frecps,\ ++ simd_frecpx,\ + simd_frint,\ + simd_fsqrt,\ + simd_icvtf,\ +@@ -303,8 +305,8 @@ + (eq_attr "simd_type" "simd_store3,simd_store4") (const_string "neon_vst1_3_4_regs") + (eq_attr "simd_type" "simd_store1s,simd_store2s") (const_string "neon_vst1_vst2_lane") + (eq_attr "simd_type" "simd_store3s,simd_store4s") (const_string "neon_vst3_vst4_lane") +- (and (eq_attr "simd_type" "simd_frcpe,simd_frcps") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vrecps_vrsqrts_ddd") +- (and (eq_attr "simd_type" "simd_frcpe,simd_frcps") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vrecps_vrsqrts_qqq") ++ (and (eq_attr "simd_type" "simd_frecpe,simd_frecps") (eq_attr "simd_mode" "V2SF")) (const_string "neon_fp_vrecps_vrsqrts_ddd") ++ (and (eq_attr "simd_type" "simd_frecpe,simd_frecps") (eq_attr "simd_mode" "V4SF,V2DF")) (const_string "neon_fp_vrecps_vrsqrts_qqq") + (eq_attr "simd_type" "none") (const_string "none") + ] + (const_string "unknown"))) +@@ -355,18 +357,6 @@ + (set_attr "simd_mode" "")] + ) + +-(define_insn "aarch64_dup_lane" +- [(set (match_operand:SDQ_I 0 "register_operand" "=w") +- (vec_select: +- (match_operand: 1 "register_operand" "w") +- (parallel [(match_operand:SI 2 "immediate_operand" "i")]) +- ))] +- "TARGET_SIMD" +- "dup\\t%0, %1.[%2]" +- [(set_attr "simd_type" "simd_dup") +- (set_attr "simd_mode" "")] +-) +- + (define_insn "aarch64_simd_dup" + [(set (match_operand:VDQF 0 "register_operand" "=w") + (vec_duplicate:VDQF (match_operand: 1 "register_operand" "w")))] +@@ -394,7 +384,7 @@ + case 4: return "ins\t%0.d[0], %1"; + case 5: return "mov\t%0, %1"; + case 6: +- return aarch64_output_simd_mov_immediate (&operands[1], ++ return aarch64_output_simd_mov_immediate (operands[1], + mode, 64); + default: gcc_unreachable (); + } +@@ -414,16 +404,20 @@ + { + switch (which_alternative) + { +- case 0: return "ld1\t{%0.}, %1"; +- case 1: return "st1\t{%1.}, %0"; +- case 2: return "orr\t%0., %1., %1."; +- case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]"; +- case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1"; +- case 5: return "#"; ++ case 0: ++ return "ld1\t{%0.}, %1"; ++ case 1: ++ return "st1\t{%1.}, %0"; ++ case 2: ++ return "orr\t%0., %1., %1."; ++ case 3: ++ case 4: ++ case 5: ++ return "#"; + case 6: +- return aarch64_output_simd_mov_immediate (&operands[1], +- mode, 128); +- default: gcc_unreachable (); ++ return aarch64_output_simd_mov_immediate (operands[1], mode, 128); ++ default: ++ gcc_unreachable (); + } + } + [(set_attr "simd_type" "simd_load1,simd_store1,simd_move,simd_movgp,simd_insgp,simd_move,simd_move_imm") +@@ -452,6 +446,77 @@ + aarch64_simd_disambiguate_copy (operands, dest, src, 2); + }) + ++(define_split ++ [(set (match_operand:VQ 0 "register_operand" "") ++ (match_operand:VQ 1 "register_operand" ""))] ++ "TARGET_SIMD && reload_completed ++ && ((FP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) ++ || (GP_REGNUM_P (REGNO (operands[0])) && FP_REGNUM_P (REGNO (operands[1]))))" ++ [(const_int 0)] ++{ ++ aarch64_split_simd_move (operands[0], operands[1]); ++ DONE; ++}) ++ ++(define_expand "aarch64_split_simd_mov" ++ [(set (match_operand:VQ 0) ++ (match_operand:VQ 1))] ++ "TARGET_SIMD" ++ { ++ rtx dst = operands[0]; ++ rtx src = operands[1]; ++ ++ if (GP_REGNUM_P (REGNO (src))) ++ { ++ rtx src_low_part = gen_lowpart (mode, src); ++ rtx src_high_part = gen_highpart (mode, src); ++ ++ emit_insn ++ (gen_move_lo_quad_ (dst, src_low_part)); ++ emit_insn ++ (gen_move_hi_quad_ (dst, src_high_part)); ++ } ++ ++ else ++ { ++ rtx dst_low_part = gen_lowpart (mode, dst); ++ rtx dst_high_part = gen_highpart (mode, dst); ++ rtx lo = aarch64_simd_vect_par_cnst_half (mode, false); ++ rtx hi = aarch64_simd_vect_par_cnst_half (mode, true); ++ ++ emit_insn ++ (gen_aarch64_simd_mov_from_low (dst_low_part, src, lo)); ++ emit_insn ++ (gen_aarch64_simd_mov_from_high (dst_high_part, src, hi)); ++ } ++ DONE; ++ } ++) ++ ++(define_insn "aarch64_simd_mov_from_low" ++ [(set (match_operand: 0 "register_operand" "=r") ++ (vec_select: ++ (match_operand:VQ 1 "register_operand" "w") ++ (match_operand:VQ 2 "vect_par_cnst_lo_half" "")))] ++ "TARGET_SIMD && reload_completed" ++ "umov\t%0, %1.d[0]" ++ [(set_attr "simd_type" "simd_movgp") ++ (set_attr "simd_mode" "") ++ (set_attr "length" "4") ++ ]) ++ ++(define_insn "aarch64_simd_mov_from_high" ++ [(set (match_operand: 0 "register_operand" "=r") ++ (vec_select: ++ (match_operand:VQ 1 "register_operand" "w") ++ (match_operand:VQ 2 "vect_par_cnst_hi_half" "")))] ++ "TARGET_SIMD && reload_completed" ++ "umov\t%0, %1.d[1]" ++ [(set_attr "simd_type" "simd_movgp") ++ (set_attr "simd_mode" "") ++ (set_attr "length" "4") ++ ]) ++ + (define_insn "orn3" + [(set (match_operand:VDQ 0 "register_operand" "=w") + (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w")) +@@ -503,8 +568,8 @@ + ) + + (define_insn "neg2" +- [(set (match_operand:VDQM 0 "register_operand" "=w") +- (neg:VDQM (match_operand:VDQM 1 "register_operand" "w")))] ++ [(set (match_operand:VDQ 0 "register_operand" "=w") ++ (neg:VDQ (match_operand:VDQ 1 "register_operand" "w")))] + "TARGET_SIMD" + "neg\t%0., %1." + [(set_attr "simd_type" "simd_negabs") +@@ -520,6 +585,51 @@ + (set_attr "simd_mode" "")] + ) + ++(define_insn "abd_3" ++ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") ++ (abs:VDQ_BHSI (minus:VDQ_BHSI ++ (match_operand:VDQ_BHSI 1 "register_operand" "w") ++ (match_operand:VDQ_BHSI 2 "register_operand" "w"))))] ++ "TARGET_SIMD" ++ "sabd\t%0., %1., %2." ++ [(set_attr "simd_type" "simd_abd") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "aba_3" ++ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") ++ (plus:VDQ_BHSI (abs:VDQ_BHSI (minus:VDQ_BHSI ++ (match_operand:VDQ_BHSI 1 "register_operand" "w") ++ (match_operand:VDQ_BHSI 2 "register_operand" "w"))) ++ (match_operand:VDQ_BHSI 3 "register_operand" "0")))] ++ "TARGET_SIMD" ++ "saba\t%0., %1., %2." ++ [(set_attr "simd_type" "simd_abd") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "fabd_3" ++ [(set (match_operand:VDQF 0 "register_operand" "=w") ++ (abs:VDQF (minus:VDQF ++ (match_operand:VDQF 1 "register_operand" "w") ++ (match_operand:VDQF 2 "register_operand" "w"))))] ++ "TARGET_SIMD" ++ "fabd\t%0., %1., %2." ++ [(set_attr "simd_type" "simd_fabd") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "*fabd_scalar3" ++ [(set (match_operand:GPF 0 "register_operand" "=w") ++ (abs:GPF (minus:GPF ++ (match_operand:GPF 1 "register_operand" "w") ++ (match_operand:GPF 2 "register_operand" "w"))))] ++ "TARGET_SIMD" ++ "fabd\t%0, %1, %2" ++ [(set_attr "simd_type" "simd_fabd") ++ (set_attr "mode" "")] ++) ++ + (define_insn "and3" + [(set (match_operand:VDQ 0 "register_operand" "=w") + (and:VDQ (match_operand:VDQ 1 "register_operand" "w") +@@ -904,12 +1014,12 @@ + ) + + ;; Max/Min operations. +-(define_insn "3" ++(define_insn "3" + [(set (match_operand:VQ_S 0 "register_operand" "=w") + (MAXMIN:VQ_S (match_operand:VQ_S 1 "register_operand" "w") + (match_operand:VQ_S 2 "register_operand" "w")))] + "TARGET_SIMD" +- "\t%0., %1., %2." ++ "\t%0., %1., %2." + [(set_attr "simd_type" "simd_minmax") + (set_attr "simd_mode" "")] + ) +@@ -917,29 +1027,39 @@ + ;; Move into low-half clearing high half to 0. + + (define_insn "move_lo_quad_" +- [(set (match_operand:VQ 0 "register_operand" "=w") ++ [(set (match_operand:VQ 0 "register_operand" "=w,w,w") + (vec_concat:VQ +- (match_operand: 1 "register_operand" "w") ++ (match_operand: 1 "register_operand" "w,r,r") + (vec_duplicate: (const_int 0))))] + "TARGET_SIMD" +- "mov\\t%d0, %d1"; +- [(set_attr "simd_type" "simd_dup") +- (set_attr "simd_mode" "")] ++ "@ ++ dup\\t%d0, %1.d[0] ++ fmov\\t%d0, %1 ++ dup\\t%d0, %1" ++ [(set_attr "v8type" "*,fmov,*") ++ (set_attr "simd_type" "simd_dup,*,simd_dup") ++ (set_attr "simd_mode" "") ++ (set_attr "simd" "yes,*,yes") ++ (set_attr "fp" "*,yes,*") ++ (set_attr "length" "4")] + ) + + ;; Move into high-half. + + (define_insn "aarch64_simd_move_hi_quad_" +- [(set (match_operand:VQ 0 "register_operand" "+w") ++ [(set (match_operand:VQ 0 "register_operand" "+w,w") + (vec_concat:VQ + (vec_select: + (match_dup 0) + (match_operand:VQ 2 "vect_par_cnst_lo_half" "")) +- (match_operand: 1 "register_operand" "w")))] ++ (match_operand: 1 "register_operand" "w,r")))] + "TARGET_SIMD" +- "ins\\t%0.d[1], %1.d[0]"; +- [(set_attr "simd_type" "simd_ins") +- (set_attr "simd_mode" "")] ++ "@ ++ ins\\t%0.d[1], %1.d[0] ++ ins\\t%0.d[1], %1" ++ [(set_attr "simd_type" "simd_ins,simd_ins") ++ (set_attr "simd_mode" "") ++ (set_attr "length" "4")] + ) + + (define_expand "move_hi_quad_" +@@ -1045,6 +1165,104 @@ + + ;; Widening arithmetic. + ++(define_insn "*aarch64_mlal_lo" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (plus: ++ (mult: ++ (ANY_EXTEND: (vec_select: ++ (match_operand:VQW 2 "register_operand" "w") ++ (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) ++ (ANY_EXTEND: (vec_select: ++ (match_operand:VQW 4 "register_operand" "w") ++ (match_dup 3)))) ++ (match_operand: 1 "register_operand" "0")))] ++ "TARGET_SIMD" ++ "mlal\t%0., %2., %4." ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "*aarch64_mlal_hi" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (plus: ++ (mult: ++ (ANY_EXTEND: (vec_select: ++ (match_operand:VQW 2 "register_operand" "w") ++ (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) ++ (ANY_EXTEND: (vec_select: ++ (match_operand:VQW 4 "register_operand" "w") ++ (match_dup 3)))) ++ (match_operand: 1 "register_operand" "0")))] ++ "TARGET_SIMD" ++ "mlal2\t%0., %2., %4." ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "*aarch64_mlsl_lo" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (minus: ++ (match_operand: 1 "register_operand" "0") ++ (mult: ++ (ANY_EXTEND: (vec_select: ++ (match_operand:VQW 2 "register_operand" "w") ++ (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) ++ (ANY_EXTEND: (vec_select: ++ (match_operand:VQW 4 "register_operand" "w") ++ (match_dup 3))))))] ++ "TARGET_SIMD" ++ "mlsl\t%0., %2., %4." ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "*aarch64_mlsl_hi" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (minus: ++ (match_operand: 1 "register_operand" "0") ++ (mult: ++ (ANY_EXTEND: (vec_select: ++ (match_operand:VQW 2 "register_operand" "w") ++ (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) ++ (ANY_EXTEND: (vec_select: ++ (match_operand:VQW 4 "register_operand" "w") ++ (match_dup 3))))))] ++ "TARGET_SIMD" ++ "mlsl2\t%0., %2., %4." ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "*aarch64_mlal" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (plus: ++ (mult: ++ (ANY_EXTEND: ++ (match_operand:VDW 1 "register_operand" "w")) ++ (ANY_EXTEND: ++ (match_operand:VDW 2 "register_operand" "w"))) ++ (match_operand: 3 "register_operand" "0")))] ++ "TARGET_SIMD" ++ "mlal\t%0., %1., %2." ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "")] ++) ++ ++(define_insn "*aarch64_mlsl" ++ [(set (match_operand: 0 "register_operand" "=w") ++ (minus: ++ (match_operand: 1 "register_operand" "0") ++ (mult: ++ (ANY_EXTEND: ++ (match_operand:VDW 2 "register_operand" "w")) ++ (ANY_EXTEND: ++ (match_operand:VDW 3 "register_operand" "w")))))] ++ "TARGET_SIMD" ++ "mlsl\t%0., %2., %3." ++ [(set_attr "simd_type" "simd_mlal") ++ (set_attr "simd_mode" "")] ++) ++ + (define_insn "aarch64_simd_vec_mult_lo_" + [(set (match_operand: 0 "register_operand" "=w") + (mult: (ANY_EXTEND: (vec_select: +@@ -1196,7 +1414,9 @@ + (set_attr "simd_mode" "")] + ) + +-(define_insn "aarch64_frint" ++;; Vector versions of the floating-point frint patterns. ++;; Expands to btrunc, ceil, floor, nearbyint, rint, round. ++(define_insn "2" + [(set (match_operand:VDQF 0 "register_operand" "=w") + (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")] + FRINT))] +@@ -1206,16 +1426,9 @@ + (set_attr "simd_mode" "")] + ) + +-;; Vector versions of the floating-point frint patterns. +-;; Expands to btrunc, ceil, floor, nearbyint, rint, round. +-(define_expand "2" +- [(set (match_operand:VDQF 0 "register_operand") +- (unspec:VDQF [(match_operand:VDQF 1 "register_operand")] +- FRINT))] +- "TARGET_SIMD" +- {}) +- +-(define_insn "aarch64_fcvt" ++;; Vector versions of the fcvt standard patterns. ++;; Expands to lbtrunc, lround, lceil, lfloor ++(define_insn "l2" + [(set (match_operand: 0 "register_operand" "=w") + (FIXUORS: (unspec: + [(match_operand:VDQF 1 "register_operand" "w")] +@@ -1226,16 +1439,141 @@ + (set_attr "simd_mode" "")] + ) + +-;; Vector versions of the fcvt standard patterns. +-;; Expands to lbtrunc, lround, lceil, lfloor +-(define_expand "l2" ++(define_expand "2" + [(set (match_operand: 0 "register_operand") + (FIXUORS: (unspec: + [(match_operand:VDQF 1 "register_operand")] +- FCVT)))] ++ UNSPEC_FRINTZ)))] + "TARGET_SIMD" + {}) + ++(define_expand "2" ++ [(set (match_operand: 0 "register_operand") ++ (FIXUORS: (unspec: ++ [(match_operand:VDQF 1 "register_operand")] ++ UNSPEC_FRINTZ)))] ++ "TARGET_SIMD" ++ {}) ++ ++(define_expand "ftrunc2" ++ [(set (match_operand:VDQF 0 "register_operand") ++ (unspec:VDQF [(match_operand:VDQF 1 "register_operand")] ++ UNSPEC_FRINTZ))] ++ "TARGET_SIMD" ++ {}) ++ ++(define_insn "2" ++ [(set (match_operand:VDQF 0 "register_operand" "=w") ++ (FLOATUORS:VDQF ++ (match_operand: 1 "register_operand" "w")))] ++ "TARGET_SIMD" ++ "cvtf\\t%0., %1." ++ [(set_attr "simd_type" "simd_icvtf") ++ (set_attr "simd_mode" "")] ++) ++ ++;; Conversions between vectors of floats and doubles. ++;; Contains a mix of patterns to match standard pattern names ++;; and those for intrinsics. ++ ++;; Float widening operations. ++ ++(define_insn "vec_unpacks_lo_v4sf" ++ [(set (match_operand:V2DF 0 "register_operand" "=w") ++ (float_extend:V2DF ++ (vec_select:V2SF ++ (match_operand:V4SF 1 "register_operand" "w") ++ (parallel [(const_int 0) (const_int 1)]) ++ )))] ++ "TARGET_SIMD" ++ "fcvtl\\t%0.2d, %1.2s" ++ [(set_attr "simd_type" "simd_fcvtl") ++ (set_attr "simd_mode" "V2DF")] ++) ++ ++(define_insn "aarch64_float_extend_lo_v2df" ++ [(set (match_operand:V2DF 0 "register_operand" "=w") ++ (float_extend:V2DF ++ (match_operand:V2SF 1 "register_operand" "w")))] ++ "TARGET_SIMD" ++ "fcvtl\\t%0.2d, %1.2s" ++ [(set_attr "simd_type" "simd_fcvtl") ++ (set_attr "simd_mode" "V2DF")] ++) ++ ++(define_insn "vec_unpacks_hi_v4sf" ++ [(set (match_operand:V2DF 0 "register_operand" "=w") ++ (float_extend:V2DF ++ (vec_select:V2SF ++ (match_operand:V4SF 1 "register_operand" "w") ++ (parallel [(const_int 2) (const_int 3)]) ++ )))] ++ "TARGET_SIMD" ++ "fcvtl2\\t%0.2d, %1.4s" ++ [(set_attr "simd_type" "simd_fcvtl") ++ (set_attr "simd_mode" "V2DF")] ++) ++ ++;; Float narrowing operations. ++ ++(define_insn "aarch64_float_truncate_lo_v2sf" ++ [(set (match_operand:V2SF 0 "register_operand" "=w") ++ (float_truncate:V2SF ++ (match_operand:V2DF 1 "register_operand" "w")))] ++ "TARGET_SIMD" ++ "fcvtn\\t%0.2s, %1.2d" ++ [(set_attr "simd_type" "simd_fcvtl") ++ (set_attr "simd_mode" "V2SF")] ++) ++ ++(define_insn "aarch64_float_truncate_hi_v4sf" ++ [(set (match_operand:V4SF 0 "register_operand" "=w") ++ (vec_concat:V4SF ++ (match_operand:V2SF 1 "register_operand" "0") ++ (float_truncate:V2SF ++ (match_operand:V2DF 2 "register_operand" "w"))))] ++ "TARGET_SIMD" ++ "fcvtn2\\t%0.4s, %2.2d" ++ [(set_attr "simd_type" "simd_fcvtl") ++ (set_attr "simd_mode" "V4SF")] ++) ++ ++(define_expand "vec_pack_trunc_v2df" ++ [(set (match_operand:V4SF 0 "register_operand") ++ (vec_concat:V4SF ++ (float_truncate:V2SF ++ (match_operand:V2DF 1 "register_operand")) ++ (float_truncate:V2SF ++ (match_operand:V2DF 2 "register_operand")) ++ ))] ++ "TARGET_SIMD" ++ { ++ rtx tmp = gen_reg_rtx (V2SFmode); ++ emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[1])); ++ emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0], ++ tmp, operands[2])); ++ DONE; ++ } ++) ++ ++(define_expand "vec_pack_trunc_df" ++ [(set (match_operand:V2SF 0 "register_operand") ++ (vec_concat:V2SF ++ (float_truncate:SF ++ (match_operand:DF 1 "register_operand")) ++ (float_truncate:SF ++ (match_operand:DF 2 "register_operand")) ++ ))] ++ "TARGET_SIMD" ++ { ++ rtx tmp = gen_reg_rtx (V2SFmode); ++ emit_insn (gen_move_lo_quad_v2df (tmp, operands[1])); ++ emit_insn (gen_move_hi_quad_v2df (tmp, operands[2])); ++ emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp)); ++ DONE; ++ } ++) ++ + (define_insn "aarch64_vmls" + [(set (match_operand:VDQF 0 "register_operand" "=w") + (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") +@@ -1261,51 +1599,70 @@ + ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring + ;; NaNs. + +-(define_insn "smax3" ++(define_insn "3" + [(set (match_operand:VDQF 0 "register_operand" "=w") +- (smax:VDQF (match_operand:VDQF 1 "register_operand" "w") ++ (FMAXMIN:VDQF (match_operand:VDQF 1 "register_operand" "w") + (match_operand:VDQF 2 "register_operand" "w")))] + "TARGET_SIMD" +- "fmaxnm\\t%0., %1., %2." ++ "fnm\\t%0., %1., %2." + [(set_attr "simd_type" "simd_fminmax") + (set_attr "simd_mode" "")] + ) + +-(define_insn "smin3" ++(define_insn "3" + [(set (match_operand:VDQF 0 "register_operand" "=w") +- (smin:VDQF (match_operand:VDQF 1 "register_operand" "w") +- (match_operand:VDQF 2 "register_operand" "w")))] ++ (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") ++ (match_operand:VDQF 2 "register_operand" "w")] ++ FMAXMIN_UNS))] + "TARGET_SIMD" +- "fminnm\\t%0., %1., %2." ++ "\\t%0., %1., %2." + [(set_attr "simd_type" "simd_fminmax") + (set_attr "simd_mode" "")] + ) + +-;; FP 'across lanes' max and min ops. ++;; 'across lanes' add. + +-(define_insn "reduc_s_v4sf" +- [(set (match_operand:V4SF 0 "register_operand" "=w") +- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] +- FMAXMINV))] ++(define_insn "reduc_plus_" ++ [(set (match_operand:VDQV 0 "register_operand" "=w") ++ (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] ++ SUADDV))] + "TARGET_SIMD" +- "fnmv\\t%s0, %1.4s"; +- [(set_attr "simd_type" "simd_fminmaxv") +- (set_attr "simd_mode" "V4SF")] ++ "addv\\t%0, %1." ++ [(set_attr "simd_type" "simd_addv") ++ (set_attr "simd_mode" "")] + ) + +-(define_insn "reduc_s_" ++(define_insn "reduc_plus_v2di" ++ [(set (match_operand:V2DI 0 "register_operand" "=w") ++ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "w")] ++ SUADDV))] ++ "TARGET_SIMD" ++ "addp\\t%d0, %1.2d" ++ [(set_attr "simd_type" "simd_addv") ++ (set_attr "simd_mode" "V2DI")] ++) ++ ++(define_insn "reduc_plus_v2si" ++ [(set (match_operand:V2SI 0 "register_operand" "=w") ++ (unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")] ++ SUADDV))] ++ "TARGET_SIMD" ++ "addp\\t%0.2s, %1.2s, %1.2s" ++ [(set_attr "simd_type" "simd_addv") ++ (set_attr "simd_mode" "V2SI")] ++) ++ ++(define_insn "reduc_plus_" + [(set (match_operand:V2F 0 "register_operand" "=w") + (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] +- FMAXMINV))] ++ SUADDV))] + "TARGET_SIMD" +- "fnmp\\t%0., %1., %1."; +- [(set_attr "simd_type" "simd_fminmax") ++ "faddp\\t%0, %1." ++ [(set_attr "simd_type" "simd_fadd") + (set_attr "simd_mode" "")] + ) + +-;; FP 'across lanes' add. +- +-(define_insn "aarch64_addvv4sf" ++(define_insn "aarch64_addpv4sf" + [(set (match_operand:V4SF 0 "register_operand" "=w") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] + UNSPEC_FADDV))] +@@ -1315,169 +1672,106 @@ (set_attr "simd_mode" "V4SF")] ) @@ -8950,7 +12874,7 @@ "TARGET_SIMD" "@ bsl\\t%0., %2., %3. -@@ -1486,28 +1808,32 @@ +@@ -1486,28 +1780,32 @@ ) (define_expand "aarch64_simd_bsl" @@ -8992,7 +12916,7 @@ rtx mask = gen_reg_rtx (mode); switch (GET_CODE (operands[3])) -@@ -1548,12 +1874,12 @@ +@@ -1548,12 +1846,12 @@ case LTU: case GEU: @@ -9007,7 +12931,7 @@ break; case NE: -@@ -1566,30 +1892,47 @@ +@@ -1566,30 +1864,47 @@ } if (inverse) @@ -9066,7 +12990,7 @@ rtx (*base_comparison) (rtx, rtx, rtx); rtx (*complimentary_comparison) (rtx, rtx, rtx); -@@ -1609,7 +1952,7 @@ +@@ -1609,7 +1924,7 @@ /* Fall through. */ default: if (!REG_P (operands[5])) @@ -9075,7 +12999,7 @@ } switch (GET_CODE (operands[3])) -@@ -1622,8 +1965,8 @@ +@@ -1622,8 +1937,8 @@ case UNGE: case ORDERED: case UNORDERED: @@ -9086,7 +13010,7 @@ break; case LE: case UNLE: -@@ -1631,14 +1974,14 @@ +@@ -1631,14 +1946,14 @@ /* Fall through. */ case GT: case UNGT: @@ -9105,7 +13029,7 @@ break; default: gcc_unreachable (); -@@ -1666,10 +2009,10 @@ +@@ -1666,10 +1981,10 @@ switch (GET_CODE (operands[3])) { case LT: @@ -9118,7 +13042,7 @@ break; default: /* Do nothing, other zero form cases already have the correct -@@ -1712,9 +2055,9 @@ +@@ -1712,9 +2027,9 @@ true iff !(a != b && a ORDERED b), swapping the operands to BSL will then give us (a == b || a UNORDERED b) as intended. */ @@ -9131,7 +13055,7 @@ swap_bsl_operands = 1; break; case UNORDERED: -@@ -1723,20 +2066,36 @@ +@@ -1723,20 +2038,36 @@ swap_bsl_operands = 1; /* Fall through. */ case ORDERED: @@ -9176,7 +13100,7 @@ DONE; }) -@@ -1746,16 +2105,32 @@ +@@ -1746,16 +2077,32 @@ (match_operator 3 "comparison_operator" [(match_operand:VALL 4 "register_operand") (match_operand:VALL 5 "nonmemory_operand")]) @@ -9212,7 +13136,7 @@ (define_expand "vcondu" [(set (match_operand:VDQ 0 "register_operand") -@@ -1763,11 +2138,11 @@ +@@ -1763,11 +2110,11 @@ (match_operator 3 "comparison_operator" [(match_operand:VDQ 4 "register_operand") (match_operand:VDQ 5 "nonmemory_operand")]) @@ -9227,7 +13151,113 @@ operands[2], operands[3], operands[4], operands[5])); DONE; -@@ -2861,28 +3236,6 @@ +@@ -1785,45 +2132,50 @@ + DONE; + }) + +-(define_insn "aarch64_get_lane_signed" +- [(set (match_operand: 0 "register_operand" "=r") +- (sign_extend: ++;; Lane extraction with sign extension to general purpose register. ++(define_insn "*aarch64_get_lane_extend" ++ [(set (match_operand:GPI 0 "register_operand" "=r") ++ (sign_extend:GPI + (vec_select: +- (match_operand:VQ_S 1 "register_operand" "w") ++ (match_operand:VDQQH 1 "register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_SIMD" +- "smov\\t%0, %1.[%2]" ++ "smov\\t%0, %1.[%2]" + [(set_attr "simd_type" "simd_movgp") +- (set_attr "simd_mode" "")] ++ (set_attr "simd_mode" "")] + ) + +-(define_insn "aarch64_get_lane_unsigned" +- [(set (match_operand: 0 "register_operand" "=r") +- (zero_extend: ++(define_insn "*aarch64_get_lane_zero_extendsi" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (zero_extend:SI + (vec_select: +- (match_operand:VDQ 1 "register_operand" "w") ++ (match_operand:VDQQH 1 "register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_SIMD" +- "umov\\t%0, %1.[%2]" ++ "umov\\t%w0, %1.[%2]" + [(set_attr "simd_type" "simd_movgp") + (set_attr "simd_mode" "")] + ) + ++;; Lane extraction of a value, neither sign nor zero extension ++;; is guaranteed so upper bits should be considered undefined. + (define_insn "aarch64_get_lane" +- [(set (match_operand: 0 "register_operand" "=w") ++ [(set (match_operand: 0 "register_operand" "=r, w") + (vec_select: +- (match_operand:VDQF 1 "register_operand" "w") +- (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] ++ (match_operand:VALL 1 "register_operand" "w, w") ++ (parallel [(match_operand:SI 2 "immediate_operand" "i, i")])))] + "TARGET_SIMD" +- "mov\\t%0.[0], %1.[%2]" +- [(set_attr "simd_type" "simd_ins") ++ "@ ++ umov\\t%0, %1.[%2] ++ dup\\t%0, %1.[%2]" ++ [(set_attr "simd_type" "simd_movgp, simd_dup") + (set_attr "simd_mode" "")] + ) + + (define_expand "aarch64_get_lanedi" +- [(match_operand:DI 0 "register_operand" "=r") +- (match_operand:DI 1 "register_operand" "w") +- (match_operand:SI 2 "immediate_operand" "i")] ++ [(match_operand:DI 0 "register_operand") ++ (match_operand:DI 1 "register_operand") ++ (match_operand:SI 2 "immediate_operand")] + "TARGET_SIMD" + { + aarch64_simd_lane_bounds (operands[2], 0, 1); +@@ -1944,16 +2296,30 @@ + (set_attr "simd_mode" "")] + ) + +-(define_insn "aarch64_combine" ++(define_insn_and_split "aarch64_combine" + [(set (match_operand: 0 "register_operand" "=&w") + (vec_concat: (match_operand:VDC 1 "register_operand" "w") + (match_operand:VDC 2 "register_operand" "w")))] + "TARGET_SIMD" +- "mov\\t%0.d[0], %1.d[0]\;ins\\t%0.d[1], %2.d[0]" +- [(set_attr "simd_type" "simd_ins") +- (set_attr "simd_mode" "")] +-) ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++{ ++ aarch64_split_simd_combine (operands[0], operands[1], operands[2]); ++ DONE; ++}) + ++(define_expand "aarch64_simd_combine" ++ [(set (match_operand: 0 "register_operand" "=&w") ++ (vec_concat: (match_operand:VDC 1 "register_operand" "w") ++ (match_operand:VDC 2 "register_operand" "w")))] ++ "TARGET_SIMD" ++ { ++ emit_insn (gen_move_lo_quad_ (operands[0], operands[1])); ++ emit_insn (gen_move_hi_quad_ (operands[0], operands[2])); ++ DONE; ++ }) ++ + ;; l. + + (define_insn "aarch64_l2_internal" +@@ -2861,28 +3227,6 @@ (set_attr "simd_mode" "")] ) @@ -9256,7 +13286,7 @@ ;; vshll_n (define_insn "aarch64_shll_n" -@@ -2927,28 +3280,6 @@ +@@ -2927,28 +3271,6 @@ (set_attr "simd_mode" "")] ) @@ -9285,7 +13315,7 @@ ;; vrshr_n (define_insn "aarch64_shr_n" -@@ -3034,52 +3365,180 @@ +@@ -3034,52 +3356,180 @@ ) @@ -9489,7 +13519,7 @@ ;; addp (define_insn "aarch64_addp" -@@ -3105,30 +3564,6 @@ +@@ -3105,30 +3555,6 @@ (set_attr "simd_mode" "DI")] ) @@ -9520,7 +13550,7 @@ ;; sqrt (define_insn "sqrt2" -@@ -3140,16 +3575,6 @@ +@@ -3140,16 +3566,6 @@ (set_attr "simd_mode" "")] ) @@ -9537,7 +13567,7 @@ ;; Patterns for vector struct loads and stores. (define_insn "vec_load_lanesoi" -@@ -3714,3 +4139,25 @@ +@@ -3736,3 +4152,25 @@ "ld1r\\t{%0.}, %1" [(set_attr "simd_type" "simd_load1r") (set_attr "simd_mode" "")]) @@ -9577,7 +13607,7 @@ (define_predicate "aarch64_reg_zero_or_m1_or_1" (and (match_code "reg,subreg,const_int") (ior (match_operand 0 "register_operand") -@@ -110,10 +115,6 @@ +@@ -110,16 +115,11 @@ (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL, 0)"))) @@ -9588,37 +13618,431 @@ (define_predicate "aarch64_valid_symref" (match_code "const, symbol_ref, label_ref") { -@@ -165,15 +166,10 @@ - }) - - (define_predicate "aarch64_mov_operand" -- (and (match_code "reg,subreg,mem,const_int,symbol_ref,high") -+ (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high") - (ior (match_operand 0 "register_operand") - (ior (match_operand 0 "memory_operand") -- (ior (match_test "GET_CODE (op) == HIGH -- && aarch64_valid_symref (XEXP (op, 0), -- GET_MODE (XEXP (op, 0)))") -- (ior (match_test "CONST_INT_P (op) -- && aarch64_move_imm (INTVAL (op), mode)") -- (match_test "aarch64_const_address (op, mode)"))))))) -+ (match_test "aarch64_mov_operand_p (op, SYMBOL_CONTEXT_ADR, mode)"))))) - - (define_predicate "aarch64_movti_operand" - (and (match_code "reg,subreg,mem,const_int") ---- a/src/gcc/config/aarch64/aarch64-elf.h -+++ b/src/gcc/config/aarch64/aarch64-elf.h -@@ -106,7 +106,6 @@ - - #define ASM_COMMENT_START "//" - --#define REGISTER_PREFIX "" - #define LOCAL_LABEL_PREFIX "." - #define USER_LABEL_PREFIX "" - ---- a/src/gcc/config/aarch64/arm_neon.h -+++ b/src/gcc/config/aarch64/arm_neon.h -@@ -4468,17 +4468,6 @@ +- enum aarch64_symbol_type symbol_type; +- return (aarch64_symbolic_constant_p (op, SYMBOL_CONTEXT_ADR, &symbol_type) +- && symbol_type != SYMBOL_FORCE_TO_MEM); ++ return (aarch64_classify_symbolic_expression (op, SYMBOL_CONTEXT_ADR) ++ != SYMBOL_FORCE_TO_MEM); + }) + + (define_predicate "aarch64_tls_ie_symref" +@@ -165,15 +165,10 @@ + }) + + (define_predicate "aarch64_mov_operand" +- (and (match_code "reg,subreg,mem,const_int,symbol_ref,high") ++ (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high") + (ior (match_operand 0 "register_operand") + (ior (match_operand 0 "memory_operand") +- (ior (match_test "GET_CODE (op) == HIGH +- && aarch64_valid_symref (XEXP (op, 0), +- GET_MODE (XEXP (op, 0)))") +- (ior (match_test "CONST_INT_P (op) +- && aarch64_move_imm (INTVAL (op), mode)") +- (match_test "aarch64_const_address (op, mode)"))))))) ++ (match_test "aarch64_mov_operand_p (op, SYMBOL_CONTEXT_ADR, mode)"))))) + + (define_predicate "aarch64_movti_operand" + (and (match_code "reg,subreg,mem,const_int") +--- a/src/gcc/config/aarch64/aarch64-elf.h ++++ b/src/gcc/config/aarch64/aarch64-elf.h +@@ -106,7 +106,6 @@ + + #define ASM_COMMENT_START "//" + +-#define REGISTER_PREFIX "" + #define LOCAL_LABEL_PREFIX "." + #define USER_LABEL_PREFIX "" + +--- a/src/gcc/config/aarch64/arm_neon.h ++++ b/src/gcc/config/aarch64/arm_neon.h +@@ -29,6 +29,9 @@ + + #include + ++#define __AARCH64_UINT64_C(__C) ((uint64_t) __C) ++#define __AARCH64_INT64_C(__C) ((int64_t) __C) ++ + typedef __builtin_aarch64_simd_qi int8x8_t + __attribute__ ((__vector_size__ (8))); + typedef __builtin_aarch64_simd_hi int16x4_t +@@ -446,7 +449,66 @@ + poly16x8_t val[4]; + } poly16x8x4_t; + ++/* vget_lane internal macros. */ + ++#define __aarch64_vget_lane_any(__size, __cast_ret, __cast_a, __a, __b) \ ++ (__cast_ret \ ++ __builtin_aarch64_get_lane##__size (__cast_a __a, __b)) ++ ++#define __aarch64_vget_lane_f32(__a, __b) \ ++ __aarch64_vget_lane_any (v2sf, , , __a, __b) ++#define __aarch64_vget_lane_f64(__a, __b) (__a) ++ ++#define __aarch64_vget_lane_p8(__a, __b) \ ++ __aarch64_vget_lane_any (v8qi, (poly8_t), (int8x8_t), __a, __b) ++#define __aarch64_vget_lane_p16(__a, __b) \ ++ __aarch64_vget_lane_any (v4hi, (poly16_t), (int16x4_t), __a, __b) ++ ++#define __aarch64_vget_lane_s8(__a, __b) \ ++ __aarch64_vget_lane_any (v8qi, , ,__a, __b) ++#define __aarch64_vget_lane_s16(__a, __b) \ ++ __aarch64_vget_lane_any (v4hi, , ,__a, __b) ++#define __aarch64_vget_lane_s32(__a, __b) \ ++ __aarch64_vget_lane_any (v2si, , ,__a, __b) ++#define __aarch64_vget_lane_s64(__a, __b) (__a) ++ ++#define __aarch64_vget_lane_u8(__a, __b) \ ++ __aarch64_vget_lane_any (v8qi, (uint8_t), (int8x8_t), __a, __b) ++#define __aarch64_vget_lane_u16(__a, __b) \ ++ __aarch64_vget_lane_any (v4hi, (uint16_t), (int16x4_t), __a, __b) ++#define __aarch64_vget_lane_u32(__a, __b) \ ++ __aarch64_vget_lane_any (v2si, (uint32_t), (int32x2_t), __a, __b) ++#define __aarch64_vget_lane_u64(__a, __b) (__a) ++ ++#define __aarch64_vgetq_lane_f32(__a, __b) \ ++ __aarch64_vget_lane_any (v4sf, , , __a, __b) ++#define __aarch64_vgetq_lane_f64(__a, __b) \ ++ __aarch64_vget_lane_any (v2df, , , __a, __b) ++ ++#define __aarch64_vgetq_lane_p8(__a, __b) \ ++ __aarch64_vget_lane_any (v16qi, (poly8_t), (int8x16_t), __a, __b) ++#define __aarch64_vgetq_lane_p16(__a, __b) \ ++ __aarch64_vget_lane_any (v8hi, (poly16_t), (int16x8_t), __a, __b) ++ ++#define __aarch64_vgetq_lane_s8(__a, __b) \ ++ __aarch64_vget_lane_any (v16qi, , ,__a, __b) ++#define __aarch64_vgetq_lane_s16(__a, __b) \ ++ __aarch64_vget_lane_any (v8hi, , ,__a, __b) ++#define __aarch64_vgetq_lane_s32(__a, __b) \ ++ __aarch64_vget_lane_any (v4si, , ,__a, __b) ++#define __aarch64_vgetq_lane_s64(__a, __b) \ ++ __aarch64_vget_lane_any (v2di, , ,__a, __b) ++ ++#define __aarch64_vgetq_lane_u8(__a, __b) \ ++ __aarch64_vget_lane_any (v16qi, (uint8_t), (int8x16_t), __a, __b) ++#define __aarch64_vgetq_lane_u16(__a, __b) \ ++ __aarch64_vget_lane_any (v8hi, (uint16_t), (int16x8_t), __a, __b) ++#define __aarch64_vgetq_lane_u32(__a, __b) \ ++ __aarch64_vget_lane_any (v4si, (uint32_t), (int32x4_t), __a, __b) ++#define __aarch64_vgetq_lane_u64(__a, __b) \ ++ __aarch64_vget_lane_any (v2di, (uint64_t), (int64x2_t), __a, __b) ++ ++/* vadd */ + __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) + vadd_s8 (int8x8_t __a, int8x8_t __b) + { +@@ -2307,155 +2369,156 @@ + return (poly16x4_t) __a; + } + ++/* vget_lane */ ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vget_lane_f32 (float32x2_t __a, const int __b) ++{ ++ return __aarch64_vget_lane_f32 (__a, __b); ++} ++ ++__extension__ static __inline float64_t __attribute__ ((__always_inline__)) ++vget_lane_f64 (float64x1_t __a, const int __b) ++{ ++ return __aarch64_vget_lane_f64 (__a, __b); ++} ++ ++__extension__ static __inline poly8_t __attribute__ ((__always_inline__)) ++vget_lane_p8 (poly8x8_t __a, const int __b) ++{ ++ return __aarch64_vget_lane_p8 (__a, __b); ++} ++ ++__extension__ static __inline poly16_t __attribute__ ((__always_inline__)) ++vget_lane_p16 (poly16x4_t __a, const int __b) ++{ ++ return __aarch64_vget_lane_p16 (__a, __b); ++} ++ + __extension__ static __inline int8_t __attribute__ ((__always_inline__)) + vget_lane_s8 (int8x8_t __a, const int __b) + { +- return (int8_t) __builtin_aarch64_get_lane_signedv8qi (__a, __b); ++ return __aarch64_vget_lane_s8 (__a, __b); + } + + __extension__ static __inline int16_t __attribute__ ((__always_inline__)) + vget_lane_s16 (int16x4_t __a, const int __b) + { +- return (int16_t) __builtin_aarch64_get_lane_signedv4hi (__a, __b); ++ return __aarch64_vget_lane_s16 (__a, __b); + } + + __extension__ static __inline int32_t __attribute__ ((__always_inline__)) + vget_lane_s32 (int32x2_t __a, const int __b) + { +- return (int32_t) __builtin_aarch64_get_lane_signedv2si (__a, __b); ++ return __aarch64_vget_lane_s32 (__a, __b); + } + +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vget_lane_f32 (float32x2_t __a, const int __b) ++__extension__ static __inline int64_t __attribute__ ((__always_inline__)) ++vget_lane_s64 (int64x1_t __a, const int __b) + { +- return (float32_t) __builtin_aarch64_get_lanev2sf (__a, __b); ++ return __aarch64_vget_lane_s64 (__a, __b); + } + + __extension__ static __inline uint8_t __attribute__ ((__always_inline__)) + vget_lane_u8 (uint8x8_t __a, const int __b) + { +- return (uint8_t) __builtin_aarch64_get_lane_unsignedv8qi ((int8x8_t) __a, +- __b); ++ return __aarch64_vget_lane_u8 (__a, __b); + } + + __extension__ static __inline uint16_t __attribute__ ((__always_inline__)) + vget_lane_u16 (uint16x4_t __a, const int __b) + { +- return (uint16_t) __builtin_aarch64_get_lane_unsignedv4hi ((int16x4_t) __a, +- __b); ++ return __aarch64_vget_lane_u16 (__a, __b); + } + + __extension__ static __inline uint32_t __attribute__ ((__always_inline__)) + vget_lane_u32 (uint32x2_t __a, const int __b) + { +- return (uint32_t) __builtin_aarch64_get_lane_unsignedv2si ((int32x2_t) __a, +- __b); ++ return __aarch64_vget_lane_u32 (__a, __b); + } + +-__extension__ static __inline poly8_t __attribute__ ((__always_inline__)) +-vget_lane_p8 (poly8x8_t __a, const int __b) ++__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) ++vget_lane_u64 (uint64x1_t __a, const int __b) + { +- return (poly8_t) __builtin_aarch64_get_lane_unsignedv8qi ((int8x8_t) __a, +- __b); ++ return __aarch64_vget_lane_u64 (__a, __b); + } + +-__extension__ static __inline poly16_t __attribute__ ((__always_inline__)) +-vget_lane_p16 (poly16x4_t __a, const int __b) ++/* vgetq_lane */ ++ ++__extension__ static __inline float32_t __attribute__ ((__always_inline__)) ++vgetq_lane_f32 (float32x4_t __a, const int __b) + { +- return (poly16_t) __builtin_aarch64_get_lane_unsignedv4hi ((int16x4_t) __a, +- __b); ++ return __aarch64_vgetq_lane_f32 (__a, __b); + } + +-__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +-vget_lane_s64 (int64x1_t __a, const int __b) ++__extension__ static __inline float64_t __attribute__ ((__always_inline__)) ++vgetq_lane_f64 (float64x2_t __a, const int __b) + { +- return (int64_t) __builtin_aarch64_get_lanedi (__a, __b); ++ return __aarch64_vgetq_lane_f64 (__a, __b); + } + +-__extension__ static __inline uint64_t __attribute__ ((__always_inline__)) +-vget_lane_u64 (uint64x1_t __a, const int __b) ++__extension__ static __inline poly8_t __attribute__ ((__always_inline__)) ++vgetq_lane_p8 (poly8x16_t __a, const int __b) + { +- return (uint64_t) __builtin_aarch64_get_lanedi ((int64x1_t) __a, __b); ++ return __aarch64_vgetq_lane_p8 (__a, __b); + } + ++__extension__ static __inline poly16_t __attribute__ ((__always_inline__)) ++vgetq_lane_p16 (poly16x8_t __a, const int __b) ++{ ++ return __aarch64_vgetq_lane_p16 (__a, __b); ++} ++ + __extension__ static __inline int8_t __attribute__ ((__always_inline__)) + vgetq_lane_s8 (int8x16_t __a, const int __b) + { +- return (int8_t) __builtin_aarch64_get_lane_signedv16qi (__a, __b); ++ return __aarch64_vgetq_lane_s8 (__a, __b); + } + + __extension__ static __inline int16_t __attribute__ ((__always_inline__)) + vgetq_lane_s16 (int16x8_t __a, const int __b) + { +- return (int16_t) __builtin_aarch64_get_lane_signedv8hi (__a, __b); ++ return __aarch64_vgetq_lane_s16 (__a, __b); + } + + __extension__ static __inline int32_t __attribute__ ((__always_inline__)) + vgetq_lane_s32 (int32x4_t __a, const int __b) + { +- return (int32_t) __builtin_aarch64_get_lane_signedv4si (__a, __b); ++ return __aarch64_vgetq_lane_s32 (__a, __b); + } + +-__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +-vgetq_lane_f32 (float32x4_t __a, const int __b) ++__extension__ static __inline int64_t __attribute__ ((__always_inline__)) ++vgetq_lane_s64 (int64x2_t __a, const int __b) + { +- return (float32_t) __builtin_aarch64_get_lanev4sf (__a, __b); ++ return __aarch64_vgetq_lane_s64 (__a, __b); + } + +-__extension__ static __inline float64_t __attribute__ ((__always_inline__)) +-vgetq_lane_f64 (float64x2_t __a, const int __b) +-{ +- return (float64_t) __builtin_aarch64_get_lanev2df (__a, __b); +-} +- + __extension__ static __inline uint8_t __attribute__ ((__always_inline__)) + vgetq_lane_u8 (uint8x16_t __a, const int __b) + { +- return (uint8_t) __builtin_aarch64_get_lane_unsignedv16qi ((int8x16_t) __a, +- __b); ++ return __aarch64_vgetq_lane_u8 (__a, __b); + } + + __extension__ static __inline uint16_t __attribute__ ((__always_inline__)) + vgetq_lane_u16 (uint16x8_t __a, const int __b) + { +- return (uint16_t) __builtin_aarch64_get_lane_unsignedv8hi ((int16x8_t) __a, +- __b); ++ return __aarch64_vgetq_lane_u16 (__a, __b); + } + + __extension__ static __inline uint32_t __attribute__ ((__always_inline__)) + vgetq_lane_u32 (uint32x4_t __a, const int __b) + { +- return (uint32_t) __builtin_aarch64_get_lane_unsignedv4si ((int32x4_t) __a, +- __b); ++ return __aarch64_vgetq_lane_u32 (__a, __b); + } + +-__extension__ static __inline poly8_t __attribute__ ((__always_inline__)) +-vgetq_lane_p8 (poly8x16_t __a, const int __b) +-{ +- return (poly8_t) __builtin_aarch64_get_lane_unsignedv16qi ((int8x16_t) __a, +- __b); +-} +- +-__extension__ static __inline poly16_t __attribute__ ((__always_inline__)) +-vgetq_lane_p16 (poly16x8_t __a, const int __b) +-{ +- return (poly16_t) __builtin_aarch64_get_lane_unsignedv8hi ((int16x8_t) __a, +- __b); +-} +- +-__extension__ static __inline int64_t __attribute__ ((__always_inline__)) +-vgetq_lane_s64 (int64x2_t __a, const int __b) +-{ +- return __builtin_aarch64_get_lane_unsignedv2di (__a, __b); +-} +- + __extension__ static __inline uint64_t __attribute__ ((__always_inline__)) + vgetq_lane_u64 (uint64x2_t __a, const int __b) + { +- return (uint64_t) __builtin_aarch64_get_lane_unsignedv2di ((int64x2_t) __a, +- __b); ++ return __aarch64_vgetq_lane_u64 (__a, __b); + } + ++/* vreinterpret */ ++ + __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) + vreinterpret_p8_s8 (int8x8_t __a) + { +@@ -3805,6 +3868,85 @@ + return (uint32x4_t) __builtin_aarch64_reinterpretv4siv8hi ((int16x8_t) __a); + } + ++#define __GET_LOW(__TYPE) \ ++ uint64x2_t tmp = vreinterpretq_u64_##__TYPE (__a); \ ++ uint64_t lo = vgetq_lane_u64 (tmp, 0); \ ++ return vreinterpret_##__TYPE##_u64 (lo); ++ ++__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) ++vget_low_f32 (float32x4_t __a) ++{ ++ __GET_LOW (f32); ++} ++ ++__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) ++vget_low_f64 (float64x2_t __a) ++{ ++ return vgetq_lane_f64 (__a, 0); ++} ++ ++__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) ++vget_low_p8 (poly8x16_t __a) ++{ ++ __GET_LOW (p8); ++} ++ ++__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) ++vget_low_p16 (poly16x8_t __a) ++{ ++ __GET_LOW (p16); ++} ++ ++__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) ++vget_low_s8 (int8x16_t __a) ++{ ++ __GET_LOW (s8); ++} ++ ++__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) ++vget_low_s16 (int16x8_t __a) ++{ ++ __GET_LOW (s16); ++} ++ ++__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) ++vget_low_s32 (int32x4_t __a) ++{ ++ __GET_LOW (s32); ++} ++ ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vget_low_s64 (int64x2_t __a) ++{ ++ return vgetq_lane_s64 (__a, 0); ++} ++ ++__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) ++vget_low_u8 (uint8x16_t __a) ++{ ++ __GET_LOW (u8); ++} ++ ++__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) ++vget_low_u16 (uint16x8_t __a) ++{ ++ __GET_LOW (u16); ++} ++ ++__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) ++vget_low_u32 (uint32x4_t __a) ++{ ++ __GET_LOW (u32); ++} ++ ++__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) ++vget_low_u64 (uint64x2_t __a) ++{ ++ return vgetq_lane_u64 (__a, 0); ++} ++ ++#undef __GET_LOW ++ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vcombine_s8 (int8x8_t __a, int8x8_t __b) + { +@@ -4468,160 +4610,6 @@ return result; } @@ -9633,13 +14057,39 @@ - return result; -} - - __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) - vabs_s8 (int8x8_t a) - { -@@ -4512,28 +4501,6 @@ - return result; - } - +-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +-vabs_s8 (int8x8_t a) +-{ +- int8x8_t result; +- __asm__ ("abs %0.8b,%1.8b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +-vabs_s16 (int16x4_t a) +-{ +- int16x4_t result; +- __asm__ ("abs %0.4h,%1.4h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +-vabs_s32 (int32x2_t a) +-{ +- int32x2_t result; +- __asm__ ("abs %0.2s,%1.2s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- -__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vabsq_f32 (float32x4_t a) -{ @@ -9662,13 +14112,50 @@ - return result; -} - - __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) - vabsq_s8 (int8x16_t a) - { -@@ -4578,50 +4545,6 @@ - return result; - } - +-__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) +-vabsq_s8 (int8x16_t a) +-{ +- int8x16_t result; +- __asm__ ("abs %0.16b,%1.16b" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +-vabsq_s16 (int16x8_t a) +-{ +- int16x8_t result; +- __asm__ ("abs %0.8h,%1.8h" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +-vabsq_s32 (int32x4_t a) +-{ +- int32x4_t result; +- __asm__ ("abs %0.4s,%1.4s" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) +-vabsq_s64 (int64x2_t a) +-{ +- int64x2_t result; +- __asm__ ("abs %0.2d,%1.2d" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- -__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -vacged_f64 (float64_t a, float64_t b) -{ @@ -9716,7 +14203,7 @@ __extension__ static __inline int16_t __attribute__ ((__always_inline__)) vaddlv_s8 (int8x8_t a) { -@@ -4732,116 +4655,6 @@ +@@ -4732,116 +4720,6 @@ return result; } @@ -9833,7 +14320,7 @@ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vbsl_f32 (uint32x2_t a, float32x2_t b, float32x2_t c) { -@@ -5095,358 +4908,6 @@ +@@ -5095,358 +4973,6 @@ return result; } @@ -10192,7 +14679,7 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vcls_s8 (int8x8_t a) { -@@ -5513,50 +4974,6 @@ +@@ -5513,50 +5039,6 @@ return result; } @@ -10243,7 +14730,7 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vclz_s8 (int8x8_t a) { -@@ -5915,100 +5332,12 @@ +@@ -5915,100 +5397,12 @@ /* vcvt_f32_f16 not supported */ @@ -10344,7 +14831,7 @@ #define vcvt_n_f32_s32(a, b) \ __extension__ \ ({ \ -@@ -6057,160 +5386,6 @@ +@@ -6057,160 +5451,6 @@ result; \ }) @@ -10505,7 +14992,7 @@ #define vcvtd_n_f64_s64(a, b) \ __extension__ \ ({ \ -@@ -6259,402 +5434,6 @@ +@@ -6259,402 +5499,6 @@ result; \ }) @@ -10908,7 +15395,7 @@ #define vcvtq_n_f32_s32(a, b) \ __extension__ \ ({ \ -@@ -6751,72 +5530,6 @@ +@@ -6751,72 +5595,6 @@ result; \ }) @@ -10981,7 +15468,7 @@ #define vcvts_n_f32_s32(a, b) \ __extension__ \ ({ \ -@@ -6865,28 +5578,6 @@ +@@ -6865,28 +5643,6 @@ result; \ }) @@ -11010,10 +15497,162 @@ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vcvtx_f32_f64 (float64x2_t a) { -@@ -9226,303 +7917,6 @@ +@@ -8110,151 +6866,7 @@ return result; } +-#define vget_lane_f64(a, b) \ +- __extension__ \ +- ({ \ +- float64x1_t a_ = (a); \ +- float64_t result; \ +- __asm__ ("umov %x0, %1.d[%2]" \ +- : "=r"(result) \ +- : "w"(a_), "i"(b) \ +- : /* No clobbers */); \ +- result; \ +- }) +- +-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +-vget_low_f32 (float32x4_t a) +-{ +- float32x2_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) +-vget_low_f64 (float64x2_t a) +-{ +- float64x1_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) +-vget_low_p8 (poly8x16_t a) +-{ +- poly8x8_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline poly16x4_t __attribute__ ((__always_inline__)) +-vget_low_p16 (poly16x8_t a) +-{ +- poly16x4_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- + __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) +-vget_low_s8 (int8x16_t a) +-{ +- int8x8_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +-vget_low_s16 (int16x8_t a) +-{ +- int16x4_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +-vget_low_s32 (int32x4_t a) +-{ +- int32x2_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) +-vget_low_s64 (int64x2_t a) +-{ +- int64x1_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) +-vget_low_u8 (uint8x16_t a) +-{ +- uint8x8_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +-vget_low_u16 (uint16x8_t a) +-{ +- uint16x4_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) +-vget_low_u32 (uint32x4_t a) +-{ +- uint32x2_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) +-vget_low_u64 (uint64x2_t a) +-{ +- uint64x1_t result; +- __asm__ ("ins %0.d[0], %1.d[0]" +- : "=w"(result) +- : "w"(a) +- : /* No clobbers */); +- return result; +-} +- +-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) + vhsub_s8 (int8x8_t a, int8x8_t b) + { + int8x8_t result; +@@ -8962,303 +7574,6 @@ + result; \ + }) + -__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -vmaxnm_f32 (float32x2_t a, float32x2_t b) -{ @@ -11314,7 +15953,322 @@ #define vmla_lane_f32(a, b, c, d) \ __extension__ \ ({ \ -@@ -14556,17 +12950,6 @@ +@@ -11382,7 +9697,7 @@ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vmovn_high_s16 (int8x8_t a, int16x8_t b) + { +- int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.16b,%1.8h" + : "+w"(result) + : "w"(b) +@@ -11393,7 +9708,7 @@ + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) + vmovn_high_s32 (int16x4_t a, int32x4_t b) + { +- int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); ++ int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.8h,%1.4s" + : "+w"(result) + : "w"(b) +@@ -11404,7 +9719,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vmovn_high_s64 (int32x2_t a, int64x2_t b) + { +- int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); ++ int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.4s,%1.2d" + : "+w"(result) + : "w"(b) +@@ -11415,7 +9730,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vmovn_high_u16 (uint8x8_t a, uint16x8_t b) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.16b,%1.8h" + : "+w"(result) + : "w"(b) +@@ -11426,7 +9741,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vmovn_high_u32 (uint16x4_t a, uint32x4_t b) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.8h,%1.4s" + : "+w"(result) + : "w"(b) +@@ -11437,7 +9752,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vmovn_high_u64 (uint32x2_t a, uint64x2_t b) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("xtn2 %0.4s,%1.2d" + : "+w"(result) + : "w"(b) +@@ -13856,7 +12171,7 @@ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vqmovn_high_s16 (int8x8_t a, int16x8_t b) + { +- int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtn2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) +@@ -13867,7 +12182,7 @@ + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) + vqmovn_high_s32 (int16x4_t a, int32x4_t b) + { +- int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); ++ int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtn2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) +@@ -13878,7 +12193,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vqmovn_high_s64 (int32x2_t a, int64x2_t b) + { +- int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); ++ int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtn2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) +@@ -13889,7 +12204,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vqmovn_high_u16 (uint8x8_t a, uint16x8_t b) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("uqxtn2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) +@@ -13900,7 +12215,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vqmovn_high_u32 (uint16x4_t a, uint32x4_t b) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("uqxtn2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) +@@ -13911,7 +12226,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vqmovn_high_u64 (uint32x2_t a, uint64x2_t b) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("uqxtn2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) +@@ -13922,7 +12237,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vqmovun_high_s16 (uint8x8_t a, int16x8_t b) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtun2 %0.16b, %1.8h" + : "+w"(result) + : "w"(b) +@@ -13933,7 +12248,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vqmovun_high_s32 (uint16x4_t a, int32x4_t b) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtun2 %0.8h, %1.4s" + : "+w"(result) + : "w"(b) +@@ -13944,7 +12259,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vqmovun_high_s64 (uint32x2_t a, int64x2_t b) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("sqxtun2 %0.4s, %1.2d" + : "+w"(result) + : "w"(b) +@@ -14002,7 +12317,8 @@ + int16x8_t b_ = (b); \ + int8x8_t a_ = (a); \ + int8x16_t result = vcombine_s8 \ +- (a_, vcreate_s8 (UINT64_C (0x0))); \ ++ (a_, vcreate_s8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrn2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14016,7 +12332,8 @@ + int32x4_t b_ = (b); \ + int16x4_t a_ = (a); \ + int16x8_t result = vcombine_s16 \ +- (a_, vcreate_s16 (UINT64_C (0x0))); \ ++ (a_, vcreate_s16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrn2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14030,7 +12347,8 @@ + int64x2_t b_ = (b); \ + int32x2_t a_ = (a); \ + int32x4_t result = vcombine_s32 \ +- (a_, vcreate_s32 (UINT64_C (0x0))); \ ++ (a_, vcreate_s32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrn2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14044,7 +12362,8 @@ + uint16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqrshrn2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14058,7 +12377,8 @@ + uint32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqrshrn2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14072,7 +12392,8 @@ + uint64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqrshrn2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14086,7 +12407,8 @@ + int16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrun2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14100,7 +12422,8 @@ + int32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrun2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14114,7 +12437,8 @@ + int64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqrshrun2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14128,7 +12452,8 @@ + int16x8_t b_ = (b); \ + int8x8_t a_ = (a); \ + int8x16_t result = vcombine_s8 \ +- (a_, vcreate_s8 (UINT64_C (0x0))); \ ++ (a_, vcreate_s8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrn2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14142,7 +12467,8 @@ + int32x4_t b_ = (b); \ + int16x4_t a_ = (a); \ + int16x8_t result = vcombine_s16 \ +- (a_, vcreate_s16 (UINT64_C (0x0))); \ ++ (a_, vcreate_s16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrn2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14156,7 +12482,8 @@ + int64x2_t b_ = (b); \ + int32x2_t a_ = (a); \ + int32x4_t result = vcombine_s32 \ +- (a_, vcreate_s32 (UINT64_C (0x0))); \ ++ (a_, vcreate_s32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrn2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14170,7 +12497,8 @@ + uint16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqshrn2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14184,7 +12512,8 @@ + uint32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqshrn2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14198,7 +12527,8 @@ + uint64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("uqshrn2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14212,7 +12542,8 @@ + int16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrun2 %0.16b, %1.8h, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14226,7 +12557,8 @@ + int32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrun2 %0.8h, %1.4s, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14240,7 +12572,8 @@ + int64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("sqshrun2 %0.4s, %1.2d, #%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -14292,17 +12625,6 @@ return result; } @@ -11332,7 +16286,7 @@ __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vrecpe_u32 (uint32x2_t a) { -@@ -14578,39 +12961,6 @@ +@@ -14314,39 +12636,6 @@ return result; } @@ -11372,7 +16326,7 @@ __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vrecpeq_u32 (uint32x4_t a) { -@@ -14622,94 +12972,6 @@ +@@ -14358,94 +12647,6 @@ return result; } @@ -11467,7 +16421,7 @@ __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) vrev16_p8 (poly8x8_t a) { -@@ -15106,171 +13368,6 @@ +@@ -14842,178 +13043,14 @@ return result; } @@ -11639,7 +16593,234 @@ #define vrshrn_high_n_s16(a, b, c) \ __extension__ \ ({ \ -@@ -18788,86 +16885,6 @@ + int16x8_t b_ = (b); \ + int8x8_t a_ = (a); \ + int8x16_t result = vcombine_s8 \ +- (a_, vcreate_s8 (UINT64_C (0x0))); \ ++ (a_, vcreate_s8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.16b,%1.8h,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15027,7 +13064,8 @@ + int32x4_t b_ = (b); \ + int16x4_t a_ = (a); \ + int16x8_t result = vcombine_s16 \ +- (a_, vcreate_s16 (UINT64_C (0x0))); \ ++ (a_, vcreate_s16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.8h,%1.4s,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15041,7 +13079,8 @@ + int64x2_t b_ = (b); \ + int32x2_t a_ = (a); \ + int32x4_t result = vcombine_s32 \ +- (a_, vcreate_s32 (UINT64_C (0x0))); \ ++ (a_, vcreate_s32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.4s,%1.2d,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15055,7 +13094,8 @@ + uint16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.16b,%1.8h,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15069,7 +13109,8 @@ + uint32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.8h,%1.4s,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15083,7 +13124,8 @@ + uint64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("rshrn2 %0.4s,%1.2d,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15320,7 +13362,7 @@ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vrsubhn_high_s16 (int8x8_t a, int16x8_t b, int16x8_t c) + { +- int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.16b, %1.8h, %2.8h" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15331,7 +13373,7 @@ + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) + vrsubhn_high_s32 (int16x4_t a, int32x4_t b, int32x4_t c) + { +- int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); ++ int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.8h, %1.4s, %2.4s" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15342,7 +13384,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vrsubhn_high_s64 (int32x2_t a, int64x2_t b, int64x2_t c) + { +- int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); ++ int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.4s, %1.2d, %2.2d" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15353,7 +13395,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vrsubhn_high_u16 (uint8x8_t a, uint16x8_t b, uint16x8_t c) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.16b, %1.8h, %2.8h" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15364,7 +13406,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vrsubhn_high_u32 (uint16x4_t a, uint32x4_t b, uint32x4_t c) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.8h, %1.4s, %2.4s" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15375,7 +13417,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vrsubhn_high_u64 (uint32x2_t a, uint64x2_t b, uint64x2_t c) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("rsubhn2 %0.4s, %1.2d, %2.2d" + : "+w"(result) + : "w"(b), "w"(c) +@@ -15767,7 +13809,8 @@ + int16x8_t b_ = (b); \ + int8x8_t a_ = (a); \ + int8x16_t result = vcombine_s8 \ +- (a_, vcreate_s8 (UINT64_C (0x0))); \ ++ (a_, vcreate_s8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.16b,%1.8h,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15781,7 +13824,8 @@ + int32x4_t b_ = (b); \ + int16x4_t a_ = (a); \ + int16x8_t result = vcombine_s16 \ +- (a_, vcreate_s16 (UINT64_C (0x0))); \ ++ (a_, vcreate_s16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.8h,%1.4s,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15795,7 +13839,8 @@ + int64x2_t b_ = (b); \ + int32x2_t a_ = (a); \ + int32x4_t result = vcombine_s32 \ +- (a_, vcreate_s32 (UINT64_C (0x0))); \ ++ (a_, vcreate_s32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.4s,%1.2d,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15809,7 +13854,8 @@ + uint16x8_t b_ = (b); \ + uint8x8_t a_ = (a); \ + uint8x16_t result = vcombine_u8 \ +- (a_, vcreate_u8 (UINT64_C (0x0))); \ ++ (a_, vcreate_u8 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.16b,%1.8h,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15823,7 +13869,8 @@ + uint32x4_t b_ = (b); \ + uint16x4_t a_ = (a); \ + uint16x8_t result = vcombine_u16 \ +- (a_, vcreate_u16 (UINT64_C (0x0))); \ ++ (a_, vcreate_u16 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.8h,%1.4s,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -15837,7 +13884,8 @@ + uint64x2_t b_ = (b); \ + uint32x2_t a_ = (a); \ + uint32x4_t result = vcombine_u32 \ +- (a_, vcreate_u32 (UINT64_C (0x0))); \ ++ (a_, vcreate_u32 \ ++ (__AARCH64_UINT64_C (0x0))); \ + __asm__ ("shrn2 %0.4s,%1.2d,#%2" \ + : "+w"(result) \ + : "w"(b_), "i"(c) \ +@@ -16289,7 +14337,7 @@ + __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) + vsubhn_high_s16 (int8x8_t a, int16x8_t b, int16x8_t c) + { +- int8x16_t result = vcombine_s8 (a, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t result = vcombine_s8 (a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.16b, %1.8h, %2.8h" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16300,7 +14348,7 @@ + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) + vsubhn_high_s32 (int16x4_t a, int32x4_t b, int32x4_t c) + { +- int16x8_t result = vcombine_s16 (a, vcreate_s16 (UINT64_C (0x0))); ++ int16x8_t result = vcombine_s16 (a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.8h, %1.4s, %2.4s" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16311,7 +14359,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vsubhn_high_s64 (int32x2_t a, int64x2_t b, int64x2_t c) + { +- int32x4_t result = vcombine_s32 (a, vcreate_s32 (UINT64_C (0x0))); ++ int32x4_t result = vcombine_s32 (a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.4s, %1.2d, %2.2d" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16322,7 +14370,7 @@ + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) + vsubhn_high_u16 (uint8x8_t a, uint16x8_t b, uint16x8_t c) + { +- uint8x16_t result = vcombine_u8 (a, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t result = vcombine_u8 (a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.16b, %1.8h, %2.8h" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16333,7 +14381,7 @@ + __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) + vsubhn_high_u32 (uint16x4_t a, uint32x4_t b, uint32x4_t c) + { +- uint16x8_t result = vcombine_u16 (a, vcreate_u16 (UINT64_C (0x0))); ++ uint16x8_t result = vcombine_u16 (a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.8h, %1.4s, %2.4s" + : "+w"(result) + : "w"(b), "w"(c) +@@ -16344,7 +14392,7 @@ + __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) + vsubhn_high_u64 (uint32x2_t a, uint64x2_t b, uint64x2_t c) + { +- uint32x4_t result = vcombine_u32 (a, vcreate_u32 (UINT64_C (0x0))); ++ uint32x4_t result = vcombine_u32 (a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); + __asm__ ("subhn2 %0.4s, %1.2d, %2.2d" + : "+w"(result) + : "w"(b), "w"(c) +@@ -18309,86 +16357,6 @@ return result; } @@ -11726,7 +16907,115 @@ __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) vpaddd_s64 (int64x2_t __a) { -@@ -19849,6 +17866,26 @@ +@@ -19022,7 +16990,7 @@ + vtbl1_s8 (int8x8_t tab, int8x8_t idx) + { + int8x8_t result; +- int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" + : "=w"(result) + : "w"(temp), "w"(idx) +@@ -19034,7 +17002,7 @@ + vtbl1_u8 (uint8x8_t tab, uint8x8_t idx) + { + uint8x8_t result; +- uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" + : "=w"(result) + : "w"(temp), "w"(idx) +@@ -19046,7 +17014,7 @@ + vtbl1_p8 (poly8x8_t tab, uint8x8_t idx) + { + poly8x8_t result; +- poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (UINT64_C (0x0))); ++ poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("tbl %0.8b, {%1.16b}, %2.8b" + : "=w"(result) + : "w"(temp), "w"(idx) +@@ -19096,7 +17064,7 @@ + int8x8_t result; + int8x16x2_t temp; + temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" + "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" + : "=w"(result) +@@ -19111,7 +17079,7 @@ + uint8x8_t result; + uint8x16x2_t temp; + temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" + "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" + : "=w"(result) +@@ -19126,7 +17094,7 @@ + poly8x8_t result; + poly8x16x2_t temp; + temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b }, %1\n\t" + "tbl %0.8b, {v16.16b - v17.16b}, %2.8b\n\t" + : "=w"(result) +@@ -19185,7 +17153,7 @@ + { + int8x8_t result; + int8x8_t tmp1; +- int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (UINT64_C (0x0))); ++ int8x16_t temp = vcombine_s8 (tab, vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("movi %0.8b, 8\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" + "tbl %1.8b, {%2.16b}, %3.8b\n\t" +@@ -19201,7 +17169,7 @@ + { + uint8x8_t result; + uint8x8_t tmp1; +- uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (UINT64_C (0x0))); ++ uint8x16_t temp = vcombine_u8 (tab, vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("movi %0.8b, 8\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" + "tbl %1.8b, {%2.16b}, %3.8b\n\t" +@@ -19217,7 +17185,7 @@ + { + poly8x8_t result; + poly8x8_t tmp1; +- poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (UINT64_C (0x0))); ++ poly8x16_t temp = vcombine_p8 (tab, vcreate_p8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("movi %0.8b, 8\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" + "tbl %1.8b, {%2.16b}, %3.8b\n\t" +@@ -19271,7 +17239,7 @@ + int8x8_t tmp1; + int8x16x2_t temp; + temp.val[0] = vcombine_s8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_s8 (tab.val[2], vcreate_s8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" + "movi %0.8b, 24\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" +@@ -19290,7 +17258,7 @@ + uint8x8_t tmp1; + uint8x16x2_t temp; + temp.val[0] = vcombine_u8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_u8 (tab.val[2], vcreate_u8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" + "movi %0.8b, 24\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" +@@ -19309,7 +17277,7 @@ + poly8x8_t tmp1; + poly8x16x2_t temp; + temp.val[0] = vcombine_p8 (tab.val[0], tab.val[1]); +- temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (UINT64_C (0x0))); ++ temp.val[1] = vcombine_p8 (tab.val[2], vcreate_p8 (__AARCH64_UINT64_C (0x0))); + __asm__ ("ld1 {v16.16b - v17.16b}, %2\n\t" + "movi %0.8b, 24\n\t" + "cmhs %0.8b, %3.8b, %0.8b\n\t" +@@ -19370,6 +17338,80 @@ /* Start of optimal implementations in approved order. */ @@ -11738,6 +17027,36 @@ + return __builtin_aarch64_absv2sf (__a); +} + ++__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) ++vabs_f64 (float64x1_t __a) ++{ ++ return __builtin_fabs (__a); ++} ++ ++__extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) ++vabs_s8 (int8x8_t __a) ++{ ++ return __builtin_aarch64_absv8qi (__a); ++} ++ ++__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) ++vabs_s16 (int16x4_t __a) ++{ ++ return __builtin_aarch64_absv4hi (__a); ++} ++ ++__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) ++vabs_s32 (int32x2_t __a) ++{ ++ return __builtin_aarch64_absv2si (__a); ++} ++ ++__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) ++vabs_s64 (int64x1_t __a) ++{ ++ return __builtin_llabs (__a); ++} ++ +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vabsq_f32 (float32x4_t __a) +{ @@ -11750,10 +17069,34 @@ + return __builtin_aarch64_absv2df (__a); +} + ++__extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) ++vabsq_s8 (int8x16_t __a) ++{ ++ return __builtin_aarch64_absv16qi (__a); ++} ++ ++__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) ++vabsq_s16 (int16x8_t __a) ++{ ++ return __builtin_aarch64_absv8hi (__a); ++} ++ ++__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) ++vabsq_s32 (int32x4_t __a) ++{ ++ return __builtin_aarch64_absv4si (__a); ++} ++ ++__extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) ++vabsq_s64 (int64x2_t __a) ++{ ++ return __builtin_aarch64_absv2di (__a); ++} ++ /* vadd */ __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) -@@ -19863,8 +17900,238 @@ +@@ -19384,8 +17426,238 @@ return __a + __b; } @@ -11993,7 +17336,7 @@ __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) vceq_p8 (poly8x8_t __a, poly8x8_t __b) { -@@ -19893,7 +18160,7 @@ +@@ -19414,7 +17686,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceq_s64 (int64x1_t __a, int64x1_t __b) { @@ -12002,7 +17345,7 @@ } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -19920,10 +18187,21 @@ +@@ -19441,10 +17713,21 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vceq_u64 (uint64x1_t __a, uint64x1_t __b) { @@ -12026,7 +17369,7 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vceqq_p8 (poly8x16_t __a, poly8x16_t __b) { -@@ -19983,27 +18261,245 @@ +@@ -19504,27 +17787,245 @@ (int64x2_t) __b); } @@ -12276,7 +17619,7 @@ vcge_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgev8qi (__a, __b); -@@ -20024,38 +18520,56 @@ +@@ -19545,38 +18046,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcge_s64 (int64x1_t __a, int64x1_t __b) { @@ -12339,7 +17682,7 @@ vcgeq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgev16qi (__a, __b); -@@ -20082,53 +18596,270 @@ +@@ -19603,53 +18122,270 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -12619,7 +17962,7 @@ vcgt_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__a, __b); -@@ -20149,38 +18880,56 @@ +@@ -19670,38 +18406,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcgt_s64 (int64x1_t __a, int64x1_t __b) { @@ -12682,7 +18025,7 @@ vcgtq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__a, __b); -@@ -20207,53 +18956,270 @@ +@@ -19728,53 +18482,270 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -12962,7 +18305,7 @@ vcle_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgev8qi (__b, __a); -@@ -20274,38 +19240,56 @@ +@@ -19795,38 +18766,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vcle_s64 (int64x1_t __a, int64x1_t __b) { @@ -13025,7 +18368,7 @@ vcleq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgev16qi (__b, __a); -@@ -20332,46 +19316,213 @@ +@@ -19853,46 +18842,213 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcleq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -13246,7 +18589,7 @@ vclt_s8 (int8x8_t __a, int8x8_t __b) { return (uint8x8_t) __builtin_aarch64_cmgtv8qi (__b, __a); -@@ -20392,38 +19543,56 @@ +@@ -19913,38 +19069,56 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vclt_s64 (int64x1_t __a, int64x1_t __b) { @@ -13309,7 +18652,7 @@ vcltq_s8 (int8x16_t __a, int8x16_t __b) { return (uint8x16_t) __builtin_aarch64_cmgtv16qi (__b, __a); -@@ -20450,91 +19619,664 @@ +@@ -19971,91 +19145,664 @@ __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vcltq_u8 (uint8x16_t __a, uint8x16_t __b) { @@ -13935,60 +19278,60 @@ vdupb_lane_s8 (int8x16_t a, int const b) { - return __builtin_aarch64_dup_laneqi (a, b); -+ return __builtin_aarch64_dup_lane_scalarv16qi (a, b); ++ return __aarch64_vgetq_lane_s8 (a, b); } __extension__ static __inline uint8x1_t __attribute__ ((__always_inline__)) vdupb_lane_u8 (uint8x16_t a, int const b) { - return (uint8x1_t) __builtin_aarch64_dup_laneqi ((int8x16_t) a, b); -+ return (uint8x1_t) __builtin_aarch64_dup_lane_scalarv16qi ((int8x16_t) a, b); ++ return __aarch64_vgetq_lane_u8 (a, b); } __extension__ static __inline int16x1_t __attribute__ ((__always_inline__)) vduph_lane_s16 (int16x8_t a, int const b) { - return __builtin_aarch64_dup_lanehi (a, b); -+ return __builtin_aarch64_dup_lane_scalarv8hi (a, b); ++ return __aarch64_vgetq_lane_s16 (a, b); } __extension__ static __inline uint16x1_t __attribute__ ((__always_inline__)) vduph_lane_u16 (uint16x8_t a, int const b) { - return (uint16x1_t) __builtin_aarch64_dup_lanehi ((int16x8_t) a, b); -+ return (uint16x1_t) __builtin_aarch64_dup_lane_scalarv8hi ((int16x8_t) a, b); ++ return __aarch64_vgetq_lane_u16 (a, b); } __extension__ static __inline int32x1_t __attribute__ ((__always_inline__)) vdups_lane_s32 (int32x4_t a, int const b) { - return __builtin_aarch64_dup_lanesi (a, b); -+ return __builtin_aarch64_dup_lane_scalarv4si (a, b); ++ return __aarch64_vgetq_lane_s32 (a, b); } __extension__ static __inline uint32x1_t __attribute__ ((__always_inline__)) vdups_lane_u32 (uint32x4_t a, int const b) { - return (uint32x1_t) __builtin_aarch64_dup_lanesi ((int32x4_t) a, b); -+ return (uint32x1_t) __builtin_aarch64_dup_lane_scalarv4si ((int32x4_t) a, b); ++ return __aarch64_vgetq_lane_u32 (a, b); } __extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) vdupd_lane_s64 (int64x2_t a, int const b) { - return __builtin_aarch64_dup_lanedi (a, b); -+ return __builtin_aarch64_dup_lane_scalarv2di (a, b); ++ return __aarch64_vgetq_lane_s64 (a, b); } __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vdupd_lane_u64 (uint64x2_t a, int const b) { - return (uint64x1_t) __builtin_aarch64_dup_lanedi ((int64x2_t) a, b); -+ return (uint64x1_t) __builtin_aarch64_dup_lane_scalarv2di ((int64x2_t) a, b); ++ return __aarch64_vgetq_lane_u64 (a, b); } - /* vldn */ -@@ -21408,7 +21150,7 @@ + /* vld1 */ +@@ -21088,7 +20835,7 @@ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vmax_f32 (float32x2_t __a, float32x2_t __b) { @@ -13997,7 +19340,7 @@ } __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -21453,13 +21195,13 @@ +@@ -21133,13 +20880,13 @@ __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vmaxq_f32 (float32x4_t __a, float32x4_t __b) { @@ -14013,7 +19356,7 @@ } __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -@@ -21501,12 +21243,150 @@ +@@ -21181,12 +20928,150 @@ (int32x4_t) __b); } @@ -14166,7 +19509,7 @@ } __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -21551,13 +21431,13 @@ +@@ -21231,13 +21116,13 @@ __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) vminq_f32 (float32x4_t __a, float32x4_t __b) { @@ -14182,7 +19525,7 @@ } __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) -@@ -21599,6 +21479,144 @@ +@@ -21279,6 +21164,144 @@ (int32x4_t) __b); } @@ -14327,7 +19670,61 @@ /* vmla */ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -@@ -23115,6 +23133,223 @@ +@@ -21430,7 +21453,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vqdmlal_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d) + { +- int16x8_t __tmp = vcombine_s16 (__c, vcreate_s16 (INT64_C (0))); ++ int16x8_t __tmp = vcombine_s16 (__c, vcreate_s16 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmlal_lanev4hi (__a, __b, __tmp, __d); + } + +@@ -21481,7 +21504,7 @@ + __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) + vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d) + { +- int32x4_t __tmp = vcombine_s32 (__c, vcreate_s32 (INT64_C (0))); ++ int32x4_t __tmp = vcombine_s32 (__c, vcreate_s32 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmlal_lanev2si (__a, __b, __tmp, __d); + } + +@@ -21558,7 +21581,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vqdmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c, int const __d) + { +- int16x8_t __tmp = vcombine_s16 (__c, vcreate_s16 (INT64_C (0))); ++ int16x8_t __tmp = vcombine_s16 (__c, vcreate_s16 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmlsl_lanev4hi (__a, __b, __tmp, __d); + } + +@@ -21609,7 +21632,7 @@ + __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) + vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c, int const __d) + { +- int32x4_t __tmp = vcombine_s32 (__c, vcreate_s32 (INT64_C (0))); ++ int32x4_t __tmp = vcombine_s32 (__c, vcreate_s32 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmlsl_lanev2si (__a, __b, __tmp, __d); + } + +@@ -21734,7 +21757,7 @@ + __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) + vqdmull_lane_s16 (int16x4_t __a, int16x4_t __b, int const __c) + { +- int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (INT64_C (0))); ++ int16x8_t __tmp = vcombine_s16 (__b, vcreate_s16 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmull_lanev4hi (__a, __tmp, __c); + } + +@@ -21783,7 +21806,7 @@ + __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) + vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b, int const __c) + { +- int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (INT64_C (0))); ++ int32x4_t __tmp = vcombine_s32 (__b, vcreate_s32 (__AARCH64_INT64_C (0))); + return __builtin_aarch64_sqdmull_lanev2si (__a, __tmp, __c); + } + +@@ -22795,6 +22818,223 @@ return (uint64x1_t) __builtin_aarch64_uqsubdi (__a, __b); } @@ -14551,7 +19948,7 @@ /* vrshl */ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -23458,109 +23693,109 @@ +@@ -23138,109 +23378,109 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vshl_n_s8 (int8x8_t __a, const int __b) { @@ -14679,7 +20076,7 @@ } __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) -@@ -23748,109 +23983,109 @@ +@@ -23428,109 +23668,109 @@ __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vshr_n_s8 (int8x8_t __a, const int __b) { @@ -14807,7 +20204,475 @@ } /* vsli */ -@@ -25320,7 +25555,7 @@ +@@ -24153,8 +24393,8 @@ + { + __builtin_aarch64_simd_oi __o; + int64x2x2_t temp; +- temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (INT64_C (0))); +- temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (INT64_C (0))); ++ temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1); + __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o); +@@ -24165,8 +24405,8 @@ + { + __builtin_aarch64_simd_oi __o; + uint64x2x2_t temp; +- temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (UINT64_C (0))); +- temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (UINT64_C (0))); ++ temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv2di (__o, (int64x2_t) temp.val[1], 1); + __builtin_aarch64_st2di ((__builtin_aarch64_simd_di *) __a, __o); +@@ -24177,8 +24417,8 @@ + { + __builtin_aarch64_simd_oi __o; + float64x2x2_t temp; +- temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (UINT64_C (0))); +- temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (UINT64_C (0))); ++ temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv2df (__o, (float64x2_t) temp.val[1], 1); + __builtin_aarch64_st2df ((__builtin_aarch64_simd_df *) __a, __o); +@@ -24189,8 +24429,8 @@ + { + __builtin_aarch64_simd_oi __o; + int8x16x2_t temp; +- temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (INT64_C (0))); +- temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (INT64_C (0))); ++ temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1); + __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o); +@@ -24201,8 +24441,8 @@ + { + __builtin_aarch64_simd_oi __o; + poly8x16x2_t temp; +- temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (UINT64_C (0))); +- temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (UINT64_C (0))); ++ temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1); + __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o); +@@ -24213,8 +24453,8 @@ + { + __builtin_aarch64_simd_oi __o; + int16x8x2_t temp; +- temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (INT64_C (0))); +- temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (INT64_C (0))); ++ temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1); + __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o); +@@ -24225,8 +24465,8 @@ + { + __builtin_aarch64_simd_oi __o; + poly16x8x2_t temp; +- temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (UINT64_C (0))); +- temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (UINT64_C (0))); ++ temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1); + __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o); +@@ -24237,8 +24477,8 @@ + { + __builtin_aarch64_simd_oi __o; + int32x4x2_t temp; +- temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (INT64_C (0))); +- temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (INT64_C (0))); ++ temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1); + __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o); +@@ -24249,8 +24489,8 @@ + { + __builtin_aarch64_simd_oi __o; + uint8x16x2_t temp; +- temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (UINT64_C (0))); +- temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (UINT64_C (0))); ++ temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv16qi (__o, (int8x16_t) temp.val[1], 1); + __builtin_aarch64_st2v8qi ((__builtin_aarch64_simd_qi *) __a, __o); +@@ -24261,8 +24501,8 @@ + { + __builtin_aarch64_simd_oi __o; + uint16x8x2_t temp; +- temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (UINT64_C (0))); +- temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (UINT64_C (0))); ++ temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv8hi (__o, (int16x8_t) temp.val[1], 1); + __builtin_aarch64_st2v4hi ((__builtin_aarch64_simd_hi *) __a, __o); +@@ -24273,8 +24513,8 @@ + { + __builtin_aarch64_simd_oi __o; + uint32x4x2_t temp; +- temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (UINT64_C (0))); +- temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (UINT64_C (0))); ++ temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv4si (__o, (int32x4_t) temp.val[1], 1); + __builtin_aarch64_st2v2si ((__builtin_aarch64_simd_si *) __a, __o); +@@ -24285,8 +24525,8 @@ + { + __builtin_aarch64_simd_oi __o; + float32x4x2_t temp; +- temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (UINT64_C (0))); +- temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (UINT64_C (0))); ++ temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregoiv4sf (__o, (float32x4_t) temp.val[1], 1); + __builtin_aarch64_st2v2sf ((__builtin_aarch64_simd_sf *) __a, __o); +@@ -24405,9 +24645,9 @@ + { + __builtin_aarch64_simd_ci __o; + int64x2x3_t temp; +- temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (INT64_C (0))); +- temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (INT64_C (0))); +- temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (INT64_C (0))); ++ temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2); +@@ -24419,9 +24659,9 @@ + { + __builtin_aarch64_simd_ci __o; + uint64x2x3_t temp; +- temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (UINT64_C (0))); +- temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (UINT64_C (0))); +- temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (UINT64_C (0))); ++ temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv2di (__o, (int64x2_t) temp.val[2], 2); +@@ -24433,9 +24673,9 @@ + { + __builtin_aarch64_simd_ci __o; + float64x2x3_t temp; +- temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (UINT64_C (0))); +- temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (UINT64_C (0))); +- temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (UINT64_C (0))); ++ temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) temp.val[2], 2); +@@ -24447,9 +24687,9 @@ + { + __builtin_aarch64_simd_ci __o; + int8x16x3_t temp; +- temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (INT64_C (0))); +- temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (INT64_C (0))); +- temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (INT64_C (0))); ++ temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24461,9 +24701,9 @@ + { + __builtin_aarch64_simd_ci __o; + poly8x16x3_t temp; +- temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (UINT64_C (0))); +- temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (UINT64_C (0))); +- temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (UINT64_C (0))); ++ temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24475,9 +24715,9 @@ + { + __builtin_aarch64_simd_ci __o; + int16x8x3_t temp; +- temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (INT64_C (0))); +- temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (INT64_C (0))); +- temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (INT64_C (0))); ++ temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24489,9 +24729,9 @@ + { + __builtin_aarch64_simd_ci __o; + poly16x8x3_t temp; +- temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (UINT64_C (0))); +- temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (UINT64_C (0))); +- temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (UINT64_C (0))); ++ temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24503,9 +24743,9 @@ + { + __builtin_aarch64_simd_ci __o; + int32x4x3_t temp; +- temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (INT64_C (0))); +- temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (INT64_C (0))); +- temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (INT64_C (0))); ++ temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2); +@@ -24517,9 +24757,9 @@ + { + __builtin_aarch64_simd_ci __o; + uint8x16x3_t temp; +- temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (UINT64_C (0))); +- temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (UINT64_C (0))); +- temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (UINT64_C (0))); ++ temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24531,9 +24771,9 @@ + { + __builtin_aarch64_simd_ci __o; + uint16x8x3_t temp; +- temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (UINT64_C (0))); +- temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (UINT64_C (0))); +- temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (UINT64_C (0))); ++ temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24545,9 +24785,9 @@ + { + __builtin_aarch64_simd_ci __o; + uint32x4x3_t temp; +- temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (UINT64_C (0))); +- temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (UINT64_C (0))); +- temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (UINT64_C (0))); ++ temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv4si (__o, (int32x4_t) temp.val[2], 2); +@@ -24559,9 +24799,9 @@ + { + __builtin_aarch64_simd_ci __o; + float32x4x3_t temp; +- temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (UINT64_C (0))); +- temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (UINT64_C (0))); +- temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (UINT64_C (0))); ++ temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregciv4sf (__o, (float32x4_t) temp.val[2], 2); +@@ -24693,10 +24933,10 @@ + { + __builtin_aarch64_simd_xi __o; + int64x2x4_t temp; +- temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (INT64_C (0))); +- temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (INT64_C (0))); +- temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (INT64_C (0))); +- temp.val[3] = vcombine_s64 (val.val[3], vcreate_s64 (INT64_C (0))); ++ temp.val[0] = vcombine_s64 (val.val[0], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s64 (val.val[1], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s64 (val.val[2], vcreate_s64 (__AARCH64_INT64_C (0))); ++ temp.val[3] = vcombine_s64 (val.val[3], vcreate_s64 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2); +@@ -24709,10 +24949,10 @@ + { + __builtin_aarch64_simd_xi __o; + uint64x2x4_t temp; +- temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (UINT64_C (0))); +- temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (UINT64_C (0))); +- temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (UINT64_C (0))); +- temp.val[3] = vcombine_u64 (val.val[3], vcreate_u64 (UINT64_C (0))); ++ temp.val[0] = vcombine_u64 (val.val[0], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u64 (val.val[1], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u64 (val.val[2], vcreate_u64 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_u64 (val.val[3], vcreate_u64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv2di (__o, (int64x2_t) temp.val[2], 2); +@@ -24725,10 +24965,10 @@ + { + __builtin_aarch64_simd_xi __o; + float64x2x4_t temp; +- temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (UINT64_C (0))); +- temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (UINT64_C (0))); +- temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (UINT64_C (0))); +- temp.val[3] = vcombine_f64 (val.val[3], vcreate_f64 (UINT64_C (0))); ++ temp.val[0] = vcombine_f64 (val.val[0], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f64 (val.val[1], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_f64 (val.val[2], vcreate_f64 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_f64 (val.val[3], vcreate_f64 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv2df (__o, (float64x2_t) temp.val[2], 2); +@@ -24741,10 +24981,10 @@ + { + __builtin_aarch64_simd_xi __o; + int8x16x4_t temp; +- temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (INT64_C (0))); +- temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (INT64_C (0))); +- temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (INT64_C (0))); +- temp.val[3] = vcombine_s8 (val.val[3], vcreate_s8 (INT64_C (0))); ++ temp.val[0] = vcombine_s8 (val.val[0], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s8 (val.val[1], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s8 (val.val[2], vcreate_s8 (__AARCH64_INT64_C (0))); ++ temp.val[3] = vcombine_s8 (val.val[3], vcreate_s8 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24757,10 +24997,10 @@ + { + __builtin_aarch64_simd_xi __o; + poly8x16x4_t temp; +- temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (UINT64_C (0))); +- temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (UINT64_C (0))); +- temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (UINT64_C (0))); +- temp.val[3] = vcombine_p8 (val.val[3], vcreate_p8 (UINT64_C (0))); ++ temp.val[0] = vcombine_p8 (val.val[0], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p8 (val.val[1], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_p8 (val.val[2], vcreate_p8 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_p8 (val.val[3], vcreate_p8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24773,10 +25013,10 @@ + { + __builtin_aarch64_simd_xi __o; + int16x8x4_t temp; +- temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (INT64_C (0))); +- temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (INT64_C (0))); +- temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (INT64_C (0))); +- temp.val[3] = vcombine_s16 (val.val[3], vcreate_s16 (INT64_C (0))); ++ temp.val[0] = vcombine_s16 (val.val[0], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s16 (val.val[1], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s16 (val.val[2], vcreate_s16 (__AARCH64_INT64_C (0))); ++ temp.val[3] = vcombine_s16 (val.val[3], vcreate_s16 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24789,10 +25029,10 @@ + { + __builtin_aarch64_simd_xi __o; + poly16x8x4_t temp; +- temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (UINT64_C (0))); +- temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (UINT64_C (0))); +- temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (UINT64_C (0))); +- temp.val[3] = vcombine_p16 (val.val[3], vcreate_p16 (UINT64_C (0))); ++ temp.val[0] = vcombine_p16 (val.val[0], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_p16 (val.val[1], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_p16 (val.val[2], vcreate_p16 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_p16 (val.val[3], vcreate_p16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24805,10 +25045,10 @@ + { + __builtin_aarch64_simd_xi __o; + int32x4x4_t temp; +- temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (INT64_C (0))); +- temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (INT64_C (0))); +- temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (INT64_C (0))); +- temp.val[3] = vcombine_s32 (val.val[3], vcreate_s32 (INT64_C (0))); ++ temp.val[0] = vcombine_s32 (val.val[0], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[1] = vcombine_s32 (val.val[1], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[2] = vcombine_s32 (val.val[2], vcreate_s32 (__AARCH64_INT64_C (0))); ++ temp.val[3] = vcombine_s32 (val.val[3], vcreate_s32 (__AARCH64_INT64_C (0))); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2); +@@ -24821,10 +25061,10 @@ + { + __builtin_aarch64_simd_xi __o; + uint8x16x4_t temp; +- temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (UINT64_C (0))); +- temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (UINT64_C (0))); +- temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (UINT64_C (0))); +- temp.val[3] = vcombine_u8 (val.val[3], vcreate_u8 (UINT64_C (0))); ++ temp.val[0] = vcombine_u8 (val.val[0], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u8 (val.val[1], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u8 (val.val[2], vcreate_u8 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_u8 (val.val[3], vcreate_u8 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv16qi (__o, (int8x16_t) temp.val[2], 2); +@@ -24837,10 +25077,10 @@ + { + __builtin_aarch64_simd_xi __o; + uint16x8x4_t temp; +- temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (UINT64_C (0))); +- temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (UINT64_C (0))); +- temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (UINT64_C (0))); +- temp.val[3] = vcombine_u16 (val.val[3], vcreate_u16 (UINT64_C (0))); ++ temp.val[0] = vcombine_u16 (val.val[0], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u16 (val.val[1], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u16 (val.val[2], vcreate_u16 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_u16 (val.val[3], vcreate_u16 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv8hi (__o, (int16x8_t) temp.val[2], 2); +@@ -24853,10 +25093,10 @@ + { + __builtin_aarch64_simd_xi __o; + uint32x4x4_t temp; +- temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (UINT64_C (0))); +- temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (UINT64_C (0))); +- temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (UINT64_C (0))); +- temp.val[3] = vcombine_u32 (val.val[3], vcreate_u32 (UINT64_C (0))); ++ temp.val[0] = vcombine_u32 (val.val[0], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_u32 (val.val[1], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_u32 (val.val[2], vcreate_u32 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_u32 (val.val[3], vcreate_u32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) temp.val[2], 2); +@@ -24869,10 +25109,10 @@ + { + __builtin_aarch64_simd_xi __o; + float32x4x4_t temp; +- temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (UINT64_C (0))); +- temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (UINT64_C (0))); +- temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (UINT64_C (0))); +- temp.val[3] = vcombine_f32 (val.val[3], vcreate_f32 (UINT64_C (0))); ++ temp.val[0] = vcombine_f32 (val.val[0], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[1] = vcombine_f32 (val.val[1], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[2] = vcombine_f32 (val.val[2], vcreate_f32 (__AARCH64_UINT64_C (0))); ++ temp.val[3] = vcombine_f32 (val.val[3], vcreate_f32 (__AARCH64_UINT64_C (0))); + __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[0], 0); + __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[1], 1); + __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) temp.val[2], 2); +@@ -25159,7 +25399,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtst_s64 (int64x1_t __a, int64x1_t __b) { @@ -14816,7 +20681,7 @@ } __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) -@@ -25347,8 +25582,7 @@ +@@ -25186,8 +25426,7 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtst_u64 (uint64x1_t __a, uint64x1_t __b) { @@ -14826,7 +20691,7 @@ } __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) -@@ -25406,14 +25640,13 @@ +@@ -25245,14 +25484,13 @@ __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) vtstd_s64 (int64x1_t __a, int64x1_t __b) { @@ -14843,6 +20708,38 @@ } /* vuqadd */ +@@ -25371,4 +25609,31 @@ + + /* End of optimal implementations in approved order. */ + ++#undef __aarch64_vget_lane_any ++#undef __aarch64_vget_lane_f32 ++#undef __aarch64_vget_lane_f64 ++#undef __aarch64_vget_lane_p8 ++#undef __aarch64_vget_lane_p16 ++#undef __aarch64_vget_lane_s8 ++#undef __aarch64_vget_lane_s16 ++#undef __aarch64_vget_lane_s32 ++#undef __aarch64_vget_lane_s64 ++#undef __aarch64_vget_lane_u8 ++#undef __aarch64_vget_lane_u16 ++#undef __aarch64_vget_lane_u32 ++#undef __aarch64_vget_lane_u64 ++ ++#undef __aarch64_vgetq_lane_f32 ++#undef __aarch64_vgetq_lane_f64 ++#undef __aarch64_vgetq_lane_p8 ++#undef __aarch64_vgetq_lane_p16 ++#undef __aarch64_vgetq_lane_s8 ++#undef __aarch64_vgetq_lane_s16 ++#undef __aarch64_vgetq_lane_s32 ++#undef __aarch64_vgetq_lane_s64 ++#undef __aarch64_vgetq_lane_u8 ++#undef __aarch64_vgetq_lane_u16 ++#undef __aarch64_vgetq_lane_u32 ++#undef __aarch64_vgetq_lane_u64 ++ + #endif --- a/src/gcc/config/aarch64/aarch64.md +++ b/src/gcc/config/aarch64/aarch64.md @@ -68,9 +68,13 @@ @@ -14946,7 +20843,7 @@ + [(set_attr "v8type" "move,alu,load1,load1,store1,store1,fmov,fmov,fmov") (set_attr "mode" "SI") - (set_attr "fp" "*,*,*,*,yes,yes,yes")] -+ (set_attr "fp" "*,*,*,*,*,*,yes,yes,yes")] ++ (set_attr "fp" "*,*,*,yes,*,yes,yes,yes,yes")] ) (define_insn "*movdi_aarch64" @@ -14975,7 +20872,7 @@ (set_attr "mode" "DI") - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,yes")] -+ (set_attr "fp" "*,*,*,*,*,*,*,*,*,*,yes,yes,yes,*") ++ (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") + (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] ) @@ -14992,7 +20889,38 @@ "movk\\t%0, %X2, lsl %1" [(set_attr "v8type" "movk") (set_attr "mode" "")] -@@ -1150,13 +1182,14 @@ +@@ -982,9 +1014,9 @@ + || register_operand (operands[1], TFmode))" + "@ + orr\\t%0.16b, %1.16b, %1.16b +- mov\\t%0, %1\;mov\\t%H0, %H1 +- fmov\\t%d0, %Q1\;fmov\\t%0.d[1], %R1 +- fmov\\t%Q0, %d1\;fmov\\t%R0, %1.d[1] ++ # ++ # ++ # + movi\\t%0.2d, #0 + fmov\\t%s0, wzr + ldr\\t%q0, %1 +@@ -998,6 +1030,17 @@ + (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")] + ) + ++(define_split ++ [(set (match_operand:TF 0 "register_operand" "") ++ (match_operand:TF 1 "aarch64_reg_or_imm" ""))] ++ "reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])" ++ [(const_int 0)] ++ { ++ aarch64_split_128bit_move (operands[0], operands[1]); ++ DONE; ++ } ++) ++ + ;; Operands 1 and 3 are tied together by the final condition; so we allow + ;; fairly lax checking on the second memory operation. + (define_insn "load_pair" +@@ -1150,13 +1193,14 @@ ) (define_insn "*zero_extend2_aarch64" @@ -15011,7 +20939,7 @@ (set_attr "mode" "")] ) -@@ -1287,6 +1320,112 @@ +@@ -1287,6 +1331,112 @@ (set_attr "mode" "SI")] ) @@ -15124,7 +21052,25 @@ (define_insn "*add3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ -@@ -1791,6 +1930,34 @@ +@@ -1302,12 +1452,12 @@ + ) + + (define_insn "*compare_neg" +- [(set (reg:CC CC_REGNUM) +- (compare:CC +- (match_operand:GPI 0 "register_operand" "r") +- (neg:GPI (match_operand:GPI 1 "register_operand" "r"))))] ++ [(set (reg:CC_SWP CC_REGNUM) ++ (compare:CC_SWP ++ (neg:GPI (match_operand:GPI 0 "register_operand" "r")) ++ (match_operand:GPI 1 "register_operand" "r")))] + "" +- "cmn\\t%0, %1" ++ "cmn\\t%1, %0" + [(set_attr "v8type" "alus") + (set_attr "mode" "")] + ) +@@ -1791,6 +1941,34 @@ (set_attr "mode" "SI")] ) @@ -15159,7 +21105,46 @@ (define_insn "*sub_uxt_multp2" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 4 "register_operand" "r") -@@ -1844,6 +2011,27 @@ +@@ -1825,6 +2003,38 @@ + (set_attr "mode" "SI")] + ) + ++(define_insn_and_split "absdi2" ++ [(set (match_operand:DI 0 "register_operand" "=r,w") ++ (abs:DI (match_operand:DI 1 "register_operand" "r,w"))) ++ (clobber (match_scratch:DI 2 "=&r,X"))] ++ "" ++ "@ ++ # ++ abs\\t%d0, %d1" ++ "reload_completed ++ && GP_REGNUM_P (REGNO (operands[0])) ++ && GP_REGNUM_P (REGNO (operands[1]))" ++ [(const_int 0)] ++ { ++ emit_insn (gen_rtx_SET (VOIDmode, operands[2], ++ gen_rtx_XOR (DImode, ++ gen_rtx_ASHIFTRT (DImode, ++ operands[1], ++ GEN_INT (63)), ++ operands[1]))); ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_MINUS (DImode, ++ operands[2], ++ gen_rtx_ASHIFTRT (DImode, ++ operands[1], ++ GEN_INT (63))))); ++ DONE; ++ } ++ [(set_attr "v8type" "alu") ++ (set_attr "mode" "DI")] ++) ++ + (define_insn "neg2" + [(set (match_operand:GPI 0 "register_operand" "=r") + (neg:GPI (match_operand:GPI 1 "register_operand" "r")))] +@@ -1844,6 +2054,27 @@ (set_attr "mode" "SI")] ) @@ -15187,7 +21172,7 @@ (define_insn "*neg2_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ (neg:GPI (match_operand:GPI 1 "register_operand" "r")) -@@ -1869,6 +2057,21 @@ +@@ -1869,6 +2100,21 @@ (set_attr "mode" "SI")] ) @@ -15209,7 +21194,7 @@ (define_insn "*neg__2" [(set (match_operand:GPI 0 "register_operand" "=r") (neg:GPI (ASHIFT:GPI -@@ -2158,6 +2361,18 @@ +@@ -2158,6 +2404,18 @@ (set_attr "mode" "")] ) @@ -15228,7 +21213,7 @@ ;; ------------------------------------------------------------------- ;; Store-flag and conditional select insns -@@ -2211,7 +2426,7 @@ +@@ -2211,7 +2469,7 @@ (set_attr "mode" "SI")] ) @@ -15237,7 +21222,7 @@ [(set (match_operand:ALLI 0 "register_operand" "=r") (neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)])))] -@@ -2434,6 +2649,69 @@ +@@ -2434,6 +2692,69 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "SI")]) @@ -15307,7 +21292,87 @@ (define_insn "*_3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI -@@ -2704,6 +2982,62 @@ +@@ -2485,6 +2806,35 @@ + [(set_attr "v8type" "logic") + (set_attr "mode" "")]) + ++(define_insn "*and_one_cmpl3_compare0" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (and:GPI (not:GPI ++ (match_operand:GPI 1 "register_operand" "r")) ++ (match_operand:GPI 2 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:GPI 0 "register_operand" "=r") ++ (and:GPI (not:GPI (match_dup 1)) (match_dup 2)))] ++ "" ++ "bics\\t%0, %2, %1" ++ [(set_attr "v8type" "logics") ++ (set_attr "mode" "")]) ++ ++;; zero_extend version of above ++(define_insn "*and_one_cmplsi3_compare0_uxtw" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (and:SI (not:SI ++ (match_operand:SI 1 "register_operand" "r")) ++ (match_operand:SI 2 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI (and:SI (not:SI (match_dup 1)) (match_dup 2))))] ++ "" ++ "bics\\t%w0, %w2, %w1" ++ [(set_attr "v8type" "logics") ++ (set_attr "mode" "SI")]) ++ + (define_insn "*_one_cmpl_3" + [(set (match_operand:GPI 0 "register_operand" "=r") + (LOGICAL:GPI (not:GPI +@@ -2497,6 +2847,43 @@ + [(set_attr "v8type" "logic_shift") + (set_attr "mode" "")]) + ++(define_insn "*and_one_cmpl_3_compare0" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (and:GPI (not:GPI ++ (SHIFT:GPI ++ (match_operand:GPI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_shift_imm_" "n"))) ++ (match_operand:GPI 3 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:GPI 0 "register_operand" "=r") ++ (and:GPI (not:GPI ++ (SHIFT:GPI ++ (match_dup 1) (match_dup 2))) (match_dup 3)))] ++ "" ++ "bics\\t%0, %3, %1, %2" ++ [(set_attr "v8type" "logics_shift") ++ (set_attr "mode" "")]) ++ ++;; zero_extend version of above ++(define_insn "*and_one_cmpl_si3_compare0_uxtw" ++ [(set (reg:CC_NZ CC_REGNUM) ++ (compare:CC_NZ ++ (and:SI (not:SI ++ (SHIFT:SI ++ (match_operand:SI 1 "register_operand" "r") ++ (match_operand:QI 2 "aarch64_shift_imm_si" "n"))) ++ (match_operand:SI 3 "register_operand" "r")) ++ (const_int 0))) ++ (set (match_operand:DI 0 "register_operand" "=r") ++ (zero_extend:DI (and:SI ++ (not:SI ++ (SHIFT:SI (match_dup 1) (match_dup 2))) (match_dup 3))))] ++ "" ++ "bics\\t%w0, %w3, %w1, %2" ++ [(set_attr "v8type" "logics_shift") ++ (set_attr "mode" "SI")]) ++ + (define_insn "clz2" + [(set (match_operand:GPI 0 "register_operand" "=r") + (clz:GPI (match_operand:GPI 1 "register_operand" "r")))] +@@ -2704,6 +3091,62 @@ (set_attr "mode" "")] ) @@ -15370,7 +21435,7 @@ (define_insn "*_ashl" [(set (match_operand:GPI 0 "register_operand" "=r") (ANY_EXTEND:GPI -@@ -2770,6 +3104,50 @@ +@@ -2770,6 +3213,65 @@ (set_attr "mode" "")] ) @@ -15418,10 +21483,25 @@ + (set_attr "mode" "")] +) + ++(define_insn "*extr_insv_lower_reg" ++ [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") ++ (match_operand 1 "const_int_operand" "n") ++ (const_int 0)) ++ (zero_extract:GPI (match_operand:GPI 2 "register_operand" "+r") ++ (match_dup 1) ++ (match_operand 3 "const_int_operand" "n")))] ++ "!(UINTVAL (operands[1]) == 0 ++ || (UINTVAL (operands[3]) + UINTVAL (operands[1]) ++ > GET_MODE_BITSIZE (mode)))" ++ "bfxil\\t%0, %2, %3, %1" ++ [(set_attr "v8type" "bfm") ++ (set_attr "mode" "")] ++) ++ (define_insn "*_shft_" [(set (match_operand:GPI 0 "register_operand" "=r") (ashift:GPI (ANY_EXTEND:GPI -@@ -3090,6 +3468,27 @@ +@@ -3090,6 +3592,27 @@ (set_attr "mode" "")] ) @@ -15449,6 +21529,77 @@ ;; ------------------------------------------------------------------- ;; Reload support ;; ------------------------------------------------------------------- +@@ -3146,9 +3669,9 @@ + ;; after or during reload as we don't want these patterns to start + ;; kicking in during the combiner. + +-(define_insn "aarch64_movdi_tilow" ++(define_insn "aarch64_movdi_low" + [(set (match_operand:DI 0 "register_operand" "=r") +- (truncate:DI (match_operand:TI 1 "register_operand" "w")))] ++ (truncate:DI (match_operand:TX 1 "register_operand" "w")))] + "reload_completed || reload_in_progress" + "fmov\\t%x0, %d1" + [(set_attr "v8type" "fmovf2i") +@@ -3156,10 +3679,10 @@ + (set_attr "length" "4") + ]) + +-(define_insn "aarch64_movdi_tihigh" ++(define_insn "aarch64_movdi_high" + [(set (match_operand:DI 0 "register_operand" "=r") + (truncate:DI +- (lshiftrt:TI (match_operand:TI 1 "register_operand" "w") ++ (lshiftrt:TX (match_operand:TX 1 "register_operand" "w") + (const_int 64))))] + "reload_completed || reload_in_progress" + "fmov\\t%x0, %1.d[1]" +@@ -3168,24 +3691,22 @@ + (set_attr "length" "4") + ]) + +-(define_insn "aarch64_movtihigh_di" +- [(set (zero_extract:TI (match_operand:TI 0 "register_operand" "+w") ++(define_insn "aarch64_movhigh_di" ++ [(set (zero_extract:TX (match_operand:TX 0 "register_operand" "+w") + (const_int 64) (const_int 64)) +- (zero_extend:TI (match_operand:DI 1 "register_operand" "r")))] ++ (zero_extend:TX (match_operand:DI 1 "register_operand" "r")))] + "reload_completed || reload_in_progress" + "fmov\\t%0.d[1], %x1" +- + [(set_attr "v8type" "fmovi2f") + (set_attr "mode" "DI") + (set_attr "length" "4") + ]) + +-(define_insn "aarch64_movtilow_di" +- [(set (match_operand:TI 0 "register_operand" "=w") +- (zero_extend:TI (match_operand:DI 1 "register_operand" "r")))] ++(define_insn "aarch64_movlow_di" ++ [(set (match_operand:TX 0 "register_operand" "=w") ++ (zero_extend:TX (match_operand:DI 1 "register_operand" "r")))] + "reload_completed || reload_in_progress" + "fmov\\t%d0, %x1" +- + [(set_attr "v8type" "fmovi2f") + (set_attr "mode" "DI") + (set_attr "length" "4") +@@ -3197,7 +3718,6 @@ + (truncate:DI (match_operand:TI 1 "register_operand" "w"))))] + "reload_completed || reload_in_progress" + "fmov\\t%d0, %d1" +- + [(set_attr "v8type" "fmovi2f") + (set_attr "mode" "DI") + (set_attr "length" "4") +--- a/src/gcc/config/aarch64/aarch64-option-extensions.def ++++ b/src/gcc/config/aarch64/aarch64-option-extensions.def +@@ -35,3 +35,4 @@ + AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, AARCH64_FL_FPSIMD | AARCH64_FL_CRYPTO) + AARCH64_OPT_EXTENSION("simd", AARCH64_FL_FPSIMD, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO) + AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO | AARCH64_FL_FPSIMD, AARCH64_FL_CRYPTO) ++AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, AARCH64_FL_CRC) --- a/src/gcc/config/aarch64/aarch64-builtins.c +++ b/src/gcc/config/aarch64/aarch64-builtins.c @@ -30,6 +30,7 @@ @@ -15780,7 +21931,7 @@ }; char namebuf[60]; tree ftype = NULL; -@@ -1258,30 +1227,82 @@ +@@ -1259,30 +1228,82 @@ && in_mode == N##Fmode && in_n == C) case BUILT_IN_FLOOR: case BUILT_IN_FLOORF: @@ -15870,7 +22021,7 @@ default: return NULL_TREE; } -@@ -1289,5 +1310,160 @@ +@@ -1290,5 +1311,160 @@ return NULL_TREE; } @@ -15888,7 +22039,7 @@ + + switch (fcode) + { -+ BUILTIN_VDQF (UNOP, abs, 2) ++ BUILTIN_VALLDI (UNOP, abs, 2) + return fold_build1 (ABS_EXPR, type, args[0]); + break; + BUILTIN_VALLDI (BINOP, cmge, 0) @@ -16033,7 +22184,21 @@ + --- a/src/gcc/config/aarch64/aarch64-protos.h +++ b/src/gcc/config/aarch64/aarch64-protos.h -@@ -81,6 +81,7 @@ +@@ -68,6 +68,13 @@ + Each of of these represents a thread-local symbol, and corresponds to the + thread local storage relocation operator for the symbol being referred to. + ++ SYMBOL_TINY_ABSOLUTE ++ ++ Generate symbol accesses as a PC relative address using a single ++ instruction. To compute the address of symbol foo, we generate: ++ ++ ADR x0, foo ++ + SYMBOL_FORCE_TO_MEM : Global variables are addressed using + constant pool. All variable addresses are spilled into constant + pools. The constant pools themselves are addressed using PC +@@ -81,6 +88,7 @@ SYMBOL_SMALL_TLSDESC, SYMBOL_SMALL_GOTTPREL, SYMBOL_SMALL_TPREL, @@ -16041,7 +22206,46 @@ SYMBOL_FORCE_TO_MEM }; -@@ -140,18 +141,26 @@ +@@ -126,35 +134,66 @@ + const int FP2FP; + }; + ++/* Cost for vector insn classes. */ ++struct cpu_vector_cost ++{ ++ const int scalar_stmt_cost; /* Cost of any scalar operation, ++ excluding load and store. */ ++ const int scalar_load_cost; /* Cost of scalar load. */ ++ const int scalar_store_cost; /* Cost of scalar store. */ ++ const int vec_stmt_cost; /* Cost of any vector operation, ++ excluding load, store, ++ vector-to-scalar and ++ scalar-to-vector operation. */ ++ const int vec_to_scalar_cost; /* Cost of vec-to-scalar operation. */ ++ const int scalar_to_vec_cost; /* Cost of scalar-to-vector ++ operation. */ ++ const int vec_align_load_cost; /* Cost of aligned vector load. */ ++ const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ ++ const int vec_unalign_store_cost; /* Cost of unaligned vector store. */ ++ const int vec_store_cost; /* Cost of vector store. */ ++ const int cond_taken_branch_cost; /* Cost of taken branch. */ ++ const int cond_not_taken_branch_cost; /* Cost of not taken branch. */ ++}; ++ + struct tune_params + { + const struct cpu_rtx_cost_table *const insn_extra_cost; + const struct cpu_addrcost_table *const addr_cost; + const struct cpu_regmove_cost *const regmove_cost; ++ const struct cpu_vector_cost *const vec_costs; + const int memmov_cost; + }; + + HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned); + bool aarch64_bitmask_imm (HOST_WIDE_INT val, enum machine_mode); ++enum aarch64_symbol_type ++aarch64_classify_symbolic_expression (rtx, enum aarch64_symbol_context); + bool aarch64_constant_address_p (rtx); bool aarch64_float_const_zero_rtx_p (rtx); bool aarch64_function_arg_regno_p (unsigned); bool aarch64_gen_movmemqi (rtx *); @@ -16066,9 +22270,22 @@ +bool aarch64_simd_valid_immediate (rtx, enum machine_mode, bool, + struct simd_immediate_info *); bool aarch64_symbolic_address_p (rtx); - bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context, - enum aarch64_symbol_type *); -@@ -177,6 +186,7 @@ +-bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context, +- enum aarch64_symbol_type *); + bool aarch64_uimm12_shift (HOST_WIDE_INT); + const char *aarch64_output_casesi (rtx *); + enum aarch64_symbol_type aarch64_classify_symbol (rtx, +@@ -165,9 +204,6 @@ + int aarch64_hard_regno_mode_ok (unsigned, enum machine_mode); + int aarch64_hard_regno_nregs (unsigned, enum machine_mode); + int aarch64_simd_attr_length_move (rtx); +-int aarch64_simd_immediate_valid_for_move (rtx, enum machine_mode, rtx *, +- int *, unsigned char *, int *, +- int *); + int aarch64_uxt_size (int, HOST_WIDE_INT); + rtx aarch64_final_eh_return_addr (void); + rtx aarch64_legitimize_reload_address (rtx *, enum machine_mode, int, int, int); +@@ -177,6 +213,7 @@ bool aarch64_simd_mem_operand_p (rtx); rtx aarch64_simd_vect_par_cnst_half (enum machine_mode, bool); rtx aarch64_tls_get_addr (void); @@ -16076,16 +22293,18 @@ unsigned aarch64_dbx_register_number (unsigned); unsigned aarch64_trampoline_size (void); void aarch64_asm_output_labelref (FILE *, const char *); -@@ -216,6 +226,8 @@ +@@ -216,6 +253,10 @@ bool aarch64_split_128bit_move_p (rtx, rtx); ++void aarch64_split_simd_combine (rtx, rtx, rtx); ++ +void aarch64_split_simd_move (rtx, rtx); + /* Check for a legitimate floating point constant for FMOV. */ bool aarch64_float_const_representable_p (rtx); -@@ -249,6 +261,4 @@ +@@ -249,6 +290,4 @@ extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); extern bool aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); @@ -16094,7 +22313,7 @@ #endif /* GCC_AARCH64_PROTOS_H */ --- a/src/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def -@@ -18,241 +18,339 @@ +@@ -18,248 +18,344 @@ along with GCC; see the file COPYING3. If not see . */ @@ -16149,10 +22368,6 @@ + 10 - CODE_FOR_. */ + + BUILTIN_VD_RE (CREATE, create, 0) -+ BUILTIN_VQ_S (GETLANE, get_lane_signed, 0) -+ BUILTIN_VDQ (GETLANE, get_lane_unsigned, 0) -+ BUILTIN_VDQF (GETLANE, get_lane, 0) -+ VAR1 (GETLANE, get_lane, 0, di) + BUILTIN_VDC (COMBINE, combine, 0) + BUILTIN_VB (BINOP, pmul, 0) + BUILTIN_VDQF (UNOP, sqrt, 2) @@ -16160,6 +22375,9 @@ + VAR1 (UNOP, addp, 0, di) + VAR1 (UNOP, clz, 2, v4si) + ++ BUILTIN_VALL (GETLANE, get_lane, 0) ++ VAR1 (GETLANE, get_lane, 0, di) ++ + BUILTIN_VD_RE (REINTERP, reinterpretdi, 0) + BUILTIN_VDC (REINTERP, reinterpretv8qi, 0) + BUILTIN_VDC (REINTERP, reinterpretv4hi, 0) @@ -16173,7 +22391,6 @@ + BUILTIN_VQ (REINTERP, reinterpretv2df, 0) + + BUILTIN_VDQ_I (BINOP, dup_lane, 0) -+ BUILTIN_VDQ_I (BINOP, dup_lane_scalar, 0) /* Implemented by aarch64_qshl. */ - BUILTIN_VSDQ_I (BINOP, sqshl) - BUILTIN_VSDQ_I (BINOP, uqshl) @@ -16607,7 +22824,7 @@ + BUILTIN_VALL (BINOP, uzp2, 0) + BUILTIN_VALL (BINOP, trn1, 0) + BUILTIN_VALL (BINOP, trn2, 0) -+ + + /* Implemented by + aarch64_frecp. */ + BUILTIN_GPF (UNOP, frecpe, 0) @@ -16617,13 +22834,22 @@ + BUILTIN_VDQF (UNOP, frecpe, 0) + BUILTIN_VDQF (BINOP, frecps, 0) + -+ BUILTIN_VDQF (UNOP, abs, 2) ++ BUILTIN_VALLDI (UNOP, abs, 2) + + VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf) + VAR1 (BINOP, float_truncate_hi_, 0, v4sf) + + VAR1 (UNOP, float_extend_lo_, 0, v2df) + VAR1 (UNOP, float_truncate_lo_, 0, v2sf) ++ + /* Implemented by aarch64_ld1. */ +- BUILTIN_VALL (LOAD1, ld1) ++ BUILTIN_VALL (LOAD1, ld1, 0) + + /* Implemented by aarch64_st1. */ +- BUILTIN_VALL (STORE1, st1) ++ BUILTIN_VALL (STORE1, st1, 0) + --- a/src/gcc/config/aarch64/constraints.md +++ b/src/gcc/config/aarch64/constraints.md @@ -75,11 +75,6 @@ @@ -16669,7 +22895,16 @@ A constraint that matches vector of immediates for left shifts." --- a/src/gcc/config/aarch64/aarch64.c +++ b/src/gcc/config/aarch64/aarch64.c -@@ -87,6 +87,14 @@ +@@ -45,6 +45,8 @@ + #include "gimple.h" + #include "optabs.h" + #include "dwarf2.h" ++#include "cfgloop.h" ++#include "tree-vectorizer.h" + + /* Classifies an address. + +@@ -87,6 +89,15 @@ enum aarch64_symbol_type symbol_type; }; @@ -16679,12 +22914,13 @@ + int shift; + int element_width; + bool mvn; ++ bool msl; +}; + /* The current code model. */ enum aarch64_code_model aarch64_cmodel; -@@ -103,8 +111,6 @@ +@@ -103,8 +114,6 @@ static void aarch64_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; static void aarch64_override_options_after_change (void); @@ -16693,7 +22929,43 @@ static bool aarch64_vector_mode_supported_p (enum machine_mode); static unsigned bit_count (unsigned HOST_WIDE_INT); static bool aarch64_const_vec_all_same_int_p (rtx, -@@ -524,13 +530,15 @@ +@@ -178,14 +187,35 @@ + NAMED_PARAM (FP2FP, 4) + }; + ++/* Generic costs for vector insn classes. */ + #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 + __extension__ + #endif ++static const struct cpu_vector_cost generic_vector_cost = ++{ ++ NAMED_PARAM (scalar_stmt_cost, 1), ++ NAMED_PARAM (scalar_load_cost, 1), ++ NAMED_PARAM (scalar_store_cost, 1), ++ NAMED_PARAM (vec_stmt_cost, 1), ++ NAMED_PARAM (vec_to_scalar_cost, 1), ++ NAMED_PARAM (scalar_to_vec_cost, 1), ++ NAMED_PARAM (vec_align_load_cost, 1), ++ NAMED_PARAM (vec_unalign_load_cost, 1), ++ NAMED_PARAM (vec_unalign_store_cost, 1), ++ NAMED_PARAM (vec_store_cost, 1), ++ NAMED_PARAM (cond_taken_branch_cost, 3), ++ NAMED_PARAM (cond_not_taken_branch_cost, 1) ++}; ++ ++#if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 ++__extension__ ++#endif + static const struct tune_params generic_tunings = + { + &generic_rtx_cost_table, + &generic_addrcost_table, + &generic_regmove_cost, ++ &generic_vector_cost, + NAMED_PARAM (memmov_cost, 4) + }; + +@@ -524,13 +554,15 @@ return; } @@ -16712,10 +22984,168 @@ emit_move_insn (tmp_reg, gen_rtx_HIGH (Pmode, imm)); emit_insn (gen_ldr_got_small (dest, tmp_reg, imm)); return; -@@ -656,6 +664,47 @@ +@@ -604,49 +636,85 @@ + { + rtx low_dst; + +- gcc_assert (GET_MODE (dst) == TImode); ++ enum machine_mode src_mode = GET_MODE (src); ++ enum machine_mode dst_mode = GET_MODE (dst); ++ int src_regno = REGNO (src); ++ int dst_regno = REGNO (dst); + ++ gcc_assert (dst_mode == TImode || dst_mode == TFmode); ++ + if (REG_P (dst) && REG_P (src)) + { +- int src_regno = REGNO (src); +- int dst_regno = REGNO (dst); ++ gcc_assert (src_mode == TImode || src_mode == TFmode); + +- gcc_assert (GET_MODE (src) == TImode); +- + /* Handle r -> w, w -> r. */ + if (FP_REGNUM_P (dst_regno) && GP_REGNUM_P (src_regno)) + { +- emit_insn (gen_aarch64_movtilow_di (dst, +- gen_lowpart (word_mode, src))); +- emit_insn (gen_aarch64_movtihigh_di (dst, +- gen_highpart (word_mode, src))); +- return; ++ switch (src_mode) { ++ case TImode: ++ emit_insn ++ (gen_aarch64_movtilow_di (dst, gen_lowpart (word_mode, src))); ++ emit_insn ++ (gen_aarch64_movtihigh_di (dst, gen_highpart (word_mode, src))); ++ return; ++ case TFmode: ++ emit_insn ++ (gen_aarch64_movtflow_di (dst, gen_lowpart (word_mode, src))); ++ emit_insn ++ (gen_aarch64_movtfhigh_di (dst, gen_highpart (word_mode, src))); ++ return; ++ default: ++ gcc_unreachable (); ++ } + } + else if (GP_REGNUM_P (dst_regno) && FP_REGNUM_P (src_regno)) + { +- emit_insn (gen_aarch64_movdi_tilow (gen_lowpart (word_mode, dst), +- src)); +- emit_insn (gen_aarch64_movdi_tihigh (gen_highpart (word_mode, dst), +- src)); +- return; ++ switch (src_mode) { ++ case TImode: ++ emit_insn ++ (gen_aarch64_movdi_tilow (gen_lowpart (word_mode, dst), src)); ++ emit_insn ++ (gen_aarch64_movdi_tihigh (gen_highpart (word_mode, dst), src)); ++ return; ++ case TFmode: ++ emit_insn ++ (gen_aarch64_movdi_tflow (gen_lowpart (word_mode, dst), src)); ++ emit_insn ++ (gen_aarch64_movdi_tfhigh (gen_highpart (word_mode, dst), src)); ++ return; ++ default: ++ gcc_unreachable (); ++ } + } + /* Fall through to r -> r cases. */ + } + +- low_dst = gen_lowpart (word_mode, dst); +- if (REG_P (low_dst) +- && reg_overlap_mentioned_p (low_dst, src)) +- { +- aarch64_emit_move (gen_highpart (word_mode, dst), +- gen_highpart_mode (word_mode, TImode, src)); +- aarch64_emit_move (low_dst, gen_lowpart (word_mode, src)); +- } +- else +- { +- aarch64_emit_move (low_dst, gen_lowpart (word_mode, src)); +- aarch64_emit_move (gen_highpart (word_mode, dst), +- gen_highpart_mode (word_mode, TImode, src)); +- } ++ switch (dst_mode) { ++ case TImode: ++ low_dst = gen_lowpart (word_mode, dst); ++ if (REG_P (low_dst) ++ && reg_overlap_mentioned_p (low_dst, src)) ++ { ++ aarch64_emit_move (gen_highpart (word_mode, dst), ++ gen_highpart_mode (word_mode, TImode, src)); ++ aarch64_emit_move (low_dst, gen_lowpart (word_mode, src)); ++ } ++ else ++ { ++ aarch64_emit_move (low_dst, gen_lowpart (word_mode, src)); ++ aarch64_emit_move (gen_highpart (word_mode, dst), ++ gen_highpart_mode (word_mode, TImode, src)); ++ } ++ return; ++ case TFmode: ++ emit_move_insn (gen_rtx_REG (DFmode, dst_regno), ++ gen_rtx_REG (DFmode, src_regno)); ++ emit_move_insn (gen_rtx_REG (DFmode, dst_regno + 1), ++ gen_rtx_REG (DFmode, src_regno + 1)); ++ return; ++ default: ++ gcc_unreachable (); ++ } + } + + bool +@@ -656,11 +724,99 @@ || ! (FP_REGNUM_P (REGNO (dst)) && FP_REGNUM_P (REGNO (src)))); } ++/* Split a complex SIMD combine. */ ++ ++void ++aarch64_split_simd_combine (rtx dst, rtx src1, rtx src2) ++{ ++ enum machine_mode src_mode = GET_MODE (src1); ++ enum machine_mode dst_mode = GET_MODE (dst); ++ ++ gcc_assert (VECTOR_MODE_P (dst_mode)); ++ ++ if (REG_P (dst) && REG_P (src1) && REG_P (src2)) ++ { ++ rtx (*gen) (rtx, rtx, rtx); ++ ++ switch (src_mode) ++ { ++ case V8QImode: ++ gen = gen_aarch64_simd_combinev8qi; ++ break; ++ case V4HImode: ++ gen = gen_aarch64_simd_combinev4hi; ++ break; ++ case V2SImode: ++ gen = gen_aarch64_simd_combinev2si; ++ break; ++ case V2SFmode: ++ gen = gen_aarch64_simd_combinev2sf; ++ break; ++ case DImode: ++ gen = gen_aarch64_simd_combinedi; ++ break; ++ case DFmode: ++ gen = gen_aarch64_simd_combinedf; ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ emit_insn (gen (dst, src1, src2)); ++ return; ++ } ++} ++ +/* Split a complex SIMD move. */ + +void @@ -16728,39 +23158,88 @@ + + if (REG_P (dst) && REG_P (src)) + { ++ rtx (*gen) (rtx, rtx); ++ + gcc_assert (VECTOR_MODE_P (src_mode)); + + switch (src_mode) + { + case V16QImode: -+ emit_insn (gen_aarch64_simd_movv16qi (dst, src)); ++ gen = gen_aarch64_split_simd_movv16qi; + break; + case V8HImode: -+ emit_insn (gen_aarch64_simd_movv8hi (dst, src)); ++ gen = gen_aarch64_split_simd_movv8hi; + break; + case V4SImode: -+ emit_insn (gen_aarch64_simd_movv4si (dst, src)); ++ gen = gen_aarch64_split_simd_movv4si; + break; + case V2DImode: -+ emit_insn (gen_aarch64_simd_movv2di (dst, src)); ++ gen = gen_aarch64_split_simd_movv2di; + break; + case V4SFmode: -+ emit_insn (gen_aarch64_simd_movv4sf (dst, src)); ++ gen = gen_aarch64_split_simd_movv4sf; + break; + case V2DFmode: -+ emit_insn (gen_aarch64_simd_movv2df (dst, src)); ++ gen = gen_aarch64_split_simd_movv2df; + break; + default: + gcc_unreachable (); + } ++ ++ emit_insn (gen (dst, src)); + return; + } +} + static rtx - aarch64_force_temporary (rtx x, rtx value) +-aarch64_force_temporary (rtx x, rtx value) ++aarch64_force_temporary (enum machine_mode mode, rtx x, rtx value) { -@@ -745,6 +794,7 @@ + if (can_create_pseudo_p ()) +- return force_reg (Pmode, value); ++ return force_reg (mode, value); + else + { + x = aarch64_emit_move (x, value); +@@ -672,15 +828,16 @@ + static rtx + aarch64_add_offset (enum machine_mode mode, rtx temp, rtx reg, HOST_WIDE_INT offset) + { +- if (!aarch64_plus_immediate (GEN_INT (offset), DImode)) ++ if (!aarch64_plus_immediate (GEN_INT (offset), mode)) + { + rtx high; + /* Load the full offset into a register. This + might be improvable in the future. */ + high = GEN_INT (offset); + offset = 0; +- high = aarch64_force_temporary (temp, high); +- reg = aarch64_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); ++ high = aarch64_force_temporary (mode, temp, high); ++ reg = aarch64_force_temporary (mode, temp, ++ gen_rtx_PLUS (mode, high, reg)); + } + return plus_constant (mode, reg, offset); + } +@@ -719,7 +876,7 @@ + && targetm.cannot_force_const_mem (mode, imm)) + { + gcc_assert(can_create_pseudo_p ()); +- base = aarch64_force_temporary (dest, base); ++ base = aarch64_force_temporary (mode, dest, base); + base = aarch64_add_offset (mode, NULL, base, INTVAL (offset)); + aarch64_emit_move (dest, base); + return; +@@ -736,7 +893,7 @@ + if (offset != const0_rtx) + { + gcc_assert(can_create_pseudo_p ()); +- base = aarch64_force_temporary (dest, base); ++ base = aarch64_force_temporary (mode, dest, base); + base = aarch64_add_offset (mode, NULL, base, INTVAL (offset)); + aarch64_emit_move (dest, base); + return; +@@ -745,6 +902,7 @@ case SYMBOL_SMALL_TPREL: case SYMBOL_SMALL_ABSOLUTE: @@ -16768,17 +23247,89 @@ aarch64_load_symref_appropriately (dest, imm, sty); return; -@@ -3087,7 +3137,8 @@ +@@ -2553,12 +2711,14 @@ + aarch64_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) + { + rtx base, offset; ++ + if (GET_CODE (x) == HIGH) + return true; + + split_const (x, &base, &offset); + if (GET_CODE (base) == SYMBOL_REF || GET_CODE (base) == LABEL_REF) +- return (aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR) != SYMBOL_FORCE_TO_MEM); ++ return (aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR) ++ != SYMBOL_FORCE_TO_MEM); + + return aarch64_tls_referenced_p (x); + } +@@ -2996,10 +3156,13 @@ + + /* Classify the base of symbolic expression X, given that X appears in + context CONTEXT. */ +-static enum aarch64_symbol_type +-aarch64_classify_symbolic_expression (rtx x, enum aarch64_symbol_context context) ++ ++enum aarch64_symbol_type ++aarch64_classify_symbolic_expression (rtx x, ++ enum aarch64_symbol_context context) + { + rtx offset; ++ + split_const (x, &x, &offset); + return aarch64_classify_symbol (x, context); + } +@@ -3087,17 +3250,19 @@ if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) && y == const0_rtx && (code == EQ || code == NE || code == LT || code == GE) - && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS || GET_CODE (x) == AND)) + && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS || GET_CODE (x) == AND + || GET_CODE (x) == NEG)) - return CC_NZmode; + return CC_NZmode; + +- /* A compare with a shifted operand. Because of canonicalization, ++ /* A compare with a shifted or negated operand. Because of canonicalization, + the comparison will have to be swapped when we emit the assembly + code. */ + if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) + && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG) + && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT + || GET_CODE (x) == LSHIFTRT +- || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)) ++ || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND ++ || GET_CODE (x) == NEG)) + return CC_SWPmode; + + /* A compare of a mode narrower than SI mode against zero can be done +@@ -3282,26 +3447,6 @@ + asm_fprintf (f, "%s", reg_names [REGNO (x) + 1]); + break; + +- case 'Q': +- /* Print the least significant register of a pair (TImode) of regs. */ +- if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1)) +- { +- output_operand_lossage ("invalid operand for '%%%c'", code); +- return; +- } +- asm_fprintf (f, "%s", reg_names [REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)]); +- break; +- +- case 'R': +- /* Print the most significant register of a pair (TImode) of regs. */ +- if (GET_CODE (x) != REG || !GP_REGNUM_P (REGNO (x) + 1)) +- { +- output_operand_lossage ("invalid operand for '%%%c'", code); +- return; +- } +- asm_fprintf (f, "%s", reg_names [REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)]); +- break; +- + case 'm': + /* Print a condition (eq, ne, etc). */ - /* A compare with a shifted operand. Because of canonicalization, -@@ -3349,7 +3400,7 @@ +@@ -3349,7 +3494,7 @@ output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code); return; } @@ -16787,7 +23338,7 @@ break; case 'S': -@@ -3362,18 +3413,17 @@ +@@ -3362,18 +3507,17 @@ output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code); return; } @@ -16809,7 +23360,7 @@ break; case 'w': -@@ -3383,20 +3433,19 @@ +@@ -3383,20 +3527,19 @@ if (x == const0_rtx || (CONST_DOUBLE_P (x) && aarch64_float_const_zero_rtx_p (x))) { @@ -16833,7 +23384,123 @@ break; } -@@ -4956,6 +5005,7 @@ +@@ -3647,13 +3790,6 @@ + output_addr_const (f, x); + } + +-void +-aarch64_function_profiler (FILE *f ATTRIBUTE_UNUSED, +- int labelno ATTRIBUTE_UNUSED) +-{ +- sorry ("function profiling"); +-} +- + bool + aarch64_label_mentioned_p (rtx x) + { +@@ -4601,6 +4737,101 @@ + return aarch64_tune_params->memmov_cost; + } + ++/* Vectorizer cost model target hooks. */ ++ ++/* Implement targetm.vectorize.builtin_vectorization_cost. */ ++static int ++aarch64_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, ++ tree vectype, ++ int misalign ATTRIBUTE_UNUSED) ++{ ++ unsigned elements; ++ ++ switch (type_of_cost) ++ { ++ case scalar_stmt: ++ return aarch64_tune_params->vec_costs->scalar_stmt_cost; ++ ++ case scalar_load: ++ return aarch64_tune_params->vec_costs->scalar_load_cost; ++ ++ case scalar_store: ++ return aarch64_tune_params->vec_costs->scalar_store_cost; ++ ++ case vector_stmt: ++ return aarch64_tune_params->vec_costs->vec_stmt_cost; ++ ++ case vector_load: ++ return aarch64_tune_params->vec_costs->vec_align_load_cost; ++ ++ case vector_store: ++ return aarch64_tune_params->vec_costs->vec_store_cost; ++ ++ case vec_to_scalar: ++ return aarch64_tune_params->vec_costs->vec_to_scalar_cost; ++ ++ case scalar_to_vec: ++ return aarch64_tune_params->vec_costs->scalar_to_vec_cost; ++ ++ case unaligned_load: ++ return aarch64_tune_params->vec_costs->vec_unalign_load_cost; ++ ++ case unaligned_store: ++ return aarch64_tune_params->vec_costs->vec_unalign_store_cost; ++ ++ case cond_branch_taken: ++ return aarch64_tune_params->vec_costs->cond_taken_branch_cost; ++ ++ case cond_branch_not_taken: ++ return aarch64_tune_params->vec_costs->cond_not_taken_branch_cost; ++ ++ case vec_perm: ++ case vec_promote_demote: ++ return aarch64_tune_params->vec_costs->vec_stmt_cost; ++ ++ case vec_construct: ++ elements = TYPE_VECTOR_SUBPARTS (vectype); ++ return elements / 2 + 1; ++ ++ default: ++ gcc_unreachable (); ++ } ++} ++ ++/* Implement targetm.vectorize.add_stmt_cost. */ ++static unsigned ++aarch64_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind, ++ struct _stmt_vec_info *stmt_info, int misalign, ++ enum vect_cost_model_location where) ++{ ++ unsigned *cost = (unsigned *) data; ++ unsigned retval = 0; ++ ++ if (flag_vect_cost_model) ++ { ++ tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE; ++ int stmt_cost = ++ aarch64_builtin_vectorization_cost (kind, vectype, misalign); ++ ++ /* Statements in an inner loop relative to the loop being ++ vectorized are weighted more heavily. The value here is ++ a function (linear for now) of the loop nest level. */ ++ if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info)) ++ { ++ loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_info); ++ struct loop *loop = LOOP_VINFO_LOOP (loop_info); ++ unsigned nest_level = loop_depth (loop); ++ ++ count *= nest_level; ++ } ++ ++ retval = (unsigned) (count * stmt_cost); ++ cost[where] += retval; ++ } ++ ++ return retval; ++} ++ + static void initialize_aarch64_code_model (void); + + /* Parse the architecture extension string. */ +@@ -4956,6 +5187,7 @@ /* Return the method that should be used to access SYMBOL_REF or LABEL_REF X in context CONTEXT. */ @@ -16841,7 +23508,7 @@ enum aarch64_symbol_type aarch64_classify_symbol (rtx x, enum aarch64_symbol_context context ATTRIBUTE_UNUSED) -@@ -4969,6 +5019,8 @@ +@@ -4969,6 +5201,8 @@ case AARCH64_CMODEL_TINY_PIC: case AARCH64_CMODEL_TINY: @@ -16850,7 +23517,7 @@ case AARCH64_CMODEL_SMALL_PIC: case AARCH64_CMODEL_SMALL: return SYMBOL_SMALL_ABSOLUTE; -@@ -4978,48 +5030,42 @@ +@@ -4978,71 +5212,47 @@ } } @@ -16924,7 +23591,30 @@ /* By default push everything into the constant pool. */ return SYMBOL_FORCE_TO_MEM; } -@@ -5092,8 +5138,7 @@ + +-/* Return true if X is a symbolic constant that can be used in context +- CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ +- + bool +-aarch64_symbolic_constant_p (rtx x, enum aarch64_symbol_context context, +- enum aarch64_symbol_type *symbol_type) +-{ +- rtx offset; +- split_const (x, &x, &offset); +- if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) +- *symbol_type = aarch64_classify_symbol (x, context); +- else +- return false; +- +- /* No checking of offset at this point. */ +- return true; +-} +- +-bool + aarch64_constant_address_p (rtx x) + { + return (CONSTANT_P (x) && memory_address_p (DImode, x)); +@@ -5092,8 +5302,7 @@ /* This could probably go away because we now decompose CONST_INTs according to expand_mov_immediate. */ if ((GET_CODE (x) == CONST_VECTOR @@ -16934,7 +23624,7 @@ || CONST_INT_P (x) || aarch64_valid_floating_const (mode, x)) return !targetm.cannot_force_const_mem (mode, x); -@@ -5924,32 +5969,57 @@ +@@ -5924,32 +6133,57 @@ return false; } @@ -17012,7 +23702,7 @@ /* Return the bitmask of possible vector sizes for the vectorizer to iterate over. */ static unsigned int -@@ -6037,7 +6107,7 @@ +@@ -6037,7 +6271,7 @@ } /* Return the equivalent letter for size. */ @@ -17021,7 +23711,7 @@ sizetochar (int size) { switch (size) -@@ -6084,15 +6154,10 @@ +@@ -6084,15 +6318,10 @@ return aarch64_float_const_representable_p (x0); } @@ -17041,7 +23731,7 @@ { #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \ matches = 1; \ -@@ -6103,7 +6168,6 @@ +@@ -6103,7 +6332,6 @@ { \ immtype = (CLASS); \ elsize = (ELSIZE); \ @@ -17049,7 +23739,7 @@ eshift = (SHIFT); \ emvn = (NEG); \ break; \ -@@ -6112,36 +6176,25 @@ +@@ -6112,36 +6340,25 @@ unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); unsigned char bytes[16]; @@ -17097,11 +23787,39 @@ } /* Splat vector constant out into a byte vector. */ -@@ -6239,23 +6292,14 @@ - if (immtype == -1 - || (immtype >= 12 && immtype <= 15) - || immtype == 18) +@@ -6215,16 +6432,16 @@ + CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1], 8, 1); + + CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] +- && bytes[i + 2] == 0 && bytes[i + 3] == 0, 0, 0); ++ && bytes[i + 2] == 0 && bytes[i + 3] == 0, 8, 0); + + CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] +- && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 0, 1); ++ && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 8, 1); + + CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff +- && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 0, 0); ++ && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 16, 0); + + CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 +- && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 0, 1); ++ && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 16, 1); + + CHECK (1, 8, 16, bytes[i] == bytes[0], 0, 0); + +@@ -6233,31 +6450,20 @@ + } + while (0); + +- /* TODO: Currently the assembler cannot handle types 12 to 15. +- And there is no way to specify cmode through the compiler. +- Disable them till there is support in the assembler. */ +- if (immtype == -1 +- || (immtype >= 12 && immtype <= 15) +- || immtype == 18) - return -1; ++ if (immtype == -1) + return false; + if (info) @@ -17112,10 +23830,13 @@ - if (elementwidth) - *elementwidth = elsize; -- ++ unsigned HOST_WIDE_INT imm = 0; + - if (elementchar) - *elementchar = elchar; -- ++ if (immtype >= 12 && immtype <= 15) ++ info->msl = true; + - if (mvn) - *mvn = emvn; - @@ -17124,10 +23845,12 @@ - - if (modconst) - { - unsigned HOST_WIDE_INT imm = 0; - +- unsigned HOST_WIDE_INT imm = 0; +- /* Un-invert bytes of recognized vector, if necessary. */ -@@ -6272,68 +6316,27 @@ + if (invmask != 0) + for (i = 0; i < idx; i++) +@@ -6272,68 +6478,27 @@ imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) << (i * BITS_PER_UNIT); @@ -17208,7 +23931,7 @@ static bool aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT minval, -@@ -6395,6 +6398,25 @@ +@@ -6395,6 +6560,25 @@ return true; } @@ -17234,7 +23957,7 @@ /* Return a const_int vector of VAL. */ rtx aarch64_simd_gen_const_vector_dup (enum machine_mode mode, int val) -@@ -6409,6 +6431,19 @@ +@@ -6409,6 +6593,19 @@ return gen_rtx_CONST_VECTOR (mode, v); } @@ -17254,7 +23977,7 @@ /* Construct and return a PARALLEL RTX vector. */ rtx aarch64_simd_vect_par_cnst_half (enum machine_mode mode, bool high) -@@ -6634,8 +6669,7 @@ +@@ -6634,8 +6831,7 @@ gcc_unreachable (); if (const_vec != NULL_RTX @@ -17264,7 +23987,7 @@ /* Load using MOVI/MVNI. */ return const_vec; else if ((const_dup = aarch64_simd_dup_constant (vals)) != NULL_RTX) -@@ -7193,49 +7227,78 @@ +@@ -7193,49 +7389,80 @@ } char* @@ -17280,6 +24003,7 @@ static char templ[40]; - int shift = 0, mvn = 0; const char *mnemonic; ++ const char *shift_op; unsigned int lane_count = 0; + char element_char; @@ -17287,7 +24011,7 @@ - aarch64_simd_immediate_valid_for_move (*const_vector, mode, - const_vector, &lane_width_bits, - &widthc, &mvn, &shift); -+ struct simd_immediate_info info; ++ struct simd_immediate_info info = { NULL_RTX, 0, 0, false, false }; + + /* This will return true to show const_vector is legal for use as either + a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will @@ -17331,6 +24055,7 @@ - gcc_assert (lane_width_bits != 0); - lane_count = width / lane_width_bits; + mnemonic = info.mvn ? "mvni" : "movi"; ++ shift_op = info.msl ? "msl" : "lsl"; if (lane_count == 1) - snprintf (templ, sizeof (templ), "%s\t%%d0, %%1", mnemonic); @@ -17341,8 +24066,8 @@ + mnemonic, UINTVAL (info.value)); + else if (info.shift) + snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX -+ ", lsl %d", mnemonic, lane_count, element_char, -+ UINTVAL (info.value), info.shift); ++ ", %s %d", mnemonic, lane_count, element_char, ++ UINTVAL (info.value), shift_op, info.shift); else - snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, %%1", - mnemonic, lane_count, widthc); @@ -17366,7 +24091,7 @@ /* Split operands into moves from op[1] + op[2] into op[0]. */ void -@@ -7860,6 +7923,9 @@ +@@ -7860,6 +8087,9 @@ #undef TARGET_EXPAND_BUILTIN_VA_START #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start @@ -17376,7 +24101,7 @@ #undef TARGET_FUNCTION_ARG #define TARGET_FUNCTION_ARG aarch64_function_arg -@@ -7881,6 +7947,9 @@ +@@ -7881,6 +8111,9 @@ #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required @@ -17386,6 +24111,20 @@ #undef TARGET_GIMPLIFY_VA_ARG_EXPR #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr +@@ -7960,6 +8193,13 @@ + #undef TARGET_ARRAY_MODE_SUPPORTED_P + #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p + ++#undef TARGET_VECTORIZE_ADD_STMT_COST ++#define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost ++ ++#undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST ++#define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \ ++ aarch64_builtin_vectorization_cost ++ + #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE + #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode + --- a/src/gcc/config/aarch64/iterators.md +++ b/src/gcc/config/aarch64/iterators.md @@ -83,6 +83,12 @@ @@ -17401,7 +24140,23 @@ ;; Vector Float modes with 2 elements. (define_mode_iterator V2F [V2SF V2DF]) -@@ -160,10 +166,15 @@ +@@ -122,9 +128,15 @@ + ;; Vector modes except double int. + (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) + ++;; Vector modes for Q and H types. ++(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) ++ + ;; Vector modes for H and S types. + (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) + ++;; Vector modes for Q, H and S types. ++(define_mode_iterator VDQQHS [V8QI V16QI V4HI V8HI V2SI V4SI]) ++ + ;; Vector and scalar integer modes for H and S + (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) + +@@ -160,10 +172,15 @@ [ UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. @@ -17418,7 +24173,7 @@ UNSPEC_SMAXV ; Used in aarch64-simd.md. UNSPEC_SMINV ; Used in aarch64-simd.md. UNSPEC_UMAXV ; Used in aarch64-simd.md. -@@ -213,13 +224,6 @@ +@@ -213,13 +230,6 @@ UNSPEC_URSHL ; Used in aarch64-simd.md. UNSPEC_SQRSHL ; Used in aarch64-simd.md. UNSPEC_UQRSHL ; Used in aarch64-simd.md. @@ -17432,7 +24187,7 @@ UNSPEC_SSLI ; Used in aarch64-simd.md. UNSPEC_USLI ; Used in aarch64-simd.md. UNSPEC_SSRI ; Used in aarch64-simd.md. -@@ -227,10 +231,6 @@ +@@ -227,10 +237,6 @@ UNSPEC_SSHLL ; Used in aarch64-simd.md. UNSPEC_USHLL ; Used in aarch64-simd.md. UNSPEC_ADDP ; Used in aarch64-simd.md. @@ -17443,7 +24198,7 @@ UNSPEC_TBL ; Used in vector permute patterns. UNSPEC_CONCAT ; Used in vector permute patterns. UNSPEC_ZIP1 ; Used in vector permute patterns. -@@ -249,8 +249,12 @@ +@@ -249,8 +255,12 @@ ;; 32-bit version and "%x0" in the 64-bit version. (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) @@ -17456,7 +24211,7 @@ (V8QI "") (V16QI "") (V4HI "") (V8HI "") (V2SI "") (V4SI "") -@@ -305,7 +309,8 @@ +@@ -305,7 +315,8 @@ (V4SF ".4s") (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") @@ -17466,7 +24221,33 @@ ;; Register suffix narrowed modes for VQN. (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") -@@ -444,7 +449,8 @@ +@@ -380,7 +391,8 @@ + ;; Double modes of vector modes (lower case). + (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") + (V2SI "v4si") (V2SF "v4sf") +- (SI "v2si") (DI "v2di")]) ++ (SI "v2si") (DI "v2di") ++ (DF "v2df")]) + + ;; Narrowed modes for VDN. + (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") +@@ -435,6 +447,15 @@ + (V2SF "s") (V4SF "s") + (V2DF "d")]) + ++;; Corresponding core element mode for each vector mode. This is a ++;; variation on mapping FP modes to GP regs. ++(define_mode_attr vwcore [(V8QI "w") (V16QI "w") ++ (V4HI "w") (V8HI "w") ++ (V2SI "w") (V4SI "w") ++ (DI "x") (V2DI "x") ++ (V2SF "w") (V4SF "w") ++ (V2DF "x")]) ++ + ;; Double vector types for ALLX. + (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) + +@@ -444,7 +465,8 @@ (V2SI "V2SI") (V4SI "V4SI") (DI "DI") (V2DI "V2DI") (V2SF "V2SI") (V4SF "V4SI") @@ -17476,7 +24257,7 @@ ;; Lower case mode of results of comparison operations. (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") -@@ -452,7 +458,8 @@ +@@ -452,7 +474,8 @@ (V2SI "v2si") (V4SI "v4si") (DI "di") (V2DI "v2di") (V2SF "v2si") (V4SF "v4si") @@ -17486,7 +24267,7 @@ ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") -@@ -528,9 +535,14 @@ +@@ -528,9 +551,14 @@ ;; Iterator for integer conversions (define_code_iterator FIXUORS [fix unsigned_fix]) @@ -17501,7 +24282,7 @@ ;; Code iterator for variants of vector max and min. (define_code_iterator ADDSUB [plus minus]) -@@ -543,6 +555,15 @@ +@@ -543,6 +571,15 @@ ;; Code iterator for signed variants of vector saturating binary ops. (define_code_iterator SBINQOPS [ss_plus ss_minus]) @@ -17517,7 +24298,7 @@ ;; ------------------------------------------------------------------- ;; Code Attributes ;; ------------------------------------------------------------------- -@@ -555,6 +576,10 @@ +@@ -555,6 +592,10 @@ (zero_extend "zero_extend") (sign_extract "extv") (zero_extract "extzv") @@ -17528,7 +24309,7 @@ (and "and") (ior "ior") (xor "xor") -@@ -571,12 +596,37 @@ +@@ -571,12 +612,37 @@ (eq "eq") (ne "ne") (lt "lt") @@ -17567,7 +24348,7 @@ (ss_plus "s") (us_plus "u") (ss_minus "s") (us_minus "u")]) -@@ -601,7 +651,9 @@ +@@ -601,7 +667,9 @@ (define_code_attr su [(sign_extend "s") (zero_extend "u") (sign_extract "s") (zero_extract "u") (fix "s") (unsigned_fix "u") @@ -17578,7 +24359,7 @@ ;; Emit cbz/cbnz depending on comparison type. (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) -@@ -610,10 +662,10 @@ +@@ -610,10 +678,10 @@ (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) ;; Max/min attributes. @@ -17593,171 +24374,1633 @@ ;; MLA/MLS attributes. (define_code_attr as [(ss_plus "a") (ss_minus "s")]) -@@ -635,8 +687,11 @@ +@@ -635,8 +703,11 @@ (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV UNSPEC_SMAXV UNSPEC_SMINV]) --(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV]) -+(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV -+ UNSPEC_FMAXNMV UNSPEC_FMINNMV]) +-(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV]) ++(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV ++ UNSPEC_FMAXNMV UNSPEC_FMINNMV]) + ++(define_int_iterator SUADDV [UNSPEC_SADDV UNSPEC_UADDV]) ++ + (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD + UNSPEC_SRHADD UNSPEC_URHADD + UNSPEC_SHSUB UNSPEC_UHSUB +@@ -649,7 +720,7 @@ + (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 + UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) + +-(define_int_iterator FMAXMIN [UNSPEC_FMAX UNSPEC_FMIN]) ++(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN]) + + (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) + +@@ -680,35 +751,44 @@ + UNSPEC_SQSHRN UNSPEC_UQSHRN + UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) + +-(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT +- UNSPEC_CMLE UNSPEC_CMLT]) +- +-(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST]) +- + (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 + UNSPEC_TRN1 UNSPEC_TRN2 + UNSPEC_UZP1 UNSPEC_UZP2]) + + (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM +- UNSPEC_FRINTI UNSPEC_FRINTX UNSPEC_FRINTA]) ++ UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX ++ UNSPEC_FRINTA]) + + (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM +- UNSPEC_FRINTA]) ++ UNSPEC_FRINTA UNSPEC_FRINTN]) + ++(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) ++ + ;; ------------------------------------------------------------------- + ;; Int Iterators Attributes. + ;; ------------------------------------------------------------------- +-(define_int_attr maxminv [(UNSPEC_UMAXV "umax") +- (UNSPEC_UMINV "umin") +- (UNSPEC_SMAXV "smax") +- (UNSPEC_SMINV "smin")]) ++(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") ++ (UNSPEC_UMINV "umin") ++ (UNSPEC_SMAXV "smax") ++ (UNSPEC_SMINV "smin") ++ (UNSPEC_FMAX "smax_nan") ++ (UNSPEC_FMAXNMV "smax") ++ (UNSPEC_FMAXV "smax_nan") ++ (UNSPEC_FMIN "smin_nan") ++ (UNSPEC_FMINNMV "smin") ++ (UNSPEC_FMINV "smin_nan")]) + +-(define_int_attr fmaxminv [(UNSPEC_FMAXV "max") +- (UNSPEC_FMINV "min")]) ++(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") ++ (UNSPEC_UMINV "umin") ++ (UNSPEC_SMAXV "smax") ++ (UNSPEC_SMINV "smin") ++ (UNSPEC_FMAX "fmax") ++ (UNSPEC_FMAXNMV "fmaxnm") ++ (UNSPEC_FMAXV "fmax") ++ (UNSPEC_FMIN "fmin") ++ (UNSPEC_FMINNMV "fminnm") ++ (UNSPEC_FMINV "fmin")]) + +-(define_int_attr fmaxmin [(UNSPEC_FMAX "fmax") +- (UNSPEC_FMIN "fmin")]) +- + (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") + (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") + (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") +@@ -719,6 +799,7 @@ + (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") + (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") + (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") ++ (UNSPEC_SADDV "s") (UNSPEC_UADDV "u") + (UNSPEC_SSLI "s") (UNSPEC_USLI "u") + (UNSPEC_SSRI "s") (UNSPEC_USRI "u") + (UNSPEC_USRA "u") (UNSPEC_SSRA "s") +@@ -768,12 +849,6 @@ + (UNSPEC_RADDHN2 "add") + (UNSPEC_RSUBHN2 "sub")]) + +-(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt") +- (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt") +- (UNSPEC_CMEQ "eq") +- (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi") +- (UNSPEC_CMTST "tst")]) +- + (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") + (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) + +@@ -783,15 +858,18 @@ + (UNSPEC_FRINTM "floor") + (UNSPEC_FRINTI "nearbyint") + (UNSPEC_FRINTX "rint") +- (UNSPEC_FRINTA "round")]) ++ (UNSPEC_FRINTA "round") ++ (UNSPEC_FRINTN "frintn")]) + + ;; frint suffix for floating-point rounding instructions. + (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") + (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") +- (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")]) ++ (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") ++ (UNSPEC_FRINTN "n")]) + + (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") +- (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")]) ++ (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") ++ (UNSPEC_FRINTN "frintn")]) + + (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") + (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") +@@ -800,3 +878,5 @@ + (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") + (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") + (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) ++ ++(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) +--- a/src/gcc/config/aarch64/aarch64.h ++++ b/src/gcc/config/aarch64/aarch64.h +@@ -151,6 +151,7 @@ + #define AARCH64_FL_FP (1 << 1) /* Has FP. */ + #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ + #define AARCH64_FL_SLOWMUL (1 << 3) /* A slow multiply core. */ ++#define AARCH64_FL_CRC (1 << 4) /* Has CRC. */ + + /* Has FP and SIMD. */ + #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) +@@ -163,6 +164,7 @@ + + /* Macros to test ISA flags. */ + extern unsigned long aarch64_isa_flags; ++#define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) + #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) + #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) + #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) +@@ -521,12 +523,6 @@ + #endif + + +-/* Which ABI to use. */ +-enum arm_abi_type +-{ +- ARM_ABI_AAPCS64 +-}; +- + enum arm_pcs + { + ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ +@@ -534,11 +530,7 @@ + }; + + +-extern enum arm_abi_type arm_abi; + extern enum arm_pcs arm_pcs_variant; +-#ifndef ARM_DEFAULT_ABI +-#define ARM_DEFAULT_ABI ARM_ABI_AAPCS64 +-#endif + + #ifndef ARM_DEFAULT_PCS + #define ARM_DEFAULT_PCS ARM_PCS_AAPCS64 +@@ -709,6 +701,8 @@ + + #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) + ++#define REVERSIBLE_CC_MODE(MODE) 1 ++ + #define REVERSE_CONDITION(CODE, MODE) \ + (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ + ? reverse_condition_maybe_unordered (CODE) \ +@@ -758,9 +752,23 @@ + #define PRINT_OPERAND_ADDRESS(STREAM, X) \ + aarch64_print_operand_address (STREAM, X) + +-#define FUNCTION_PROFILER(STREAM, LABELNO) \ +- aarch64_function_profiler (STREAM, LABELNO) ++#define MCOUNT_NAME "_mcount" + ++#define NO_PROFILE_COUNTERS 1 ++ ++/* Emit rtl for profiling. Output assembler code to FILE ++ to call "_mcount" for profiling a function entry. */ ++#define PROFILE_HOOK(LABEL) \ ++{ \ ++ rtx fun,lr; \ ++ lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ ++ fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ ++ emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ ++} ++ ++/* All the work done in PROFILE_HOOK, but still required. */ ++#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) ++ + /* For some reason, the Linux headers think they know how to define + these macros. They don't!!! */ + #undef ASM_APP_ON +--- a/src/gcc/config/arm/arm1020e.md ++++ b/src/gcc/config/arm/arm1020e.md +@@ -66,13 +66,14 @@ + ;; ALU operations with no shifted operand + (define_insn_reservation "1020alu_op" 1 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "type" "alu_reg,simple_alu_imm")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg")) + "1020a_e,1020a_m,1020a_w") + + ;; ALU operations with a shift-by-constant operand + (define_insn_reservation "1020alu_shift_op" 1 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "type" "simple_alu_shift,alu_shift")) ++ (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift")) + "1020a_e,1020a_m,1020a_w") + + ;; ALU operations with a shift-by-register operand +@@ -81,7 +82,7 @@ + ;; the execute stage. + (define_insn_reservation "1020alu_shift_reg_op" 2 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "type" "alu_shift_reg")) ++ (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) + "1020a_e*2,1020a_m,1020a_w") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +@@ -96,7 +97,7 @@ + ;; until after the memory stage. + (define_insn_reservation "1020mult1" 2 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "insn" "smulxy,smulwy")) ++ (eq_attr "type" "smulxy,smulwy")) + "1020a_e,1020a_m,1020a_w") + + ;; The "smlaxy" and "smlawx" instructions require two iterations through +@@ -104,7 +105,7 @@ + ;; the execute stage. + (define_insn_reservation "1020mult2" 2 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "insn" "smlaxy,smlalxy,smlawx")) ++ (eq_attr "type" "smlaxy,smlalxy,smlawx")) + "1020a_e*2,1020a_m,1020a_w") + + ;; The "smlalxy", "mul", and "mla" instructions require two iterations +@@ -112,7 +113,7 @@ + ;; the memory stage. + (define_insn_reservation "1020mult3" 3 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "insn" "smlalxy,mul,mla")) ++ (eq_attr "type" "smlalxy,mul,mla")) + "1020a_e*2,1020a_m,1020a_w") + + ;; The "muls" and "mlas" instructions loop in the execute stage for +@@ -120,7 +121,7 @@ + ;; available after three iterations. + (define_insn_reservation "1020mult4" 3 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "insn" "muls,mlas")) ++ (eq_attr "type" "muls,mlas")) + "1020a_e*4,1020a_m,1020a_w") + + ;; Long multiply instructions that produce two registers of +@@ -135,7 +136,7 @@ + ;; available after the memory cycle. + (define_insn_reservation "1020mult5" 4 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "insn" "umull,umlal,smull,smlal")) ++ (eq_attr "type" "umull,umlal,smull,smlal")) + "1020a_e*3,1020a_m,1020a_w") + + ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in +@@ -143,7 +144,7 @@ + ;; The value result is available after four iterations. + (define_insn_reservation "1020mult6" 4 + (and (eq_attr "tune" "arm1020e,arm1022e") +- (eq_attr "insn" "umulls,umlals,smulls,smlals")) ++ (eq_attr "type" "umulls,umlals,smulls,smlals")) + "1020a_e*5,1020a_m,1020a_w") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/cortex-a15.md ++++ b/src/gcc/config/arm/cortex-a15.md +@@ -61,14 +61,16 @@ + ;; Simple ALU without shift + (define_insn_reservation "cortex_a15_alu" 2 + (and (eq_attr "tune" "cortexa15") +- (and (eq_attr "type" "alu_reg,simple_alu_imm") ++ (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,\ ++ mvn_imm,mvn_reg") + (eq_attr "neon_type" "none"))) + "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") + + ;; ALU ops with immediate shift + (define_insn_reservation "cortex_a15_alu_shift" 3 + (and (eq_attr "tune" "cortexa15") +- (and (eq_attr "type" "simple_alu_shift,alu_shift") ++ (and (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift") + (eq_attr "neon_type" "none"))) + "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\ + |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)") +@@ -76,7 +78,7 @@ + ;; ALU ops with register controlled shift + (define_insn_reservation "cortex_a15_alu_shift_reg" 3 + (and (eq_attr "tune" "cortexa15") +- (and (eq_attr "type" "alu_shift_reg") ++ (and (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg") + (eq_attr "neon_type" "none"))) + "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\ + |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\ +@@ -87,28 +89,26 @@ + ;; 32-bit multiplies + (define_insn_reservation "cortex_a15_mult32" 3 + (and (eq_attr "tune" "cortexa15") +- (and (eq_attr "type" "mult") +- (and (eq_attr "neon_type" "none") +- (eq_attr "mul64" "no")))) ++ (and (eq_attr "mul32" "yes") ++ (eq_attr "neon_type" "none"))) + "ca15_issue1,ca15_mx") + + ;; 64-bit multiplies + (define_insn_reservation "cortex_a15_mult64" 4 + (and (eq_attr "tune" "cortexa15") +- (and (eq_attr "type" "mult") +- (and (eq_attr "neon_type" "none") +- (eq_attr "mul64" "yes")))) ++ (and (eq_attr "mul64" "yes") ++ (eq_attr "neon_type" "none"))) + "ca15_issue1,ca15_mx*2") + + ;; Integer divide + (define_insn_reservation "cortex_a15_udiv" 9 + (and (eq_attr "tune" "cortexa15") +- (eq_attr "insn" "udiv")) ++ (eq_attr "type" "udiv")) + "ca15_issue1,ca15_mx") + + (define_insn_reservation "cortex_a15_sdiv" 10 + (and (eq_attr "tune" "cortexa15") +- (eq_attr "insn" "sdiv")) ++ (eq_attr "type" "sdiv")) + "ca15_issue1,ca15_mx") + + ;; Block all issue pipes for a cycle +--- a/src/gcc/config/arm/arm-tables.opt ++++ b/src/gcc/config/arm/arm-tables.opt +@@ -250,6 +250,9 @@ + Enum(processor_type) String(cortex-a15) Value(cortexa15) + + EnumValue ++Enum(processor_type) String(cortex-a53) Value(cortexa53) ++ ++EnumValue + Enum(processor_type) String(cortex-r4) Value(cortexr4) + + EnumValue +@@ -259,6 +262,9 @@ + Enum(processor_type) String(cortex-r5) Value(cortexr5) + + EnumValue ++Enum(processor_type) String(cortex-r7) Value(cortexr7) ++ ++EnumValue + Enum(processor_type) String(cortex-m4) Value(cortexm4) + + EnumValue +--- a/src/gcc/config/arm/arm1026ejs.md ++++ b/src/gcc/config/arm/arm1026ejs.md +@@ -66,13 +66,14 @@ + ;; ALU operations with no shifted operand + (define_insn_reservation "alu_op" 1 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "type" "alu_reg,simple_alu_imm")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg")) + "a_e,a_m,a_w") + + ;; ALU operations with a shift-by-constant operand + (define_insn_reservation "alu_shift_op" 1 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "type" "simple_alu_shift,alu_shift")) ++ (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift")) + "a_e,a_m,a_w") + + ;; ALU operations with a shift-by-register operand +@@ -81,7 +82,7 @@ + ;; the execute stage. + (define_insn_reservation "alu_shift_reg_op" 2 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "type" "alu_shift_reg")) ++ (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) + "a_e*2,a_m,a_w") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +@@ -96,7 +97,7 @@ + ;; until after the memory stage. + (define_insn_reservation "mult1" 2 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "insn" "smulxy,smulwy")) ++ (eq_attr "type" "smulxy,smulwy")) + "a_e,a_m,a_w") + + ;; The "smlaxy" and "smlawx" instructions require two iterations through +@@ -104,7 +105,7 @@ + ;; the execute stage. + (define_insn_reservation "mult2" 2 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "insn" "smlaxy,smlalxy,smlawx")) ++ (eq_attr "type" "smlaxy,smlalxy,smlawx")) + "a_e*2,a_m,a_w") + + ;; The "smlalxy", "mul", and "mla" instructions require two iterations +@@ -112,7 +113,7 @@ + ;; the memory stage. + (define_insn_reservation "mult3" 3 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "insn" "smlalxy,mul,mla")) ++ (eq_attr "type" "smlalxy,mul,mla")) + "a_e*2,a_m,a_w") + + ;; The "muls" and "mlas" instructions loop in the execute stage for +@@ -120,7 +121,7 @@ + ;; available after three iterations. + (define_insn_reservation "mult4" 3 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "insn" "muls,mlas")) ++ (eq_attr "type" "muls,mlas")) + "a_e*4,a_m,a_w") + + ;; Long multiply instructions that produce two registers of +@@ -135,7 +136,7 @@ + ;; available after the memory cycle. + (define_insn_reservation "mult5" 4 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "insn" "umull,umlal,smull,smlal")) ++ (eq_attr "type" "umull,umlal,smull,smlal")) + "a_e*3,a_m,a_w") + + ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in +@@ -143,7 +144,7 @@ + ;; The value result is available after four iterations. + (define_insn_reservation "mult6" 4 + (and (eq_attr "tune" "arm1026ejs") +- (eq_attr "insn" "umulls,umlals,smulls,smlals")) ++ (eq_attr "type" "umulls,umlals,smulls,smlals")) + "a_e*5,a_m,a_w") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/linux-elf.h ++++ b/src/gcc/config/arm/linux-elf.h +@@ -44,9 +44,9 @@ + + #define SUBTARGET_EXTRA_LINK_SPEC " -m " TARGET_LINKER_EMULATION " -p" + ++/* We do not have any MULTILIB_OPTIONS specified, so there are no ++ MULTILIB_DEFAULTS. */ + #undef MULTILIB_DEFAULTS +-#define MULTILIB_DEFAULTS \ +- { "marm", "mlittle-endian", "mfloat-abi=hard", "mno-thumb-interwork" } + + /* Now we define the strings used to build the spec file. */ + #undef LIB_SPEC +--- a/src/gcc/config/arm/arm1136jfs.md ++++ b/src/gcc/config/arm/arm1136jfs.md +@@ -75,13 +75,14 @@ + ;; ALU operations with no shifted operand + (define_insn_reservation "11_alu_op" 2 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "type" "alu_reg,simple_alu_imm")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg")) + "e_1,e_2,e_3,e_wb") + + ;; ALU operations with a shift-by-constant operand + (define_insn_reservation "11_alu_shift_op" 2 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "type" "simple_alu_shift,alu_shift")) ++ (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift")) + "e_1,e_2,e_3,e_wb") + + ;; ALU operations with a shift-by-register operand +@@ -90,7 +91,7 @@ + ;; the shift stage. + (define_insn_reservation "11_alu_shift_reg_op" 3 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "type" "alu_shift_reg")) ++ (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) + "e_1*2,e_2,e_3,e_wb") + + ;; alu_ops can start sooner, if there is no shifter dependency +@@ -129,13 +130,13 @@ + ;; Multiply and multiply-accumulate results are available after four stages. + (define_insn_reservation "11_mult1" 4 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "insn" "mul,mla")) ++ (eq_attr "type" "mul,mla")) + "e_1*2,e_2,e_3,e_wb") + + ;; The *S variants set the condition flags, which requires three more cycles. + (define_insn_reservation "11_mult2" 4 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "insn" "muls,mlas")) ++ (eq_attr "type" "muls,mlas")) + "e_1*2,e_2,e_3,e_wb") + + (define_bypass 3 "11_mult1,11_mult2" +@@ -160,13 +161,13 @@ + ;; the two multiply-accumulate instructions. + (define_insn_reservation "11_mult3" 5 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "insn" "smull,umull,smlal,umlal")) ++ (eq_attr "type" "smull,umull,smlal,umlal")) + "e_1*3,e_2,e_3,e_wb*2") + + ;; The *S variants set the condition flags, which requires three more cycles. + (define_insn_reservation "11_mult4" 5 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "insn" "smulls,umulls,smlals,umlals")) ++ (eq_attr "type" "smulls,umulls,smlals,umlals")) + "e_1*3,e_2,e_3,e_wb*2") + + (define_bypass 4 "11_mult3,11_mult4" +@@ -190,7 +191,8 @@ + ;; cycles. + (define_insn_reservation "11_mult5" 3 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "insn" "smulxy,smlaxy,smulwy,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx")) ++ (eq_attr "type" "smulxy,smlaxy,smulwy,smlawy,smuad,smuadx,smlad,smladx,\ ++ smusd,smusdx,smlsd,smlsdx")) + "e_1,e_2,e_3,e_wb") + + (define_bypass 2 "11_mult5" +@@ -211,14 +213,14 @@ + ;; The same idea, then the 32-bit result is added to a 64-bit quantity. + (define_insn_reservation "11_mult6" 4 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "insn" "smlalxy")) ++ (eq_attr "type" "smlalxy")) + "e_1*2,e_2,e_3,e_wb*2") + + ;; Signed 32x32 multiply, then the most significant 32 bits are extracted + ;; and are available after the memory stage. + (define_insn_reservation "11_mult7" 4 + (and (eq_attr "tune" "arm1136js,arm1136jfs") +- (eq_attr "insn" "smmul,smmulr")) ++ (eq_attr "type" "smmul,smmulr")) + "e_1*2,e_2,e_3,e_wb") + + (define_bypass 3 "11_mult6,11_mult7" +--- a/src/gcc/config/arm/marvell-pj4.md ++++ b/src/gcc/config/arm/marvell-pj4.md +@@ -41,64 +41,68 @@ + + (define_insn_reservation "pj4_alu_e1" 1 + (and (eq_attr "tune" "marvell_pj4") +- (eq_attr "type" "simple_alu_imm,alu_reg") +- (not (eq_attr "conds" "set")) +- (eq_attr "insn" "mov,mvn")) ++ (eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg") ++ (not (eq_attr "conds" "set"))) + "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") + + (define_insn_reservation "pj4_alu_e1_conds" 4 + (and (eq_attr "tune" "marvell_pj4") +- (eq_attr "type" "simple_alu_imm,alu_reg") +- (eq_attr "conds" "set") +- (eq_attr "insn" "mov,mvn")) ++ (eq_attr "type" "mov_imm,mov_reg,mvn_imm,mvn_reg") ++ (eq_attr "conds" "set")) + "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") + + (define_insn_reservation "pj4_alu" 1 + (and (eq_attr "tune" "marvell_pj4") +- (eq_attr "type" "simple_alu_imm,alu_reg") +- (not (eq_attr "conds" "set")) +- (not (eq_attr "insn" "mov,mvn"))) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") ++ (not (eq_attr "conds" "set"))) + "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") + + (define_insn_reservation "pj4_alu_conds" 4 + (and (eq_attr "tune" "marvell_pj4") +- (eq_attr "type" "simple_alu_imm,alu_reg") +- (eq_attr "conds" "set") +- (not (eq_attr "insn" "mov,mvn"))) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") ++ (eq_attr "conds" "set")) + "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") + + (define_insn_reservation "pj4_shift" 1 + (and (eq_attr "tune" "marvell_pj4") +- (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift") ++ (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ ++ mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg") + (not (eq_attr "conds" "set")) + (eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") + + (define_insn_reservation "pj4_shift_conds" 4 + (and (eq_attr "tune" "marvell_pj4") +- (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift") ++ (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ ++ mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg") + (eq_attr "conds" "set") + (eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") + + (define_insn_reservation "pj4_alu_shift" 1 + (and (eq_attr "tune" "marvell_pj4") + (not (eq_attr "conds" "set")) +- (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")) ++ (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ ++ mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")) + "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)") + + (define_insn_reservation "pj4_alu_shift_conds" 4 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "conds" "set") +- (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")) ++ (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\ ++ mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")) + "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)") + + (define_bypass 2 "pj4_alu_shift,pj4_shift" + "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp") + + (define_insn_reservation "pj4_ir_mul" 3 +- (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "mult")) "pj4_is,pj4_mul,nothing*2,pj4_cp") ++ (and (eq_attr "tune" "marvell_pj4") ++ (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes"))) ++ "pj4_is,pj4_mul,nothing*2,pj4_cp") + + (define_insn_reservation "pj4_ir_div" 20 +- (and (eq_attr "tune" "marvell_pj4") (eq_attr "insn" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp") ++ (and (eq_attr "tune" "marvell_pj4") ++ (eq_attr "type" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp") + + ;; Branches and calls. + +--- a/src/gcc/config/arm/thumb2.md ++++ b/src/gcc/config/arm/thumb2.md +@@ -60,105 +60,230 @@ + "TARGET_THUMB2" + "bic%?\\t%0, %1, %2%S4" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "shift" "2") +- (set_attr "type" "alu_shift")] ++ (set_attr "type" "arlo_shift")] + ) + +-(define_insn "*thumb2_smaxsi3" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") +- (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) ++;; We use the '0' constraint for operand 1 because reload should ++;; be smart enough to generate an appropriate move for the r/r/r case. ++(define_insn_and_split "*thumb2_smaxsi3" ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") ++ (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0") ++ (match_operand:SI 2 "arm_rhs_operand" "r,Py,I"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_THUMB2" +- "@ +- cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2 +- cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1 +- cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2" ++ "TARGET_THUMB2" ++ "#" ++ ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2 ++ "TARGET_THUMB2 && reload_completed" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) ++ (match_dup 2)))] ++ "" + [(set_attr "conds" "clob") +- (set_attr "length" "10,10,14")] ++ (set_attr "enabled_for_depr_it" "yes,yes,no") ++ (set_attr "length" "6,6,10")] + ) + +-(define_insn "*thumb2_sminsi3" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") +- (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) ++(define_insn_and_split "*thumb2_sminsi3" ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") ++ (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0") ++ (match_operand:SI 2 "arm_rhs_operand" "r,Py,I"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2" +- "@ +- cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2 +- cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1 +- cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2" ++ "#" ++ ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2 ++ "TARGET_THUMB2 && reload_completed" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) ++ (match_dup 2)))] ++ "" + [(set_attr "conds" "clob") +- (set_attr "length" "10,10,14")] ++ (set_attr "enabled_for_depr_it" "yes,yes,no") ++ (set_attr "length" "6,6,10")] + ) + +-(define_insn "*thumb32_umaxsi3" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") +- (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) +- (clobber (reg:CC CC_REGNUM))] ++(define_insn_and_split "*thumb32_umaxsi3" ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") ++ (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0") ++ (match_operand:SI 2 "arm_rhs_operand" "r,Py,I"))) ++ (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2" +- "@ +- cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2 +- cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1 +- cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2" ++ "#" ++ ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2 ++ "TARGET_THUMB2 && reload_completed" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) ++ (match_dup 2)))] ++ "" + [(set_attr "conds" "clob") +- (set_attr "length" "10,10,14")] ++ (set_attr "length" "6,6,10") ++ (set_attr "enabled_for_depr_it" "yes,yes,no")] + ) -+(define_int_iterator SUADDV [UNSPEC_SADDV UNSPEC_UADDV]) -+ - (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD - UNSPEC_SRHADD UNSPEC_URHADD - UNSPEC_SHSUB UNSPEC_UHSUB -@@ -649,7 +704,7 @@ - (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 - UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) +-(define_insn "*thumb2_uminsi3" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") +- (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) ++(define_insn_and_split "*thumb2_uminsi3" ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") ++ (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0") ++ (match_operand:SI 2 "arm_rhs_operand" "r,Py,I"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2" +- "@ +- cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2 +- cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1 +- cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2" ++ "#" ++ ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2 ++ "TARGET_THUMB2 && reload_completed" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) ++ (match_dup 2)))] ++ "" + [(set_attr "conds" "clob") +- (set_attr "length" "10,10,14")] ++ (set_attr "length" "6,6,10") ++ (set_attr "enabled_for_depr_it" "yes,yes,no")] + ) --(define_int_iterator FMAXMIN [UNSPEC_FMAX UNSPEC_FMIN]) -+(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN]) + ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands. +-(define_insn "*thumb2_negdi2" ++(define_insn_and_split "*thumb2_negdi2" + [(set (match_operand:DI 0 "s_register_operand" "=&r,r") + (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2" +- "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1" ++ "#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1 ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (const_int 0) (match_dup 1))) ++ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))]) ++ (set (match_dup 2) (minus:SI (minus:SI (match_dup 3) ++ (ashift:SI (match_dup 3) ++ (const_int 1))) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[3] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ } + [(set_attr "conds" "clob") + (set_attr "length" "8")] + ) - (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) +-(define_insn "*thumb2_abssi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r,&r") +- (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) ++(define_insn_and_split "*thumb2_abssi2" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r") ++ (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2" +- "@ +- cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0 +- eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31" +- [(set_attr "conds" "clob,*") ++ "#" ++ ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31 ++ ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0 ++ ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0 ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ if (REGNO(operands[0]) == REGNO(operands[1])) ++ { ++ rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); ++ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ cc_reg, ++ gen_rtx_COMPARE (CCmode, operands[0], const0_rtx))); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ (gen_rtx_LT (SImode, ++ cc_reg, ++ const0_rtx)), ++ (gen_rtx_SET (VOIDmode, ++ operands[0], ++ (gen_rtx_MINUS (SImode, ++ const0_rtx, ++ operands[1])))))); ++ } ++ else ++ { ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_XOR (SImode, ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31)), ++ operands[1]))); ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_MINUS (SImode, ++ operands[0], ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31))))); ++ } ++ DONE; ++ } ++ [(set_attr "conds" "*,clob,clob") + (set_attr "shift" "1") +- (set_attr "predicable" "no, yes") ++ (set_attr "predicable" "yes,no,no") ++ (set_attr "predicable_short_it" "no") ++ (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "ce_count" "2") +- (set_attr "length" "10,8")] ++ (set_attr "length" "8,6,10")] + ) -@@ -680,35 +735,44 @@ - UNSPEC_SQSHRN UNSPEC_UQSHRN - UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) +-(define_insn "*thumb2_neg_abssi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r,&r") +- (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))) ++(define_insn_and_split "*thumb2_neg_abssi2" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r") ++ (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2" +- "@ +- cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0 +- eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31" +- [(set_attr "conds" "clob,*") ++ "#" ++ ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31 ++ ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0 ++ ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0 ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ if (REGNO(operands[0]) == REGNO(operands[1])) ++ { ++ rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); ++ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ cc_reg, ++ gen_rtx_COMPARE (CCmode, operands[0], const0_rtx))); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ (gen_rtx_GT (SImode, ++ cc_reg, ++ const0_rtx)), ++ (gen_rtx_SET (VOIDmode, ++ operands[0], ++ (gen_rtx_MINUS (SImode, ++ const0_rtx, ++ operands[1])))))); ++ } ++ else ++ { ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_XOR (SImode, ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31)), ++ operands[1]))); ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_MINUS (SImode, ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31)), ++ operands[0]))); ++ } ++ DONE; ++ } ++ [(set_attr "conds" "*,clob,clob") + (set_attr "shift" "1") +- (set_attr "predicable" "no, yes") ++ (set_attr "predicable" "yes,no,no") ++ (set_attr "enabled_for_depr_it" "yes,yes,no") ++ (set_attr "predicable_short_it" "no") + (set_attr "ce_count" "2") +- (set_attr "length" "10,8")] ++ (set_attr "length" "8,6,10")] + ) --(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT -- UNSPEC_CMLE UNSPEC_CMLT]) -- --(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST]) -- - (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 - UNSPEC_TRN1 UNSPEC_TRN2 - UNSPEC_UZP1 UNSPEC_UZP2]) + ;; We have two alternatives here for memory loads (and similarly for stores) +@@ -167,8 +292,8 @@ + ;; regs. The high register alternatives are not taken into account when + ;; choosing register preferences in order to reflect their expense. + (define_insn "*thumb2_movsi_insn" +- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l ,*hk,m,*m") +- (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))] ++ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m") ++ (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk"))] + "TARGET_THUMB2 && ! TARGET_IWMMXT + && !(TARGET_HARD_FLOAT && TARGET_VFP) + && ( register_operand (operands[0], SImode) +@@ -176,16 +301,19 @@ + "@ + mov%?\\t%0, %1 + mov%?\\t%0, %1 ++ mov%?\\t%0, %1 + mvn%?\\t%0, #%B1 + movw%?\\t%0, %1 + ldr%?\\t%0, %1 + ldr%?\\t%0, %1 + str%?\\t%1, %0 + str%?\\t%1, %0" +- [(set_attr "type" "*,*,simple_alu_imm,*,load1,load1,store1,store1") ++ [(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,*,load1,load1,store1,store1") ++ (set_attr "length" "2,4,2,4,4,4,4,4,4") + (set_attr "predicable" "yes") +- (set_attr "pool_range" "*,*,*,*,1018,4094,*,*") +- (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")] ++ (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no") ++ (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*") ++ (set_attr "neg_pool_range" "*,*,*,*,*,0,0,*,*")] + ) + + (define_insn "tls_load_dot_plus_four" +@@ -223,6 +351,21 @@ + (set_attr "neg_pool_range" "*,*,*,250")] + ) + ++(define_insn "*thumb2_storewb_pairsi" ++ [(set (match_operand:SI 0 "register_operand" "=&kr") ++ (plus:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "const_int_operand" "n"))) ++ (set (mem:SI (plus:SI (match_dup 0) (match_dup 2))) ++ (match_operand:SI 3 "register_operand" "r")) ++ (set (mem:SI (plus:SI (match_dup 0) ++ (match_operand:SI 5 "const_int_operand" "n"))) ++ (match_operand:SI 4 "register_operand" "r"))] ++ "TARGET_THUMB2 ++ && INTVAL (operands[5]) == INTVAL (operands[2]) + 4" ++ "strd\\t%3, %4, [%0, %2]!" ++ [(set_attr "type" "store2")] ++) ++ + (define_insn "*thumb2_cmpsi_neg_shiftsi" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 0 "s_register_operand" "r") +@@ -233,57 +376,170 @@ + "cmn%?\\t%0, %1%S3" + [(set_attr "conds" "set") + (set_attr "shift" "1") +- (set_attr "type" "alu_shift")] ++ (set_attr "type" "arlo_shift")] + ) - (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM -- UNSPEC_FRINTI UNSPEC_FRINTX UNSPEC_FRINTA]) -+ UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX -+ UNSPEC_FRINTA]) +-(define_insn "*thumb2_mov_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") ++(define_insn_and_split "*thumb2_mov_scc" ++ [(set (match_operand:SI 0 "s_register_operand" "=l,r") + (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]))] + "TARGET_THUMB2" +- "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1" ++ "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1" ++ "TARGET_THUMB2" ++ [(set (match_dup 0) ++ (if_then_else:SI (match_dup 1) ++ (const_int 1) ++ (const_int 0)))] ++ "" + [(set_attr "conds" "use") +- (set_attr "length" "10")] ++ (set_attr "enabled_for_depr_it" "yes,no") ++ (set_attr "length" "8,10")] + ) - (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM -- UNSPEC_FRINTA]) -+ UNSPEC_FRINTA UNSPEC_FRINTN]) +-(define_insn "*thumb2_mov_negscc" ++(define_insn_and_split "*thumb2_mov_negscc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (neg:SI (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])))] ++ "TARGET_THUMB2 && !arm_restrict_it" ++ "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" + "TARGET_THUMB2" +- "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" ++ [(set (match_dup 0) ++ (if_then_else:SI (match_dup 1) ++ (match_dup 3) ++ (const_int 0)))] ++ { ++ operands[3] = GEN_INT (~0); ++ } + [(set_attr "conds" "use") + (set_attr "length" "10")] + ) -+(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) +-(define_insn "*thumb2_mov_notscc" ++(define_insn_and_split "*thumb2_mov_negscc_strict_it" ++ [(set (match_operand:SI 0 "low_register_operand" "=l") ++ (neg:SI (match_operator:SI 1 "arm_comparison_operator" ++ [(match_operand 2 "cc_register" "") (const_int 0)])))] ++ "TARGET_THUMB2 && arm_restrict_it" ++ "#" ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\" ++ "&& reload_completed" ++ [(set (match_dup 0) ++ (match_dup 3)) ++ (cond_exec (match_dup 4) ++ (set (match_dup 0) ++ (const_int 0)))] ++ { ++ operands[3] = GEN_INT (~0); ++ enum machine_mode mode = GET_MODE (operands[2]); ++ enum rtx_code rc = GET_CODE (operands[1]); + - ;; ------------------------------------------------------------------- - ;; Int Iterators Attributes. - ;; ------------------------------------------------------------------- --(define_int_attr maxminv [(UNSPEC_UMAXV "umax") -- (UNSPEC_UMINV "umin") -- (UNSPEC_SMAXV "smax") -- (UNSPEC_SMINV "smin")]) -+(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") -+ (UNSPEC_UMINV "umin") -+ (UNSPEC_SMAXV "smax") -+ (UNSPEC_SMINV "smin") -+ (UNSPEC_FMAX "smax_nan") -+ (UNSPEC_FMAXNMV "smax") -+ (UNSPEC_FMAXV "smax_nan") -+ (UNSPEC_FMIN "smin_nan") -+ (UNSPEC_FMINNMV "smin") -+ (UNSPEC_FMINV "smin_nan")]) ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rc = reverse_condition_maybe_unordered (rc); ++ else ++ rc = reverse_condition (rc); ++ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); ++ ++ } ++ [(set_attr "conds" "use") ++ (set_attr "length" "8")] ++) ++ ++(define_insn_and_split "*thumb2_mov_notscc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (not:SI (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])))] ++ "TARGET_THUMB2 && !arm_restrict_it" ++ "#" ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1" + "TARGET_THUMB2" +- "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1" ++ [(set (match_dup 0) ++ (if_then_else:SI (match_dup 1) ++ (match_dup 3) ++ (match_dup 4)))] ++ { ++ operands[3] = GEN_INT (~1); ++ operands[4] = GEN_INT (~0); ++ } + [(set_attr "conds" "use") + (set_attr "length" "10")] + ) --(define_int_attr fmaxminv [(UNSPEC_FMAXV "max") -- (UNSPEC_FMINV "min")]) -+(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") -+ (UNSPEC_UMINV "umin") -+ (UNSPEC_SMAXV "smax") -+ (UNSPEC_SMINV "smin") -+ (UNSPEC_FMAX "fmax") -+ (UNSPEC_FMAXNMV "fmaxnm") -+ (UNSPEC_FMAXV "fmax") -+ (UNSPEC_FMIN "fmin") -+ (UNSPEC_FMINNMV "fminnm") -+ (UNSPEC_FMINV "fmin")]) +-(define_insn "*thumb2_movsicc_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") ++(define_insn_and_split "*thumb2_mov_notscc_strict_it" ++ [(set (match_operand:SI 0 "low_register_operand" "=l") ++ (not:SI (match_operator:SI 1 "arm_comparison_operator" ++ [(match_operand 2 "cc_register" "") (const_int 0)])))] ++ "TARGET_THUMB2 && arm_restrict_it" ++ "#" ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1" ++ "&& reload_completed" ++ [(set (match_dup 0) ++ (match_dup 3)) ++ (cond_exec (match_dup 4) ++ (set (match_dup 0) ++ (ashift:SI (match_dup 0) ++ (const_int 1))))] ++ { ++ operands[3] = GEN_INT (~0); ++ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]), ++ VOIDmode, operands[2], const0_rtx); ++ } ++ [(set_attr "conds" "use") ++ (set_attr "length" "8")] ++) ++ ++(define_insn_and_split "*thumb2_movsicc_insn" ++ [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r") + (if_then_else:SI + (match_operator 3 "arm_comparison_operator" + [(match_operand 4 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K") +- (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))] ++ (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,rI,rI,K ,K,r") ++ (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,K ,rI,K,r")))] + "TARGET_THUMB2" + "@ + it\\t%D3\;mov%D3\\t%0, %2 ++ it\\t%d3\;mov%d3\\t%0, %1 ++ it\\t%D3\;mov%D3\\t%0, %2 + it\\t%D3\;mvn%D3\\t%0, #%B2 + it\\t%d3\;mov%d3\\t%0, %1 + it\\t%d3\;mvn%d3\\t%0, #%B1 +- ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2 +- ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 +- ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 +- ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" +- [(set_attr "length" "6,6,6,6,10,10,10,10") ++ # ++ # ++ # ++ # ++ #" ++ ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2 ++ ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 ++ ; alt 8: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 ++ ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2 ++ ; alt 10: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2 ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ enum rtx_code rev_code; ++ enum machine_mode mode; ++ rtx rev_cond; ++ ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ operands[3], ++ gen_rtx_SET (VOIDmode, ++ operands[0], ++ operands[1]))); ++ rev_code = GET_CODE (operands[3]); ++ mode = GET_MODE (operands[4]); ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rev_code = reverse_condition_maybe_unordered (rev_code); ++ else ++ rev_code = reverse_condition (rev_code); ++ ++ rev_cond = gen_rtx_fmt_ee (rev_code, ++ VOIDmode, ++ gen_rtx_REG (mode, CC_REGNUM), ++ const0_rtx); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ rev_cond, ++ gen_rtx_SET (VOIDmode, ++ operands[0], ++ operands[2]))); ++ DONE; ++ } ++ [(set_attr "length" "4,4,6,6,6,6,10,10,10,10,6") ++ (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,yes") + (set_attr "conds" "use")] + ) --(define_int_attr fmaxmin [(UNSPEC_FMAX "fmax") -- (UNSPEC_FMIN "fmin")]) -- - (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") - (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") - (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") -@@ -719,6 +783,7 @@ - (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") - (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") - (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") -+ (UNSPEC_SADDV "s") (UNSPEC_UADDV "u") - (UNSPEC_SSLI "s") (UNSPEC_USLI "u") - (UNSPEC_SSRI "s") (UNSPEC_USRI "u") - (UNSPEC_USRA "u") (UNSPEC_SSRA "s") -@@ -768,12 +833,6 @@ - (UNSPEC_RADDHN2 "add") - (UNSPEC_RSUBHN2 "sub")]) +@@ -333,28 +589,74 @@ + ;; addresses will have the thumb bit set correctly. --(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt") -- (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt") -- (UNSPEC_CMEQ "eq") -- (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi") -- (UNSPEC_CMTST "tst")]) -- - (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") - (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) -@@ -783,15 +842,18 @@ - (UNSPEC_FRINTM "floor") - (UNSPEC_FRINTI "nearbyint") - (UNSPEC_FRINTX "rint") -- (UNSPEC_FRINTA "round")]) -+ (UNSPEC_FRINTA "round") -+ (UNSPEC_FRINTN "frintn")]) +-(define_insn "*thumb2_and_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") ++(define_insn_and_split "*thumb2_and_scc" ++ [(set (match_operand:SI 0 "s_register_operand" "=Ts") + (and:SI (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 2 "s_register_operand" "r")))] ++ [(match_operand 2 "cc_register" "") (const_int 0)]) ++ (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_THUMB2" +- "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" ++ "#" ; "and\\t%0, %3, #1\;it\\t%D1\;mov%D1\\t%0, #0" ++ "&& reload_completed" ++ [(set (match_dup 0) ++ (and:SI (match_dup 3) (const_int 1))) ++ (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))] ++ { ++ enum machine_mode mode = GET_MODE (operands[2]); ++ enum rtx_code rc = GET_CODE (operands[1]); ++ ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rc = reverse_condition_maybe_unordered (rc); ++ else ++ rc = reverse_condition (rc); ++ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); ++ } + [(set_attr "conds" "use") +- (set_attr "length" "10")] ++ (set (attr "length") (if_then_else (match_test "arm_restrict_it") ++ (const_int 8) ++ (const_int 10)))] + ) - ;; frint suffix for floating-point rounding instructions. - (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") - (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") -- (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")]) -+ (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") -+ (UNSPEC_FRINTN "n")]) +-(define_insn "*thumb2_ior_scc" ++(define_insn_and_split "*thumb2_ior_scc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ (ior:SI (match_operator:SI 1 "arm_comparison_operator" ++ [(match_operand 2 "cc_register" "") (const_int 0)]) ++ (match_operand:SI 3 "s_register_operand" "0,?r")))] ++ "TARGET_THUMB2 && !arm_restrict_it" ++ "@ ++ it\\t%d1\;orr%d1\\t%0, %3, #1 ++ #" ++ ; alt 1: ite\\t%D1\;mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1 ++ "&& reload_completed ++ && REGNO (operands [0]) != REGNO (operands[3])" ++ [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3))) ++ (cond_exec (match_dup 4) (set (match_dup 0) ++ (ior:SI (match_dup 3) (const_int 1))))] ++ { ++ enum machine_mode mode = GET_MODE (operands[2]); ++ enum rtx_code rc = GET_CODE (operands[1]); ++ ++ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rc = reverse_condition_maybe_unordered (rc); ++ else ++ rc = reverse_condition (rc); ++ operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); ++ } ++ [(set_attr "conds" "use") ++ (set_attr "length" "6,10")] ++) ++ ++(define_insn "*thumb2_ior_scc_strict_it" ++ [(set (match_operand:SI 0 "s_register_operand" "=l,l") + (ior:SI (match_operator:SI 2 "arm_comparison_operator" + [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "s_register_operand" "0,?r")))] +- "TARGET_THUMB2" ++ (match_operand:SI 1 "s_register_operand" "0,?l")))] ++ "TARGET_THUMB2 && arm_restrict_it" + "@ +- it\\t%d2\;orr%d2\\t%0, %1, #1 +- ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" ++ it\\t%d2\;mov%d2\\t%0, #1\;it\\t%d2\;orr%d2\\t%0, %1 ++ mov\\t%0, #1\;orr\\t%0, %1\;it\\t%D2\;mov%D2\\t%0, %1" + [(set_attr "conds" "use") +- (set_attr "length" "6,10")] ++ (set_attr "length" "8")] + ) - (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") -- (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")]) -+ (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") -+ (UNSPEC_FRINTN "frintn")]) + (define_insn "*thumb2_cond_move" +@@ -384,13 +686,20 @@ + output_asm_insn (\"it\\t%D4\", operands); + break; + case 2: +- output_asm_insn (\"ite\\t%D4\", operands); ++ if (arm_restrict_it) ++ output_asm_insn (\"it\\t%D4\", operands); ++ else ++ output_asm_insn (\"ite\\t%D4\", operands); + break; + default: + abort(); + } + if (which_alternative != 0) +- output_asm_insn (\"mov%D4\\t%0, %1\", operands); ++ { ++ output_asm_insn (\"mov%D4\\t%0, %1\", operands); ++ if (arm_restrict_it && which_alternative == 2) ++ output_asm_insn (\"it\\t%d4\", operands); ++ } + if (which_alternative != 1) + output_asm_insn (\"mov%d4\\t%0, %2\", operands); + return \"\"; +@@ -407,7 +716,7 @@ + (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) + (match_operand:SI 1 "s_register_operand" "0,?r")])) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_THUMB2" ++ "TARGET_THUMB2 && !arm_restrict_it" + "* + if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) + return \"%i5\\t%0, %1, %2, lsr #31\"; +@@ -436,9 +745,78 @@ + (set_attr "length" "14")] + ) - (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") - (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") -@@ -800,3 +862,5 @@ - (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") - (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") - (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) ++(define_insn_and_split "*thumb2_cond_arith_strict_it" ++ [(set (match_operand:SI 0 "s_register_operand" "=l") ++ (match_operator:SI 5 "shiftable_operator_strict_it" ++ [(match_operator:SI 4 "arm_comparison_operator" ++ [(match_operand:SI 2 "s_register_operand" "r") ++ (match_operand:SI 3 "arm_rhs_operand" "rI")]) ++ (match_operand:SI 1 "s_register_operand" "0")])) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_THUMB2 && arm_restrict_it" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) ++ { ++ /* %i5 %0, %1, %2, lsr #31 */ ++ rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31)); ++ rtx op = NULL_RTX; + -+(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) ---- a/src/gcc/config/aarch64/aarch64.h -+++ b/src/gcc/config/aarch64/aarch64.h -@@ -709,6 +709,8 @@ ++ switch (GET_CODE (operands[5])) ++ { ++ case AND: ++ op = gen_rtx_AND (SImode, shifted_op, operands[1]); ++ break; ++ case PLUS: ++ op = gen_rtx_PLUS (SImode, shifted_op, operands[1]); ++ break; ++ default: gcc_unreachable (); ++ } ++ emit_insn (gen_rtx_SET (VOIDmode, operands[0], op)); ++ DONE; ++ } ++ ++ /* "cmp %2, %3" */ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ gen_rtx_REG (CCmode, CC_REGNUM), ++ gen_rtx_COMPARE (CCmode, operands[2], operands[3]))); ++ ++ if (GET_CODE (operands[5]) == AND) ++ { ++ /* %i5 %0, %1, #1 ++ it%D4 ++ mov%D4 %0, #0 */ ++ enum rtx_code rc = reverse_condition (GET_CODE (operands[4])); ++ emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_AND (SImode, operands[1], GEN_INT (1)))); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx), ++ gen_rtx_SET (VOIDmode, operands[0], const0_rtx))); ++ DONE; ++ } ++ else ++ { ++ /* it\\t%d4 ++ %i5%d4\\t%0, %1, #1 */ ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]), ++ VOIDmode, ++ gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx), ++ gen_rtx_SET(VOIDmode, operands[0], ++ gen_rtx_PLUS (SImode, ++ operands[1], ++ GEN_INT (1))))); ++ DONE; ++ } ++ FAIL; ++ } ++ [(set_attr "conds" "clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*thumb2_cond_sub" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") ++ [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts") ++ (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts") + (match_operator:SI 4 "arm_comparison_operator" + [(match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) +@@ -448,8 +826,16 @@ + output_asm_insn (\"cmp\\t%2, %3\", operands); + if (which_alternative != 0) + { +- output_asm_insn (\"ite\\t%D4\", operands); +- output_asm_insn (\"mov%D4\\t%0, %1\", operands); ++ if (arm_restrict_it) ++ { ++ output_asm_insn (\"mov\\t%0, %1\", operands); ++ output_asm_insn (\"it\\t%d4\", operands); ++ } ++ else ++ { ++ output_asm_insn (\"ite\\t%D4\", operands); ++ output_asm_insn (\"mov%D4\\t%0, %1\", operands); ++ } + } + else + output_asm_insn (\"it\\t%d4\", operands); +@@ -459,37 +845,82 @@ + (set_attr "length" "10,14")] + ) - #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) +-(define_insn "*thumb2_negscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") ++(define_insn_and_split "*thumb2_negscc" ++ [(set (match_operand:SI 0 "s_register_operand" "=Ts") + (neg:SI (match_operator 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_rhs_operand" "rI")]))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2" +- "* +- if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx) +- return \"asr\\t%0, %1, #31\"; ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); -+#define REVERSIBLE_CC_MODE(MODE) 1 -+ - #define REVERSE_CONDITION(CODE, MODE) \ - (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ - ? reverse_condition_maybe_unordered (CODE) \ ---- a/src/gcc/config/arm/arm-tables.opt -+++ b/src/gcc/config/arm/arm-tables.opt -@@ -250,6 +250,9 @@ - Enum(processor_type) String(cortex-a15) Value(cortexa15) +- if (GET_CODE (operands[3]) == NE) +- return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\"; ++ if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx) ++ { ++ /* Emit asr\\t%0, %1, #31 */ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31)))); ++ DONE; ++ } ++ else if (GET_CODE (operands[3]) == NE && !arm_restrict_it) ++ { ++ /* Emit subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0 */ ++ if (CONST_INT_P (operands[2])) ++ emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2], ++ GEN_INT (- INTVAL (operands[2])))); ++ else ++ emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2])); - EnumValue -+Enum(processor_type) String(cortex-a53) Value(cortexa53) +- output_asm_insn (\"cmp\\t%1, %2\", operands); +- output_asm_insn (\"ite\\t%D3\", operands); +- output_asm_insn (\"mov%D3\\t%0, #0\", operands); +- return \"mvn%d3\\t%0, #0\"; +- " ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ gen_rtx_NE (SImode, ++ cc_reg, ++ const0_rtx), ++ gen_rtx_SET (SImode, ++ operands[0], ++ GEN_INT (~0)))); ++ DONE; ++ } ++ else ++ { ++ /* Emit: cmp\\t%1, %2\;mvn\\t%0, #0\;it\\t%D3\;mov%D3\\t%0, #0\;*/ ++ enum rtx_code rc = reverse_condition (GET_CODE (operands[3])); ++ enum machine_mode mode = SELECT_CC_MODE (rc, operands[1], operands[2]); ++ rtx tmp1 = gen_rtx_REG (mode, CC_REGNUM); + -+EnumValue - Enum(processor_type) String(cortex-r4) Value(cortexr4) ++ emit_insn (gen_rtx_SET (VOIDmode, ++ cc_reg, ++ gen_rtx_COMPARE (CCmode, operands[1], operands[2]))); ++ ++ emit_insn (gen_rtx_SET (VOIDmode, operands[0], GEN_INT (~0))); ++ ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ gen_rtx_fmt_ee (rc, ++ VOIDmode, ++ tmp1, ++ const0_rtx), ++ gen_rtx_SET (VOIDmode, operands[0], const0_rtx))); ++ DONE; ++ } ++ FAIL; ++ } + [(set_attr "conds" "clob") + (set_attr "length" "14")] + ) - EnumValue -@@ -259,6 +262,9 @@ - Enum(processor_type) String(cortex-r5) Value(cortexr5) + (define_insn "*thumb2_movcond" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++ [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts") + (if_then_else:SI + (match_operator 5 "arm_comparison_operator" + [(match_operand:SI 3 "s_register_operand" "r,r,r") + (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")]) +- (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") +- (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) ++ (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI") ++ (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_THUMB2" + "* +@@ -544,12 +975,18 @@ + output_asm_insn (\"it\\t%d5\", operands); + break; + case 2: +- output_asm_insn (\"ite\\t%d5\", operands); ++ if (arm_restrict_it) ++ { ++ output_asm_insn (\"mov\\t%0, %1\", operands); ++ output_asm_insn (\"it\\t%D5\", operands); ++ } ++ else ++ output_asm_insn (\"ite\\t%d5\", operands); + break; + default: + abort(); + } +- if (which_alternative != 0) ++ if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2)) + output_asm_insn (\"mov%d5\\t%0, %1\", operands); + if (which_alternative != 1) + output_asm_insn (\"mov%D5\\t%0, %2\", operands); +@@ -570,8 +1007,9 @@ + "@ + sxtb%?\\t%0, %1 + ldr%(sb%)\\t%0, %1" +- [(set_attr "type" "simple_alu_shift,load_byte") ++ [(set_attr "type" "extend,load_byte") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "pool_range" "*,4094") + (set_attr "neg_pool_range" "*,250")] + ) +@@ -583,8 +1021,9 @@ + "@ + uxth%?\\t%0, %1 + ldr%(h%)\\t%0, %1" +- [(set_attr "type" "simple_alu_shift,load_byte") ++ [(set_attr "type" "extend,load_byte") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "pool_range" "*,4094") + (set_attr "neg_pool_range" "*,250")] + ) +@@ -596,8 +1035,9 @@ + "@ + uxtb%(%)\\t%0, %1 + ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" +- [(set_attr "type" "simple_alu_shift,load_byte") ++ [(set_attr "type" "extend,load_byte") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "pool_range" "*,4094") + (set_attr "neg_pool_range" "*,250")] + ) +@@ -688,8 +1128,8 @@ + (set_attr "shift" "1") + (set_attr "length" "2") + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++ (const_string "arlo_shift") ++ (const_string "arlo_shift_reg")))] + ) - EnumValue -+Enum(processor_type) String(cortex-r7) Value(cortexr7) -+ -+EnumValue - Enum(processor_type) String(cortex-m4) Value(cortexm4) + (define_insn "*thumb2_mov_shortim" +@@ -811,7 +1251,7 @@ + " + [(set_attr "conds" "set") + (set_attr "length" "2,2,4,4") +- (set_attr "type" "simple_alu_imm,*,simple_alu_imm,*")] ++ (set_attr "type" "arlo_imm,*,arlo_imm,*")] + ) + + (define_insn "*thumb2_mulsi_short" +@@ -823,7 +1263,7 @@ + "mul%!\\t%0, %2, %0" + [(set_attr "predicable" "yes") + (set_attr "length" "2") +- (set_attr "insn" "muls")]) ++ (set_attr "type" "muls")]) + + (define_insn "*thumb2_mulsi_short_compare0" + [(set (reg:CC_NOOV CC_REGNUM) +@@ -836,7 +1276,7 @@ + "TARGET_THUMB2 && optimize_size" + "muls\\t%0, %2, %0" + [(set_attr "length" "2") +- (set_attr "insn" "muls")]) ++ (set_attr "type" "muls")]) + + (define_insn "*thumb2_mulsi_short_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) +@@ -848,7 +1288,7 @@ + "TARGET_THUMB2 && optimize_size" + "muls\\t%0, %2, %0" + [(set_attr "length" "2") +- (set_attr "insn" "muls")]) ++ (set_attr "type" "muls")]) + + (define_insn "*thumb2_cbz" + [(set (pc) (if_then_else +@@ -922,7 +1362,8 @@ + (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_THUMB2" + "orn%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")] ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "*orsi_not_shiftsi_si" +@@ -934,8 +1375,9 @@ + "TARGET_THUMB2" + "orn%?\\t%0, %1, %2%S4" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "shift" "2") +- (set_attr "type" "alu_shift")] ++ (set_attr "type" "arlo_shift")] + ) - EnumValue + (define_peephole2 --- a/src/gcc/config/arm/arm.c +++ b/src/gcc/config/arm/arm.c @@ -173,6 +173,7 @@ @@ -17871,7 +26114,15 @@ }; const struct tune_params arm_cortex_a15_tune = -@@ -1038,6 +1065,7 @@ +@@ -1031,13 +1058,14 @@ + arm_9e_rtx_costs, + NULL, + 1, /* Constant limit. */ +- 5, /* Max cond insns. */ ++ 2, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ + arm_default_branch_cost, true, /* Prefer LDRD/STRD. */ {true, true}, /* Prefer non short circuit. */ &arm_default_vec_cost, /* Vectorizer costs. */ @@ -17924,7 +26175,7 @@ /* If we are not using the default (ARM mode) section anchor offset ranges, then set the correct ranges now. */ if (TARGET_THUMB1) -@@ -2129,6 +2166,12 @@ +@@ -2129,11 +2166,25 @@ global_options.x_param_values, global_options_set.x_param_values); @@ -17937,7 +26188,20 @@ /* Use the alternative scheduling-pressure algorithm by default. */ maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2, global_options.x_param_values, -@@ -2382,6 +2425,10 @@ + global_options_set.x_param_values); + ++ /* Disable shrink-wrap when optimizing function for size, since it tends to ++ generate additional returns. */ ++ if (optimize_function_for_size_p (cfun) && TARGET_THUMB2) ++ flag_shrink_wrap = false; ++ /* TBD: Dwarf info for apcs frame is not handled yet. */ ++ if (TARGET_APCS_FRAME) ++ flag_shrink_wrap = false; ++ + /* Register global variables with the garbage collector. */ + arm_add_gc_roots (); + } +@@ -2382,6 +2433,10 @@ if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB)) return 0; @@ -17948,17 +26212,140 @@ offsets = arm_get_frame_offsets (); stack_adjust = offsets->outgoing_args - offsets->saved_regs; -@@ -2617,6 +2664,9 @@ +@@ -2479,6 +2534,18 @@ + return 1; + } + ++/* Return TRUE if we should try to use a simple_return insn, i.e. perform ++ shrink-wrapping if possible. This is the case if we need to emit a ++ prologue, which we can test by looking at the offsets. */ ++bool ++use_simple_return_p (void) ++{ ++ arm_stack_offsets *offsets; ++ ++ offsets = arm_get_frame_offsets (); ++ return offsets->outgoing_args != 0; ++} ++ + /* Return TRUE if int I is a valid immediate ARM constant. */ + + int +@@ -2617,6 +2684,11 @@ switch (code) { + case AND: ++ case IOR: ++ case XOR: + return (const_ok_for_op (hi_val, code) || hi_val == 0xFFFFFFFF) + && (const_ok_for_op (lo_val, code) || lo_val == 0xFFFFFFFF); case PLUS: return arm_not_operand (hi, SImode) && arm_add_operand (lo, SImode); -@@ -11803,6 +11853,134 @@ +@@ -5337,9 +5409,8 @@ + if (cfun->machine->sibcall_blocked) + return false; + +- /* Never tailcall something for which we have no decl, or if we +- are generating code for Thumb-1. */ +- if (decl == NULL || TARGET_THUMB1) ++ /* Never tailcall something if we are generating code for Thumb-1. */ ++ if (TARGET_THUMB1) + return false; + + /* The PIC register is live on entry to VxWorks PLT entries, so we +@@ -5349,13 +5420,14 @@ + + /* Cannot tail-call to long calls, since these are out of range of + a branch instruction. */ +- if (arm_is_long_call_p (decl)) ++ if (decl && arm_is_long_call_p (decl)) + return false; + + /* If we are interworking and the function is not declared static + then we can't tail-call it unless we know that it exists in this + compilation unit (since it might be a Thumb routine). */ +- if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) ++ if (TARGET_INTERWORK && decl && TREE_PUBLIC (decl) ++ && !TREE_ASM_WRITTEN (decl)) + return false; + + func_type = arm_current_func_type (); +@@ -5387,6 +5459,7 @@ + sibling calls. */ + if (TARGET_AAPCS_BASED + && arm_abi == ARM_ABI_AAPCS ++ && decl + && DECL_WEAK (decl)) + return false; + +@@ -8578,7 +8651,12 @@ + instruction we depend on is another ALU instruction, then we may + have to account for an additional stall. */ + if (shift_opnum != 0 +- && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) ++ && (attr_type == TYPE_ARLO_SHIFT ++ || attr_type == TYPE_ARLO_SHIFT_REG ++ || attr_type == TYPE_MOV_SHIFT ++ || attr_type == TYPE_MVN_SHIFT ++ || attr_type == TYPE_MOV_SHIFT_REG ++ || attr_type == TYPE_MVN_SHIFT_REG)) + { + rtx shifted_operand; + int opno; +@@ -8859,12 +8937,12 @@ + if (recog_memoized (insn) < 0) + return false; + +- if (get_attr_insn (insn) == INSN_MOV) +- return false; +- + switch (get_attr_type (insn)) + { +- case TYPE_ALU_REG: ++ case TYPE_ARLO_REG: ++ case TYPE_MVN_REG: ++ case TYPE_SHIFT: ++ case TYPE_SHIFT_REG: + case TYPE_LOAD_BYTE: + case TYPE_LOAD1: + case TYPE_STORE1: +@@ -8905,13 +8983,15 @@ + return false; + } + +- if (get_attr_insn (insn) == INSN_MOV) +- return true; +- + switch (get_attr_type (insn)) + { +- case TYPE_SIMPLE_ALU_IMM: +- case TYPE_SIMPLE_ALU_SHIFT: ++ case TYPE_ARLO_IMM: ++ case TYPE_EXTEND: ++ case TYPE_MVN_IMM: ++ case TYPE_MOV_IMM: ++ case TYPE_MOV_REG: ++ case TYPE_MOV_SHIFT: ++ case TYPE_MOV_SHIFT_REG: + case TYPE_BRANCH: + case TYPE_CALL: + return true; +@@ -9070,6 +9150,12 @@ + return cost; + } + ++int ++arm_max_conditional_execute (void) ++{ ++ return max_insns_skipped; ++} ++ + static int + arm_default_branch_cost (bool speed_p, bool predictable_p ATTRIBUTE_UNUSED) + { +@@ -11825,6 +11911,142 @@ return 1; } @@ -17986,1755 +26373,3305 @@ + bool src_aligned, dst_aligned; + bool src_volatile, dst_volatile; + -+ gcc_assert (CONST_INT_P (operands[2])); -+ gcc_assert (CONST_INT_P (operands[3])); ++ gcc_assert (CONST_INT_P (operands[2])); ++ gcc_assert (CONST_INT_P (operands[3])); ++ ++ len = UINTVAL (operands[2]); ++ if (len > 64) ++ return false; ++ ++ /* Maximum alignment we can assume for both src and dst buffers. */ ++ align = INTVAL (operands[3]); ++ ++ if ((!unaligned_access) && (len >= 4) && ((align & 3) != 0)) ++ return false; ++ ++ /* Place src and dst addresses in registers ++ and update the corresponding mem rtx. */ ++ dst = operands[0]; ++ dst_volatile = MEM_VOLATILE_P (dst); ++ dst_aligned = MEM_ALIGN (dst) >= BITS_PER_WORD; ++ base = copy_to_mode_reg (SImode, XEXP (dst, 0)); ++ dst = adjust_automodify_address (dst, VOIDmode, base, 0); ++ ++ src = operands[1]; ++ src_volatile = MEM_VOLATILE_P (src); ++ src_aligned = MEM_ALIGN (src) >= BITS_PER_WORD; ++ base = copy_to_mode_reg (SImode, XEXP (src, 0)); ++ src = adjust_automodify_address (src, VOIDmode, base, 0); ++ ++ if (!unaligned_access && !(src_aligned && dst_aligned)) ++ return false; ++ ++ if (src_volatile || dst_volatile) ++ return false; ++ ++ /* If we cannot generate any LDRD/STRD, try to generate LDM/STM. */ ++ if (!(dst_aligned || src_aligned)) ++ return arm_gen_movmemqi (operands); ++ ++ src = adjust_address (src, DImode, 0); ++ dst = adjust_address (dst, DImode, 0); ++ while (len >= 8) ++ { ++ len -= 8; ++ reg0 = gen_reg_rtx (DImode); ++ if (src_aligned) ++ emit_move_insn (reg0, src); ++ else ++ emit_insn (gen_unaligned_loaddi (reg0, src)); ++ ++ if (dst_aligned) ++ emit_move_insn (dst, reg0); ++ else ++ emit_insn (gen_unaligned_storedi (dst, reg0)); ++ ++ src = next_consecutive_mem (src); ++ dst = next_consecutive_mem (dst); ++ } ++ ++ gcc_assert (len < 8); ++ if (len >= 4) ++ { ++ /* More than a word but less than a double-word to copy. Copy a word. */ ++ reg0 = gen_reg_rtx (SImode); ++ src = adjust_address (src, SImode, 0); ++ dst = adjust_address (dst, SImode, 0); ++ if (src_aligned) ++ emit_move_insn (reg0, src); ++ else ++ emit_insn (gen_unaligned_loadsi (reg0, src)); ++ ++ if (dst_aligned) ++ emit_move_insn (dst, reg0); ++ else ++ emit_insn (gen_unaligned_storesi (dst, reg0)); ++ ++ src = next_consecutive_mem (src); ++ dst = next_consecutive_mem (dst); ++ len -= 4; ++ } ++ ++ if (len == 0) ++ return true; ++ ++ /* Copy the remaining bytes. */ ++ if (len >= 2) ++ { ++ dst = adjust_address (dst, HImode, 0); ++ src = adjust_address (src, HImode, 0); ++ reg0 = gen_reg_rtx (SImode); ++ if (src_aligned) ++ emit_insn (gen_zero_extendhisi2 (reg0, src)); ++ else ++ emit_insn (gen_unaligned_loadhiu (reg0, src)); ++ ++ if (dst_aligned) ++ emit_insn (gen_movhi (dst, gen_lowpart(HImode, reg0))); ++ else ++ emit_insn (gen_unaligned_storehi (dst, gen_lowpart (HImode, reg0))); ++ ++ src = next_consecutive_mem (src); ++ dst = next_consecutive_mem (dst); ++ if (len == 2) ++ return true; ++ } ++ ++ dst = adjust_address (dst, QImode, 0); ++ src = adjust_address (src, QImode, 0); ++ reg0 = gen_reg_rtx (QImode); ++ emit_move_insn (reg0, src); ++ emit_move_insn (dst, reg0); ++ return true; ++} ++ + /* Select a dominance comparison mode if possible for a test of the general + form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. + COND_OR == DOM_CC_X_AND_Y => (X && Y) +@@ -12625,6 +12847,277 @@ + return true; + } + ++/* Helper for gen_operands_ldrd_strd. Returns true iff the memory ++ operand ADDR is an immediate offset from the base register and is ++ not volatile, in which case it sets BASE and OFFSET ++ accordingly. */ ++bool ++mem_ok_for_ldrd_strd (rtx addr, rtx *base, rtx *offset) ++{ ++ /* TODO: Handle more general memory operand patterns, such as ++ PRE_DEC and PRE_INC. */ ++ ++ /* Convert a subreg of mem into mem itself. */ ++ if (GET_CODE (addr) == SUBREG) ++ addr = alter_subreg (&addr, true); ++ ++ gcc_assert (MEM_P (addr)); ++ ++ /* Don't modify volatile memory accesses. */ ++ if (MEM_VOLATILE_P (addr)) ++ return false; ++ ++ *offset = const0_rtx; ++ ++ addr = XEXP (addr, 0); ++ if (REG_P (addr)) ++ { ++ *base = addr; ++ return true; ++ } ++ else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == MINUS) ++ { ++ *base = XEXP (addr, 0); ++ *offset = XEXP (addr, 1); ++ return (REG_P (*base) && CONST_INT_P (*offset)); ++ } ++ ++ return false; ++} ++ ++#define SWAP_RTX(x,y) do { rtx tmp = x; x = y; y = tmp; } while (0) ++ ++/* Called from a peephole2 to replace two word-size accesses with a ++ single LDRD/STRD instruction. Returns true iff we can generate a ++ new instruction sequence. That is, both accesses use the same base ++ register and the gap between constant offsets is 4. This function ++ may reorder its operands to match ldrd/strd RTL templates. ++ OPERANDS are the operands found by the peephole matcher; ++ OPERANDS[0,1] are register operands, and OPERANDS[2,3] are the ++ corresponding memory operands. LOAD indicaates whether the access ++ is load or store. CONST_STORE indicates a store of constant ++ integer values held in OPERANDS[4,5] and assumes that the pattern ++ is of length 4 insn, for the purpose of checking dead registers. ++ COMMUTE indicates that register operands may be reordered. */ ++bool ++gen_operands_ldrd_strd (rtx *operands, bool load, ++ bool const_store, bool commute) ++{ ++ int nops = 2; ++ HOST_WIDE_INT offsets[2], offset; ++ rtx base = NULL_RTX; ++ rtx cur_base, cur_offset, tmp; ++ int i, gap; ++ HARD_REG_SET regset; ++ ++ gcc_assert (!const_store || !load); ++ /* Check that the memory references are immediate offsets from the ++ same base register. Extract the base register, the destination ++ registers, and the corresponding memory offsets. */ ++ for (i = 0; i < nops; i++) ++ { ++ if (!mem_ok_for_ldrd_strd (operands[nops+i], &cur_base, &cur_offset)) ++ return false; ++ ++ if (i == 0) ++ base = cur_base; ++ else if (REGNO (base) != REGNO (cur_base)) ++ return false; ++ ++ offsets[i] = INTVAL (cur_offset); ++ if (GET_CODE (operands[i]) == SUBREG) ++ { ++ tmp = SUBREG_REG (operands[i]); ++ gcc_assert (GET_MODE (operands[i]) == GET_MODE (tmp)); ++ operands[i] = tmp; ++ } ++ } ++ ++ /* Make sure there is no dependency between the individual loads. */ ++ if (load && REGNO (operands[0]) == REGNO (base)) ++ return false; /* RAW */ ++ ++ if (load && REGNO (operands[0]) == REGNO (operands[1])) ++ return false; /* WAW */ ++ ++ /* If the same input register is used in both stores ++ when storing different constants, try to find a free register. ++ For example, the code ++ mov r0, 0 ++ str r0, [r2] ++ mov r0, 1 ++ str r0, [r2, #4] ++ can be transformed into ++ mov r1, 0 ++ strd r1, r0, [r2] ++ in Thumb mode assuming that r1 is free. */ ++ if (const_store ++ && REGNO (operands[0]) == REGNO (operands[1]) ++ && INTVAL (operands[4]) != INTVAL (operands[5])) ++ { ++ if (TARGET_THUMB2) ++ { ++ CLEAR_HARD_REG_SET (regset); ++ tmp = peep2_find_free_register (0, 4, "r", SImode, ®set); ++ if (tmp == NULL_RTX) ++ return false; ++ ++ /* Use the new register in the first load to ensure that ++ if the original input register is not dead after peephole, ++ then it will have the correct constant value. */ ++ operands[0] = tmp; ++ } ++ else if (TARGET_ARM) ++ { ++ return false; ++ int regno = REGNO (operands[0]); ++ if (!peep2_reg_dead_p (4, operands[0])) ++ { ++ /* When the input register is even and is not dead after the ++ pattern, it has to hold the second constant but we cannot ++ form a legal STRD in ARM mode with this register as the second ++ register. */ ++ if (regno % 2 == 0) ++ return false; + -+ len = UINTVAL (operands[2]); -+ if (len > 64) -+ return false; ++ /* Is regno-1 free? */ ++ SET_HARD_REG_SET (regset); ++ CLEAR_HARD_REG_BIT(regset, regno - 1); ++ tmp = peep2_find_free_register (0, 4, "r", SImode, ®set); ++ if (tmp == NULL_RTX) ++ return false; + -+ /* Maximum alignment we can assume for both src and dst buffers. */ -+ align = INTVAL (operands[3]); ++ operands[0] = tmp; ++ } ++ else ++ { ++ /* Find a DImode register. */ ++ CLEAR_HARD_REG_SET (regset); ++ tmp = peep2_find_free_register (0, 4, "r", DImode, ®set); ++ if (tmp != NULL_RTX) ++ { ++ operands[0] = simplify_gen_subreg (SImode, tmp, DImode, 0); ++ operands[1] = simplify_gen_subreg (SImode, tmp, DImode, 4); ++ } ++ else ++ { ++ /* Can we use the input register to form a DI register? */ ++ SET_HARD_REG_SET (regset); ++ CLEAR_HARD_REG_BIT(regset, ++ regno % 2 == 0 ? regno + 1 : regno - 1); ++ tmp = peep2_find_free_register (0, 4, "r", SImode, ®set); ++ if (tmp == NULL_RTX) ++ return false; ++ operands[regno % 2 == 1 ? 0 : 1] = tmp; ++ } ++ } + -+ if ((!unaligned_access) && (len >= 4) && ((align & 3) != 0)) -+ return false; ++ gcc_assert (operands[0] != NULL_RTX); ++ gcc_assert (operands[1] != NULL_RTX); ++ gcc_assert (REGNO (operands[0]) % 2 == 0); ++ gcc_assert (REGNO (operands[1]) == REGNO (operands[0]) + 1); ++ } ++ } + -+ /* Place src and dst addresses in registers -+ and update the corresponding mem rtx. */ -+ dst = operands[0]; -+ dst_volatile = MEM_VOLATILE_P (dst); -+ dst_aligned = MEM_ALIGN (dst) >= BITS_PER_WORD; -+ base = copy_to_mode_reg (SImode, XEXP (dst, 0)); -+ dst = adjust_automodify_address (dst, VOIDmode, base, 0); ++ /* Make sure the instructions are ordered with lower memory access first. */ ++ if (offsets[0] > offsets[1]) ++ { ++ gap = offsets[0] - offsets[1]; ++ offset = offsets[1]; + -+ src = operands[1]; -+ src_volatile = MEM_VOLATILE_P (src); -+ src_aligned = MEM_ALIGN (src) >= BITS_PER_WORD; -+ base = copy_to_mode_reg (SImode, XEXP (src, 0)); -+ src = adjust_automodify_address (src, VOIDmode, base, 0); ++ /* Swap the instructions such that lower memory is accessed first. */ ++ SWAP_RTX (operands[0], operands[1]); ++ SWAP_RTX (operands[2], operands[3]); ++ if (const_store) ++ SWAP_RTX (operands[4], operands[5]); ++ } ++ else ++ { ++ gap = offsets[1] - offsets[0]; ++ offset = offsets[0]; ++ } + -+ if (!unaligned_access && !(src_aligned && dst_aligned)) ++ /* Make sure accesses are to consecutive memory locations. */ ++ if (gap != 4) + return false; + -+ if (src_volatile || dst_volatile) -+ return false; ++ /* Make sure we generate legal instructions. */ ++ if (operands_ok_ldrd_strd (operands[0], operands[1], base, offset, ++ false, load)) ++ return true; + -+ /* If we cannot generate any LDRD/STRD, try to generate LDM/STM. */ -+ if (!(dst_aligned || src_aligned)) -+ return arm_gen_movmemqi (operands); ++ /* In Thumb state, where registers are almost unconstrained, there ++ is little hope to fix it. */ ++ if (TARGET_THUMB2) ++ return false; + -+ src = adjust_address (src, DImode, 0); -+ dst = adjust_address (dst, DImode, 0); -+ while (len >= 8) ++ if (load && commute) + { -+ len -= 8; -+ reg0 = gen_reg_rtx (DImode); -+ if (src_aligned) -+ emit_move_insn (reg0, src); -+ else -+ emit_insn (gen_unaligned_loaddi (reg0, src)); -+ -+ if (dst_aligned) -+ emit_move_insn (dst, reg0); -+ else -+ emit_insn (gen_unaligned_storedi (dst, reg0)); -+ -+ src = next_consecutive_mem (src); -+ dst = next_consecutive_mem (dst); ++ /* Try reordering registers. */ ++ SWAP_RTX (operands[0], operands[1]); ++ if (operands_ok_ldrd_strd (operands[0], operands[1], base, offset, ++ false, load)) ++ return true; + } + -+ gcc_assert (len < 8); -+ if (len >= 4) ++ if (const_store) + { -+ /* More than a word but less than a double-word to copy. Copy a word. */ -+ reg0 = gen_reg_rtx (SImode); -+ src = adjust_address (src, SImode, 0); -+ dst = adjust_address (dst, SImode, 0); -+ if (src_aligned) -+ emit_move_insn (reg0, src); -+ else -+ emit_insn (gen_unaligned_loadsi (reg0, src)); ++ /* If input registers are dead after this pattern, they can be ++ reordered or replaced by other registers that are free in the ++ current pattern. */ ++ if (!peep2_reg_dead_p (4, operands[0]) ++ || !peep2_reg_dead_p (4, operands[1])) ++ return false; + -+ if (dst_aligned) -+ emit_move_insn (dst, reg0); -+ else -+ emit_insn (gen_unaligned_storesi (dst, reg0)); ++ /* Try to reorder the input registers. */ ++ /* For example, the code ++ mov r0, 0 ++ mov r1, 1 ++ str r1, [r2] ++ str r0, [r2, #4] ++ can be transformed into ++ mov r1, 0 ++ mov r0, 1 ++ strd r0, [r2] ++ */ ++ if (operands_ok_ldrd_strd (operands[1], operands[0], base, offset, ++ false, false)) ++ { ++ SWAP_RTX (operands[0], operands[1]); ++ return true; ++ } + -+ src = next_consecutive_mem (src); -+ dst = next_consecutive_mem (dst); -+ len -= 4; -+ } ++ /* Try to find a free DI register. */ ++ CLEAR_HARD_REG_SET (regset); ++ add_to_hard_reg_set (®set, SImode, REGNO (operands[0])); ++ add_to_hard_reg_set (®set, SImode, REGNO (operands[1])); ++ while (true) ++ { ++ tmp = peep2_find_free_register (0, 4, "r", DImode, ®set); ++ if (tmp == NULL_RTX) ++ return false; + -+ if (len == 0) -+ return true; ++ /* DREG must be an even-numbered register in DImode. ++ Split it into SI registers. */ ++ operands[0] = simplify_gen_subreg (SImode, tmp, DImode, 0); ++ operands[1] = simplify_gen_subreg (SImode, tmp, DImode, 4); ++ gcc_assert (operands[0] != NULL_RTX); ++ gcc_assert (operands[1] != NULL_RTX); ++ gcc_assert (REGNO (operands[0]) % 2 == 0); ++ gcc_assert (REGNO (operands[0]) + 1 == REGNO (operands[1])); + -+ /* Copy the remaining bytes. */ -+ if (len >= 2) -+ { -+ dst = adjust_address (dst, HImode, 0); -+ src = adjust_address (src, HImode, 0); -+ reg0 = gen_reg_rtx (SImode); -+ emit_insn (gen_unaligned_loadhiu (reg0, src)); -+ emit_insn (gen_unaligned_storehi (dst, gen_lowpart (HImode, reg0))); -+ src = next_consecutive_mem (src); -+ dst = next_consecutive_mem (dst); -+ if (len == 2) -+ return true; ++ return (operands_ok_ldrd_strd (operands[0], operands[1], ++ base, offset, ++ false, load)); ++ } + } + -+ dst = adjust_address (dst, QImode, 0); -+ src = adjust_address (src, QImode, 0); -+ reg0 = gen_reg_rtx (QImode); -+ emit_move_insn (reg0, src); -+ emit_move_insn (dst, reg0); -+ return true; ++ return false; +} ++#undef SWAP_RTX + - /* Select a dominance comparison mode if possible for a test of the general - form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. - COND_OR == DOM_CC_X_AND_Y => (X && Y) -@@ -12603,6 +12781,277 @@ - return true; ++ ++ + + /* Print a symbolic form of X to the debug file, F. */ + static void +@@ -13858,6 +14351,16 @@ + && IN_RANGE (INTVAL (op1), -7, 7)) + action = CONV; + } ++ /* ADCS , */ ++ else if (GET_CODE (XEXP (src, 0)) == PLUS ++ && rtx_equal_p (XEXP (XEXP (src, 0), 0), dst) ++ && low_register_operand (XEXP (XEXP (src, 0), 1), ++ SImode) ++ && COMPARISON_P (op1) ++ && cc_register (XEXP (op1, 0), VOIDmode) ++ && maybe_get_arm_condition_code (op1) == ARM_CS ++ && XEXP (op1, 1) == const0_rtx) ++ action = CONV; + break; + + case MINUS: +@@ -14816,7 +15319,8 @@ + { + /* Constraints should ensure this. */ + gcc_assert (code0 == MEM && code1 == REG); +- gcc_assert (REGNO (operands[1]) != IP_REGNUM); ++ gcc_assert ((REGNO (operands[1]) != IP_REGNUM) ++ || (TARGET_ARM && TARGET_LDRD)); + + switch (GET_CODE (XEXP (operands[0], 0))) + { +@@ -16289,124 +16793,308 @@ + } } -+/* Helper for gen_operands_ldrd_strd. Returns true iff the memory -+ operand ADDR is an immediate offset from the base register and is -+ not volatile, in which case it sets BASE and OFFSET -+ accordingly. */ -+bool -+mem_ok_for_ldrd_strd (rtx addr, rtx *base, rtx *offset) -+{ -+ /* TODO: Handle more general memory operand patterns, such as -+ PRE_DEC and PRE_INC. */ -+ -+ /* Convert a subreg of mem into mem itself. */ -+ if (GET_CODE (addr) == SUBREG) -+ addr = alter_subreg (&addr, true); +-/* Generate and emit a pattern that will be recognized as STRD pattern. If even +- number of registers are being pushed, multiple STRD patterns are created for +- all register pairs. If odd number of registers are pushed, emit a +- combination of STRDs and STR for the prologue saves. */ ++/* Generate and emit a sequence of insns equivalent to PUSH, but using ++ STR and STRD. If an even number of registers are being pushed, one ++ or more STRD patterns are created for each register pair. If an ++ odd number of registers are pushed, emit an initial STR followed by ++ as many STRD instructions as are needed. This works best when the ++ stack is initially 64-bit aligned (the normal case), since it ++ ensures that each STRD is also 64-bit aligned. */ + static void + thumb2_emit_strd_push (unsigned long saved_regs_mask) + { + int num_regs = 0; +- int i, j; ++ int i; ++ int regno; + rtx par = NULL_RTX; +- rtx insn = NULL_RTX; + rtx dwarf = NULL_RTX; +- rtx tmp, reg, tmp1; ++ rtx tmp; ++ bool first = true; + ++ num_regs = bit_count (saved_regs_mask); + -+ gcc_assert (MEM_P (addr)); ++ /* Must be at least one register to save, and can't save SP or PC. */ ++ gcc_assert (num_regs > 0 && num_regs <= 14); ++ gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM))); ++ gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); + -+ /* Don't modify volatile memory accesses. */ -+ if (MEM_VOLATILE_P (addr)) -+ return false; ++ /* Create sequence for DWARF info. All the frame-related data for ++ debugging is held in this wrapper. */ ++ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1)); + -+ *offset = const0_rtx; ++ /* Describe the stack adjustment. */ ++ tmp = gen_rtx_SET (VOIDmode, ++ stack_pointer_rtx, ++ plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs)); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (dwarf, 0, 0) = tmp; + -+ addr = XEXP (addr, 0); -+ if (REG_P (addr)) -+ { -+ *base = addr; -+ return true; -+ } -+ else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == MINUS) ++ /* Find the first register. */ ++ for (regno = 0; (saved_regs_mask & (1 << regno)) == 0; regno++) ++ ; ++ ++ i = 0; ++ ++ /* If there's an odd number of registers to push. Start off by ++ pushing a single register. This ensures that subsequent strd ++ operations are dword aligned (assuming that SP was originally ++ 64-bit aligned). */ ++ if ((num_regs & 1) != 0) + { -+ *base = XEXP (addr, 0); -+ *offset = XEXP (addr, 1); -+ return (REG_P (*base) && CONST_INT_P (*offset)); ++ rtx reg, mem, insn; ++ ++ reg = gen_rtx_REG (SImode, regno); ++ if (num_regs == 1) ++ mem = gen_frame_mem (Pmode, gen_rtx_PRE_DEC (Pmode, ++ stack_pointer_rtx)); ++ else ++ mem = gen_frame_mem (Pmode, ++ gen_rtx_PRE_MODIFY ++ (Pmode, stack_pointer_rtx, ++ plus_constant (Pmode, stack_pointer_rtx, ++ -4 * num_regs))); ++ ++ tmp = gen_rtx_SET (VOIDmode, mem, reg); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ insn = emit_insn (tmp); ++ RTX_FRAME_RELATED_P (insn) = 1; ++ add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); ++ tmp = gen_rtx_SET (VOIDmode, gen_frame_mem (Pmode, stack_pointer_rtx), ++ reg); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ i++; ++ regno++; ++ XVECEXP (dwarf, 0, i) = tmp; ++ first = false; + } + -+ return false; -+} ++ while (i < num_regs) ++ if (saved_regs_mask & (1 << regno)) ++ { ++ rtx reg1, reg2, mem1, mem2; ++ rtx tmp0, tmp1, tmp2; ++ int regno2; ++ ++ /* Find the register to pair with this one. */ ++ for (regno2 = regno + 1; (saved_regs_mask & (1 << regno2)) == 0; ++ regno2++) ++ ; + -+#define SWAP_RTX(x,y) do { rtx tmp = x; x = y; y = tmp; } while (0) ++ reg1 = gen_rtx_REG (SImode, regno); ++ reg2 = gen_rtx_REG (SImode, regno2); + -+/* Called from a peephole2 to replace two word-size accesses with a -+ single LDRD/STRD instruction. Returns true iff we can generate a -+ new instruction sequence. That is, both accesses use the same base -+ register and the gap between constant offsets is 4. This function -+ may reorder its operands to match ldrd/strd RTL templates. -+ OPERANDS are the operands found by the peephole matcher; -+ OPERANDS[0,1] are register operands, and OPERANDS[2,3] are the -+ corresponding memory operands. LOAD indicaates whether the access -+ is load or store. CONST_STORE indicates a store of constant -+ integer values held in OPERANDS[4,5] and assumes that the pattern -+ is of length 4 insn, for the purpose of checking dead registers. -+ COMMUTE indicates that register operands may be reordered. */ -+bool -+gen_operands_ldrd_strd (rtx *operands, bool load, -+ bool const_store, bool commute) -+{ -+ int nops = 2; -+ HOST_WIDE_INT offsets[2], offset; -+ rtx base = NULL_RTX; -+ rtx cur_base, cur_offset, tmp; -+ int i, gap; -+ HARD_REG_SET regset; ++ if (first) ++ { ++ rtx insn; + -+ gcc_assert (!const_store || !load); -+ /* Check that the memory references are immediate offsets from the -+ same base register. Extract the base register, the destination -+ registers, and the corresponding memory offsets. */ -+ for (i = 0; i < nops; i++) -+ { -+ if (!mem_ok_for_ldrd_strd (operands[nops+i], &cur_base, &cur_offset)) -+ return false; ++ first = false; ++ mem1 = gen_frame_mem (Pmode, plus_constant (Pmode, ++ stack_pointer_rtx, ++ -4 * num_regs)); ++ mem2 = gen_frame_mem (Pmode, plus_constant (Pmode, ++ stack_pointer_rtx, ++ -4 * (num_regs - 1))); ++ tmp0 = gen_rtx_SET (VOIDmode, stack_pointer_rtx, ++ plus_constant (Pmode, stack_pointer_rtx, ++ -4 * (num_regs))); ++ tmp1 = gen_rtx_SET (VOIDmode, mem1, reg1); ++ tmp2 = gen_rtx_SET (VOIDmode, mem2, reg2); ++ RTX_FRAME_RELATED_P (tmp0) = 1; ++ RTX_FRAME_RELATED_P (tmp1) = 1; ++ RTX_FRAME_RELATED_P (tmp2) = 1; ++ par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); ++ XVECEXP (par, 0, 0) = tmp0; ++ XVECEXP (par, 0, 1) = tmp1; ++ XVECEXP (par, 0, 2) = tmp2; ++ insn = emit_insn (par); ++ RTX_FRAME_RELATED_P (insn) = 1; ++ add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); ++ } ++ else ++ { ++ mem1 = gen_frame_mem (Pmode, plus_constant (Pmode, ++ stack_pointer_rtx, ++ 4 * i)); ++ mem2 = gen_frame_mem (Pmode, plus_constant (Pmode, ++ stack_pointer_rtx, ++ 4 * (i + 1))); ++ tmp1 = gen_rtx_SET (VOIDmode, mem1, reg1); ++ tmp2 = gen_rtx_SET (VOIDmode, mem2, reg2); ++ RTX_FRAME_RELATED_P (tmp1) = 1; ++ RTX_FRAME_RELATED_P (tmp2) = 1; ++ par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); ++ XVECEXP (par, 0, 0) = tmp1; ++ XVECEXP (par, 0, 1) = tmp2; ++ emit_insn (par); ++ } + -+ if (i == 0) -+ base = cur_base; -+ else if (REGNO (base) != REGNO (cur_base)) -+ return false; ++ /* Create unwind information. This is an approximation. */ ++ tmp1 = gen_rtx_SET (VOIDmode, ++ gen_frame_mem (Pmode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ 4 * i)), ++ reg1); ++ tmp2 = gen_rtx_SET (VOIDmode, ++ gen_frame_mem (Pmode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ 4 * (i + 1))), ++ reg2); ++ ++ RTX_FRAME_RELATED_P (tmp1) = 1; ++ RTX_FRAME_RELATED_P (tmp2) = 1; ++ XVECEXP (dwarf, 0, i + 1) = tmp1; ++ XVECEXP (dwarf, 0, i + 2) = tmp2; ++ i += 2; ++ regno = regno2 + 1; ++ } ++ else ++ regno++; + -+ offsets[i] = INTVAL (cur_offset); -+ if (GET_CODE (operands[i]) == SUBREG) -+ { -+ tmp = SUBREG_REG (operands[i]); -+ gcc_assert (GET_MODE (operands[i]) == GET_MODE (tmp)); -+ operands[i] = tmp; -+ } -+ } ++ return; ++} + -+ /* Make sure there is no dependency between the individual loads. */ -+ if (load && REGNO (operands[0]) == REGNO (base)) -+ return false; /* RAW */ ++/* STRD in ARM mode requires consecutive registers. This function emits STRD ++ whenever possible, otherwise it emits single-word stores. The first store ++ also allocates stack space for all saved registers, using writeback with ++ post-addressing mode. All other stores use offset addressing. If no STRD ++ can be emitted, this function emits a sequence of single-word stores, ++ and not an STM as before, because single-word stores provide more freedom ++ scheduling and can be turned into an STM by peephole optimizations. */ ++static void ++arm_emit_strd_push (unsigned long saved_regs_mask) ++{ ++ int num_regs = 0; ++ int i, j, dwarf_index = 0; ++ int offset = 0; ++ rtx dwarf = NULL_RTX; ++ rtx insn = NULL_RTX; ++ rtx tmp, mem; + -+ if (load && REGNO (operands[0]) == REGNO (operands[1])) -+ return false; /* WAW */ ++ /* TODO: A more efficient code can be emitted by changing the ++ layout, e.g., first push all pairs that can use STRD to keep the ++ stack aligned, and then push all other registers. */ + for (i = 0; i <= LAST_ARM_REGNUM; i++) + if (saved_regs_mask & (1 << i)) + num_regs++; + +- gcc_assert (num_regs && num_regs <= 16); ++ gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM))); ++ gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); ++ gcc_assert (num_regs > 0); + +- /* Pre-decrement the stack pointer, based on there being num_regs 4-byte +- registers to push. */ +- tmp = gen_rtx_SET (VOIDmode, +- stack_pointer_rtx, +- plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs)); +- RTX_FRAME_RELATED_P (tmp) = 1; +- insn = emit_insn (tmp); +- + /* Create sequence for DWARF info. */ + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1)); + +- /* RTLs cannot be shared, hence create new copy for dwarf. */ +- tmp1 = gen_rtx_SET (VOIDmode, ++ /* For dwarf info, we generate explicit stack update. */ ++ tmp = gen_rtx_SET (VOIDmode, + stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs)); +- RTX_FRAME_RELATED_P (tmp1) = 1; +- XVECEXP (dwarf, 0, 0) = tmp1; ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (dwarf, 0, dwarf_index++) = tmp; + +- gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM))); +- gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); +- +- /* Var j iterates over all the registers to gather all the registers in +- saved_regs_mask. Var i gives index of register R_j in stack frame. +- A PARALLEL RTX of register-pair is created here, so that pattern for +- STRD can be matched. If num_regs is odd, 1st register will be pushed +- using STR and remaining registers will be pushed with STRD in pairs. +- If num_regs is even, all registers are pushed with STRD in pairs. +- Hence, skip first element for odd num_regs. */ +- for (i = num_regs - 1, j = LAST_ARM_REGNUM; i >= (num_regs % 2); j--) ++ /* Save registers. */ ++ offset = - 4 * num_regs; ++ j = 0; ++ while (j <= LAST_ARM_REGNUM) + if (saved_regs_mask & (1 << j)) + { +- /* Create RTX for store. New RTX is created for dwarf as +- they are not sharable. */ +- reg = gen_rtx_REG (SImode, j); +- tmp = gen_rtx_SET (SImode, +- gen_frame_mem +- (SImode, +- plus_constant (Pmode, stack_pointer_rtx, 4 * i)), +- reg); ++ if ((j % 2 == 0) ++ && (saved_regs_mask & (1 << (j + 1)))) ++ { ++ /* Current register and previous register form register pair for ++ which STRD can be generated. */ ++ if (offset < 0) ++ { ++ /* Allocate stack space for all saved registers. */ ++ tmp = plus_constant (Pmode, stack_pointer_rtx, offset); ++ tmp = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, tmp); ++ mem = gen_frame_mem (DImode, tmp); ++ offset = 0; ++ } ++ else if (offset > 0) ++ mem = gen_frame_mem (DImode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ offset)); ++ else ++ mem = gen_frame_mem (DImode, stack_pointer_rtx); + +- tmp1 = gen_rtx_SET (SImode, +- gen_frame_mem +- (SImode, +- plus_constant (Pmode, stack_pointer_rtx, 4 * i)), +- reg); +- RTX_FRAME_RELATED_P (tmp) = 1; +- RTX_FRAME_RELATED_P (tmp1) = 1; ++ tmp = gen_rtx_SET (DImode, mem, gen_rtx_REG (DImode, j)); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ tmp = emit_insn (tmp); + +- if (((i - (num_regs % 2)) % 2) == 1) +- /* When (i - (num_regs % 2)) is odd, the RTX to be emitted is yet to +- be created. Hence create it first. The STRD pattern we are +- generating is : +- [ (SET (MEM (PLUS (SP) (NUM))) (reg_t1)) +- (SET (MEM (PLUS (SP) (NUM + 4))) (reg_t2)) ] +- where the target registers need not be consecutive. */ +- par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); ++ /* Record the first store insn. */ ++ if (dwarf_index == 1) ++ insn = tmp; + +- /* Register R_j is added in PARALLEL RTX. If (i - (num_regs % 2)) is +- even, the reg_j is added as 0th element and if it is odd, reg_i is +- added as 1st element of STRD pattern shown above. */ +- XVECEXP (par, 0, ((i - (num_regs % 2)) % 2)) = tmp; +- XVECEXP (dwarf, 0, (i + 1)) = tmp1; ++ /* Generate dwarf info. */ ++ mem = gen_frame_mem (SImode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ offset)); ++ tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (dwarf, 0, dwarf_index++) = tmp; + +- if (((i - (num_regs % 2)) % 2) == 0) +- /* When (i - (num_regs % 2)) is even, RTXs for both the registers +- to be loaded are generated in above given STRD pattern, and the +- pattern can be emitted now. */ +- emit_insn (par); ++ mem = gen_frame_mem (SImode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ offset + 4)); ++ tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j + 1)); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (dwarf, 0, dwarf_index++) = tmp; + +- i--; +- } ++ offset += 8; ++ j += 2; ++ } ++ else ++ { ++ /* Emit a single word store. */ ++ if (offset < 0) ++ { ++ /* Allocate stack space for all saved registers. */ ++ tmp = plus_constant (Pmode, stack_pointer_rtx, offset); ++ tmp = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, tmp); ++ mem = gen_frame_mem (SImode, tmp); ++ offset = 0; ++ } ++ else if (offset > 0) ++ mem = gen_frame_mem (SImode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ offset)); ++ else ++ mem = gen_frame_mem (SImode, stack_pointer_rtx); + +- if ((num_regs % 2) == 1) +- { +- /* If odd number of registers are pushed, generate STR pattern to store +- lone register. */ +- for (; (saved_regs_mask & (1 << j)) == 0; j--); ++ tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ tmp = emit_insn (tmp); + +- tmp1 = gen_frame_mem (SImode, plus_constant (Pmode, +- stack_pointer_rtx, 4 * i)); +- reg = gen_rtx_REG (SImode, j); +- tmp = gen_rtx_SET (SImode, tmp1, reg); +- RTX_FRAME_RELATED_P (tmp) = 1; ++ /* Record the first store insn. */ ++ if (dwarf_index == 1) ++ insn = tmp; + +- emit_insn (tmp); ++ /* Generate dwarf info. */ ++ mem = gen_frame_mem (SImode, ++ plus_constant(Pmode, ++ stack_pointer_rtx, ++ offset)); ++ tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (dwarf, 0, dwarf_index++) = tmp; + +- tmp1 = gen_rtx_SET (SImode, +- gen_frame_mem +- (SImode, +- plus_constant (Pmode, stack_pointer_rtx, 4 * i)), +- reg); +- RTX_FRAME_RELATED_P (tmp1) = 1; +- XVECEXP (dwarf, 0, (i + 1)) = tmp1; +- } ++ offset += 4; ++ j += 1; ++ } ++ } ++ else ++ j++; + ++ /* Attach dwarf info to the first insn we generate. */ ++ gcc_assert (insn != NULL_RTX); + add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); + RTX_FRAME_RELATED_P (insn) = 1; +- return; + } + + /* Generate and emit an insn that we will recognize as a push_multi. +@@ -16551,6 +17239,19 @@ + return par; + } + ++/* Add a REG_CFA_ADJUST_CFA REG note to INSN. ++ SIZE is the offset to be adjusted. ++ DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx. */ ++static void ++arm_add_cfa_adjust_cfa_note (rtx insn, int size, rtx dest, rtx src) ++{ ++ rtx dwarf; + -+ /* If the same input register is used in both stores -+ when storing different constants, try to find a free register. -+ For example, the code -+ mov r0, 0 -+ str r0, [r2] -+ mov r0, 1 -+ str r0, [r2, #4] -+ can be transformed into -+ mov r1, 0 -+ strd r1, r0, [r2] -+ in Thumb mode assuming that r1 is free. */ -+ if (const_store -+ && REGNO (operands[0]) == REGNO (operands[1]) -+ && INTVAL (operands[4]) != INTVAL (operands[5])) ++ RTX_FRAME_RELATED_P (insn) = 1; ++ dwarf = gen_rtx_SET (VOIDmode, dest, plus_constant (Pmode, src, size)); ++ add_reg_note (insn, REG_CFA_ADJUST_CFA, dwarf); ++} ++ + /* Generate and emit an insn pattern that we will recognize as a pop_multi. + SAVED_REGS_MASK shows which registers need to be restored. + +@@ -16608,6 +17309,17 @@ + if (saved_regs_mask & (1 << i)) + { + reg = gen_rtx_REG (SImode, i); ++ if ((num_regs == 1) && emit_update && !return_in_pc) ++ { ++ /* Emit single load with writeback. */ ++ tmp = gen_frame_mem (SImode, ++ gen_rtx_POST_INC (Pmode, ++ stack_pointer_rtx)); ++ tmp = emit_insn (gen_rtx_SET (VOIDmode, reg, tmp)); ++ REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); ++ return; ++ } ++ + tmp = gen_rtx_SET (VOIDmode, + reg, + gen_frame_mem +@@ -16630,6 +17342,9 @@ + par = emit_insn (par); + + REG_NOTES (par) = dwarf; ++ if (!return_in_pc) ++ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs, ++ stack_pointer_rtx, stack_pointer_rtx); + } + + /* Generate and emit an insn pattern that we will recognize as a pop_multi +@@ -16700,6 +17415,9 @@ + + par = emit_insn (par); + REG_NOTES (par) = dwarf; ++ ++ arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs, ++ base_reg, base_reg); + } + + /* Generate and emit a pattern that will be recognized as LDRD pattern. If even +@@ -16775,6 +17493,7 @@ + pattern can be emitted now. */ + par = emit_insn (par); + REG_NOTES (par) = dwarf; ++ RTX_FRAME_RELATED_P (par) = 1; + } + + i++; +@@ -16791,7 +17510,12 @@ + stack_pointer_rtx, + plus_constant (Pmode, stack_pointer_rtx, 4 * i)); + RTX_FRAME_RELATED_P (tmp) = 1; +- emit_insn (tmp); ++ tmp = emit_insn (tmp); ++ if (!return_in_pc) + { -+ if (TARGET_THUMB2) -+ { -+ CLEAR_HARD_REG_SET (regset); -+ tmp = peep2_find_free_register (0, 4, "r", SImode, ®set); -+ if (tmp == NULL_RTX) -+ return false; ++ arm_add_cfa_adjust_cfa_note (tmp, UNITS_PER_WORD * i, ++ stack_pointer_rtx, stack_pointer_rtx); ++ } + + dwarf = NULL_RTX; + +@@ -16825,9 +17549,11 @@ + else + { + par = emit_insn (tmp); ++ REG_NOTES (par) = dwarf; ++ arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD, ++ stack_pointer_rtx, stack_pointer_rtx); + } + +- REG_NOTES (par) = dwarf; + } + else if ((num_regs % 2) == 1 && return_in_pc) + { +@@ -16839,6 +17565,129 @@ + return; + } + ++/* LDRD in ARM mode needs consecutive registers as operands. This function ++ emits LDRD whenever possible, otherwise it emits single-word loads. It uses ++ offset addressing and then generates one separate stack udpate. This provides ++ more scheduling freedom, compared to writeback on every load. However, ++ if the function returns using load into PC directly ++ (i.e., if PC is in SAVED_REGS_MASK), the stack needs to be updated ++ before the last load. TODO: Add a peephole optimization to recognize ++ the new epilogue sequence as an LDM instruction whenever possible. TODO: Add ++ peephole optimization to merge the load at stack-offset zero ++ with the stack update instruction using load with writeback ++ in post-index addressing mode. */ ++static void ++arm_emit_ldrd_pop (unsigned long saved_regs_mask) ++{ ++ int j = 0; ++ int offset = 0; ++ rtx par = NULL_RTX; ++ rtx dwarf = NULL_RTX; ++ rtx tmp, mem; + -+ /* Use the new register in the first load to ensure that -+ if the original input register is not dead after peephole, -+ then it will have the correct constant value. */ -+ operands[0] = tmp; -+ } -+ else if (TARGET_ARM) ++ /* Restore saved registers. */ ++ gcc_assert (!((saved_regs_mask & (1 << SP_REGNUM)))); ++ j = 0; ++ while (j <= LAST_ARM_REGNUM) ++ if (saved_regs_mask & (1 << j)) + { -+ return false; -+ int regno = REGNO (operands[0]); -+ if (!peep2_reg_dead_p (4, operands[0])) ++ if ((j % 2) == 0 ++ && (saved_regs_mask & (1 << (j + 1))) ++ && (j + 1) != PC_REGNUM) + { -+ /* When the input register is even and is not dead after the -+ pattern, it has to hold the second constant but we cannot -+ form a legal STRD in ARM mode with this register as the second -+ register. */ -+ if (regno % 2 == 0) -+ return false; ++ /* Current register and next register form register pair for which ++ LDRD can be generated. PC is always the last register popped, and ++ we handle it separately. */ ++ if (offset > 0) ++ mem = gen_frame_mem (DImode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ offset)); ++ else ++ mem = gen_frame_mem (DImode, stack_pointer_rtx); + -+ /* Is regno-1 free? */ -+ SET_HARD_REG_SET (regset); -+ CLEAR_HARD_REG_BIT(regset, regno - 1); -+ tmp = peep2_find_free_register (0, 4, "r", SImode, ®set); -+ if (tmp == NULL_RTX) -+ return false; ++ tmp = gen_rtx_SET (DImode, gen_rtx_REG (DImode, j), mem); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ tmp = emit_insn (tmp); + -+ operands[0] = tmp; -+ } -+ else -+ { -+ /* Find a DImode register. */ -+ CLEAR_HARD_REG_SET (regset); -+ tmp = peep2_find_free_register (0, 4, "r", DImode, ®set); -+ if (tmp != NULL_RTX) -+ { -+ operands[0] = simplify_gen_subreg (SImode, tmp, DImode, 0); -+ operands[1] = simplify_gen_subreg (SImode, tmp, DImode, 4); -+ } -+ else -+ { -+ /* Can we use the input register to form a DI register? */ -+ SET_HARD_REG_SET (regset); -+ CLEAR_HARD_REG_BIT(regset, -+ regno % 2 == 0 ? regno + 1 : regno - 1); -+ tmp = peep2_find_free_register (0, 4, "r", SImode, ®set); -+ if (tmp == NULL_RTX) -+ return false; -+ operands[regno % 2 == 1 ? 0 : 1] = tmp; -+ } -+ } ++ /* Generate dwarf info. */ + -+ gcc_assert (operands[0] != NULL_RTX); -+ gcc_assert (operands[1] != NULL_RTX); -+ gcc_assert (REGNO (operands[0]) % 2 == 0); -+ gcc_assert (REGNO (operands[1]) == REGNO (operands[0]) + 1); -+ } -+ } ++ dwarf = alloc_reg_note (REG_CFA_RESTORE, ++ gen_rtx_REG (SImode, j), ++ NULL_RTX); ++ dwarf = alloc_reg_note (REG_CFA_RESTORE, ++ gen_rtx_REG (SImode, j + 1), ++ dwarf); + -+ /* Make sure the instructions are ordered with lower memory access first. */ -+ if (offsets[0] > offsets[1]) -+ { -+ gap = offsets[0] - offsets[1]; -+ offset = offsets[1]; ++ REG_NOTES (tmp) = dwarf; + -+ /* Swap the instructions such that lower memory is accessed first. */ -+ SWAP_RTX (operands[0], operands[1]); -+ SWAP_RTX (operands[2], operands[3]); -+ if (const_store) -+ SWAP_RTX (operands[4], operands[5]); -+ } -+ else -+ { -+ gap = offsets[1] - offsets[0]; -+ offset = offsets[0]; -+ } ++ offset += 8; ++ j += 2; ++ } ++ else if (j != PC_REGNUM) ++ { ++ /* Emit a single word load. */ ++ if (offset > 0) ++ mem = gen_frame_mem (SImode, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ offset)); ++ else ++ mem = gen_frame_mem (SImode, stack_pointer_rtx); + -+ /* Make sure accesses are to consecutive memory locations. */ -+ if (gap != 4) -+ return false; ++ tmp = gen_rtx_SET (SImode, gen_rtx_REG (SImode, j), mem); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ tmp = emit_insn (tmp); + -+ /* Make sure we generate legal instructions. */ -+ if (operands_ok_ldrd_strd (operands[0], operands[1], base, offset, -+ false, load)) -+ return true; ++ /* Generate dwarf info. */ ++ REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, ++ gen_rtx_REG (SImode, j), ++ NULL_RTX); + -+ /* In Thumb state, where registers are almost unconstrained, there -+ is little hope to fix it. */ -+ if (TARGET_THUMB2) -+ return false; ++ offset += 4; ++ j += 1; ++ } ++ else /* j == PC_REGNUM */ ++ j++; ++ } ++ else ++ j++; + -+ if (load && commute) ++ /* Update the stack. */ ++ if (offset > 0) + { -+ /* Try reordering registers. */ -+ SWAP_RTX (operands[0], operands[1]); -+ if (operands_ok_ldrd_strd (operands[0], operands[1], base, offset, -+ false, load)) -+ return true; ++ tmp = gen_rtx_SET (Pmode, ++ stack_pointer_rtx, ++ plus_constant (Pmode, ++ stack_pointer_rtx, ++ offset)); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ emit_insn (tmp); ++ offset = 0; + } + -+ if (const_store) ++ if (saved_regs_mask & (1 << PC_REGNUM)) + { -+ /* If input registers are dead after this pattern, they can be -+ reordered or replaced by other registers that are free in the -+ current pattern. */ -+ if (!peep2_reg_dead_p (4, operands[0]) -+ || !peep2_reg_dead_p (4, operands[1])) -+ return false; -+ -+ /* Try to reorder the input registers. */ -+ /* For example, the code -+ mov r0, 0 -+ mov r1, 1 -+ str r1, [r2] -+ str r0, [r2, #4] -+ can be transformed into -+ mov r1, 0 -+ mov r0, 1 -+ strd r0, [r2] -+ */ -+ if (operands_ok_ldrd_strd (operands[1], operands[0], base, offset, -+ false, false)) -+ { -+ SWAP_RTX (operands[0], operands[1]); -+ return true; -+ } -+ -+ /* Try to find a free DI register. */ -+ CLEAR_HARD_REG_SET (regset); -+ add_to_hard_reg_set (®set, SImode, REGNO (operands[0])); -+ add_to_hard_reg_set (®set, SImode, REGNO (operands[1])); -+ while (true) -+ { -+ tmp = peep2_find_free_register (0, 4, "r", DImode, ®set); -+ if (tmp == NULL_RTX) -+ return false; -+ -+ /* DREG must be an even-numbered register in DImode. -+ Split it into SI registers. */ -+ operands[0] = simplify_gen_subreg (SImode, tmp, DImode, 0); -+ operands[1] = simplify_gen_subreg (SImode, tmp, DImode, 4); -+ gcc_assert (operands[0] != NULL_RTX); -+ gcc_assert (operands[1] != NULL_RTX); -+ gcc_assert (REGNO (operands[0]) % 2 == 0); -+ gcc_assert (REGNO (operands[0]) + 1 == REGNO (operands[1])); ++ /* Only PC is to be popped. */ ++ par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); ++ XVECEXP (par, 0, 0) = ret_rtx; ++ tmp = gen_rtx_SET (SImode, ++ gen_rtx_REG (SImode, PC_REGNUM), ++ gen_frame_mem (SImode, ++ gen_rtx_POST_INC (SImode, ++ stack_pointer_rtx))); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (par, 0, 1) = tmp; ++ par = emit_jump_insn (par); + -+ return (operands_ok_ldrd_strd (operands[0], operands[1], -+ base, offset, -+ false, load)); -+ } ++ /* Generate dwarf info. */ ++ dwarf = alloc_reg_note (REG_CFA_RESTORE, ++ gen_rtx_REG (SImode, PC_REGNUM), ++ NULL_RTX); ++ REG_NOTES (par) = dwarf; + } ++} ++ + /* Calculate the size of the return value that is passed in registers. */ + static unsigned + arm_size_return_regs (void) +@@ -16863,11 +17712,27 @@ + || df_regs_ever_live_p (LR_REGNUM)); + } + ++/* We do not know if r3 will be available because ++ we do have an indirect tailcall happening in this ++ particular case. */ ++static bool ++is_indirect_tailcall_p (rtx call) ++{ ++ rtx pat = PATTERN (call); + ++ /* Indirect tail call. */ ++ pat = XVECEXP (pat, 0, 0); ++ if (GET_CODE (pat) == SET) ++ pat = SET_SRC (pat); + -+ return false; ++ pat = XEXP (XEXP (pat, 0), 0); ++ return REG_P (pat); +} -+#undef SWAP_RTX + + /* Return true if r3 is used by any of the tail call insns in the + current function. */ + static bool +-any_sibcall_uses_r3 (void) ++any_sibcall_could_use_r3 (void) + { + edge_iterator ei; + edge e; +@@ -16881,7 +17746,8 @@ + if (!CALL_P (call)) + call = prev_nonnote_nondebug_insn (call); + gcc_assert (CALL_P (call) && SIBLING_CALL_P (call)); +- if (find_regno_fusage (call, USE, 3)) ++ if (find_regno_fusage (call, USE, 3) ++ || is_indirect_tailcall_p (call)) + return true; + } + return false; +@@ -17048,9 +17914,11 @@ + /* If it is safe to use r3, then do so. This sometimes + generates better code on Thumb-2 by avoiding the need to + use 32-bit push/pop instructions. */ +- if (! any_sibcall_uses_r3 () ++ if (! any_sibcall_could_use_r3 () + && arm_size_return_regs () <= 12 +- && (offsets->saved_regs_mask & (1 << 3)) == 0) ++ && (offsets->saved_regs_mask & (1 << 3)) == 0 ++ && (TARGET_THUMB2 ++ || !(TARGET_LDRD && current_tune->prefer_ldrd_strd))) + { + reg = 3; + } +@@ -17483,6 +18351,12 @@ + { + thumb2_emit_strd_push (live_regs_mask); + } ++ else if (TARGET_ARM ++ && !TARGET_APCS_FRAME ++ && !IS_INTERRUPT (func_type)) ++ { ++ arm_emit_strd_push (live_regs_mask); ++ } + else + { + insn = emit_multi_reg_push (live_regs_mask); +@@ -18760,7 +19634,14 @@ + enum arm_cond_code code; + int n; + int mask; ++ int max; + ++ /* Maximum number of conditionally executed instructions in a block ++ is minimum of the two max values: maximum allowed in an IT block ++ and maximum that is beneficial according to the cost model and tune. */ ++ max = (max_insns_skipped < MAX_INSN_PER_IT_BLOCK) ? ++ max_insns_skipped : MAX_INSN_PER_IT_BLOCK; ++ + /* Remove the previous insn from the count of insns to be output. */ + if (arm_condexec_count) + arm_condexec_count--; +@@ -18802,9 +19683,9 @@ + /* ??? Recognize conditional jumps, and combine them with IT blocks. */ + if (GET_CODE (body) != COND_EXEC) + break; +- /* Allow up to 4 conditionally executed instructions in a block. */ ++ /* Maximum number of conditionally executed instructions in a block. */ + n = get_attr_ce_count (insn); +- if (arm_condexec_masklen + n > 4) ++ if (arm_condexec_masklen + n > max) + break; + + predicate = COND_EXEC_TEST (body); +@@ -19362,6 +20243,7 @@ + typedef enum { + T_V8QI, + T_V4HI, ++ T_V4HF, + T_V2SI, + T_V2SF, + T_DI, +@@ -19379,14 +20261,15 @@ + #define TYPE_MODE_BIT(X) (1 << (X)) + + #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \ +- | TYPE_MODE_BIT (T_V2SI) | TYPE_MODE_BIT (T_V2SF) \ +- | TYPE_MODE_BIT (T_DI)) ++ | TYPE_MODE_BIT (T_V4HF) | TYPE_MODE_BIT (T_V2SI) \ ++ | TYPE_MODE_BIT (T_V2SF) | TYPE_MODE_BIT (T_DI)) + #define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \ + | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \ + | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI)) + + #define v8qi_UP T_V8QI + #define v4hi_UP T_V4HI ++#define v4hf_UP T_V4HF + #define v2si_UP T_V2SI + #define v2sf_UP T_V2SF + #define di_UP T_DI +@@ -19422,6 +20305,8 @@ + NEON_SCALARMULH, + NEON_SCALARMAC, + NEON_CONVERT, ++ NEON_FLOAT_WIDEN, ++ NEON_FLOAT_NARROW, + NEON_FIXCONV, + NEON_SELECT, + NEON_RESULTPAIR, +@@ -19482,7 +20367,8 @@ + VAR9 (T, N, A, B, C, D, E, F, G, H, I), \ + {#N, NEON_##T, UP (J), CF (N, J), 0} + +-/* The mode entries in the following table correspond to the "key" type of the ++/* The NEON builtin data can be found in arm_neon_builtins.def. ++ The mode entries in the following table correspond to the "key" type of the + instruction variant, i.e. equivalent to that which would be specified after + the assembler mnemonic, which usually refers to the last vector operand. + (Signed/unsigned/polynomial types are not differentiated between though, and +@@ -19492,196 +20378,7 @@ + + static neon_builtin_datum neon_builtin_data[] = + { +- VAR10 (BINOP, vadd, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR3 (BINOP, vaddl, v8qi, v4hi, v2si), +- VAR3 (BINOP, vaddw, v8qi, v4hi, v2si), +- VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR3 (BINOP, vaddhn, v8hi, v4si, v2di), +- VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si), +- VAR2 (TERNOP, vfma, v2sf, v4sf), +- VAR2 (TERNOP, vfms, v2sf, v4sf), +- VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si), +- VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si), +- VAR2 (TERNOP, vqdmlal, v4hi, v2si), +- VAR2 (TERNOP, vqdmlsl, v4hi, v2si), +- VAR3 (BINOP, vmull, v8qi, v4hi, v2si), +- VAR2 (SCALARMULL, vmull_n, v4hi, v2si), +- VAR2 (LANEMULL, vmull_lane, v4hi, v2si), +- VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si), +- VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si), +- VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si), +- VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si), +- VAR2 (BINOP, vqdmull, v4hi, v2si), +- VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di), +- VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di), +- VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di), +- VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si), +- VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR10 (BINOP, vsub, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR3 (BINOP, vsubl, v8qi, v4hi, v2si), +- VAR3 (BINOP, vsubw, v8qi, v4hi, v2si), +- VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR3 (BINOP, vsubhn, v8hi, v4si, v2di), +- VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR6 (BINOP, vcgeu, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR2 (BINOP, vcage, v2sf, v4sf), +- VAR2 (BINOP, vcagt, v2sf, v4sf), +- VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR3 (BINOP, vabdl, v8qi, v4hi, v2si), +- VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR3 (TERNOP, vabal, v8qi, v4hi, v2si), +- VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf), +- VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf), +- VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf), +- VAR2 (BINOP, vrecps, v2sf, v4sf), +- VAR2 (BINOP, vrsqrts, v2sf, v4sf), +- VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), +- VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- VAR2 (UNOP, vcnt, v8qi, v16qi), +- VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf), +- VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf), +- VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si), +- /* FIXME: vget_lane supports more variants than this! */ +- VAR10 (GETLANE, vget_lane, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (SETLANE, vset_lane, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di), +- VAR10 (DUP, vdup_n, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (DUPLANE, vdup_lane, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di), +- VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di), +- VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di), +- VAR3 (UNOP, vmovn, v8hi, v4si, v2di), +- VAR3 (UNOP, vqmovn, v8hi, v4si, v2di), +- VAR3 (UNOP, vqmovun, v8hi, v4si, v2di), +- VAR3 (UNOP, vmovl, v8qi, v4hi, v2si), +- VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR2 (LANEMAC, vmlal_lane, v4hi, v2si), +- VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si), +- VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si), +- VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si), +- VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR2 (SCALARMAC, vmlal_n, v4hi, v2si), +- VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si), +- VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si), +- VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si), +- VAR10 (BINOP, vext, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi), +- VAR2 (UNOP, vrev16, v8qi, v16qi), +- VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf), +- VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf), +- VAR10 (SELECT, vbsl, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR2 (RINT, vrintn, v2sf, v4sf), +- VAR2 (RINT, vrinta, v2sf, v4sf), +- VAR2 (RINT, vrintp, v2sf, v4sf), +- VAR2 (RINT, vrintm, v2sf, v4sf), +- VAR2 (RINT, vrintz, v2sf, v4sf), +- VAR2 (RINT, vrintx, v2sf, v4sf), +- VAR1 (VTBL, vtbl1, v8qi), +- VAR1 (VTBL, vtbl2, v8qi), +- VAR1 (VTBL, vtbl3, v8qi), +- VAR1 (VTBL, vtbl4, v8qi), +- VAR1 (VTBX, vtbx1, v8qi), +- VAR1 (VTBX, vtbx2, v8qi), +- VAR1 (VTBX, vtbx3, v8qi), +- VAR1 (VTBX, vtbx4, v8qi), +- VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), +- VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di), +- VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di), +- VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di), +- VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di), +- VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di), +- VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di), +- VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di), +- VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di), +- VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di), +- VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (LOAD1, vld1, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (LOAD1LANE, vld1_lane, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (LOAD1, vld1_dup, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (STORE1, vst1, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (STORE1LANE, vst1_lane, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR9 (LOADSTRUCT, +- vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), +- VAR7 (LOADSTRUCTLANE, vld2_lane, +- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di), +- VAR9 (STORESTRUCT, vst2, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), +- VAR7 (STORESTRUCTLANE, vst2_lane, +- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR9 (LOADSTRUCT, +- vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), +- VAR7 (LOADSTRUCTLANE, vld3_lane, +- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di), +- VAR9 (STORESTRUCT, vst3, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), +- VAR7 (STORESTRUCTLANE, vst3_lane, +- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR9 (LOADSTRUCT, vld4, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), +- VAR7 (LOADSTRUCTLANE, vld4_lane, +- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di), +- VAR9 (STORESTRUCT, vst4, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), +- VAR7 (STORESTRUCTLANE, vst4_lane, +- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), +- VAR10 (LOGICBINOP, vand, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (LOGICBINOP, vorr, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (BINOP, veor, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (LOGICBINOP, vbic, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), +- VAR10 (LOGICBINOP, vorn, +- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) ++#include "arm_neon_builtins.def" + }; + + #undef CF +@@ -19696,9 +20393,36 @@ + #undef VAR9 + #undef VAR10 + +-/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have +- symbolic names defined here (which would require too much duplication). +- FIXME? */ ++#define CF(N,X) ARM_BUILTIN_NEON_##N##X ++#define VAR1(T, N, A) \ ++ CF (N, A) ++#define VAR2(T, N, A, B) \ ++ VAR1 (T, N, A), \ ++ CF (N, B) ++#define VAR3(T, N, A, B, C) \ ++ VAR2 (T, N, A, B), \ ++ CF (N, C) ++#define VAR4(T, N, A, B, C, D) \ ++ VAR3 (T, N, A, B, C), \ ++ CF (N, D) ++#define VAR5(T, N, A, B, C, D, E) \ ++ VAR4 (T, N, A, B, C, D), \ ++ CF (N, E) ++#define VAR6(T, N, A, B, C, D, E, F) \ ++ VAR5 (T, N, A, B, C, D, E), \ ++ CF (N, F) ++#define VAR7(T, N, A, B, C, D, E, F, G) \ ++ VAR6 (T, N, A, B, C, D, E, F), \ ++ CF (N, G) ++#define VAR8(T, N, A, B, C, D, E, F, G, H) \ ++ VAR7 (T, N, A, B, C, D, E, F, G), \ ++ CF (N, H) ++#define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ ++ VAR8 (T, N, A, B, C, D, E, F, G, H), \ ++ CF (N, I) ++#define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ ++ VAR9 (T, N, A, B, C, D, E, F, G, H, I), \ ++ CF (N, J) + enum arm_builtins + { + ARM_BUILTIN_GETWCGR0, +@@ -19947,11 +20671,25 @@ + + ARM_BUILTIN_WMERGE, + +- ARM_BUILTIN_NEON_BASE, ++#include "arm_neon_builtins.def" + +- ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE + ARRAY_SIZE (neon_builtin_data) ++ ,ARM_BUILTIN_MAX + }; + ++#define ARM_BUILTIN_NEON_BASE (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data)) + ++#undef CF ++#undef VAR1 ++#undef VAR2 ++#undef VAR3 ++#undef VAR4 ++#undef VAR5 ++#undef VAR6 ++#undef VAR7 ++#undef VAR8 ++#undef VAR9 ++#undef VAR10 + - - /* Print a symbolic form of X to the debug file, F. */ + static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX]; + static void -@@ -14794,7 +15243,8 @@ - { - /* Constraints should ensure this. */ - gcc_assert (code0 == MEM && code1 == REG); -- gcc_assert (REGNO (operands[1]) != IP_REGNUM); -+ gcc_assert ((REGNO (operands[1]) != IP_REGNUM) -+ || (TARGET_ARM && TARGET_LDRD)); +@@ -19962,6 +20700,7 @@ - switch (GET_CODE (XEXP (operands[0], 0))) - { -@@ -16387,6 +16837,148 @@ - return; - } + tree neon_intQI_type_node; + tree neon_intHI_type_node; ++ tree neon_floatHF_type_node; + tree neon_polyQI_type_node; + tree neon_polyHI_type_node; + tree neon_intSI_type_node; +@@ -19988,6 +20727,7 @@ -+/* STRD in ARM mode requires consecutive registers. This function emits STRD -+ whenever possible, otherwise it emits single-word stores. The first store -+ also allocates stack space for all saved registers, using writeback with -+ post-addressing mode. All other stores use offset addressing. If no STRD -+ can be emitted, this function emits a sequence of single-word stores, -+ and not an STM as before, because single-word stores provide more freedom -+ scheduling and can be turned into an STM by peephole optimizations. */ -+static void -+arm_emit_strd_push (unsigned long saved_regs_mask) -+{ -+ int num_regs = 0; -+ int i, j, dwarf_index = 0; -+ int offset = 0; -+ rtx dwarf = NULL_RTX; -+ rtx insn = NULL_RTX; -+ rtx tmp, mem; -+ -+ /* TODO: A more efficient code can be emitted by changing the -+ layout, e.g., first push all pairs that can use STRD to keep the -+ stack aligned, and then push all other registers. */ -+ for (i = 0; i <= LAST_ARM_REGNUM; i++) -+ if (saved_regs_mask & (1 << i)) -+ num_regs++; -+ -+ gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM))); -+ gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); -+ gcc_assert (num_regs > 0); -+ -+ /* Create sequence for DWARF info. */ -+ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1)); -+ -+ /* For dwarf info, we generate explicit stack update. */ -+ tmp = gen_rtx_SET (VOIDmode, -+ stack_pointer_rtx, -+ plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs)); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ XVECEXP (dwarf, 0, dwarf_index++) = tmp; -+ -+ /* Save registers. */ -+ offset = - 4 * num_regs; -+ j = 0; -+ while (j <= LAST_ARM_REGNUM) -+ if (saved_regs_mask & (1 << j)) -+ { -+ if ((j % 2 == 0) -+ && (saved_regs_mask & (1 << (j + 1)))) -+ { -+ /* Current register and previous register form register pair for -+ which STRD can be generated. */ -+ if (offset < 0) -+ { -+ /* Allocate stack space for all saved registers. */ -+ tmp = plus_constant (Pmode, stack_pointer_rtx, offset); -+ tmp = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, tmp); -+ mem = gen_frame_mem (DImode, tmp); -+ offset = 0; -+ } -+ else if (offset > 0) -+ mem = gen_frame_mem (DImode, -+ plus_constant (Pmode, -+ stack_pointer_rtx, -+ offset)); -+ else -+ mem = gen_frame_mem (DImode, stack_pointer_rtx); -+ -+ tmp = gen_rtx_SET (DImode, mem, gen_rtx_REG (DImode, j)); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ tmp = emit_insn (tmp); -+ -+ /* Record the first store insn. */ -+ if (dwarf_index == 1) -+ insn = tmp; -+ -+ /* Generate dwarf info. */ -+ mem = gen_frame_mem (SImode, -+ plus_constant (Pmode, -+ stack_pointer_rtx, -+ offset)); -+ tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ XVECEXP (dwarf, 0, dwarf_index++) = tmp; -+ -+ mem = gen_frame_mem (SImode, -+ plus_constant (Pmode, -+ stack_pointer_rtx, -+ offset + 4)); -+ tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j + 1)); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ XVECEXP (dwarf, 0, dwarf_index++) = tmp; -+ -+ offset += 8; -+ j += 2; -+ } -+ else -+ { -+ /* Emit a single word store. */ -+ if (offset < 0) -+ { -+ /* Allocate stack space for all saved registers. */ -+ tmp = plus_constant (Pmode, stack_pointer_rtx, offset); -+ tmp = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, tmp); -+ mem = gen_frame_mem (SImode, tmp); -+ offset = 0; -+ } -+ else if (offset > 0) -+ mem = gen_frame_mem (SImode, -+ plus_constant (Pmode, -+ stack_pointer_rtx, -+ offset)); -+ else -+ mem = gen_frame_mem (SImode, stack_pointer_rtx); -+ -+ tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ tmp = emit_insn (tmp); -+ -+ /* Record the first store insn. */ -+ if (dwarf_index == 1) -+ insn = tmp; -+ -+ /* Generate dwarf info. */ -+ mem = gen_frame_mem (SImode, -+ plus_constant(Pmode, -+ stack_pointer_rtx, -+ offset)); -+ tmp = gen_rtx_SET (SImode, mem, gen_rtx_REG (SImode, j)); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ XVECEXP (dwarf, 0, dwarf_index++) = tmp; -+ -+ offset += 4; -+ j += 1; -+ } -+ } -+ else -+ j++; -+ -+ /* Attach dwarf info to the first insn we generate. */ -+ gcc_assert (insn != NULL_RTX); -+ add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); -+ RTX_FRAME_RELATED_P (insn) = 1; -+} + tree V8QI_type_node; + tree V4HI_type_node; ++ tree V4HF_type_node; + tree V2SI_type_node; + tree V2SF_type_node; + tree V16QI_type_node; +@@ -20042,6 +20782,9 @@ + neon_float_type_node = make_node (REAL_TYPE); + TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; + layout_type (neon_float_type_node); ++ neon_floatHF_type_node = make_node (REAL_TYPE); ++ TYPE_PRECISION (neon_floatHF_type_node) = GET_MODE_PRECISION (HFmode); ++ layout_type (neon_floatHF_type_node); + + /* Define typedefs which exactly correspond to the modes we are basing vector + types on. If you change these names you'll need to change +@@ -20050,6 +20793,8 @@ + "__builtin_neon_qi"); + (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, + "__builtin_neon_hi"); ++ (*lang_hooks.types.register_builtin_type) (neon_floatHF_type_node, ++ "__builtin_neon_hf"); + (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, + "__builtin_neon_si"); + (*lang_hooks.types.register_builtin_type) (neon_float_type_node, +@@ -20091,6 +20836,8 @@ + build_vector_type_for_mode (neon_intQI_type_node, V8QImode); + V4HI_type_node = + build_vector_type_for_mode (neon_intHI_type_node, V4HImode); ++ V4HF_type_node = ++ build_vector_type_for_mode (neon_floatHF_type_node, V4HFmode); + V2SI_type_node = + build_vector_type_for_mode (neon_intSI_type_node, V2SImode); + V2SF_type_node = +@@ -20213,7 +20960,7 @@ + neon_builtin_datum *d = &neon_builtin_data[i]; + + const char* const modenames[] = { +- "v8qi", "v4hi", "v2si", "v2sf", "di", ++ "v8qi", "v4hi", "v4hf", "v2si", "v2sf", "di", + "v16qi", "v8hi", "v4si", "v4sf", "v2di", + "ti", "ei", "oi" + }; +@@ -20416,8 +21163,9 @@ + case NEON_REINTERP: + { + /* We iterate over 5 doubleword types, then 5 quadword +- types. */ +- int rhs = d->mode % 5; ++ types. V4HF is not a type used in reinterpret, so we translate ++ d->mode to the correct index in reinterp_ftype_dreg. */ ++ int rhs = (d->mode - ((d->mode > T_V4HF) ? 1 : 0)) % 5; + switch (insn_data[d->code].operand[0].mode) + { + case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; +@@ -20434,7 +21182,38 @@ + } + } + break; ++ case NEON_FLOAT_WIDEN: ++ { ++ tree eltype = NULL_TREE; ++ tree return_type = NULL_TREE; + ++ switch (insn_data[d->code].operand[1].mode) ++ { ++ case V4HFmode: ++ eltype = V4HF_type_node; ++ return_type = V4SF_type_node; ++ break; ++ default: gcc_unreachable (); ++ } ++ ftype = build_function_type_list (return_type, eltype, NULL); ++ break; ++ } ++ case NEON_FLOAT_NARROW: ++ { ++ tree eltype = NULL_TREE; ++ tree return_type = NULL_TREE; + - /* Generate and emit an insn that we will recognize as a push_multi. - Unfortunately, since this insn does not reflect very well the actual - semantics of the operation, we need to annotate the insn for the benefit -@@ -16586,6 +17178,17 @@ ++ switch (insn_data[d->code].operand[1].mode) ++ { ++ case V4SFmode: ++ eltype = V4SF_type_node; ++ return_type = V4HF_type_node; ++ break; ++ default: gcc_unreachable (); ++ } ++ ftype = build_function_type_list (return_type, eltype, NULL); ++ break; ++ } + default: + gcc_unreachable (); + } +@@ -21431,6 +22210,8 @@ + case NEON_DUP: + case NEON_RINT: + case NEON_SPLIT: ++ case NEON_FLOAT_WIDEN: ++ case NEON_FLOAT_NARROW: + case NEON_REINTERP: + return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, + NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); +@@ -21628,7 +22409,7 @@ + rtx op1; + rtx op2; + rtx pat; +- int fcode = DECL_FUNCTION_CODE (fndecl); ++ unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + size_t i; + enum machine_mode tmode; + enum machine_mode mode0; +@@ -23345,7 +24126,7 @@ + all we really need to check here is if single register is to be + returned, or multiple register return. */ + void +-thumb2_expand_return (void) ++thumb2_expand_return (bool simple_return) + { + int i, num_regs; + unsigned long saved_regs_mask; +@@ -23358,7 +24139,7 @@ if (saved_regs_mask & (1 << i)) - { - reg = gen_rtx_REG (SImode, i); -+ if ((num_regs == 1) && emit_update && !return_in_pc) -+ { -+ /* Emit single load with writeback. */ -+ tmp = gen_frame_mem (SImode, -+ gen_rtx_POST_INC (Pmode, -+ stack_pointer_rtx)); -+ tmp = emit_insn (gen_rtx_SET (VOIDmode, reg, tmp)); -+ REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); -+ return; -+ } + num_regs++; + +- if (saved_regs_mask) ++ if (!simple_return && saved_regs_mask) + { + if (num_regs == 1) + { +@@ -23636,6 +24417,7 @@ + + if (frame_pointer_needed) + { ++ rtx insn; + /* Restore stack pointer if necessary. */ + if (TARGET_ARM) + { +@@ -23646,9 +24428,12 @@ + /* Force out any pending memory operations that reference stacked data + before stack de-allocation occurs. */ + emit_insn (gen_blockage ()); +- emit_insn (gen_addsi3 (stack_pointer_rtx, +- hard_frame_pointer_rtx, +- GEN_INT (amount))); ++ insn = emit_insn (gen_addsi3 (stack_pointer_rtx, ++ hard_frame_pointer_rtx, ++ GEN_INT (amount))); ++ arm_add_cfa_adjust_cfa_note (insn, amount, ++ stack_pointer_rtx, ++ hard_frame_pointer_rtx); + + /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not + deleted. */ +@@ -23658,16 +24443,25 @@ + { + /* In Thumb-2 mode, the frame pointer points to the last saved + register. */ +- amount = offsets->locals_base - offsets->saved_regs; +- if (amount) +- emit_insn (gen_addsi3 (hard_frame_pointer_rtx, +- hard_frame_pointer_rtx, +- GEN_INT (amount))); ++ amount = offsets->locals_base - offsets->saved_regs; ++ if (amount) ++ { ++ insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ++ hard_frame_pointer_rtx, ++ GEN_INT (amount))); ++ arm_add_cfa_adjust_cfa_note (insn, amount, ++ hard_frame_pointer_rtx, ++ hard_frame_pointer_rtx); ++ } + + /* Force out any pending memory operations that reference stacked data + before stack de-allocation occurs. */ + emit_insn (gen_blockage ()); +- emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); ++ insn = emit_insn (gen_movsi (stack_pointer_rtx, ++ hard_frame_pointer_rtx)); ++ arm_add_cfa_adjust_cfa_note (insn, 0, ++ stack_pointer_rtx, ++ hard_frame_pointer_rtx); + /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not + deleted. */ + emit_insn (gen_force_register_use (stack_pointer_rtx)); +@@ -23680,12 +24474,15 @@ + amount = offsets->outgoing_args - offsets->saved_regs; + if (amount) + { ++ rtx tmp; + /* Force out any pending memory operations that reference stacked data + before stack de-allocation occurs. */ + emit_insn (gen_blockage ()); +- emit_insn (gen_addsi3 (stack_pointer_rtx, +- stack_pointer_rtx, +- GEN_INT (amount))); ++ tmp = emit_insn (gen_addsi3 (stack_pointer_rtx, ++ stack_pointer_rtx, ++ GEN_INT (amount))); ++ arm_add_cfa_adjust_cfa_note (tmp, amount, ++ stack_pointer_rtx, stack_pointer_rtx); + /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is + not deleted. */ + emit_insn (gen_force_register_use (stack_pointer_rtx)); +@@ -23738,6 +24535,8 @@ + REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, + gen_rtx_REG (V2SImode, i), + NULL_RTX); ++ arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, ++ stack_pointer_rtx, stack_pointer_rtx); + } + + if (saved_regs_mask) +@@ -23785,6 +24584,9 @@ + REG_NOTES (insn) = alloc_reg_note (REG_CFA_RESTORE, + gen_rtx_REG (SImode, i), + NULL_RTX); ++ arm_add_cfa_adjust_cfa_note (insn, UNITS_PER_WORD, ++ stack_pointer_rtx, ++ stack_pointer_rtx); + } + } + } +@@ -23796,6 +24598,8 @@ + { + if (TARGET_THUMB2) + thumb2_emit_ldrd_pop (saved_regs_mask); ++ else if (TARGET_ARM && !IS_INTERRUPT (func_type)) ++ arm_emit_ldrd_pop (saved_regs_mask); + else + arm_emit_multi_reg_pop (saved_regs_mask); + } +@@ -23808,10 +24612,34 @@ + } + + if (crtl->args.pretend_args_size) +- emit_insn (gen_addsi3 (stack_pointer_rtx, +- stack_pointer_rtx, +- GEN_INT (crtl->args.pretend_args_size))); ++ { ++ int i, j; ++ rtx dwarf = NULL_RTX; ++ rtx tmp = emit_insn (gen_addsi3 (stack_pointer_rtx, ++ stack_pointer_rtx, ++ GEN_INT (crtl->args.pretend_args_size))); + ++ RTX_FRAME_RELATED_P (tmp) = 1; + - tmp = gen_rtx_SET (VOIDmode, - reg, - gen_frame_mem -@@ -16817,6 +17420,129 @@ - return; ++ if (cfun->machine->uses_anonymous_args) ++ { ++ /* Restore pretend args. Refer arm_expand_prologue on how to save ++ pretend_args in stack. */ ++ int num_regs = crtl->args.pretend_args_size / 4; ++ saved_regs_mask = (0xf0 >> num_regs) & 0xf; ++ for (j = 0, i = 0; j < num_regs; i++) ++ if (saved_regs_mask & (1 << i)) ++ { ++ rtx reg = gen_rtx_REG (SImode, i); ++ dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); ++ j++; ++ } ++ REG_NOTES (tmp) = dwarf; ++ } ++ arm_add_cfa_adjust_cfa_note (tmp, crtl->args.pretend_args_size, ++ stack_pointer_rtx, stack_pointer_rtx); ++ } ++ + if (!really_return) + return; + +@@ -25064,7 +25892,7 @@ + { + /* Neon also supports V2SImode, etc. listed in the clause below. */ + if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode +- || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) ++ || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) + return true; + + if ((TARGET_NEON || TARGET_IWMMXT) +@@ -25227,9 +26055,8 @@ + + nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; + p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); +- regno = (regno - FIRST_VFP_REGNUM) / 2; + for (i = 0; i < nregs; i++) +- XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i); ++ XVECEXP (p, 0, i) = gen_rtx_REG (DImode, regno + i); + + return p; } +@@ -25479,9 +26306,17 @@ + handled_one = true; + break; -+/* LDRD in ARM mode needs consecutive registers as operands. This function -+ emits LDRD whenever possible, otherwise it emits single-word loads. It uses -+ offset addressing and then generates one separate stack udpate. This provides -+ more scheduling freedom, compared to writeback on every load. However, -+ if the function returns using load into PC directly -+ (i.e., if PC is in SAVED_REGS_MASK), the stack needs to be updated -+ before the last load. TODO: Add a peephole optimization to recognize -+ the new epilogue sequence as an LDM instruction whenever possible. TODO: Add -+ peephole optimization to merge the load at stack-offset zero -+ with the stack update instruction using load with writeback -+ in post-index addressing mode. */ -+static void -+arm_emit_ldrd_pop (unsigned long saved_regs_mask) ++ /* The INSN is generated in epilogue. It is set as RTX_FRAME_RELATED_P ++ to get correct dwarf information for shrink-wrap. We should not ++ emit unwind information for it because these are used either for ++ pretend arguments or notes to adjust sp and restore registers from ++ stack. */ ++ case REG_CFA_ADJUST_CFA: ++ case REG_CFA_RESTORE: ++ return; ++ + case REG_CFA_DEF_CFA: + case REG_CFA_EXPRESSION: +- case REG_CFA_ADJUST_CFA: + case REG_CFA_OFFSET: + /* ??? Only handling here what we actually emit. */ + gcc_unreachable (); +@@ -25879,6 +26714,7 @@ + case cortexa7: + case cortexa8: + case cortexa9: ++ case cortexa53: + case fa726te: + case marvell_pj4: + return 2; +@@ -25907,6 +26743,7 @@ + { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, + { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, + { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, ++ { V4HFmode, "__builtin_neon_hf", "18__simd64_float16_t" }, + { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, + { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, + { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, +@@ -26005,6 +26842,60 @@ + return !TARGET_THUMB1; + } + ++tree ++arm_builtin_vectorized_function (tree fndecl, tree type_out, tree type_in) +{ -+ int j = 0; -+ int offset = 0; -+ rtx par = NULL_RTX; -+ rtx dwarf = NULL_RTX; -+ rtx tmp, mem; -+ -+ /* Restore saved registers. */ -+ gcc_assert (!((saved_regs_mask & (1 << SP_REGNUM)))); -+ j = 0; -+ while (j <= LAST_ARM_REGNUM) -+ if (saved_regs_mask & (1 << j)) -+ { -+ if ((j % 2) == 0 -+ && (saved_regs_mask & (1 << (j + 1))) -+ && (j + 1) != PC_REGNUM) -+ { -+ /* Current register and next register form register pair for which -+ LDRD can be generated. PC is always the last register popped, and -+ we handle it separately. */ -+ if (offset > 0) -+ mem = gen_frame_mem (DImode, -+ plus_constant (Pmode, -+ stack_pointer_rtx, -+ offset)); -+ else -+ mem = gen_frame_mem (DImode, stack_pointer_rtx); -+ -+ tmp = gen_rtx_SET (DImode, gen_rtx_REG (DImode, j), mem); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ tmp = emit_insn (tmp); -+ -+ /* Generate dwarf info. */ -+ -+ dwarf = alloc_reg_note (REG_CFA_RESTORE, -+ gen_rtx_REG (SImode, j), -+ NULL_RTX); -+ dwarf = alloc_reg_note (REG_CFA_RESTORE, -+ gen_rtx_REG (SImode, j + 1), -+ dwarf); -+ -+ REG_NOTES (tmp) = dwarf; ++ enum machine_mode in_mode, out_mode; ++ int in_n, out_n; + -+ offset += 8; -+ j += 2; -+ } -+ else if (j != PC_REGNUM) -+ { -+ /* Emit a single word load. */ -+ if (offset > 0) -+ mem = gen_frame_mem (SImode, -+ plus_constant (Pmode, -+ stack_pointer_rtx, -+ offset)); -+ else -+ mem = gen_frame_mem (SImode, stack_pointer_rtx); ++ if (TREE_CODE (type_out) != VECTOR_TYPE ++ || TREE_CODE (type_in) != VECTOR_TYPE ++ || !(TARGET_NEON && TARGET_FPU_ARMV8 && flag_unsafe_math_optimizations)) ++ return NULL_TREE; + -+ tmp = gen_rtx_SET (SImode, gen_rtx_REG (SImode, j), mem); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ tmp = emit_insn (tmp); ++ out_mode = TYPE_MODE (TREE_TYPE (type_out)); ++ out_n = TYPE_VECTOR_SUBPARTS (type_out); ++ in_mode = TYPE_MODE (TREE_TYPE (type_in)); ++ in_n = TYPE_VECTOR_SUBPARTS (type_in); + -+ /* Generate dwarf info. */ -+ REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, -+ gen_rtx_REG (SImode, j), -+ NULL_RTX); ++/* ARM_CHECK_BUILTIN_MODE and ARM_FIND_VRINT_VARIANT are used to find the ++ decl of the vectorized builtin for the appropriate vector mode. ++ NULL_TREE is returned if no such builtin is available. */ ++#undef ARM_CHECK_BUILTIN_MODE ++#define ARM_CHECK_BUILTIN_MODE(C) \ ++ (out_mode == SFmode && out_n == C \ ++ && in_mode == SFmode && in_n == C) + -+ offset += 4; -+ j += 1; -+ } -+ else /* j == PC_REGNUM */ -+ j++; -+ } -+ else -+ j++; ++#undef ARM_FIND_VRINT_VARIANT ++#define ARM_FIND_VRINT_VARIANT(N) \ ++ (ARM_CHECK_BUILTIN_MODE (2) \ ++ ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v2sf, false) \ ++ : (ARM_CHECK_BUILTIN_MODE (4) \ ++ ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v4sf, false) \ ++ : NULL_TREE)) + -+ /* Update the stack. */ -+ if (offset > 0) ++ if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL) + { -+ tmp = gen_rtx_SET (Pmode, -+ stack_pointer_rtx, -+ plus_constant (Pmode, -+ stack_pointer_rtx, -+ offset)); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ emit_insn (tmp); -+ offset = 0; ++ enum built_in_function fn = DECL_FUNCTION_CODE (fndecl); ++ switch (fn) ++ { ++ case BUILT_IN_FLOORF: ++ return ARM_FIND_VRINT_VARIANT (vrintm); ++ case BUILT_IN_CEILF: ++ return ARM_FIND_VRINT_VARIANT (vrintp); ++ case BUILT_IN_TRUNCF: ++ return ARM_FIND_VRINT_VARIANT (vrintz); ++ case BUILT_IN_ROUNDF: ++ return ARM_FIND_VRINT_VARIANT (vrinta); ++ default: ++ return NULL_TREE; ++ } + } ++ return NULL_TREE; ++} ++#undef ARM_CHECK_BUILTIN_MODE ++#undef ARM_FIND_VRINT_VARIANT + -+ if (saved_regs_mask & (1 << PC_REGNUM)) + /* The AAPCS sets the maximum alignment of a vector to 64 bits. */ + static HOST_WIDE_INT + arm_vector_alignment (const_tree type) +@@ -26235,40 +27126,72 @@ + emit_insn (gen_memory_barrier ()); + } + +-/* Emit the load-exclusive and store-exclusive instructions. */ ++/* Emit the load-exclusive and store-exclusive instructions. ++ Use acquire and release versions if necessary. */ + + static void +-arm_emit_load_exclusive (enum machine_mode mode, rtx rval, rtx mem) ++arm_emit_load_exclusive (enum machine_mode mode, rtx rval, rtx mem, bool acq) + { + rtx (*gen) (rtx, rtx); + +- switch (mode) ++ if (acq) + { +- case QImode: gen = gen_arm_load_exclusiveqi; break; +- case HImode: gen = gen_arm_load_exclusivehi; break; +- case SImode: gen = gen_arm_load_exclusivesi; break; +- case DImode: gen = gen_arm_load_exclusivedi; break; +- default: +- gcc_unreachable (); ++ switch (mode) ++ { ++ case QImode: gen = gen_arm_load_acquire_exclusiveqi; break; ++ case HImode: gen = gen_arm_load_acquire_exclusivehi; break; ++ case SImode: gen = gen_arm_load_acquire_exclusivesi; break; ++ case DImode: gen = gen_arm_load_acquire_exclusivedi; break; ++ default: ++ gcc_unreachable (); ++ } + } ++ else + { -+ /* Only PC is to be popped. */ -+ par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); -+ XVECEXP (par, 0, 0) = ret_rtx; -+ tmp = gen_rtx_SET (SImode, -+ gen_rtx_REG (SImode, PC_REGNUM), -+ gen_frame_mem (SImode, -+ gen_rtx_POST_INC (SImode, -+ stack_pointer_rtx))); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ XVECEXP (par, 0, 1) = tmp; -+ par = emit_jump_insn (par); -+ -+ /* Generate dwarf info. */ -+ dwarf = alloc_reg_note (REG_CFA_RESTORE, -+ gen_rtx_REG (SImode, PC_REGNUM), -+ NULL_RTX); -+ REG_NOTES (par) = dwarf; ++ switch (mode) ++ { ++ case QImode: gen = gen_arm_load_exclusiveqi; break; ++ case HImode: gen = gen_arm_load_exclusivehi; break; ++ case SImode: gen = gen_arm_load_exclusivesi; break; ++ case DImode: gen = gen_arm_load_exclusivedi; break; ++ default: ++ gcc_unreachable (); ++ } + } -+} + + emit_insn (gen (rval, mem)); + } + + static void +-arm_emit_store_exclusive (enum machine_mode mode, rtx bval, rtx rval, rtx mem) ++arm_emit_store_exclusive (enum machine_mode mode, rtx bval, rtx rval, ++ rtx mem, bool rel) + { + rtx (*gen) (rtx, rtx, rtx); + +- switch (mode) ++ if (rel) + { +- case QImode: gen = gen_arm_store_exclusiveqi; break; +- case HImode: gen = gen_arm_store_exclusivehi; break; +- case SImode: gen = gen_arm_store_exclusivesi; break; +- case DImode: gen = gen_arm_store_exclusivedi; break; +- default: +- gcc_unreachable (); ++ switch (mode) ++ { ++ case QImode: gen = gen_arm_store_release_exclusiveqi; break; ++ case HImode: gen = gen_arm_store_release_exclusivehi; break; ++ case SImode: gen = gen_arm_store_release_exclusivesi; break; ++ case DImode: gen = gen_arm_store_release_exclusivedi; break; ++ default: ++ gcc_unreachable (); ++ } + } ++ else ++ { ++ switch (mode) ++ { ++ case QImode: gen = gen_arm_store_exclusiveqi; break; ++ case HImode: gen = gen_arm_store_exclusivehi; break; ++ case SImode: gen = gen_arm_store_exclusivesi; break; ++ case DImode: gen = gen_arm_store_exclusivedi; break; ++ default: ++ gcc_unreachable (); ++ } ++ } + + emit_insn (gen (bval, rval, mem)); + } +@@ -26303,6 +27226,15 @@ + mod_f = operands[7]; + mode = GET_MODE (mem); + ++ /* Normally the succ memory model must be stronger than fail, but in the ++ unlikely event of fail being ACQUIRE and succ being RELEASE we need to ++ promote succ to ACQ_REL so that we don't lose the acquire semantics. */ + - /* Calculate the size of the return value that is passed in registers. */ - static unsigned - arm_size_return_regs (void) -@@ -17026,9 +17752,10 @@ - /* If it is safe to use r3, then do so. This sometimes - generates better code on Thumb-2 by avoiding the need to - use 32-bit push/pop instructions. */ -- if (! any_sibcall_uses_r3 () -+ if (! any_sibcall_uses_r3 () - && arm_size_return_regs () <= 12 -- && (offsets->saved_regs_mask & (1 << 3)) == 0) -+ && (offsets->saved_regs_mask & (1 << 3)) == 0 -+ && (TARGET_THUMB2 || !current_tune->prefer_ldrd_strd)) - { - reg = 3; - } -@@ -17460,6 +18187,12 @@ - { - thumb2_emit_strd_push (live_regs_mask); - } -+ else if (TARGET_ARM -+ && !TARGET_APCS_FRAME -+ && !IS_INTERRUPT (func_type)) -+ { -+ arm_emit_strd_push (live_regs_mask); -+ } - else - { - insn = emit_multi_reg_push (live_regs_mask); -@@ -18781,7 +19514,7 @@ - break; - /* Allow up to 4 conditionally executed instructions in a block. */ - n = get_attr_ce_count (insn); -- if (arm_condexec_masklen + n > 4) -+ if (arm_condexec_masklen + n > MAX_INSN_PER_IT_BLOCK) - break; ++ if (TARGET_HAVE_LDACQ ++ && INTVAL (mod_f) == MEMMODEL_ACQUIRE ++ && INTVAL (mod_s) == MEMMODEL_RELEASE) ++ mod_s = GEN_INT (MEMMODEL_ACQ_REL); ++ + switch (mode) + { + case QImode: +@@ -26377,8 +27309,20 @@ + scratch = operands[7]; + mode = GET_MODE (mem); + +- arm_pre_atomic_barrier (mod_s); ++ bool use_acquire = TARGET_HAVE_LDACQ ++ && !(mod_s == MEMMODEL_RELAXED ++ || mod_s == MEMMODEL_CONSUME ++ || mod_s == MEMMODEL_RELEASE); + ++ bool use_release = TARGET_HAVE_LDACQ ++ && !(mod_s == MEMMODEL_RELAXED ++ || mod_s == MEMMODEL_CONSUME ++ || mod_s == MEMMODEL_ACQUIRE); ++ ++ /* Checks whether a barrier is needed and emits one accordingly. */ ++ if (!(use_acquire || use_release)) ++ arm_pre_atomic_barrier (mod_s); ++ + label1 = NULL_RTX; + if (!is_weak) + { +@@ -26387,7 +27331,7 @@ + } + label2 = gen_label_rtx (); + +- arm_emit_load_exclusive (mode, rval, mem); ++ arm_emit_load_exclusive (mode, rval, mem, use_acquire); + + cond = arm_gen_compare_reg (NE, rval, oldval, scratch); + x = gen_rtx_NE (VOIDmode, cond, const0_rtx); +@@ -26395,7 +27339,7 @@ + gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); + emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); + +- arm_emit_store_exclusive (mode, scratch, mem, newval); ++ arm_emit_store_exclusive (mode, scratch, mem, newval, use_release); + + /* Weak or strong, we want EQ to be true for success, so that we + match the flags that we got from the compare above. */ +@@ -26414,7 +27358,9 @@ + if (mod_f != MEMMODEL_RELAXED) + emit_label (label2); + +- arm_post_atomic_barrier (mod_s); ++ /* Checks whether a barrier is needed and emits one accordingly. */ ++ if (!(use_acquire || use_release)) ++ arm_post_atomic_barrier (mod_s); + + if (mod_f == MEMMODEL_RELAXED) + emit_label (label2); +@@ -26429,8 +27375,20 @@ + enum machine_mode wmode = (mode == DImode ? DImode : SImode); + rtx label, x; + +- arm_pre_atomic_barrier (model); ++ bool use_acquire = TARGET_HAVE_LDACQ ++ && !(model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_RELEASE); - predicate = COND_EXEC_TEST (body); -@@ -19339,6 +20072,7 @@ - typedef enum { - T_V8QI, - T_V4HI, -+ T_V4HF, - T_V2SI, - T_V2SF, - T_DI, -@@ -19356,14 +20090,15 @@ - #define TYPE_MODE_BIT(X) (1 << (X)) ++ bool use_release = TARGET_HAVE_LDACQ ++ && !(model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_ACQUIRE); ++ ++ /* Checks whether a barrier is needed and emits one accordingly. */ ++ if (!(use_acquire || use_release)) ++ arm_pre_atomic_barrier (model); ++ + label = gen_label_rtx (); + emit_label (label); - #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \ -- | TYPE_MODE_BIT (T_V2SI) | TYPE_MODE_BIT (T_V2SF) \ -- | TYPE_MODE_BIT (T_DI)) -+ | TYPE_MODE_BIT (T_V4HF) | TYPE_MODE_BIT (T_V2SI) \ -+ | TYPE_MODE_BIT (T_V2SF) | TYPE_MODE_BIT (T_DI)) - #define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \ - | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \ - | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI)) +@@ -26442,7 +27400,7 @@ + old_out = new_out; + value = simplify_gen_subreg (wmode, value, mode, 0); - #define v8qi_UP T_V8QI - #define v4hi_UP T_V4HI -+#define v4hf_UP T_V4HF - #define v2si_UP T_V2SI - #define v2sf_UP T_V2SF - #define di_UP T_DI -@@ -19399,6 +20134,8 @@ - NEON_SCALARMULH, - NEON_SCALARMAC, - NEON_CONVERT, -+ NEON_FLOAT_WIDEN, -+ NEON_FLOAT_NARROW, - NEON_FIXCONV, - NEON_SELECT, - NEON_RESULTPAIR, -@@ -19459,7 +20196,8 @@ - VAR9 (T, N, A, B, C, D, E, F, G, H, I), \ - {#N, NEON_##T, UP (J), CF (N, J), 0} +- arm_emit_load_exclusive (mode, old_out, mem); ++ arm_emit_load_exclusive (mode, old_out, mem, use_acquire); --/* The mode entries in the following table correspond to the "key" type of the -+/* The NEON builtin data can be found in arm_neon_builtins.def. -+ The mode entries in the following table correspond to the "key" type of the - instruction variant, i.e. equivalent to that which would be specified after - the assembler mnemonic, which usually refers to the last vector operand. - (Signed/unsigned/polynomial types are not differentiated between though, and -@@ -19469,196 +20207,7 @@ + switch (code) + { +@@ -26490,12 +27448,15 @@ + break; + } - static neon_builtin_datum neon_builtin_data[] = - { -- VAR10 (BINOP, vadd, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR3 (BINOP, vaddl, v8qi, v4hi, v2si), -- VAR3 (BINOP, vaddw, v8qi, v4hi, v2si), -- VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR3 (BINOP, vaddhn, v8hi, v4si, v2di), -- VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si), -- VAR2 (TERNOP, vfma, v2sf, v4sf), -- VAR2 (TERNOP, vfms, v2sf, v4sf), -- VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si), -- VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si), -- VAR2 (TERNOP, vqdmlal, v4hi, v2si), -- VAR2 (TERNOP, vqdmlsl, v4hi, v2si), -- VAR3 (BINOP, vmull, v8qi, v4hi, v2si), -- VAR2 (SCALARMULL, vmull_n, v4hi, v2si), -- VAR2 (LANEMULL, vmull_lane, v4hi, v2si), -- VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si), -- VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si), -- VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si), -- VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si), -- VAR2 (BINOP, vqdmull, v4hi, v2si), -- VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di), -- VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di), -- VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di), -- VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si), -- VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR10 (BINOP, vsub, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR3 (BINOP, vsubl, v8qi, v4hi, v2si), -- VAR3 (BINOP, vsubw, v8qi, v4hi, v2si), -- VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR3 (BINOP, vsubhn, v8hi, v4si, v2di), -- VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR6 (BINOP, vcgeu, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR2 (BINOP, vcage, v2sf, v4sf), -- VAR2 (BINOP, vcagt, v2sf, v4sf), -- VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR3 (BINOP, vabdl, v8qi, v4hi, v2si), -- VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR3 (TERNOP, vabal, v8qi, v4hi, v2si), -- VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf), -- VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf), -- VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf), -- VAR2 (BINOP, vrecps, v2sf, v4sf), -- VAR2 (BINOP, vrsqrts, v2sf, v4sf), -- VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di), -- VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- VAR2 (UNOP, vcnt, v8qi, v16qi), -- VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf), -- VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf), -- VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si), -- /* FIXME: vget_lane supports more variants than this! */ -- VAR10 (GETLANE, vget_lane, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (SETLANE, vset_lane, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di), -- VAR10 (DUP, vdup_n, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (DUPLANE, vdup_lane, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di), -- VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di), -- VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di), -- VAR3 (UNOP, vmovn, v8hi, v4si, v2di), -- VAR3 (UNOP, vqmovn, v8hi, v4si, v2di), -- VAR3 (UNOP, vqmovun, v8hi, v4si, v2di), -- VAR3 (UNOP, vmovl, v8qi, v4hi, v2si), -- VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR2 (LANEMAC, vmlal_lane, v4hi, v2si), -- VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si), -- VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si), -- VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si), -- VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR2 (SCALARMAC, vmlal_n, v4hi, v2si), -- VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si), -- VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si), -- VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si), -- VAR10 (BINOP, vext, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi), -- VAR2 (UNOP, vrev16, v8qi, v16qi), -- VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf), -- VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf), -- VAR10 (SELECT, vbsl, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR2 (RINT, vrintn, v2sf, v4sf), -- VAR2 (RINT, vrinta, v2sf, v4sf), -- VAR2 (RINT, vrintp, v2sf, v4sf), -- VAR2 (RINT, vrintm, v2sf, v4sf), -- VAR2 (RINT, vrintz, v2sf, v4sf), -- VAR2 (RINT, vrintx, v2sf, v4sf), -- VAR1 (VTBL, vtbl1, v8qi), -- VAR1 (VTBL, vtbl2, v8qi), -- VAR1 (VTBL, vtbl3, v8qi), -- VAR1 (VTBL, vtbl4, v8qi), -- VAR1 (VTBX, vtbx1, v8qi), -- VAR1 (VTBX, vtbx2, v8qi), -- VAR1 (VTBX, vtbx3, v8qi), -- VAR1 (VTBX, vtbx4, v8qi), -- VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf), -- VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di), -- VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di), -- VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di), -- VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di), -- VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di), -- VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di), -- VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di), -- VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di), -- VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di), -- VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (LOAD1, vld1, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (LOAD1LANE, vld1_lane, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (LOAD1, vld1_dup, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (STORE1, vst1, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (STORE1LANE, vst1_lane, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR9 (LOADSTRUCT, -- vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), -- VAR7 (LOADSTRUCTLANE, vld2_lane, -- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di), -- VAR9 (STORESTRUCT, vst2, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), -- VAR7 (STORESTRUCTLANE, vst2_lane, -- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR9 (LOADSTRUCT, -- vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), -- VAR7 (LOADSTRUCTLANE, vld3_lane, -- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di), -- VAR9 (STORESTRUCT, vst3, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), -- VAR7 (STORESTRUCTLANE, vst3_lane, -- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR9 (LOADSTRUCT, vld4, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), -- VAR7 (LOADSTRUCTLANE, vld4_lane, -- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di), -- VAR9 (STORESTRUCT, vst4, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf), -- VAR7 (STORESTRUCTLANE, vst4_lane, -- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf), -- VAR10 (LOGICBINOP, vand, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (LOGICBINOP, vorr, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (BINOP, veor, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (LOGICBINOP, vbic, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di), -- VAR10 (LOGICBINOP, vorn, -- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) -+#include "arm_neon_builtins.def" - }; +- arm_emit_store_exclusive (mode, cond, mem, gen_lowpart (mode, new_out)); ++ arm_emit_store_exclusive (mode, cond, mem, gen_lowpart (mode, new_out), ++ use_release); - #undef CF -@@ -19673,9 +20222,36 @@ - #undef VAR9 - #undef VAR10 + x = gen_rtx_NE (VOIDmode, cond, const0_rtx); + emit_unlikely_jump (gen_cbranchsi4 (x, cond, const0_rtx, label)); --/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have -- symbolic names defined here (which would require too much duplication). -- FIXME? */ -+#define CF(N,X) ARM_BUILTIN_NEON_##N##X -+#define VAR1(T, N, A) \ -+ CF (N, A) -+#define VAR2(T, N, A, B) \ -+ VAR1 (T, N, A), \ -+ CF (N, B) -+#define VAR3(T, N, A, B, C) \ -+ VAR2 (T, N, A, B), \ -+ CF (N, C) -+#define VAR4(T, N, A, B, C, D) \ -+ VAR3 (T, N, A, B, C), \ -+ CF (N, D) -+#define VAR5(T, N, A, B, C, D, E) \ -+ VAR4 (T, N, A, B, C, D), \ -+ CF (N, E) -+#define VAR6(T, N, A, B, C, D, E, F) \ -+ VAR5 (T, N, A, B, C, D, E), \ -+ CF (N, F) -+#define VAR7(T, N, A, B, C, D, E, F, G) \ -+ VAR6 (T, N, A, B, C, D, E, F), \ -+ CF (N, G) -+#define VAR8(T, N, A, B, C, D, E, F, G, H) \ -+ VAR7 (T, N, A, B, C, D, E, F, G), \ -+ CF (N, H) -+#define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ -+ VAR8 (T, N, A, B, C, D, E, F, G, H), \ -+ CF (N, I) -+#define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ -+ VAR9 (T, N, A, B, C, D, E, F, G, H, I), \ -+ CF (N, J) - enum arm_builtins - { - ARM_BUILTIN_GETWCGR0, -@@ -19924,11 +20500,25 @@ +- arm_post_atomic_barrier (model); ++ /* Checks whether a barrier is needed and emits one accordingly. */ ++ if (!(use_acquire || use_release)) ++ arm_post_atomic_barrier (model); + } + + #define MAX_VECT_LEN 16 +@@ -27435,4 +28396,12 @@ - ARM_BUILTIN_WMERGE, + } -- ARM_BUILTIN_NEON_BASE, -+#include "arm_neon_builtins.def" ++/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */ ++ ++static unsigned HOST_WIDE_INT ++arm_asan_shadow_offset (void) ++{ ++ return (unsigned HOST_WIDE_INT) 1 << 29; ++} ++ + #include "gt-arm.h" +--- a/src/gcc/config/arm/arm.h ++++ b/src/gcc/config/arm/arm.h +@@ -183,6 +183,11 @@ -- ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE + ARRAY_SIZE (neon_builtin_data) -+ ,ARM_BUILTIN_MAX - }; + #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) -+#define ARM_BUILTIN_NEON_BASE (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data)) ++/* The maximaum number of instructions that is beneficial to ++ conditionally execute. */ ++#undef MAX_CONDITIONAL_EXECUTE ++#define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () ++ + extern int arm_target_label; + extern int arm_ccfsm_state; + extern GTY(()) rtx arm_target_insn; +@@ -350,10 +355,16 @@ + #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ + && arm_arch_notm) + ++/* Nonzero if this chip supports load-acquire and store-release. */ ++#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) + -+#undef CF -+#undef VAR1 -+#undef VAR2 -+#undef VAR3 -+#undef VAR4 -+#undef VAR5 -+#undef VAR6 -+#undef VAR7 -+#undef VAR8 -+#undef VAR9 -+#undef VAR10 + /* Nonzero if integer division instructions supported. */ + #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ + || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) + ++/* Should NEON be used for 64-bits bitops. */ ++#define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) + - static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX]; + /* True iff the full BPABI is being used. If TARGET_BPABI is true, + then TARGET_AAPCS_BASED must be true -- but the converse does not + hold. TARGET_BPABI implies the use of the BPABI runtime library, +@@ -539,6 +550,10 @@ + /* Nonzero if chip supports integer division instruction in Thumb mode. */ + extern int arm_arch_thumb_hwdiv; - static void -@@ -19939,6 +20529,7 @@ ++/* Nonzero if we should use Neon to handle 64-bits operations rather ++ than core registers. */ ++extern int prefer_neon_for_64bits; ++ + #ifndef TARGET_DEFAULT + #define TARGET_DEFAULT (MASK_APCS_FRAME) + #endif +@@ -630,6 +645,8 @@ - tree neon_intQI_type_node; - tree neon_intHI_type_node; -+ tree neon_floatHF_type_node; - tree neon_polyQI_type_node; - tree neon_polyHI_type_node; - tree neon_intSI_type_node; -@@ -19965,6 +20556,7 @@ + #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) - tree V8QI_type_node; - tree V4HI_type_node; -+ tree V4HF_type_node; - tree V2SI_type_node; - tree V2SF_type_node; - tree V16QI_type_node; -@@ -20019,6 +20611,9 @@ - neon_float_type_node = make_node (REAL_TYPE); - TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; - layout_type (neon_float_type_node); -+ neon_floatHF_type_node = make_node (REAL_TYPE); -+ TYPE_PRECISION (neon_floatHF_type_node) = GET_MODE_PRECISION (HFmode); -+ layout_type (neon_floatHF_type_node); ++#define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT ++ + /* XXX Blah -- this macro is used directly by libobjc. Since it + supports no vector modes, cut out the complexity and fall back + on BIGGEST_FIELD_ALIGNMENT. */ +@@ -1040,7 +1057,7 @@ + /* Modes valid for Neon D registers. */ + #define VALID_NEON_DREG_MODE(MODE) \ + ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ +- || (MODE) == V2SFmode || (MODE) == DImode) ++ || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) - /* Define typedefs which exactly correspond to the modes we are basing vector - types on. If you change these names you'll need to change -@@ -20027,6 +20622,8 @@ - "__builtin_neon_qi"); - (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, - "__builtin_neon_hi"); -+ (*lang_hooks.types.register_builtin_type) (neon_floatHF_type_node, -+ "__builtin_neon_hf"); - (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, - "__builtin_neon_si"); - (*lang_hooks.types.register_builtin_type) (neon_float_type_node, -@@ -20068,6 +20665,8 @@ - build_vector_type_for_mode (neon_intQI_type_node, V8QImode); - V4HI_type_node = - build_vector_type_for_mode (neon_intHI_type_node, V4HImode); -+ V4HF_type_node = -+ build_vector_type_for_mode (neon_floatHF_type_node, V4HFmode); - V2SI_type_node = - build_vector_type_for_mode (neon_intSI_type_node, V2SImode); - V2SF_type_node = -@@ -20190,7 +20789,7 @@ - neon_builtin_datum *d = &neon_builtin_data[i]; + /* Modes valid for Neon Q registers. */ + #define VALID_NEON_QREG_MODE(MODE) \ +@@ -1130,6 +1147,7 @@ + STACK_REG, + BASE_REGS, + HI_REGS, ++ CALLER_SAVE_REGS, + GENERAL_REGS, + CORE_REGS, + VFP_D0_D7_REGS, +@@ -1156,6 +1174,7 @@ + "STACK_REG", \ + "BASE_REGS", \ + "HI_REGS", \ ++ "CALLER_SAVE_REGS", \ + "GENERAL_REGS", \ + "CORE_REGS", \ + "VFP_D0_D7_REGS", \ +@@ -1181,6 +1200,7 @@ + { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ + { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ + { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ ++ { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ + { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ + { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ + { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ +@@ -1639,7 +1659,7 @@ + frame. */ + #define EXIT_IGNORE_STACK 1 - const char* const modenames[] = { -- "v8qi", "v4hi", "v2si", "v2sf", "di", -+ "v8qi", "v4hi", "v4hf", "v2si", "v2sf", "di", - "v16qi", "v8hi", "v4si", "v4sf", "v2di", - "ti", "ei", "oi" - }; -@@ -20393,8 +20992,9 @@ - case NEON_REINTERP: - { - /* We iterate over 5 doubleword types, then 5 quadword -- types. */ -- int rhs = d->mode % 5; -+ types. V4HF is not a type used in reinterpret, so we translate -+ d->mode to the correct index in reinterp_ftype_dreg. */ -+ int rhs = (d->mode - ((d->mode > T_V4HF) ? 1 : 0)) % 5; - switch (insn_data[d->code].operand[0].mode) - { - case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; -@@ -20411,7 +21011,38 @@ - } - } - break; -+ case NEON_FLOAT_WIDEN: -+ { -+ tree eltype = NULL_TREE; -+ tree return_type = NULL_TREE; +-#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) ++#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) + + /* Determine if the epilogue should be output as RTL. + You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ +--- a/src/gcc/config/arm/cortex-a8.md ++++ b/src/gcc/config/arm/cortex-a8.md +@@ -85,30 +85,27 @@ + ;; (source read in E2 and destination available at the end of that cycle). + (define_insn_reservation "cortex_a8_alu" 2 + (and (eq_attr "tune" "cortexa8") +- (ior (and (and (eq_attr "type" "alu_reg,simple_alu_imm") +- (eq_attr "neon_type" "none")) +- (not (eq_attr "insn" "mov,mvn"))) +- (eq_attr "insn" "clz"))) ++ (ior (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg") ++ (eq_attr "neon_type" "none")) ++ (eq_attr "type" "clz"))) + "cortex_a8_default") + + (define_insn_reservation "cortex_a8_alu_shift" 2 + (and (eq_attr "tune" "cortexa8") +- (and (eq_attr "type" "simple_alu_shift,alu_shift") +- (not (eq_attr "insn" "mov,mvn")))) ++ (eq_attr "type" "extend,arlo_shift")) + "cortex_a8_default") + + (define_insn_reservation "cortex_a8_alu_shift_reg" 2 + (and (eq_attr "tune" "cortexa8") +- (and (eq_attr "type" "alu_shift_reg") +- (not (eq_attr "insn" "mov,mvn")))) ++ (eq_attr "type" "arlo_shift_reg")) + "cortex_a8_default") + + ;; Move instructions. + + (define_insn_reservation "cortex_a8_mov" 1 + (and (eq_attr "tune" "cortexa8") +- (and (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg") +- (eq_attr "insn" "mov,mvn"))) ++ (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\ ++ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) + "cortex_a8_default") + + ;; Exceptions to the default latencies for data processing instructions. +@@ -139,22 +136,22 @@ + + (define_insn_reservation "cortex_a8_mul" 6 + (and (eq_attr "tune" "cortexa8") +- (eq_attr "insn" "mul,smulxy,smmul")) ++ (eq_attr "type" "mul,smulxy,smmul")) + "cortex_a8_multiply_2") + + (define_insn_reservation "cortex_a8_mla" 6 + (and (eq_attr "tune" "cortexa8") +- (eq_attr "insn" "mla,smlaxy,smlawy,smmla,smlad,smlsd")) ++ (eq_attr "type" "mla,smlaxy,smlawy,smmla,smlad,smlsd")) + "cortex_a8_multiply_2") + + (define_insn_reservation "cortex_a8_mull" 7 + (and (eq_attr "tune" "cortexa8") +- (eq_attr "insn" "smull,umull,smlal,umlal,umaal,smlalxy")) ++ (eq_attr "type" "smull,umull,smlal,umlal,umaal,smlalxy")) + "cortex_a8_multiply_3") + + (define_insn_reservation "cortex_a8_smulwy" 5 + (and (eq_attr "tune" "cortexa8") +- (eq_attr "insn" "smulwy,smuad,smusd")) ++ (eq_attr "type" "smulwy,smuad,smusd")) + "cortex_a8_multiply") + + ;; smlald and smlsld are multiply-accumulate instructions but do not +@@ -162,7 +159,7 @@ + ;; cannot go in cortex_a8_mla above. (See below for bypass details.) + (define_insn_reservation "cortex_a8_smlald" 6 + (and (eq_attr "tune" "cortexa8") +- (eq_attr "insn" "smlald,smlsld")) ++ (eq_attr "type" "smlald,smlsld")) + "cortex_a8_multiply_2") + + ;; A multiply with a single-register result or an MLA, followed by an +--- a/src/gcc/config/arm/arm-fixed.md ++++ b/src/gcc/config/arm/arm-fixed.md +@@ -19,12 +19,13 @@ + ;; This file contains ARM instructions that support fixed-point operations. + + (define_insn "add3" +- [(set (match_operand:FIXED 0 "s_register_operand" "=r") +- (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "r") +- (match_operand:FIXED 2 "s_register_operand" "r")))] ++ [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") ++ (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") ++ (match_operand:FIXED 2 "s_register_operand" "l,r")))] + "TARGET_32BIT" + "add%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no")]) + + (define_insn "add3" + [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") +@@ -32,7 +33,8 @@ + (match_operand:ADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "sadd%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "usadd3" + [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") +@@ -40,7 +42,8 @@ + (match_operand:UQADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "uqadd%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "ssadd3" + [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") +@@ -48,15 +51,17 @@ + (match_operand:QADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "qadd%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "sub3" +- [(set (match_operand:FIXED 0 "s_register_operand" "=r") +- (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "r") +- (match_operand:FIXED 2 "s_register_operand" "r")))] ++ [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") ++ (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") ++ (match_operand:FIXED 2 "s_register_operand" "l,r")))] + "TARGET_32BIT" + "sub%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no")]) + + (define_insn "sub3" + [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") +@@ -64,7 +69,8 @@ + (match_operand:ADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "ssub%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "ussub3" + [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") +@@ -73,7 +79,8 @@ + (match_operand:UQADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "uqsub%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) -+ switch (insn_data[d->code].operand[1].mode) -+ { -+ case V4HFmode: -+ eltype = V4HF_type_node; -+ return_type = V4SF_type_node; -+ break; -+ default: gcc_unreachable (); -+ } -+ ftype = build_function_type_list (return_type, eltype, NULL); -+ break; -+ } -+ case NEON_FLOAT_NARROW: -+ { -+ tree eltype = NULL_TREE; -+ tree return_type = NULL_TREE; + (define_insn "sssub3" + [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") +@@ -81,7 +88,8 @@ + (match_operand:QADDSUB 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "qsub%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + ;; Fractional multiplies. + +@@ -96,7 +104,7 @@ + rtx tmp1 = gen_reg_rtx (HImode); + rtx tmp2 = gen_reg_rtx (HImode); + rtx tmp3 = gen_reg_rtx (SImode); +- ++ + emit_insn (gen_extendqihi2 (tmp1, gen_lowpart (QImode, operands[1]))); + emit_insn (gen_extendqihi2 (tmp2, gen_lowpart (QImode, operands[2]))); + emit_insn (gen_mulhisi3 (tmp3, tmp1, tmp2)); +@@ -132,7 +140,7 @@ + rtx tmp1 = gen_reg_rtx (DImode); + rtx tmp2 = gen_reg_rtx (SImode); + rtx tmp3 = gen_reg_rtx (SImode); +- ++ + /* s.31 * s.31 -> s.62 multiplication. */ + emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), + gen_lowpart (SImode, operands[2]))); +@@ -154,7 +162,7 @@ + rtx tmp1 = gen_reg_rtx (DImode); + rtx tmp2 = gen_reg_rtx (SImode); + rtx tmp3 = gen_reg_rtx (SImode); +- ++ + emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), + gen_lowpart (SImode, operands[2]))); + emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (15))); +@@ -173,13 +181,13 @@ + rtx tmp1 = gen_reg_rtx (DImode); + rtx tmp2 = gen_reg_rtx (SImode); + rtx tmp3 = gen_reg_rtx (SImode); +- ++ + emit_insn (gen_umulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), + gen_lowpart (SImode, operands[2]))); + emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (16))); + emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (16))); + emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3)); +- + -+ switch (insn_data[d->code].operand[1].mode) -+ { -+ case V4SFmode: -+ eltype = V4SF_type_node; -+ return_type = V4HF_type_node; -+ break; -+ default: gcc_unreachable (); -+ } -+ ftype = build_function_type_list (return_type, eltype, NULL); -+ break; -+ } - default: - gcc_unreachable (); - } -@@ -21408,6 +22039,8 @@ - case NEON_DUP: - case NEON_RINT: - case NEON_SPLIT: -+ case NEON_FLOAT_WIDEN: -+ case NEON_FLOAT_NARROW: - case NEON_REINTERP: - return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode, - NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); -@@ -21605,7 +22238,7 @@ - rtx op1; - rtx op2; - rtx pat; -- int fcode = DECL_FUNCTION_CODE (fndecl); -+ unsigned int fcode = DECL_FUNCTION_CODE (fndecl); - size_t i; - enum machine_mode tmode; - enum machine_mode mode0; -@@ -23772,6 +24405,8 @@ - { - if (TARGET_THUMB2) - thumb2_emit_ldrd_pop (saved_regs_mask); -+ else if (TARGET_ARM && !IS_INTERRUPT (func_type)) -+ arm_emit_ldrd_pop (saved_regs_mask); - else - arm_emit_multi_reg_pop (saved_regs_mask); - } -@@ -25040,7 +25675,7 @@ - { - /* Neon also supports V2SImode, etc. listed in the clause below. */ - if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode -- || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) -+ || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) - return true; + DONE; + }) - if ((TARGET_NEON || TARGET_IWMMXT) -@@ -25203,9 +25838,8 @@ +@@ -209,7 +217,7 @@ + } - nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; - p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); -- regno = (regno - FIRST_VFP_REGNUM) / 2; - for (i = 0; i < nregs; i++) -- XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i); -+ XVECEXP (p, 0, i) = gen_rtx_REG (DImode, regno + i); + /* We have: +- 31 high word 0 31 low word 0 ++ 31 high word 0 31 low word 0 + + [ S i i .... i i i ] [ i f f f ... f f ] + | +@@ -221,9 +229,18 @@ + output_asm_insn ("ssat\\t%R3, #15, %R3", operands); + output_asm_insn ("mrs\\t%4, APSR", operands); + output_asm_insn ("tst\\t%4, #1<<27", operands); +- if (TARGET_THUMB2) +- output_asm_insn ("it\\tne", operands); +- output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands); ++ if (arm_restrict_it) ++ { ++ output_asm_insn ("mvn\\t%4, %R3, asr #32", operands); ++ output_asm_insn ("it\\tne", operands); ++ output_asm_insn ("movne\\t%Q3, %4", operands); ++ } ++ else ++ { ++ if (TARGET_THUMB2) ++ output_asm_insn ("it\\tne", operands); ++ output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands); ++ } + output_asm_insn ("mov\\t%0, %Q3, lsr #15", operands); + output_asm_insn ("orr\\t%0, %0, %R3, asl #17", operands); + return ""; +@@ -231,7 +248,9 @@ + [(set_attr "conds" "clob") + (set (attr "length") + (if_then_else (eq_attr "is_thumb" "yes") +- (const_int 38) ++ (if_then_else (match_test "arm_restrict_it") ++ (const_int 40) ++ (const_int 38)) + (const_int 32)))]) - return p; - } -@@ -25855,6 +26489,7 @@ - case cortexa7: - case cortexa8: - case cortexa9: -+ case cortexa53: - case fa726te: - case marvell_pj4: - return 2; -@@ -25883,6 +26518,7 @@ - { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, - { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, - { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, -+ { V4HFmode, "__builtin_neon_hf", "18__simd64_float16_t" }, - { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, - { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, - { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, -@@ -25981,6 +26617,60 @@ - return !TARGET_THUMB1; - } + ;; Same goes for this. +@@ -257,7 +276,7 @@ + } -+tree -+arm_builtin_vectorized_function (tree fndecl, tree type_out, tree type_in) -+{ -+ enum machine_mode in_mode, out_mode; -+ int in_n, out_n; -+ -+ if (TREE_CODE (type_out) != VECTOR_TYPE -+ || TREE_CODE (type_in) != VECTOR_TYPE -+ || !(TARGET_NEON && TARGET_FPU_ARMV8 && flag_unsafe_math_optimizations)) -+ return NULL_TREE; -+ -+ out_mode = TYPE_MODE (TREE_TYPE (type_out)); -+ out_n = TYPE_VECTOR_SUBPARTS (type_out); -+ in_mode = TYPE_MODE (TREE_TYPE (type_in)); -+ in_n = TYPE_VECTOR_SUBPARTS (type_in); -+ -+/* ARM_CHECK_BUILTIN_MODE and ARM_FIND_VRINT_VARIANT are used to find the -+ decl of the vectorized builtin for the appropriate vector mode. -+ NULL_TREE is returned if no such builtin is available. */ -+#undef ARM_CHECK_BUILTIN_MODE -+#define ARM_CHECK_BUILTIN_MODE(C) \ -+ (out_mode == SFmode && out_n == C \ -+ && in_mode == SFmode && in_n == C) -+ -+#undef ARM_FIND_VRINT_VARIANT -+#define ARM_FIND_VRINT_VARIANT(N) \ -+ (ARM_CHECK_BUILTIN_MODE (2) \ -+ ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v2sf, false) \ -+ : (ARM_CHECK_BUILTIN_MODE (4) \ -+ ? arm_builtin_decl(ARM_BUILTIN_NEON_##N##v4sf, false) \ -+ : NULL_TREE)) -+ -+ if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL) + /* We have: +- 31 high word 0 31 low word 0 ++ 31 high word 0 31 low word 0 + + [ i i i .... i i i ] [ f f f f ... f f ] + | +@@ -269,9 +288,18 @@ + output_asm_insn ("usat\\t%R3, #16, %R3", operands); + output_asm_insn ("mrs\\t%4, APSR", operands); + output_asm_insn ("tst\\t%4, #1<<27", operands); +- if (TARGET_THUMB2) +- output_asm_insn ("it\\tne", operands); +- output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands); ++ if (arm_restrict_it) + { -+ enum built_in_function fn = DECL_FUNCTION_CODE (fndecl); -+ switch (fn) -+ { -+ case BUILT_IN_FLOORF: -+ return ARM_FIND_VRINT_VARIANT (vrintm); -+ case BUILT_IN_CEILF: -+ return ARM_FIND_VRINT_VARIANT (vrintp); -+ case BUILT_IN_TRUNCF: -+ return ARM_FIND_VRINT_VARIANT (vrintz); -+ case BUILT_IN_ROUNDF: -+ return ARM_FIND_VRINT_VARIANT (vrinta); -+ default: -+ return NULL_TREE; -+ } ++ output_asm_insn ("sbfx\\t%4, %R3, #15, #1", operands); ++ output_asm_insn ("it\\tne", operands); ++ output_asm_insn ("movne\\t%Q3, %4", operands); + } -+ return NULL_TREE; -+} -+#undef ARM_CHECK_BUILTIN_MODE -+#undef ARM_FIND_VRINT_VARIANT ++ else ++ { ++ if (TARGET_THUMB2) ++ output_asm_insn ("it\\tne", operands); ++ output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands); ++ } + output_asm_insn ("lsr\\t%0, %Q3, #16", operands); + output_asm_insn ("orr\\t%0, %0, %R3, asl #16", operands); + return ""; +@@ -279,7 +307,9 @@ + [(set_attr "conds" "clob") + (set (attr "length") + (if_then_else (eq_attr "is_thumb" "yes") +- (const_int 38) ++ (if_then_else (match_test "arm_restrict_it") ++ (const_int 40) ++ (const_int 38)) + (const_int 32)))]) + + (define_expand "mulha3" +@@ -289,7 +319,7 @@ + "TARGET_DSP_MULTIPLY && arm_arch_thumb2" + { + rtx tmp = gen_reg_rtx (SImode); +- ++ + emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), + gen_lowpart (HImode, operands[2]))); + emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, GEN_INT (16), +@@ -307,7 +337,7 @@ + rtx tmp1 = gen_reg_rtx (SImode); + rtx tmp2 = gen_reg_rtx (SImode); + rtx tmp3 = gen_reg_rtx (SImode); +- ++ + /* 8.8 * 8.8 -> 16.16 multiply. */ + emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1]))); + emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2]))); +@@ -326,7 +356,7 @@ + { + rtx tmp = gen_reg_rtx (SImode); + rtx rshift; +- ++ + emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), + gen_lowpart (HImode, operands[2]))); + +@@ -348,12 +378,12 @@ + rtx tmp2 = gen_reg_rtx (SImode); + rtx tmp3 = gen_reg_rtx (SImode); + rtx rshift_tmp = gen_reg_rtx (SImode); +- ++ + /* Note: there's no smul[bt][bt] equivalent for unsigned multiplies. Use a + normal 32x32->32-bit multiply instead. */ + emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1]))); + emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2]))); +- + - /* The AAPCS sets the maximum alignment of a vector to 64 bits. */ - static HOST_WIDE_INT - arm_vector_alignment (const_tree type) -@@ -26211,40 +26901,72 @@ - emit_insn (gen_memory_barrier ()); - } + emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2)); + + /* The operand to "usat" is signed, so we cannot use the "..., asr #8" +@@ -374,9 +404,9 @@ + "TARGET_32BIT && arm_arch6" + "ssat%?\\t%0, #16, %2%S1" + [(set_attr "predicable" "yes") +- (set_attr "insn" "sat") ++ (set_attr "predicable_short_it" "no") + (set_attr "shift" "1") +- (set_attr "type" "alu_shift")]) ++ (set_attr "type" "arlo_shift")]) + + (define_insn "arm_usatsihi" + [(set (match_operand:HI 0 "s_register_operand" "=r") +@@ -384,4 +414,5 @@ + "TARGET_INT_SIMD" + "usat%?\\t%0, #16, %1" + [(set_attr "predicable" "yes") +- (set_attr "insn" "sat")]) ++ (set_attr "predicable_short_it" "no")] ++) +--- a/src/gcc/config/arm/unspecs.md ++++ b/src/gcc/config/arm/unspecs.md +@@ -139,6 +139,10 @@ + VUNSPEC_ATOMIC_OP ; Represent an atomic operation. + VUNSPEC_LL ; Represent a load-register-exclusive. + VUNSPEC_SC ; Represent a store-register-exclusive. ++ VUNSPEC_LAX ; Represent a load-register-acquire-exclusive. ++ VUNSPEC_SLX ; Represent a store-register-release-exclusive. ++ VUNSPEC_LDA ; Represent a store-register-acquire. ++ VUNSPEC_STL ; Represent a store-register-release. + ]) + + ;; Enumerators for NEON unspecs. +--- a/src/gcc/config/arm/cortex-m4.md ++++ b/src/gcc/config/arm/cortex-m4.md +@@ -31,7 +31,12 @@ + ;; ALU and multiply is one cycle. + (define_insn_reservation "cortex_m4_alu" 1 + (and (eq_attr "tune" "cortexm4") +- (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg,mult")) ++ (ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\ ++ arlo_shift,arlo_shift_reg,\ ++ mov_imm,mov_reg,mov_shift,mov_shift_reg,\ ++ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg") ++ (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes")))) + "cortex_m4_ex") + + ;; Byte, half-word and word load is two cycles. +--- a/src/gcc/config/arm/linux-eabi.h ++++ b/src/gcc/config/arm/linux-eabi.h +@@ -84,10 +84,14 @@ + LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ + LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) + ++#undef ASAN_CC1_SPEC ++#define ASAN_CC1_SPEC "%{fsanitize=*:-funwind-tables}" ++ + #undef CC1_SPEC + #define CC1_SPEC \ +- LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC, \ +- GNU_USER_TARGET_CC1_SPEC " " ANDROID_CC1_SPEC) ++ LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC, \ ++ GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC " " \ ++ ANDROID_CC1_SPEC) + + #define CC1PLUS_SPEC \ + LINUX_OR_ANDROID_CC ("", ANDROID_CC1PLUS_SPEC) +@@ -95,7 +99,7 @@ + #undef LIB_SPEC + #define LIB_SPEC \ + LINUX_OR_ANDROID_LD (GNU_USER_TARGET_LIB_SPEC, \ +- GNU_USER_TARGET_LIB_SPEC " " ANDROID_LIB_SPEC) ++ GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC " " ANDROID_LIB_SPEC) + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ +--- a/src/gcc/config/arm/arm-cores.def ++++ b/src/gcc/config/arm/arm-cores.def +@@ -129,9 +129,11 @@ + ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) + ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) + ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) ++ARM_CORE("cortex-a53", cortexa53, 8A, FL_LDSCHED, cortex_a5) + ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex) + ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex) + ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) ++ARM_CORE("cortex-r7", cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) + ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex) + ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex) + ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, v6m) +--- a/src/gcc/config/arm/cortex-r4.md ++++ b/src/gcc/config/arm/cortex-r4.md +@@ -78,24 +78,22 @@ + ;; for the purposes of the dual-issue constraints above. + (define_insn_reservation "cortex_r4_alu" 2 + (and (eq_attr "tune_cortexr4" "yes") +- (and (eq_attr "type" "alu_reg,simple_alu_imm") +- (not (eq_attr "insn" "mov")))) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,mvn_imm,mvn_reg")) + "cortex_r4_alu") + + (define_insn_reservation "cortex_r4_mov" 2 + (and (eq_attr "tune_cortexr4" "yes") +- (and (eq_attr "type" "alu_reg,simple_alu_imm") +- (eq_attr "insn" "mov"))) ++ (eq_attr "type" "mov_imm,mov_reg")) + "cortex_r4_mov") + + (define_insn_reservation "cortex_r4_alu_shift" 2 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "type" "simple_alu_shift,alu_shift")) ++ (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift")) + "cortex_r4_alu") + + (define_insn_reservation "cortex_r4_alu_shift_reg" 2 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "type" "alu_shift_reg")) ++ (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) + "cortex_r4_alu_shift_reg") + + ;; An ALU instruction followed by an ALU instruction with no early dep. +@@ -128,32 +126,32 @@ + + (define_insn_reservation "cortex_r4_mul_4" 4 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "insn" "mul,smmul")) ++ (eq_attr "type" "mul,smmul")) + "cortex_r4_mul_2") + + (define_insn_reservation "cortex_r4_mul_3" 3 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "insn" "smulxy,smulwy,smuad,smusd")) ++ (eq_attr "type" "smulxy,smulwy,smuad,smusd")) + "cortex_r4_mul") + + (define_insn_reservation "cortex_r4_mla_4" 4 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "insn" "mla,smmla")) ++ (eq_attr "type" "mla,smmla")) + "cortex_r4_mul_2") + + (define_insn_reservation "cortex_r4_mla_3" 3 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "insn" "smlaxy,smlawy,smlad,smlsd")) ++ (eq_attr "type" "smlaxy,smlawy,smlad,smlsd")) + "cortex_r4_mul") + + (define_insn_reservation "cortex_r4_smlald" 3 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "insn" "smlald,smlsld")) ++ (eq_attr "type" "smlald,smlsld")) + "cortex_r4_mul") + + (define_insn_reservation "cortex_r4_mull" 4 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "insn" "smull,umull,umlal,umaal")) ++ (eq_attr "type" "smull,umull,umlal,umaal")) + "cortex_r4_mul_2") + + ;; A multiply or an MLA with a single-register result, followed by an +@@ -196,12 +194,12 @@ + ;; This gives a latency of nine for udiv and ten for sdiv. + (define_insn_reservation "cortex_r4_udiv" 9 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "insn" "udiv")) ++ (eq_attr "type" "udiv")) + "cortex_r4_div_9") + + (define_insn_reservation "cortex_r4_sdiv" 10 + (and (eq_attr "tune_cortexr4" "yes") +- (eq_attr "insn" "sdiv")) ++ (eq_attr "type" "sdiv")) + "cortex_r4_div_10") + + ;; Branches. We assume correct prediction. +--- a/src/gcc/config/arm/arm-tune.md ++++ b/src/gcc/config/arm/arm-tune.md +@@ -1,5 +1,5 @@ + ;; -*- buffer-read-only: t -*- + ;; Generated automatically by gentune.sh from arm-cores.def + (define_attr "tune" +- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4" ++ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexa53,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4" + (const (symbol_ref "((enum attr_tune) arm_tune)"))) +--- a/src/gcc/config/arm/arm-protos.h ++++ b/src/gcc/config/arm/arm-protos.h +@@ -24,12 +24,13 @@ + + extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); + extern int use_return_insn (int, rtx); ++extern bool use_simple_return_p (void); + extern enum reg_class arm_regno_class (int); + extern void arm_load_pic_register (unsigned long); + extern int arm_volatile_func (void); + extern void arm_expand_prologue (void); + extern void arm_expand_epilogue (bool); +-extern void thumb2_expand_return (void); ++extern void thumb2_expand_return (bool); + extern const char *arm_strip_name_encoding (const char *); + extern void arm_asm_output_labelref (FILE *, const char *); + extern void thumb2_asm_output_opcode (FILE *); +@@ -78,6 +79,7 @@ + extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode, + rtx (*) (rtx, rtx, rtx)); + extern rtx neon_make_constant (rtx); ++extern tree arm_builtin_vectorized_function (tree, tree, tree); + extern void neon_expand_vector_init (rtx, rtx); + extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); + extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); +@@ -117,7 +119,9 @@ + extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); + extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT); + extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool); ++extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool); + extern int arm_gen_movmemqi (rtx *); ++extern bool gen_movmem_ldrd_strd (rtx *); + extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); + extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, + HOST_WIDE_INT); +@@ -224,6 +228,8 @@ --/* Emit the load-exclusive and store-exclusive instructions. */ -+/* Emit the load-exclusive and store-exclusive instructions. -+ Use acquire and release versions if necessary. */ + extern void arm_order_regs_for_local_alloc (void); - static void --arm_emit_load_exclusive (enum machine_mode mode, rtx rval, rtx mem) -+arm_emit_load_exclusive (enum machine_mode mode, rtx rval, rtx mem, bool acq) - { - rtx (*gen) (rtx, rtx); ++extern int arm_max_conditional_execute (); ++ + /* Vectorizer cost model implementation. */ + struct cpu_vec_costs { + const int scalar_stmt_cost; /* Cost of any scalar operation, excluding +@@ -253,8 +259,7 @@ + bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool); + bool (*sched_adjust_cost) (rtx, rtx, rtx, int *); + int constant_limit; +- /* Maximum number of instructions to conditionalise in +- arm_final_prescan_insn. */ ++ /* Maximum number of instructions to conditionalise. */ + int max_insns_skipped; + int num_prefetch_slots; + int l1_cache_size; +@@ -269,6 +274,8 @@ + bool logical_op_non_short_circuit[2]; + /* Vectorizer costs. */ + const struct cpu_vec_costs* vec_costs; ++ /* Prefer Neon for 64-bit bitops. */ ++ bool prefer_neon_for_64bits; + }; -- switch (mode) -+ if (acq) + extern const struct tune_params *current_tune; +--- a/src/gcc/config/arm/vfp.md ++++ b/src/gcc/config/arm/vfp.md +@@ -18,31 +18,6 @@ + ;; along with GCC; see the file COPYING3. If not see + ;; . */ + +-;; The VFP "type" attributes differ from those used in the FPA model. +-;; fcpys Single precision cpy. +-;; ffariths Single precision abs, neg. +-;; ffarithd Double precision abs, neg, cpy. +-;; fadds Single precision add/sub. +-;; faddd Double precision add/sub. +-;; fconsts Single precision load immediate. +-;; fconstd Double precision load immediate. +-;; fcmps Single precision comparison. +-;; fcmpd Double precision comparison. +-;; fmuls Single precision multiply. +-;; fmuld Double precision multiply. +-;; fmacs Single precision multiply-accumulate. +-;; fmacd Double precision multiply-accumulate. +-;; ffmas Single precision fused multiply-accumulate. +-;; ffmad Double precision fused multiply-accumulate. +-;; fdivs Single precision sqrt or division. +-;; fdivd Double precision sqrt or division. +-;; f_flag fmstat operation +-;; f_load[sd] Floating point load from memory. +-;; f_store[sd] Floating point store to memory. +-;; f_2_r Transfer vfp to arm reg. +-;; r_2_f Transfer arm to vfp reg. +-;; f_cvt Convert floating<->integral +- + ;; SImode moves + ;; ??? For now do not allow loading constants into vfp regs. This causes + ;; problems because small constants get converted into adds. +@@ -78,62 +53,67 @@ + } + " + [(set_attr "predicable" "yes") +- (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") ++ (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") + (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") +- (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*") + (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] + ) + + ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split + ;; high/low register alternatives for loads and stores here. ++;; The l/Py alternative should come after r/I to ensure that the short variant ++;; is chosen with length 2 when the instruction is predicated for ++;; arm_restrict_it. + (define_insn "*thumb2_movsi_vfp" +- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv") +- (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))] ++ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv") ++ (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))] + "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT + && ( s_register_operand (operands[0], SImode) + || s_register_operand (operands[1], SImode))" + "* + switch (which_alternative) { -- case QImode: gen = gen_arm_load_exclusiveqi; break; -- case HImode: gen = gen_arm_load_exclusivehi; break; -- case SImode: gen = gen_arm_load_exclusivesi; break; -- case DImode: gen = gen_arm_load_exclusivedi; break; -- default: -- gcc_unreachable (); -+ switch (mode) -+ { -+ case QImode: gen = gen_arm_load_acquire_exclusiveqi; break; -+ case HImode: gen = gen_arm_load_acquire_exclusivehi; break; -+ case SImode: gen = gen_arm_load_acquire_exclusivesi; break; -+ case DImode: gen = gen_arm_load_acquire_exclusivedi; break; -+ default: -+ gcc_unreachable (); -+ } +- case 0: case 1: ++ case 0: ++ case 1: ++ case 2: + return \"mov%?\\t%0, %1\"; +- case 2: ++ case 3: + return \"mvn%?\\t%0, #%B1\"; +- case 3: ++ case 4: + return \"movw%?\\t%0, %1\"; +- case 4: + case 5: ++ case 6: + return \"ldr%?\\t%0, %1\"; +- case 6: + case 7: ++ case 8: + return \"str%?\\t%1, %0\"; +- case 8: ++ case 9: + return \"fmsr%?\\t%0, %1\\t%@ int\"; +- case 9: ++ case 10: + return \"fmrs%?\\t%0, %1\\t%@ int\"; +- case 10: ++ case 11: + return \"fcpys%?\\t%0, %1\\t%@ int\"; +- case 11: case 12: ++ case 12: case 13: + return output_move_vfp (operands); + default: + gcc_unreachable (); } -+ else -+ { -+ switch (mode) -+ { -+ case QImode: gen = gen_arm_load_exclusiveqi; break; -+ case HImode: gen = gen_arm_load_exclusivehi; break; -+ case SImode: gen = gen_arm_load_exclusivesi; break; -+ case DImode: gen = gen_arm_load_exclusivedi; break; -+ default: -+ gcc_unreachable (); -+ } -+ } + " + [(set_attr "predicable" "yes") +- (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") +- (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") +- (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*") +- (set_attr "pool_range" "*,*,*,*,1018,4094,*,*,*,*,*,1018,*") +- (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] ++ (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no") ++ (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_reg,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") ++ (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4") ++ (set_attr "neon_type" "*,*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") ++ (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*") ++ (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] + ) - emit_insn (gen (rval, mem)); - } - static void --arm_emit_store_exclusive (enum machine_mode mode, rtx bval, rtx rval, rtx mem) -+arm_emit_store_exclusive (enum machine_mode mode, rtx bval, rtx rval, -+ rtx mem, bool rel) - { - rtx (*gen) (rtx, rtx, rtx); + ;; DImode moves -- switch (mode) -+ if (rel) - { -- case QImode: gen = gen_arm_store_exclusiveqi; break; -- case HImode: gen = gen_arm_store_exclusivehi; break; -- case SImode: gen = gen_arm_store_exclusivesi; break; -- case DImode: gen = gen_arm_store_exclusivedi; break; -- default: -- gcc_unreachable (); -+ switch (mode) -+ { -+ case QImode: gen = gen_arm_store_release_exclusiveqi; break; -+ case HImode: gen = gen_arm_store_release_exclusivehi; break; -+ case SImode: gen = gen_arm_store_release_exclusivesi; break; -+ case DImode: gen = gen_arm_store_release_exclusivedi; break; -+ default: -+ gcc_unreachable (); -+ } + (define_insn "*movdi_vfp" +- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,r,w,w, Uv") +- (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] ++ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv") ++ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode)) +@@ -375,9 +355,8 @@ + " + [(set_attr "predicable" "yes") + (set_attr "type" +- "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") ++ "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") + (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") +- (set_attr "insn" "*,*,*,*,*,*,*,*,mov") + (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") + (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] + ) +@@ -412,15 +391,14 @@ } -+ else -+ { -+ switch (mode) -+ { -+ case QImode: gen = gen_arm_store_exclusiveqi; break; -+ case HImode: gen = gen_arm_store_exclusivehi; break; -+ case SImode: gen = gen_arm_store_exclusivesi; break; -+ case DImode: gen = gen_arm_store_exclusivedi; break; -+ default: -+ gcc_unreachable (); -+ } -+ } + " + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" +- "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") ++ "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,mov_reg") + (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") +- (set_attr "insn" "*,*,*,*,*,*,*,*,mov") + (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") + (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] + ) - emit_insn (gen (bval, rval, mem)); - } -@@ -26279,6 +27001,15 @@ - mod_f = operands[7]; - mode = GET_MODE (mem); +- + ;; DFmode moves + + (define_insn "*movdf_vfp" +@@ -550,7 +528,7 @@ + [(match_operand 4 "cc_register" "") (const_int 0)]) + (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t") + (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))] +- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" ++ "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it" + "@ + it\\t%D3\;fcpys%D3\\t%0, %2 + it\\t%d3\;fcpys%d3\\t%0, %1 +@@ -598,7 +576,7 @@ + [(match_operand 4 "cc_register" "") (const_int 0)]) + (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w") + (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))] +- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" ++ "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && !arm_restrict_it" + "@ + it\\t%D3\;fcpyd%D3\\t%P0, %P2 + it\\t%d3\;fcpyd%d3\\t%P0, %P1 +@@ -624,6 +602,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fabss%?\\t%0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "ffariths")] + ) -+ /* Normally the succ memory model must be stronger than fail, but in the -+ unlikely event of fail being ACQUIRE and succ being RELEASE we need to -+ promote succ to ACQ_REL so that we don't lose the acquire semantics. */ -+ -+ if (TARGET_HAVE_LDACQ -+ && INTVAL (mod_f) == MEMMODEL_ACQUIRE -+ && INTVAL (mod_s) == MEMMODEL_RELEASE) -+ mod_s = GEN_INT (MEMMODEL_ACQ_REL); -+ - switch (mode) - { - case QImode: -@@ -26353,8 +27084,20 @@ - scratch = operands[7]; - mode = GET_MODE (mem); +@@ -633,6 +612,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fabsd%?\\t%P0, %P1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "ffarithd")] + ) -- arm_pre_atomic_barrier (mod_s); -+ bool use_acquire = TARGET_HAVE_LDACQ -+ && !(mod_s == MEMMODEL_RELAXED -+ || mod_s == MEMMODEL_CONSUME -+ || mod_s == MEMMODEL_RELEASE); +@@ -644,6 +624,7 @@ + fnegs%?\\t%0, %1 + eor%?\\t%0, %1, #-2147483648" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "ffariths")] + ) -+ bool use_release = TARGET_HAVE_LDACQ -+ && !(mod_s == MEMMODEL_RELAXED -+ || mod_s == MEMMODEL_CONSUME -+ || mod_s == MEMMODEL_ACQUIRE); -+ -+ /* Checks whether a barrier is needed and emits one accordingly. */ -+ if (!(use_acquire || use_release)) -+ arm_pre_atomic_barrier (mod_s); -+ - label1 = NULL_RTX; - if (!is_weak) - { -@@ -26363,7 +27106,7 @@ +@@ -689,6 +670,7 @@ } - label2 = gen_label_rtx (); + " + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "length" "4,4,8") + (set_attr "type" "ffarithd")] + ) +@@ -703,6 +685,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fadds%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fadds")] + ) -- arm_emit_load_exclusive (mode, rval, mem); -+ arm_emit_load_exclusive (mode, rval, mem, use_acquire); +@@ -713,6 +696,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "faddd%?\\t%P0, %P1, %P2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "faddd")] + ) - cond = arm_gen_compare_reg (NE, rval, oldval, scratch); - x = gen_rtx_NE (VOIDmode, cond, const0_rtx); -@@ -26371,7 +27114,7 @@ - gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); - emit_unlikely_jump (gen_rtx_SET (VOIDmode, pc_rtx, x)); +@@ -724,6 +708,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fsubs%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fadds")] + ) -- arm_emit_store_exclusive (mode, scratch, mem, newval); -+ arm_emit_store_exclusive (mode, scratch, mem, newval, use_release); +@@ -734,6 +719,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fsubd%?\\t%P0, %P1, %P2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "faddd")] + ) - /* Weak or strong, we want EQ to be true for success, so that we - match the flags that we got from the compare above. */ -@@ -26390,7 +27133,9 @@ - if (mod_f != MEMMODEL_RELAXED) - emit_label (label2); +@@ -747,6 +733,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fdivs%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fdivs")] + ) -- arm_post_atomic_barrier (mod_s); -+ /* Checks whether a barrier is needed and emits one accordingly. */ -+ if (!(use_acquire || use_release)) -+ arm_post_atomic_barrier (mod_s); +@@ -757,6 +744,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fdivd%?\\t%P0, %P1, %P2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fdivd")] + ) - if (mod_f == MEMMODEL_RELAXED) - emit_label (label2); -@@ -26405,8 +27150,20 @@ - enum machine_mode wmode = (mode == DImode ? DImode : SImode); - rtx label, x; +@@ -770,6 +758,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fmuls%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmuls")] + ) -- arm_pre_atomic_barrier (model); -+ bool use_acquire = TARGET_HAVE_LDACQ -+ && !(model == MEMMODEL_RELAXED -+ || model == MEMMODEL_CONSUME -+ || model == MEMMODEL_RELEASE); +@@ -780,6 +769,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fmuld%?\\t%P0, %P1, %P2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmuld")] + ) -+ bool use_release = TARGET_HAVE_LDACQ -+ && !(model == MEMMODEL_RELAXED -+ || model == MEMMODEL_CONSUME -+ || model == MEMMODEL_ACQUIRE); -+ -+ /* Checks whether a barrier is needed and emits one accordingly. */ -+ if (!(use_acquire || use_release)) -+ arm_pre_atomic_barrier (model); -+ - label = gen_label_rtx (); - emit_label (label); +@@ -790,6 +780,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fnmuls%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmuls")] + ) -@@ -26418,7 +27175,7 @@ - old_out = new_out; - value = simplify_gen_subreg (wmode, value, mode, 0); +@@ -800,6 +791,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fnmuld%?\\t%P0, %P1, %P2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmuld")] + ) -- arm_emit_load_exclusive (mode, old_out, mem); -+ arm_emit_load_exclusive (mode, old_out, mem, use_acquire); +@@ -815,6 +807,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fmacs%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmacs")] + ) - switch (code) - { -@@ -26466,12 +27223,15 @@ - break; - } +@@ -826,6 +819,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fmacd%?\\t%P0, %P2, %P3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmacd")] + ) + +@@ -838,6 +832,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fmscs%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmacs")] + ) -- arm_emit_store_exclusive (mode, cond, mem, gen_lowpart (mode, new_out)); -+ arm_emit_store_exclusive (mode, cond, mem, gen_lowpart (mode, new_out), -+ use_release); +@@ -849,6 +844,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fmscd%?\\t%P0, %P2, %P3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmacd")] + ) - x = gen_rtx_NE (VOIDmode, cond, const0_rtx); - emit_unlikely_jump (gen_cbranchsi4 (x, cond, const0_rtx, label)); +@@ -861,6 +857,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fnmacs%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmacs")] + ) -- arm_post_atomic_barrier (model); -+ /* Checks whether a barrier is needed and emits one accordingly. */ -+ if (!(use_acquire || use_release)) -+ arm_post_atomic_barrier (model); - } - - #define MAX_VECT_LEN 16 -@@ -27411,4 +28171,12 @@ +@@ -872,6 +869,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fnmacd%?\\t%P0, %P2, %P3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmacd")] + ) - } +@@ -886,6 +884,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fnmscs%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmacs")] + ) -+/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */ -+ -+static unsigned HOST_WIDE_INT -+arm_asan_shadow_offset (void) -+{ -+ return (unsigned HOST_WIDE_INT) 1 << 29; -+} -+ - #include "gt-arm.h" ---- a/src/gcc/config/arm/arm.h -+++ b/src/gcc/config/arm/arm.h -@@ -350,10 +350,16 @@ - #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ - && arm_arch_notm) +@@ -898,6 +897,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fnmscd%?\\t%P0, %P2, %P3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fmacd")] + ) -+/* Nonzero if this chip supports load-acquire and store-release. */ -+#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) -+ - /* Nonzero if integer division instructions supported. */ - #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ - || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) +@@ -911,6 +911,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" + "vfma%?.\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "ffma")] + ) -+/* Should NEON be used for 64-bits bitops. */ -+#define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) -+ - /* True iff the full BPABI is being used. If TARGET_BPABI is true, - then TARGET_AAPCS_BASED must be true -- but the converse does not - hold. TARGET_BPABI implies the use of the BPABI runtime library, -@@ -539,6 +545,10 @@ - /* Nonzero if chip supports integer division instruction in Thumb mode. */ - extern int arm_arch_thumb_hwdiv; +@@ -923,6 +924,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" + "vfms%?.\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "ffma")] + ) -+/* Nonzero if we should use Neon to handle 64-bits operations rather -+ than core registers. */ -+extern int prefer_neon_for_64bits; -+ - #ifndef TARGET_DEFAULT - #define TARGET_DEFAULT (MASK_APCS_FRAME) - #endif -@@ -1040,7 +1050,7 @@ - /* Modes valid for Neon D registers. */ - #define VALID_NEON_DREG_MODE(MODE) \ - ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ -- || (MODE) == V2SFmode || (MODE) == DImode) -+ || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) +@@ -934,6 +936,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" + "vfnms%?.\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "ffma")] + ) - /* Modes valid for Neon Q registers. */ - #define VALID_NEON_QREG_MODE(MODE) \ -@@ -1639,7 +1649,7 @@ - frame. */ - #define EXIT_IGNORE_STACK 1 +@@ -946,6 +949,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" + "vfnma%?.\\t%0, %1, %2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "ffma")] + ) --#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) -+#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) +@@ -958,6 +962,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fcvtds%?\\t%P0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - /* Determine if the epilogue should be output as RTL. - You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ ---- a/src/gcc/config/arm/arm-fixed.md -+++ b/src/gcc/config/arm/arm-fixed.md -@@ -19,12 +19,13 @@ - ;; This file contains ARM instructions that support fixed-point operations. +@@ -967,6 +972,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fcvtsd%?\\t%0, %P1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - (define_insn "add3" -- [(set (match_operand:FIXED 0 "s_register_operand" "=r") -- (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "r") -- (match_operand:FIXED 2 "s_register_operand" "r")))] -+ [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") -+ (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") -+ (match_operand:FIXED 2 "s_register_operand" "l,r")))] - "TARGET_32BIT" - "add%?\\t%0, %1, %2" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "yes,no")]) +@@ -976,6 +982,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16" + "vcvtb%?.f32.f16\\t%0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - (define_insn "add3" - [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") -@@ -32,7 +33,8 @@ - (match_operand:ADDSUB 2 "s_register_operand" "r")))] - "TARGET_INT_SIMD" - "sadd%?\\t%0, %1, %2" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) +@@ -985,6 +992,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16" + "vcvtb%?.f16.f32\\t%0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - (define_insn "usadd3" - [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") -@@ -40,7 +42,8 @@ - (match_operand:UQADDSUB 2 "s_register_operand" "r")))] - "TARGET_INT_SIMD" - "uqadd%?\\t%0, %1, %2" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) +@@ -994,6 +1002,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "ftosizs%?\\t%0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - (define_insn "ssadd3" - [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") -@@ -48,15 +51,17 @@ - (match_operand:QADDSUB 2 "s_register_operand" "r")))] - "TARGET_INT_SIMD" - "qadd%?\\t%0, %1, %2" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) +@@ -1003,6 +1012,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "ftosizd%?\\t%0, %P1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - (define_insn "sub3" -- [(set (match_operand:FIXED 0 "s_register_operand" "=r") -- (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "r") -- (match_operand:FIXED 2 "s_register_operand" "r")))] -+ [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") -+ (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") -+ (match_operand:FIXED 2 "s_register_operand" "l,r")))] - "TARGET_32BIT" - "sub%?\\t%0, %1, %2" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "yes,no")]) +@@ -1013,6 +1023,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "ftouizs%?\\t%0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - (define_insn "sub3" - [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") -@@ -64,7 +69,8 @@ - (match_operand:ADDSUB 2 "s_register_operand" "r")))] - "TARGET_INT_SIMD" - "ssub%?\\t%0, %1, %2" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) +@@ -1022,6 +1033,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "ftouizd%?\\t%0, %P1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - (define_insn "ussub3" - [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") -@@ -73,7 +79,8 @@ - (match_operand:UQADDSUB 2 "s_register_operand" "r")))] - "TARGET_INT_SIMD" - "uqsub%?\\t%0, %1, %2" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) +@@ -1032,6 +1044,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fsitos%?\\t%0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - (define_insn "sssub3" - [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") -@@ -81,7 +88,8 @@ - (match_operand:QADDSUB 2 "s_register_operand" "r")))] - "TARGET_INT_SIMD" - "qsub%?\\t%0, %1, %2" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) +@@ -1041,6 +1054,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fsitod%?\\t%P0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) - ;; Fractional multiplies. +@@ -1051,6 +1065,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fuitos%?\\t%0, %1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvt")] + ) -@@ -374,6 +382,7 @@ - "TARGET_32BIT && arm_arch6" - "ssat%?\\t%0, #16, %2%S1" +@@ -1060,6 +1075,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fuitod%?\\t%P0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") - (set_attr "insn" "sat") - (set_attr "shift" "1") - (set_attr "type" "alu_shift")]) -@@ -384,4 +393,5 @@ - "TARGET_INT_SIMD" - "usat%?\\t%0, #16, %1" + (set_attr "type" "f_cvt")] + ) + +@@ -1072,6 +1088,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" + "fsqrts%?\\t%0, %1" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") - (set_attr "insn" "sat")]) ---- a/src/gcc/config/arm/unspecs.md -+++ b/src/gcc/config/arm/unspecs.md -@@ -83,6 +83,8 @@ - ; FPSCR rounding mode and signal inexactness. - UNSPEC_VRINTA ; Represent a float to integral float rounding - ; towards nearest, ties away from zero. -+ UNSPEC_RRX ; Rotate Right with Extend shifts register right -+ ; by one place, with Carry flag shifted into bit[31]. - ]) + (set_attr "type" "fdivs")] + ) - (define_c_enum "unspec" [ -@@ -139,6 +141,10 @@ - VUNSPEC_ATOMIC_OP ; Represent an atomic operation. - VUNSPEC_LL ; Represent a load-register-exclusive. - VUNSPEC_SC ; Represent a store-register-exclusive. -+ VUNSPEC_LAX ; Represent a load-register-acquire-exclusive. -+ VUNSPEC_SLX ; Represent a store-register-release-exclusive. -+ VUNSPEC_LDA ; Represent a store-register-acquire. -+ VUNSPEC_STL ; Represent a store-register-release. - ]) +@@ -1081,6 +1098,7 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "fsqrtd%?\\t%P0, %P1" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fdivd")] + ) - ;; Enumerators for NEON unspecs. ---- a/src/gcc/config/arm/linux-eabi.h -+++ b/src/gcc/config/arm/linux-eabi.h -@@ -84,10 +84,14 @@ - LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ - LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) +@@ -1168,6 +1186,7 @@ + fcmps%?\\t%0, %1 + fcmpzs%?\\t%0" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fcmps")] + ) -+#undef ASAN_CC1_SPEC -+#define ASAN_CC1_SPEC "%{fsanitize=*:-funwind-tables}" -+ - #undef CC1_SPEC - #define CC1_SPEC \ -- LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC, \ -- GNU_USER_TARGET_CC1_SPEC " " ANDROID_CC1_SPEC) -+ LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC, \ -+ GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC " " \ -+ ANDROID_CC1_SPEC) +@@ -1180,6 +1199,7 @@ + fcmpes%?\\t%0, %1 + fcmpezs%?\\t%0" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fcmps")] + ) - #define CC1PLUS_SPEC \ - LINUX_OR_ANDROID_CC ("", ANDROID_CC1PLUS_SPEC) ---- a/src/gcc/config/arm/arm-cores.def -+++ b/src/gcc/config/arm/arm-cores.def -@@ -129,9 +129,11 @@ - ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) - ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) - ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) -+ARM_CORE("cortex-a53", cortexa53, 8A, FL_LDSCHED, cortex_a5) - ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex) - ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex) - ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) -+ARM_CORE("cortex-r7", cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) - ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex) - ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex) - ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, v6m) ---- a/src/gcc/config/arm/arm-tune.md -+++ b/src/gcc/config/arm/arm-tune.md -@@ -1,5 +1,5 @@ - ;; -*- buffer-read-only: t -*- - ;; Generated automatically by gentune.sh from arm-cores.def - (define_attr "tune" -- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4" -+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexa53,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4" - (const (symbol_ref "((enum attr_tune) arm_tune)"))) ---- a/src/gcc/config/arm/arm-protos.h -+++ b/src/gcc/config/arm/arm-protos.h -@@ -78,6 +78,7 @@ - extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode, - rtx (*) (rtx, rtx, rtx)); - extern rtx neon_make_constant (rtx); -+extern tree arm_builtin_vectorized_function (tree, tree, tree); - extern void neon_expand_vector_init (rtx, rtx); - extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); - extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); -@@ -117,7 +118,9 @@ - extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); - extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT); - extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool); -+extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool); - extern int arm_gen_movmemqi (rtx *); -+extern bool gen_movmem_ldrd_strd (rtx *); - extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); - extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, - HOST_WIDE_INT); -@@ -269,6 +272,8 @@ - bool logical_op_non_short_circuit[2]; - /* Vectorizer costs. */ - const struct cpu_vec_costs* vec_costs; -+ /* Prefer Neon for 64-bit bitops. */ -+ bool prefer_neon_for_64bits; - }; +@@ -1192,6 +1212,7 @@ + fcmpd%?\\t%P0, %P1 + fcmpzd%?\\t%P0" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fcmpd")] + ) - extern const struct tune_params *current_tune; ---- a/src/gcc/config/arm/vfp.md -+++ b/src/gcc/config/arm/vfp.md -@@ -132,8 +132,8 @@ - ;; DImode moves +@@ -1204,6 +1225,7 @@ + fcmped%?\\t%P0, %P1 + fcmpezd%?\\t%P0" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "fcmpd")] + ) + +@@ -1264,6 +1286,7 @@ + "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " + "vrint%?.\\t%0, %1" + [(set_attr "predicable" "") ++ (set_attr "predicable_short_it" "no") + (set_attr "type" "f_rint")] + ) + +--- a/src/gcc/config/arm/t-linux-eabi ++++ b/src/gcc/config/arm/t-linux-eabi +@@ -18,6 +18,8 @@ + + # We do not build a Thumb multilib for Linux because the definition of + # CLEAR_INSN_CACHE in linux-gas.h does not work in Thumb mode. ++# If you set MULTILIB_OPTIONS to a non-empty value you should also set ++# MULTILIB_DEFAULTS in linux-elf.h. + MULTILIB_OPTIONS = + MULTILIB_DIRNAMES = - (define_insn "*movdi_vfp" -- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,r,w,w, Uv") -- (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] -+ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv") -+ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))] - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 - && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode)) --- a/src/gcc/config/arm/neon.md +++ b/src/gcc/config/arm/neon.md -@@ -487,7 +487,7 @@ +@@ -61,8 +61,7 @@ + } + } + [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*") +- (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2") +- (set_attr "insn" "*,*,*,*,*,*,mov,*,*") ++ (set_attr "type" "*,f_stored,*,f_loadd,*,*,mov_reg,load2,store2") + (set_attr "length" "4,4,4,4,4,4,8,8,8") + (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*") + (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*") +@@ -107,8 +106,7 @@ + } + [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\ + neon_mrrc,neon_mcr_2_mcrr,*,*,*") +- (set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4") +- (set_attr "insn" "*,*,*,*,*,*,mov,*,*") ++ (set_attr "type" "*,*,*,*,*,*,mov_reg,load4,store4") + (set_attr "length" "4,8,4,8,8,8,16,8,16") + (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*") + (set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*") +@@ -487,7 +485,7 @@ [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1,*,*,*") (set_attr "conds" "*,clob,clob,*,clob,clob,clob") (set_attr "length" "*,8,8,*,8,8,8") @@ -19743,7 +29680,7 @@ ) (define_insn "*sub3_neon" -@@ -524,7 +524,7 @@ +@@ -524,7 +522,7 @@ [(set_attr "neon_type" "neon_int_2,*,*,*,neon_int_2") (set_attr "conds" "*,clob,clob,clob,*") (set_attr "length" "*,8,8,8,*") @@ -19752,16 +29689,37 @@ ) (define_insn "*mul3_neon" -@@ -699,7 +699,7 @@ - } - [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1") - (set_attr "length" "*,*,8,8,*,*") -- (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")] -+ (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] +@@ -679,29 +677,6 @@ + [(set_attr "neon_type" "neon_int_1")] ) +-(define_insn "iordi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r,?w,?w") +- (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0") +- (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r,w,Dl")))] +- "TARGET_NEON" +-{ +- switch (which_alternative) +- { +- case 0: /* fall through */ +- case 4: return "vorr\t%P0, %P1, %P2"; +- case 1: /* fall through */ +- case 5: return neon_output_logic_immediate ("vorr", &operands[2], +- DImode, 0, VALID_NEON_QREG_MODE (DImode)); +- case 2: return "#"; +- case 3: return "#"; +- default: gcc_unreachable (); +- } +-} +- [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1") +- (set_attr "length" "*,*,8,8,*,*") +- (set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")] +-) +- ;; The concrete forms of the Neon immediate-logic instructions are vbic and -@@ -724,29 +724,6 @@ + ;; vorr. We support the pseudo-instruction vand instead, because that + ;; corresponds to the canonical form the middle-end expects to use for +@@ -724,29 +699,6 @@ [(set_attr "neon_type" "neon_int_1")] ) @@ -19791,16 +29749,29 @@ (define_insn "orn3_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (ior:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w")) -@@ -840,7 +817,7 @@ - veor\t%P0, %P1, %P2" - [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1") - (set_attr "length" "*,8,8,*") -- (set_attr "arch" "nota8,*,*,onlya8")] -+ (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] +@@ -828,21 +780,6 @@ + [(set_attr "neon_type" "neon_int_1")] ) +-(define_insn "xordi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w") +- (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r,w") +- (match_operand:DI 2 "s_register_operand" "w,r,r,w")))] +- "TARGET_NEON" +- "@ +- veor\t%P0, %P1, %P2 +- # +- # +- veor\t%P0, %P1, %P2" +- [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1") +- (set_attr "length" "*,8,8,*") +- (set_attr "arch" "nota8,*,*,onlya8")] +-) +- (define_insn "one_cmpl2" -@@ -1162,7 +1139,7 @@ + [(set (match_operand:VDQ 0 "s_register_operand" "=w") + (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))] +@@ -1162,7 +1099,7 @@ } DONE; }" @@ -19809,7 +29780,7 @@ (set_attr "opt" "*,*,speed,speed,*,*")] ) -@@ -1263,7 +1240,7 @@ +@@ -1263,7 +1200,7 @@ DONE; }" @@ -19818,7 +29789,7 @@ (set_attr "opt" "*,*,speed,speed,*,*")] ) -@@ -3281,6 +3258,24 @@ +@@ -3305,6 +3242,24 @@ (const_string "neon_fp_vadd_qqq_vabs_qq")))] ) @@ -19843,7 +29814,42 @@ (define_insn "neon_vcvt_n" [(set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") -@@ -5611,7 +5606,7 @@ +@@ -4660,21 +4615,22 @@ + ) + + (define_insn "neon_vld1_dup" +- [(set (match_operand:VDX 0 "s_register_operand" "=w") +- (vec_duplicate:VDX (match_operand: 1 "neon_struct_operand" "Um")))] ++ [(set (match_operand:VD 0 "s_register_operand" "=w") ++ (vec_duplicate:VD (match_operand: 1 "neon_struct_operand" "Um")))] + "TARGET_NEON" +-{ +- if (GET_MODE_NUNITS (mode) > 1) +- return "vld1.\t{%P0[]}, %A1"; +- else +- return "vld1.\t%h0, %A1"; +-} +- [(set (attr "neon_type") +- (if_then_else (gt (const_string "") (const_string "1")) +- (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes") +- (const_string "neon_vld1_1_2_regs")))] ++ "vld1.\t{%P0[]}, %A1" ++ [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")] + ) + ++;; Special case for DImode. Treat it exactly like a simple load. ++(define_expand "neon_vld1_dupdi" ++ [(set (match_operand:DI 0 "s_register_operand" "") ++ (unspec:DI [(match_operand:DI 1 "neon_struct_operand" "")] ++ UNSPEC_VLD1))] ++ "TARGET_NEON" ++ "" ++) ++ + (define_insn "neon_vld1_dup" + [(set (match_operand:VQ 0 "s_register_operand" "=w") + (vec_duplicate:VQ (match_operand: 1 "neon_struct_operand" "Um")))] +@@ -5635,7 +5591,7 @@ (match_operand:SI 3 "immediate_operand" "")] "TARGET_NEON" { @@ -19852,6 +29858,24 @@ DONE; }) +@@ -5646,7 +5602,7 @@ + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" + { +- emit_insn (gen_ior3 (operands[0], operands[1], operands[2])); ++ emit_insn (gen_ior3 (operands[0], operands[1], operands[2])); + DONE; + }) + +@@ -5657,7 +5613,7 @@ + (match_operand:SI 3 "immediate_operand" "")] + "TARGET_NEON" + { +- emit_insn (gen_xor3 (operands[0], operands[1], operands[2])); ++ emit_insn (gen_xor3 (operands[0], operands[1], operands[2])); + DONE; + }) + --- a/src/gcc/config/arm/ldmstm.md +++ b/src/gcc/config/arm/ldmstm.md @@ -37,7 +37,8 @@ @@ -20540,7 +30564,7 @@ ;; - in ARM/Thumb-2 state: t, w, x, y, z ;; - in Thumb state: h, b -;; - in both states: l, c, k -+;; - in both states: l, c, k, q ++;; - in both states: l, c, k, q, US ;; In ARM state, 'l' is an alias for 'r' ;; 'f' and 'v' were previously used for FPA and MAVERICK registers. @@ -20554,7 +30578,41 @@ (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS" "@internal Thumb only. The union of the low registers and the stack register.") -@@ -248,6 +251,12 @@ +@@ -93,6 +96,9 @@ + (define_register_constraint "c" "CC_REG" + "@internal The condition code register.") + ++(define_register_constraint "Cs" "CALLER_SAVE_REGS" ++ "@internal The caller save registers. Useful for sibcalls.") ++ + (define_constraint "I" + "In ARM/Thumb-2 state a constant that can be used as an immediate value in a + Data Processing instruction. In Thumb-1 state a constant in the range +@@ -164,9 +170,9 @@ + && ival > 1020 && ival <= 1275"))) + + (define_constraint "Pd" +- "@internal In Thumb-1 state a constant in the range 0 to 7" ++ "@internal In Thumb state a constant in the range 0 to 7" + (and (match_code "const_int") +- (match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7"))) ++ (match_test "TARGET_THUMB && ival >= 0 && ival <= 7"))) + + (define_constraint "Pe" + "@internal In Thumb-1 state a constant in the range 256 to +510" +@@ -208,6 +214,11 @@ + (and (match_code "const_int") + (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255"))) + ++(define_constraint "Pz" ++ "@internal In Thumb-2 state the constant 0" ++ (and (match_code "const_int") ++ (match_test "TARGET_THUMB2 && (ival == 0)"))) ++ + (define_constraint "G" + "In ARM/Thumb-2 state the floating-point constant 0." + (and (match_code "const_double") +@@ -248,6 +259,24 @@ (and (match_code "const_int") (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)"))) @@ -20564,9 +30622,102 @@ + (and (match_code "const_int") + (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, AND)"))) + ++(define_constraint "Df" ++ "@internal ++ In ARM/Thumb-2 state a const_int that can be used by insn iordi." ++ (and (match_code "const_int") ++ (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, IOR)"))) ++ ++(define_constraint "Dg" ++ "@internal ++ In ARM/Thumb-2 state a const_int that can be used by insn xordi." ++ (and (match_code "const_int") ++ (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, XOR)"))) ++ (define_constraint "Di" "@internal In ARM/Thumb-2 state a const_int or const_double where both the high +@@ -305,6 +334,9 @@ + (and (match_code "const_double") + (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)"))) + ++(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS" ++ "For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.") ++ + (define_memory_constraint "Ua" + "@internal + An address valid for loading/storing register exclusive" +@@ -385,9 +417,16 @@ + 0) + && GET_CODE (XEXP (op, 0)) != POST_INC"))) + ++(define_constraint "US" ++ "@internal ++ US is a symbol reference." ++ (match_code "symbol_ref") ++) ++ + ;; We used to have constraint letters for S and R in ARM state, but + ;; all uses of these now appear to have been removed. + + ;; Additionally, we used to have a Q constraint in Thumb state, but + ;; this wasn't really a valid memory constraint. Again, all uses of + ;; this now seem to have been removed. ++ +--- a/src/gcc/config/arm/cortex-a7.md ++++ b/src/gcc/config/arm/cortex-a7.md +@@ -88,9 +88,9 @@ + ;; ALU instruction with an immediate operand can dual-issue. + (define_insn_reservation "cortex_a7_alu_imm" 2 + (and (eq_attr "tune" "cortexa7") +- (and (ior (eq_attr "type" "simple_alu_imm") +- (ior (eq_attr "type" "simple_alu_shift") +- (and (eq_attr "insn" "mov") ++ (and (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm") ++ (ior (eq_attr "type" "extend") ++ (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg") + (not (eq_attr "length" "8"))))) + (eq_attr "neon_type" "none"))) + "cortex_a7_ex2|cortex_a7_ex1") +@@ -99,13 +99,15 @@ + ;; with a younger immediate-based instruction. + (define_insn_reservation "cortex_a7_alu_reg" 2 + (and (eq_attr "tune" "cortexa7") +- (and (eq_attr "type" "alu_reg") ++ (and (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg") + (eq_attr "neon_type" "none"))) + "cortex_a7_ex1") + + (define_insn_reservation "cortex_a7_alu_shift" 2 + (and (eq_attr "tune" "cortexa7") +- (and (eq_attr "type" "alu_shift,alu_shift_reg") ++ (and (eq_attr "type" "arlo_shift,arlo_shift_reg,\ ++ mov_shift,mov_shift_reg,\ ++ mvn_shift,mvn_shift_reg") + (eq_attr "neon_type" "none"))) + "cortex_a7_ex1") + +@@ -127,8 +129,9 @@ + + (define_insn_reservation "cortex_a7_mul" 2 + (and (eq_attr "tune" "cortexa7") +- (and (eq_attr "type" "mult") +- (eq_attr "neon_type" "none"))) ++ (and (eq_attr "neon_type" "none") ++ (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes")))) + "cortex_a7_both") + + ;; Forward the result of a multiply operation to the accumulator +@@ -140,7 +143,7 @@ + ;; The latency depends on the operands, so we use an estimate here. + (define_insn_reservation "cortex_a7_idiv" 5 + (and (eq_attr "tune" "cortexa7") +- (eq_attr "insn" "udiv,sdiv")) ++ (eq_attr "type" "udiv,sdiv")) + "cortex_a7_both*5") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; --- a/src/gcc/config/arm/arm-arches.def +++ b/src/gcc/config/arm/arm-arches.def @@ -53,6 +53,6 @@ @@ -20626,6 +30777,67 @@ +mneon-for-64bits +Target Report RejectNegative Var(use_neon_for_64bits) Init(0) +Use Neon to perform 64-bits operations rather than core registers. +--- a/src/gcc/config/arm/arm926ejs.md ++++ b/src/gcc/config/arm/arm926ejs.md +@@ -58,7 +58,9 @@ + ;; ALU operations with no shifted operand + (define_insn_reservation "9_alu_op" 1 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,\ ++ mov_imm,mov_reg,mov_shift,\ ++ mvn_imm,mvn_reg,mvn_shift")) + "e,m,w") + + ;; ALU operations with a shift-by-register operand +@@ -67,7 +69,7 @@ + ;; the execute stage. + (define_insn_reservation "9_alu_shift_reg_op" 2 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "type" "alu_shift_reg")) ++ (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg")) + "e*2,m,w") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +@@ -81,32 +83,32 @@ + + (define_insn_reservation "9_mult1" 3 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "insn" "smlalxy,mul,mla")) ++ (eq_attr "type" "smlalxy,mul,mla")) + "e*2,m,w") + + (define_insn_reservation "9_mult2" 4 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "insn" "muls,mlas")) ++ (eq_attr "type" "muls,mlas")) + "e*3,m,w") + + (define_insn_reservation "9_mult3" 4 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "insn" "umull,umlal,smull,smlal")) ++ (eq_attr "type" "umull,umlal,smull,smlal")) + "e*3,m,w") + + (define_insn_reservation "9_mult4" 5 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "insn" "umulls,umlals,smulls,smlals")) ++ (eq_attr "type" "umulls,umlals,smulls,smlals")) + "e*4,m,w") + + (define_insn_reservation "9_mult5" 2 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "insn" "smulxy,smlaxy,smlawx")) ++ (eq_attr "type" "smulxy,smlaxy,smlawx")) + "e,m,w") + + (define_insn_reservation "9_mult6" 3 + (and (eq_attr "tune" "arm926ejs") +- (eq_attr "insn" "smlalxy")) ++ (eq_attr "type" "smlalxy")) + "e*2,m,w") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; --- a/src/gcc/config/arm/ldrdstrd.md +++ b/src/gcc/config/arm/ldrdstrd.md @@ -0,0 +1,260 @@ @@ -20886,149 +31098,1303 @@ + } +) + -+;; TODO: Handle LDRD/STRD with writeback: -+;; (a) memory operands can be POST_INC, POST_DEC, PRE_MODIFY, POST_MODIFY -+;; (b) Patterns may be followed by an update of the base address. ---- a/src/gcc/config/arm/predicates.md -+++ b/src/gcc/config/arm/predicates.md -@@ -31,6 +31,17 @@ - || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); - }) ++;; TODO: Handle LDRD/STRD with writeback: ++;; (a) memory operands can be POST_INC, POST_DEC, PRE_MODIFY, POST_MODIFY ++;; (b) Patterns may be followed by an update of the base address. +--- a/src/gcc/config/arm/predicates.md ++++ b/src/gcc/config/arm/predicates.md +@@ -31,6 +31,28 @@ + || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); + }) + ++(define_predicate "imm_for_neon_inv_logic_operand" ++ (match_code "const_vector") ++{ ++ return (TARGET_NEON ++ && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); ++}) ++ ++(define_predicate "neon_inv_logic_op2" ++ (ior (match_operand 0 "imm_for_neon_inv_logic_operand") ++ (match_operand 0 "s_register_operand"))) ++ ++(define_predicate "imm_for_neon_logic_operand" ++ (match_code "const_vector") ++{ ++ return (TARGET_NEON ++ && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); ++}) ++ ++(define_predicate "neon_logic_op2" ++ (ior (match_operand 0 "imm_for_neon_logic_operand") ++ (match_operand 0 "s_register_operand"))) ++ + ;; Any hard register. + (define_predicate "arm_hard_register_operand" + (match_code "reg") +@@ -145,6 +167,23 @@ + (ior (match_operand 0 "arm_rhs_operand") + (match_operand 0 "arm_neg_immediate_operand"))) + ++(define_predicate "arm_anddi_operand_neon" ++ (ior (match_operand 0 "s_register_operand") ++ (and (match_code "const_int") ++ (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")) ++ (match_operand 0 "neon_inv_logic_op2"))) ++ ++(define_predicate "arm_iordi_operand_neon" ++ (ior (match_operand 0 "s_register_operand") ++ (and (match_code "const_int") ++ (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)")) ++ (match_operand 0 "neon_logic_op2"))) ++ ++(define_predicate "arm_xordi_operand" ++ (ior (match_operand 0 "s_register_operand") ++ (and (match_code "const_int") ++ (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)")))) ++ + (define_predicate "arm_adddi_operand" + (ior (match_operand 0 "s_register_operand") + (and (match_code "const_int") +@@ -207,6 +246,10 @@ + (and (match_code "plus,minus,ior,xor,and") + (match_test "mode == GET_MODE (op)"))) + ++(define_special_predicate "shiftable_operator_strict_it" ++ (and (match_code "plus,and") ++ (match_test "mode == GET_MODE (op)"))) ++ + ;; True for logical binary operators. + (define_special_predicate "logical_binary_operator" + (and (match_code "ior,xor,and") +@@ -270,6 +313,24 @@ + (define_special_predicate "lt_ge_comparison_operator" + (match_code "lt,ge")) + ++;; The vsel instruction only accepts the ARM condition codes listed below. ++(define_special_predicate "arm_vsel_comparison_operator" ++ (and (match_operand 0 "expandable_comparison_operator") ++ (match_test "maybe_get_arm_condition_code (op) == ARM_GE ++ || maybe_get_arm_condition_code (op) == ARM_GT ++ || maybe_get_arm_condition_code (op) == ARM_EQ ++ || maybe_get_arm_condition_code (op) == ARM_VS ++ || maybe_get_arm_condition_code (op) == ARM_LT ++ || maybe_get_arm_condition_code (op) == ARM_LE ++ || maybe_get_arm_condition_code (op) == ARM_NE ++ || maybe_get_arm_condition_code (op) == ARM_VC"))) ++ ++(define_special_predicate "arm_cond_move_operator" ++ (if_then_else (match_test "arm_restrict_it") ++ (and (match_test "TARGET_FPU_ARMV8") ++ (match_operand 0 "arm_vsel_comparison_operator")) ++ (match_operand 0 "expandable_comparison_operator"))) ++ + (define_special_predicate "noov_comparison_operator" + (match_code "lt,ge,eq,ne")) + +@@ -506,28 +567,6 @@ + (ior (match_operand 0 "s_register_operand") + (match_operand 0 "imm_for_neon_rshift_operand"))) + +-(define_predicate "imm_for_neon_logic_operand" +- (match_code "const_vector") +-{ +- return (TARGET_NEON +- && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); +-}) +- +-(define_predicate "imm_for_neon_inv_logic_operand" +- (match_code "const_vector") +-{ +- return (TARGET_NEON +- && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); +-}) +- +-(define_predicate "neon_logic_op2" +- (ior (match_operand 0 "imm_for_neon_logic_operand") +- (match_operand 0 "s_register_operand"))) +- +-(define_predicate "neon_inv_logic_op2" +- (ior (match_operand 0 "imm_for_neon_inv_logic_operand") +- (match_operand 0 "s_register_operand"))) +- + ;; Predicates for named expanders that overlap multiple ISAs. + + (define_predicate "cmpdi_operand" +@@ -617,3 +656,7 @@ + (define_predicate "mem_noofs_operand" + (and (match_code "mem") + (match_code "reg" "0"))) ++ ++(define_predicate "call_insn_operand" ++ (ior (match_code "symbol_ref") ++ (match_operand 0 "s_register_operand"))) +--- a/src/gcc/config/arm/arm_neon.h ++++ b/src/gcc/config/arm/arm_neon.h +@@ -43,6 +43,7 @@ + typedef __builtin_neon_si int32x2_t __attribute__ ((__vector_size__ (8))); + typedef __builtin_neon_di int64x1_t; + typedef __builtin_neon_sf float32x2_t __attribute__ ((__vector_size__ (8))); ++typedef __builtin_neon_hf float16x4_t __attribute__ ((__vector_size__ (8))); + typedef __builtin_neon_poly8 poly8x8_t __attribute__ ((__vector_size__ (8))); + typedef __builtin_neon_poly16 poly16x4_t __attribute__ ((__vector_size__ (8))); + typedef __builtin_neon_uqi uint8x8_t __attribute__ ((__vector_size__ (8))); +@@ -6016,6 +6017,22 @@ + return (uint32x4_t)__builtin_neon_vcvtv4sf (__a, 0); + } + ++#if ((__ARM_FP & 0x2) != 0) ++__extension__ static __inline float16x4_t __attribute__ ((__always_inline__)) ++vcvt_f16_f32 (float32x4_t __a) ++{ ++ return (float16x4_t)__builtin_neon_vcvtv4hfv4sf (__a); ++} ++ ++#endif ++#if ((__ARM_FP & 0x2) != 0) ++__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) ++vcvt_f32_f16 (float16x4_t __a) ++{ ++ return (float32x4_t)__builtin_neon_vcvtv4sfv4hf (__a); ++} ++ ++#endif + __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) + vcvt_n_s32_f32 (float32x2_t __a, const int __b) + { +--- a/src/gcc/config/arm/arm-ldmstm.ml ++++ b/src/gcc/config/arm/arm-ldmstm.ml +@@ -146,12 +146,15 @@ + | IA, true, true -> true + | _ -> false + ++exception InvalidAddrMode of string;; ++ + let target addrmode thumb = + match addrmode, thumb with + IA, true -> "TARGET_THUMB1" + | IA, false -> "TARGET_32BIT" + | DB, false -> "TARGET_32BIT" + | _, false -> "TARGET_ARM" ++ | _, _ -> raise (InvalidAddrMode "ERROR: Invalid Addressing mode for Thumb1.") + + let write_pattern_1 name ls addrmode nregs write_set_fn update thumb = + let astr = string_of_addrmode addrmode in +@@ -181,8 +184,10 @@ + done; + Printf.printf "}\"\n"; + Printf.printf " [(set_attr \"type\" \"%s%d\")" ls nregs; +- begin if not thumb then ++ if not thumb then begin + Printf.printf "\n (set_attr \"predicable\" \"yes\")"; ++ if addrmode == IA || addrmode == DB then ++ Printf.printf "\n (set_attr \"predicable_short_it\" \"no\")"; + end; + Printf.printf "])\n\n" + +--- a/src/gcc/config/arm/iwmmxt.md ++++ b/src/gcc/config/arm/iwmmxt.md +@@ -33,7 +33,7 @@ + "TARGET_REALLY_IWMMXT" + "tbcstb%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tbcst")] ++ (set_attr "type" "wmmx_tbcst")] + ) + + (define_insn "tbcstv4hi" +@@ -42,7 +42,7 @@ + "TARGET_REALLY_IWMMXT" + "tbcsth%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tbcst")] ++ (set_attr "type" "wmmx_tbcst")] + ) + + (define_insn "tbcstv2si" +@@ -51,7 +51,7 @@ + "TARGET_REALLY_IWMMXT" + "tbcstw%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tbcst")] ++ (set_attr "type" "wmmx_tbcst")] + ) + + (define_insn "iwmmxt_iordi3" +@@ -65,7 +65,7 @@ + #" + [(set_attr "predicable" "yes") + (set_attr "length" "4,8,8") +- (set_attr "wtype" "wor,none,none")] ++ (set_attr "type" "wmmx_wor,*,*")] + ) + + (define_insn "iwmmxt_xordi3" +@@ -79,7 +79,7 @@ + #" + [(set_attr "predicable" "yes") + (set_attr "length" "4,8,8") +- (set_attr "wtype" "wxor,none,none")] ++ (set_attr "type" "wmmx_wxor,*,*")] + ) + + (define_insn "iwmmxt_anddi3" +@@ -93,7 +93,7 @@ + #" + [(set_attr "predicable" "yes") + (set_attr "length" "4,8,8") +- (set_attr "wtype" "wand,none,none")] ++ (set_attr "type" "wmmx_wand,*,*")] + ) + + (define_insn "iwmmxt_nanddi3" +@@ -103,7 +103,7 @@ + "TARGET_REALLY_IWMMXT" + "wandn%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wandn")] ++ (set_attr "type" "wmmx_wandn")] + ) + + (define_insn "*iwmmxt_arm_movdi" +@@ -155,10 +155,9 @@ + (const_int 8) + (const_int 4))] + (const_int 4))) +- (set_attr "type" "*,*,*,load2,store2,*,*,*,*,*,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") ++ (set_attr "type" "*,*,*,load2,store2,wmmx_wmov,wmmx_tmcrr,wmmx_tmrrc,wmmx_wldr,wmmx_wstr,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") + (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*") +- (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*") +- (set_attr "wtype" "*,*,*,*,*,wmov,tmcrr,tmrrc,wldr,wstr,*,*,*,*,*")] ++ (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")] + ) + + (define_insn "*iwmmxt_movsi_insn" +@@ -188,7 +187,7 @@ + default: + gcc_unreachable (); + }" +- [(set_attr "type" "*,*,*,*,load1,store1,*,*,*,*,r_2_f,f_2_r,fcpys,f_loads,f_stores") ++ [(set_attr "type" "*,*,*,*,load1,store1,wmmx_tmcr,wmmx_tmrc,wmmx_wldr,wmmx_wstr,r_2_f,f_2_r,fcpys,f_loads,f_stores") + (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*") + (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*") +@@ -200,8 +199,7 @@ + ;; Also - we have to pretend that these insns clobber the condition code + ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize + ;; them. +- (set_attr "conds" "clob") +- (set_attr "wtype" "*,*,*,*,*,*,tmcr,tmrc,wldr,wstr,*,*,*,*,*")] ++ (set_attr "conds" "clob")] + ) + + ;; Because iwmmxt_movsi_insn is not predicable, we provide the +@@ -249,10 +247,9 @@ + }" + [(set_attr "predicable" "yes") + (set_attr "length" "4, 4, 4,4,4,8, 8,8") +- (set_attr "type" "*,*,*,*,*,*,load1,store1") ++ (set_attr "type" "wmmx_wmov,wmmx_wstr,wmmx_wldr,wmmx_tmrrc,wmmx_tmcrr,*,load1,store1") + (set_attr "pool_range" "*, *, 256,*,*,*, 256,*") +- (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*") +- (set_attr "wtype" "wmov,wstr,wldr,tmrrc,tmcrr,*,*,*")] ++ (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")] + ) + + (define_expand "iwmmxt_setwcgr0" +@@ -318,7 +315,7 @@ + "TARGET_REALLY_IWMMXT" + "wand\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wand")] ++ (set_attr "type" "wmmx_wand")] + ) + + (define_insn "*ior3_iwmmxt" +@@ -328,7 +325,7 @@ + "TARGET_REALLY_IWMMXT" + "wor\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wor")] ++ (set_attr "type" "wmmx_wor")] + ) + + (define_insn "*xor3_iwmmxt" +@@ -338,7 +335,7 @@ + "TARGET_REALLY_IWMMXT" + "wxor\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wxor")] ++ (set_attr "type" "wmmx_wxor")] + ) + + +@@ -351,7 +348,7 @@ + "TARGET_REALLY_IWMMXT" + "wadd%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wadd")] ++ (set_attr "type" "wmmx_wadd")] + ) + + (define_insn "ssaddv8qi3" +@@ -361,7 +358,7 @@ + "TARGET_REALLY_IWMMXT" + "waddbss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wadd")] ++ (set_attr "type" "wmmx_wadd")] + ) + + (define_insn "ssaddv4hi3" +@@ -371,7 +368,7 @@ + "TARGET_REALLY_IWMMXT" + "waddhss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wadd")] ++ (set_attr "type" "wmmx_wadd")] + ) + + (define_insn "ssaddv2si3" +@@ -381,7 +378,7 @@ + "TARGET_REALLY_IWMMXT" + "waddwss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wadd")] ++ (set_attr "type" "wmmx_wadd")] + ) + + (define_insn "usaddv8qi3" +@@ -391,7 +388,7 @@ + "TARGET_REALLY_IWMMXT" + "waddbus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wadd")] ++ (set_attr "type" "wmmx_wadd")] + ) + + (define_insn "usaddv4hi3" +@@ -401,7 +398,7 @@ + "TARGET_REALLY_IWMMXT" + "waddhus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wadd")] ++ (set_attr "type" "wmmx_wadd")] + ) + + (define_insn "usaddv2si3" +@@ -411,7 +408,7 @@ + "TARGET_REALLY_IWMMXT" + "waddwus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wadd")] ++ (set_attr "type" "wmmx_wadd")] + ) + + (define_insn "*sub3_iwmmxt" +@@ -421,7 +418,7 @@ + "TARGET_REALLY_IWMMXT" + "wsub%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsub")] ++ (set_attr "type" "wmmx_wsub")] + ) + + (define_insn "sssubv8qi3" +@@ -431,7 +428,7 @@ + "TARGET_REALLY_IWMMXT" + "wsubbss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsub")] ++ (set_attr "type" "wmmx_wsub")] + ) + + (define_insn "sssubv4hi3" +@@ -441,7 +438,7 @@ + "TARGET_REALLY_IWMMXT" + "wsubhss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsub")] ++ (set_attr "type" "wmmx_wsub")] + ) + + (define_insn "sssubv2si3" +@@ -451,7 +448,7 @@ + "TARGET_REALLY_IWMMXT" + "wsubwss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsub")] ++ (set_attr "type" "wmmx_wsub")] + ) + + (define_insn "ussubv8qi3" +@@ -461,7 +458,7 @@ + "TARGET_REALLY_IWMMXT" + "wsubbus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsub")] ++ (set_attr "type" "wmmx_wsub")] + ) + + (define_insn "ussubv4hi3" +@@ -471,7 +468,7 @@ + "TARGET_REALLY_IWMMXT" + "wsubhus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsub")] ++ (set_attr "type" "wmmx_wsub")] + ) + + (define_insn "ussubv2si3" +@@ -481,7 +478,7 @@ + "TARGET_REALLY_IWMMXT" + "wsubwus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsub")] ++ (set_attr "type" "wmmx_wsub")] + ) + + (define_insn "*mulv4hi3_iwmmxt" +@@ -491,7 +488,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulul%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmul")] ++ (set_attr "type" "wmmx_wmul")] + ) + + (define_insn "smulv4hi3_highpart" +@@ -504,7 +501,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulsm%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmul")] ++ (set_attr "type" "wmmx_wmul")] + ) + + (define_insn "umulv4hi3_highpart" +@@ -517,7 +514,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulum%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmul")] ++ (set_attr "type" "wmmx_wmul")] + ) + + (define_insn "iwmmxt_wmacs" +@@ -528,7 +525,7 @@ + "TARGET_REALLY_IWMMXT" + "wmacs%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmac")] ++ (set_attr "type" "wmmx_wmac")] + ) + + (define_insn "iwmmxt_wmacsz" +@@ -538,7 +535,7 @@ + "TARGET_REALLY_IWMMXT" + "wmacsz%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmac")] ++ (set_attr "type" "wmmx_wmac")] + ) + + (define_insn "iwmmxt_wmacu" +@@ -549,7 +546,7 @@ + "TARGET_REALLY_IWMMXT" + "wmacu%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmac")] ++ (set_attr "type" "wmmx_wmac")] + ) + + (define_insn "iwmmxt_wmacuz" +@@ -559,7 +556,7 @@ + "TARGET_REALLY_IWMMXT" + "wmacuz%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmac")] ++ (set_attr "type" "wmmx_wmac")] + ) + + ;; Same as xordi3, but don't show input operands so that we don't think +@@ -570,7 +567,7 @@ + "TARGET_REALLY_IWMMXT" + "wxor%?\\t%0, %0, %0" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wxor")] ++ (set_attr "type" "wmmx_wxor")] + ) + + ;; Seems like cse likes to generate these, so we have to support them. +@@ -584,7 +581,7 @@ + "TARGET_REALLY_IWMMXT" + "wxor%?\\t%0, %0, %0" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wxor")] ++ (set_attr "type" "wmmx_wxor")] + ) + + (define_insn "iwmmxt_clrv4hi" +@@ -594,7 +591,7 @@ + "TARGET_REALLY_IWMMXT" + "wxor%?\\t%0, %0, %0" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wxor")] ++ (set_attr "type" "wmmx_wxor")] + ) + + (define_insn "iwmmxt_clrv2si" +@@ -603,7 +600,7 @@ + "TARGET_REALLY_IWMMXT" + "wxor%?\\t%0, %0, %0" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wxor")] ++ (set_attr "type" "wmmx_wxor")] + ) + + ;; Unsigned averages/sum of absolute differences +@@ -627,7 +624,7 @@ + "TARGET_REALLY_IWMMXT" + "wavg2br%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wavg2")] ++ (set_attr "type" "wmmx_wavg2")] + ) + + (define_insn "iwmmxt_uavgrndv4hi3" +@@ -645,7 +642,7 @@ + "TARGET_REALLY_IWMMXT" + "wavg2hr%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wavg2")] ++ (set_attr "type" "wmmx_wavg2")] + ) + + (define_insn "iwmmxt_uavgv8qi3" +@@ -658,7 +655,7 @@ + "TARGET_REALLY_IWMMXT" + "wavg2b%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wavg2")] ++ (set_attr "type" "wmmx_wavg2")] + ) + + (define_insn "iwmmxt_uavgv4hi3" +@@ -671,7 +668,7 @@ + "TARGET_REALLY_IWMMXT" + "wavg2h%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wavg2")] ++ (set_attr "type" "wmmx_wavg2")] + ) + + ;; Insert/extract/shuffle +@@ -690,7 +687,7 @@ + } + " + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tinsr")] ++ (set_attr "type" "wmmx_tinsr")] + ) + + (define_insn "iwmmxt_tinsrh" +@@ -707,7 +704,7 @@ + } + " + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tinsr")] ++ (set_attr "type" "wmmx_tinsr")] + ) + + (define_insn "iwmmxt_tinsrw" +@@ -724,7 +721,7 @@ + } + " + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tinsr")] ++ (set_attr "type" "wmmx_tinsr")] + ) + + (define_insn "iwmmxt_textrmub" +@@ -735,7 +732,7 @@ + "TARGET_REALLY_IWMMXT" + "textrmub%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "textrm")] ++ (set_attr "type" "wmmx_textrm")] + ) + + (define_insn "iwmmxt_textrmsb" +@@ -746,7 +743,7 @@ + "TARGET_REALLY_IWMMXT" + "textrmsb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "textrm")] ++ (set_attr "type" "wmmx_textrm")] + ) + + (define_insn "iwmmxt_textrmuh" +@@ -757,7 +754,7 @@ + "TARGET_REALLY_IWMMXT" + "textrmuh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "textrm")] ++ (set_attr "type" "wmmx_textrm")] + ) + + (define_insn "iwmmxt_textrmsh" +@@ -768,7 +765,7 @@ + "TARGET_REALLY_IWMMXT" + "textrmsh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "textrm")] ++ (set_attr "type" "wmmx_textrm")] + ) + + ;; There are signed/unsigned variants of this instruction, but they are +@@ -780,7 +777,7 @@ + "TARGET_REALLY_IWMMXT" + "textrmsw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "textrm")] ++ (set_attr "type" "wmmx_textrm")] + ) + + (define_insn "iwmmxt_wshufh" +@@ -790,7 +787,7 @@ + "TARGET_REALLY_IWMMXT" + "wshufh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wshufh")] ++ (set_attr "type" "wmmx_wshufh")] + ) + + ;; Mask-generating comparisons +@@ -812,7 +809,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpeqb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpeq")] ++ (set_attr "type" "wmmx_wcmpeq")] + ) + + (define_insn "eqv4hi3" +@@ -823,7 +820,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpeqh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpeq")] ++ (set_attr "type" "wmmx_wcmpeq")] + ) + + (define_insn "eqv2si3" +@@ -835,7 +832,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpeqw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpeq")] ++ (set_attr "type" "wmmx_wcmpeq")] + ) + + (define_insn "gtuv8qi3" +@@ -846,7 +843,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpgtub%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpgt")] ++ (set_attr "type" "wmmx_wcmpgt")] + ) + + (define_insn "gtuv4hi3" +@@ -857,7 +854,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpgtuh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpgt")] ++ (set_attr "type" "wmmx_wcmpgt")] + ) + + (define_insn "gtuv2si3" +@@ -868,7 +865,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpgtuw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpgt")] ++ (set_attr "type" "wmmx_wcmpgt")] + ) + + (define_insn "gtv8qi3" +@@ -879,7 +876,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpgtsb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpgt")] ++ (set_attr "type" "wmmx_wcmpgt")] + ) + + (define_insn "gtv4hi3" +@@ -890,7 +887,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpgtsh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpgt")] ++ (set_attr "type" "wmmx_wcmpgt")] + ) + + (define_insn "gtv2si3" +@@ -901,7 +898,7 @@ + "TARGET_REALLY_IWMMXT" + "wcmpgtsw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wcmpgt")] ++ (set_attr "type" "wmmx_wcmpgt")] + ) + + ;; Max/min insns +@@ -913,7 +910,7 @@ + "TARGET_REALLY_IWMMXT" + "wmaxs%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmax")] ++ (set_attr "type" "wmmx_wmax")] + ) + + (define_insn "*umax3_iwmmxt" +@@ -923,7 +920,7 @@ + "TARGET_REALLY_IWMMXT" + "wmaxu%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmax")] ++ (set_attr "type" "wmmx_wmax")] + ) + + (define_insn "*smin3_iwmmxt" +@@ -933,7 +930,7 @@ + "TARGET_REALLY_IWMMXT" + "wmins%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmin")] ++ (set_attr "type" "wmmx_wmin")] + ) + + (define_insn "*umin3_iwmmxt" +@@ -943,7 +940,7 @@ + "TARGET_REALLY_IWMMXT" + "wminu%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmin")] ++ (set_attr "type" "wmmx_wmin")] + ) + + ;; Pack/unpack insns. +@@ -956,7 +953,7 @@ + "TARGET_REALLY_IWMMXT" + "wpackhss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wpack")] ++ (set_attr "type" "wmmx_wpack")] + ) + + (define_insn "iwmmxt_wpackwss" +@@ -967,7 +964,7 @@ + "TARGET_REALLY_IWMMXT" + "wpackwss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wpack")] ++ (set_attr "type" "wmmx_wpack")] + ) + + (define_insn "iwmmxt_wpackdss" +@@ -978,7 +975,7 @@ + "TARGET_REALLY_IWMMXT" + "wpackdss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wpack")] ++ (set_attr "type" "wmmx_wpack")] + ) + + (define_insn "iwmmxt_wpackhus" +@@ -989,7 +986,7 @@ + "TARGET_REALLY_IWMMXT" + "wpackhus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wpack")] ++ (set_attr "type" "wmmx_wpack")] + ) + + (define_insn "iwmmxt_wpackwus" +@@ -1000,7 +997,7 @@ + "TARGET_REALLY_IWMMXT" + "wpackwus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wpack")] ++ (set_attr "type" "wmmx_wpack")] + ) + + (define_insn "iwmmxt_wpackdus" +@@ -1011,7 +1008,7 @@ + "TARGET_REALLY_IWMMXT" + "wpackdus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wpack")] ++ (set_attr "type" "wmmx_wpack")] + ) + + (define_insn "iwmmxt_wunpckihb" +@@ -1039,7 +1036,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckihb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckih")] ++ (set_attr "type" "wmmx_wunpckih")] + ) + + (define_insn "iwmmxt_wunpckihh" +@@ -1059,7 +1056,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckihh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckih")] ++ (set_attr "type" "wmmx_wunpckih")] + ) -+(define_predicate "imm_for_neon_inv_logic_operand" -+ (match_code "const_vector") -+{ -+ return (TARGET_NEON -+ && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); -+}) -+ -+(define_predicate "neon_inv_logic_op2" -+ (ior (match_operand 0 "imm_for_neon_inv_logic_operand") -+ (match_operand 0 "s_register_operand"))) -+ - ;; Any hard register. - (define_predicate "arm_hard_register_operand" - (match_code "reg") -@@ -145,6 +156,12 @@ - (ior (match_operand 0 "arm_rhs_operand") - (match_operand 0 "arm_neg_immediate_operand"))) + (define_insn "iwmmxt_wunpckihw" +@@ -1075,7 +1072,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckihw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckih")] ++ (set_attr "type" "wmmx_wunpckih")] + ) -+(define_predicate "arm_anddi_operand_neon" -+ (ior (match_operand 0 "s_register_operand") -+ (and (match_code "const_int") -+ (match_test "const_ok_for_dimode_op (INTVAL (op), AND)")) -+ (match_operand 0 "neon_inv_logic_op2"))) -+ - (define_predicate "arm_adddi_operand" - (ior (match_operand 0 "s_register_operand") - (and (match_code "const_int") -@@ -270,6 +287,18 @@ - (define_special_predicate "lt_ge_comparison_operator" - (match_code "lt,ge")) + (define_insn "iwmmxt_wunpckilb" +@@ -1103,7 +1100,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckilb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckil")] ++ (set_attr "type" "wmmx_wunpckil")] + ) -+;; The vsel instruction only accepts the ARM condition codes listed below. -+(define_special_predicate "arm_vsel_comparison_operator" -+ (and (match_operand 0 "expandable_comparison_operator") -+ (match_test "maybe_get_arm_condition_code (op) == ARM_GE -+ || maybe_get_arm_condition_code (op) == ARM_GT -+ || maybe_get_arm_condition_code (op) == ARM_EQ -+ || maybe_get_arm_condition_code (op) == ARM_VS -+ || maybe_get_arm_condition_code (op) == ARM_LT -+ || maybe_get_arm_condition_code (op) == ARM_LE -+ || maybe_get_arm_condition_code (op) == ARM_NE -+ || maybe_get_arm_condition_code (op) == ARM_VC"))) -+ - (define_special_predicate "noov_comparison_operator" - (match_code "lt,ge,eq,ne")) + (define_insn "iwmmxt_wunpckilh" +@@ -1123,7 +1120,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckilh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckil")] ++ (set_attr "type" "wmmx_wunpckil")] + ) -@@ -513,21 +542,10 @@ - && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); - }) + (define_insn "iwmmxt_wunpckilw" +@@ -1139,7 +1136,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckilw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckil")] ++ (set_attr "type" "wmmx_wunpckil")] + ) --(define_predicate "imm_for_neon_inv_logic_operand" -- (match_code "const_vector") --{ -- return (TARGET_NEON -- && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); --}) -- - (define_predicate "neon_logic_op2" - (ior (match_operand 0 "imm_for_neon_logic_operand") - (match_operand 0 "s_register_operand"))) + (define_insn "iwmmxt_wunpckehub" +@@ -1151,7 +1148,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckehub%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckeh")] ++ (set_attr "type" "wmmx_wunpckeh")] + ) --(define_predicate "neon_inv_logic_op2" -- (ior (match_operand 0 "imm_for_neon_inv_logic_operand") -- (match_operand 0 "s_register_operand"))) -- - ;; Predicates for named expanders that overlap multiple ISAs. + (define_insn "iwmmxt_wunpckehuh" +@@ -1162,7 +1159,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckehuh%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckeh")] ++ (set_attr "type" "wmmx_wunpckeh")] + ) - (define_predicate "cmpdi_operand" ---- a/src/gcc/config/arm/arm_neon.h -+++ b/src/gcc/config/arm/arm_neon.h -@@ -43,6 +43,7 @@ - typedef __builtin_neon_si int32x2_t __attribute__ ((__vector_size__ (8))); - typedef __builtin_neon_di int64x1_t; - typedef __builtin_neon_sf float32x2_t __attribute__ ((__vector_size__ (8))); -+typedef __builtin_neon_hf float16x4_t __attribute__ ((__vector_size__ (8))); - typedef __builtin_neon_poly8 poly8x8_t __attribute__ ((__vector_size__ (8))); - typedef __builtin_neon_poly16 poly16x4_t __attribute__ ((__vector_size__ (8))); - typedef __builtin_neon_uqi uint8x8_t __attribute__ ((__vector_size__ (8))); -@@ -6016,6 +6017,22 @@ - return (uint32x4_t)__builtin_neon_vcvtv4sf (__a, 0); - } + (define_insn "iwmmxt_wunpckehuw" +@@ -1173,7 +1170,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckehuw%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckeh")] ++ (set_attr "type" "wmmx_wunpckeh")] + ) -+#if ((__ARM_FP & 0x2) != 0) -+__extension__ static __inline float16x4_t __attribute__ ((__always_inline__)) -+vcvt_f16_f32 (float32x4_t __a) -+{ -+ return (float16x4_t)__builtin_neon_vcvtv4hfv4sf (__a); -+} -+ -+#endif -+#if ((__ARM_FP & 0x2) != 0) -+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -+vcvt_f32_f16 (float16x4_t __a) -+{ -+ return (float32x4_t)__builtin_neon_vcvtv4sfv4hf (__a); -+} -+ -+#endif - __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) - vcvt_n_s32_f32 (float32x2_t __a, const int __b) - { ---- a/src/gcc/config/arm/arm-ldmstm.ml -+++ b/src/gcc/config/arm/arm-ldmstm.ml -@@ -146,12 +146,15 @@ - | IA, true, true -> true - | _ -> false + (define_insn "iwmmxt_wunpckehsb" +@@ -1185,7 +1182,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckehsb%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckeh")] ++ (set_attr "type" "wmmx_wunpckeh")] + ) -+exception InvalidAddrMode of string;; -+ - let target addrmode thumb = - match addrmode, thumb with - IA, true -> "TARGET_THUMB1" - | IA, false -> "TARGET_32BIT" - | DB, false -> "TARGET_32BIT" - | _, false -> "TARGET_ARM" -+ | _, _ -> raise (InvalidAddrMode "ERROR: Invalid Addressing mode for Thumb1.") + (define_insn "iwmmxt_wunpckehsh" +@@ -1196,7 +1193,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckehsh%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckeh")] ++ (set_attr "type" "wmmx_wunpckeh")] + ) - let write_pattern_1 name ls addrmode nregs write_set_fn update thumb = - let astr = string_of_addrmode addrmode in -@@ -181,8 +184,10 @@ - done; - Printf.printf "}\"\n"; - Printf.printf " [(set_attr \"type\" \"%s%d\")" ls nregs; -- begin if not thumb then -+ if not thumb then begin - Printf.printf "\n (set_attr \"predicable\" \"yes\")"; -+ if addrmode == IA || addrmode == DB then -+ Printf.printf "\n (set_attr \"predicable_short_it\" \"no\")"; - end; - Printf.printf "])\n\n" + (define_insn "iwmmxt_wunpckehsw" +@@ -1207,7 +1204,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckehsw%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckeh")] ++ (set_attr "type" "wmmx_wunpckeh")] + ) + + (define_insn "iwmmxt_wunpckelub" +@@ -1219,7 +1216,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckelub%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckel")] ++ (set_attr "type" "wmmx_wunpckel")] + ) + + (define_insn "iwmmxt_wunpckeluh" +@@ -1230,7 +1227,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckeluh%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckel")] ++ (set_attr "type" "wmmx_wunpckel")] + ) + + (define_insn "iwmmxt_wunpckeluw" +@@ -1241,7 +1238,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckeluw%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckel")] ++ (set_attr "type" "wmmx_wunpckel")] + ) + + (define_insn "iwmmxt_wunpckelsb" +@@ -1253,7 +1250,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckelsb%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckel")] ++ (set_attr "type" "wmmx_wunpckel")] + ) + + (define_insn "iwmmxt_wunpckelsh" +@@ -1264,7 +1261,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckelsh%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckel")] ++ (set_attr "type" "wmmx_wunpckel")] + ) + + (define_insn "iwmmxt_wunpckelsw" +@@ -1275,7 +1272,7 @@ + "TARGET_REALLY_IWMMXT" + "wunpckelsw%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wunpckel")] ++ (set_attr "type" "wmmx_wunpckel")] + ) + + ;; Shifts +@@ -1298,7 +1295,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "arch" "*, iwmmxt2") +- (set_attr "wtype" "wror, wror")] ++ (set_attr "type" "wmmx_wror, wmmx_wror")] + ) + + (define_insn "ashr3_iwmmxt" +@@ -1319,7 +1316,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "arch" "*, iwmmxt2") +- (set_attr "wtype" "wsra, wsra")] ++ (set_attr "type" "wmmx_wsra, wmmx_wsra")] + ) + + (define_insn "lshr3_iwmmxt" +@@ -1340,7 +1337,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "arch" "*, iwmmxt2") +- (set_attr "wtype" "wsrl, wsrl")] ++ (set_attr "type" "wmmx_wsrl, wmmx_wsrl")] + ) + + (define_insn "ashl3_iwmmxt" +@@ -1361,7 +1358,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "arch" "*, iwmmxt2") +- (set_attr "wtype" "wsll, wsll")] ++ (set_attr "type" "wmmx_wsll, wmmx_wsll")] + ) + + (define_insn "ror3_di" +@@ -1382,7 +1379,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "arch" "*, iwmmxt2") +- (set_attr "wtype" "wror, wror")] ++ (set_attr "type" "wmmx_wror, wmmx_wror")] + ) + + (define_insn "ashr3_di" +@@ -1403,7 +1400,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "arch" "*, iwmmxt2") +- (set_attr "wtype" "wsra, wsra")] ++ (set_attr "type" "wmmx_wsra, wmmx_wsra")] + ) + + (define_insn "lshr3_di" +@@ -1424,7 +1421,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "arch" "*, iwmmxt2") +- (set_attr "wtype" "wsrl, wsrl")] ++ (set_attr "type" "wmmx_wsrl, wmmx_wsrl")] + ) + + (define_insn "ashl3_di" +@@ -1445,7 +1442,7 @@ + " + [(set_attr "predicable" "yes") + (set_attr "arch" "*, iwmmxt2") +- (set_attr "wtype" "wsll, wsll")] ++ (set_attr "type" "wmmx_wsll, wmmx_wsll")] + ) + + (define_insn "iwmmxt_wmadds" +@@ -1464,7 +1461,7 @@ + "TARGET_REALLY_IWMMXT" + "wmadds%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmadd")] ++ (set_attr "type" "wmmx_wmadd")] + ) + + (define_insn "iwmmxt_wmaddu" +@@ -1483,7 +1480,7 @@ + "TARGET_REALLY_IWMMXT" + "wmaddu%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmadd")] ++ (set_attr "type" "wmmx_wmadd")] + ) + + (define_insn "iwmmxt_tmia" +@@ -1496,7 +1493,7 @@ + "TARGET_REALLY_IWMMXT" + "tmia%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmia")] ++ (set_attr "type" "wmmx_tmia")] + ) + + (define_insn "iwmmxt_tmiaph" +@@ -1514,7 +1511,7 @@ + "TARGET_REALLY_IWMMXT" + "tmiaph%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmiaph")] ++ (set_attr "type" "wmmx_tmiaph")] + ) + + (define_insn "iwmmxt_tmiabb" +@@ -1527,7 +1524,7 @@ + "TARGET_REALLY_IWMMXT" + "tmiabb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmiaxy")] ++ (set_attr "type" "wmmx_tmiaxy")] + ) + + (define_insn "iwmmxt_tmiatb" +@@ -1544,7 +1541,7 @@ + "TARGET_REALLY_IWMMXT" + "tmiatb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmiaxy")] ++ (set_attr "type" "wmmx_tmiaxy")] + ) + + (define_insn "iwmmxt_tmiabt" +@@ -1561,7 +1558,7 @@ + "TARGET_REALLY_IWMMXT" + "tmiabt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmiaxy")] ++ (set_attr "type" "wmmx_tmiaxy")] + ) + + (define_insn "iwmmxt_tmiatt" +@@ -1580,7 +1577,7 @@ + "TARGET_REALLY_IWMMXT" + "tmiatt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmiaxy")] ++ (set_attr "type" "wmmx_tmiaxy")] + ) + + (define_insn "iwmmxt_tmovmskb" +@@ -1589,7 +1586,7 @@ + "TARGET_REALLY_IWMMXT" + "tmovmskb%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmovmsk")] ++ (set_attr "type" "wmmx_tmovmsk")] + ) + + (define_insn "iwmmxt_tmovmskh" +@@ -1598,7 +1595,7 @@ + "TARGET_REALLY_IWMMXT" + "tmovmskh%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmovmsk")] ++ (set_attr "type" "wmmx_tmovmsk")] + ) + + (define_insn "iwmmxt_tmovmskw" +@@ -1607,7 +1604,7 @@ + "TARGET_REALLY_IWMMXT" + "tmovmskw%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tmovmsk")] ++ (set_attr "type" "wmmx_tmovmsk")] + ) + + (define_insn "iwmmxt_waccb" +@@ -1616,7 +1613,7 @@ + "TARGET_REALLY_IWMMXT" + "waccb%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wacc")] ++ (set_attr "type" "wmmx_wacc")] + ) + + (define_insn "iwmmxt_wacch" +@@ -1625,7 +1622,7 @@ + "TARGET_REALLY_IWMMXT" + "wacch%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wacc")] ++ (set_attr "type" "wmmx_wacc")] + ) + + (define_insn "iwmmxt_waccw" +@@ -1634,7 +1631,7 @@ + "TARGET_REALLY_IWMMXT" + "waccw%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wacc")] ++ (set_attr "type" "wmmx_wacc")] + ) + + ;; use unspec here to prevent 8 * imm to be optimized by cse +@@ -1651,7 +1648,7 @@ + "TARGET_REALLY_IWMMXT" + "waligni%?\\t%0, %1, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "waligni")] ++ (set_attr "type" "wmmx_waligni")] + ) + + (define_insn "iwmmxt_walignr" +@@ -1666,7 +1663,7 @@ + "TARGET_REALLY_IWMMXT" + "walignr%U3%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "walignr")] ++ (set_attr "type" "wmmx_walignr")] + ) + + (define_insn "iwmmxt_walignr0" +@@ -1681,7 +1678,7 @@ + "TARGET_REALLY_IWMMXT" + "walignr0%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "walignr")] ++ (set_attr "type" "wmmx_walignr")] + ) + + (define_insn "iwmmxt_walignr1" +@@ -1696,7 +1693,7 @@ + "TARGET_REALLY_IWMMXT" + "walignr1%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "walignr")] ++ (set_attr "type" "wmmx_walignr")] + ) + + (define_insn "iwmmxt_walignr2" +@@ -1711,7 +1708,7 @@ + "TARGET_REALLY_IWMMXT" + "walignr2%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "walignr")] ++ (set_attr "type" "wmmx_walignr")] + ) + + (define_insn "iwmmxt_walignr3" +@@ -1726,7 +1723,7 @@ + "TARGET_REALLY_IWMMXT" + "walignr3%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "walignr")] ++ (set_attr "type" "wmmx_walignr")] + ) + + (define_insn "iwmmxt_wsadb" +@@ -1738,7 +1735,7 @@ + "TARGET_REALLY_IWMMXT" + "wsadb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsad")] ++ (set_attr "type" "wmmx_wsad")] + ) + + (define_insn "iwmmxt_wsadh" +@@ -1750,7 +1747,7 @@ + "TARGET_REALLY_IWMMXT" + "wsadh%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsad")] ++ (set_attr "type" "wmmx_wsad")] + ) + + (define_insn "iwmmxt_wsadbz" +@@ -1760,7 +1757,7 @@ + "TARGET_REALLY_IWMMXT" + "wsadbz%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsad")] ++ (set_attr "type" "wmmx_wsad")] + ) + + (define_insn "iwmmxt_wsadhz" +@@ -1770,7 +1767,7 @@ + "TARGET_REALLY_IWMMXT" + "wsadhz%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsad")] ++ (set_attr "type" "wmmx_wsad")] + ) + (include "iwmmxt2.md") --- a/src/gcc/config/arm/cortex-a53.md +++ b/src/gcc/config/arm/cortex-a53.md -@@ -0,0 +1,296 @@ +@@ -0,0 +1,300 @@ +;; ARM Cortex-A53 pipeline description +;; Copyright (C) 2013 Free Software Foundation, Inc. +;; @@ -21098,12 +32464,15 @@ + +(define_insn_reservation "cortex_a53_alu" 2 + (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "alu_reg,simple_alu_imm")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg")) + "cortex_a53_slot_any") + +(define_insn_reservation "cortex_a53_alu_shift" 2 + (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "alu_shift,alu_shift_reg")) ++ (eq_attr "type" "arlo_shift,arlo_shift_reg,\ ++ mov_shift,mov_shift_reg,\ ++ mvn_shift,mvn_shift_reg")) + "cortex_a53_slot_any") + +;; Forwarding path for unshifted operands. @@ -21120,7 +32489,8 @@ + +(define_insn_reservation "cortex_a53_mul" 3 + (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "mult")) ++ (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes"))) + "cortex_a53_single_issue") + +;; A multiply with a single-register result or an MLA, followed by an @@ -21134,12 +32504,12 @@ +;; Punt with a high enough latency for divides. +(define_insn_reservation "cortex_a53_udiv" 8 + (and (eq_attr "tune" "cortexa53") -+ (eq_attr "insn" "udiv")) ++ (eq_attr "type" "udiv")) + "(cortex_a53_slot0+cortex_a53_idiv),cortex_a53_idiv*7") + +(define_insn_reservation "cortex_a53_sdiv" 9 + (and (eq_attr "tune" "cortexa53") -+ (eq_attr "insn" "sdiv")) ++ (eq_attr "type" "sdiv")) + "(cortex_a53_slot0+cortex_a53_idiv),cortex_a53_idiv*8") + + @@ -21242,1906 +32612,5690 @@ + (eq_attr "type" "fmuls,fmuld")) + "cortex_a53_slot0") + -+;; For single-precision multiply-accumulate, the add (accumulate) is issued after -+;; the multiply completes. Model that accordingly. ++;; For single-precision multiply-accumulate, the add (accumulate) is issued after ++;; the multiply completes. Model that accordingly. ++ ++(define_insn_reservation "cortex_a53_fpmac" 8 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "fmacs,fmacd,ffmas,ffmad")) ++ "cortex_a53_slot0, nothing*3, cortex_a53_fpadd_pipe") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Floating-point divide/square root instructions. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; fsqrt really takes one cycle less, but that is not modelled. ++ ++(define_insn_reservation "cortex_a53_fdivs" 14 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "fdivs")) ++ "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 13") ++ ++(define_insn_reservation "cortex_a53_fdivd" 29 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "fdivd")) ++ "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 28") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP to/from core transfers. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a53_r2f" 4 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "r_2_f")) ++ "cortex_a53_slot0") ++ ++(define_insn_reservation "cortex_a53_f2r" 2 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "f_2_r")) ++ "cortex_a53_slot0") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP flag transfer. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a53_f_flags" 4 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "f_flag")) ++ "cortex_a53_slot0") ++ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; VFP load/store. ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_insn_reservation "cortex_a53_f_loads" 4 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "f_loads")) ++ "cortex_a53_slot0") ++ ++(define_insn_reservation "cortex_a53_f_loadd" 5 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "f_loadd")) ++ "cortex_a53_slot0") ++ ++(define_insn_reservation "cortex_a53_f_stores" 0 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "f_stores")) ++ "cortex_a53_slot0") ++ ++(define_insn_reservation "cortex_a53_f_stored" 0 ++ (and (eq_attr "tune" "cortexa53") ++ (eq_attr "type" "f_stored")) ++ "cortex_a53_slot0") ++ ++;; Load-to-use for floating-point values has a penalty of one cycle, ++;; i.e. a latency of two. ++ ++(define_bypass 2 "cortex_a53_f_loads" ++ "cortex_a53_fpalu, cortex_a53_fpmac, cortex_a53_fpmul,\ ++ cortex_a53_fdivs, cortex_a53_fdivd,\ ++ cortex_a53_f2r") ++ ++(define_bypass 2 "cortex_a53_f_loadd" ++ "cortex_a53_fpalu, cortex_a53_fpmac, cortex_a53_fpmul,\ ++ cortex_a53_fdivs, cortex_a53_fdivd,\ ++ cortex_a53_f2r") ++ +--- a/src/gcc/config/arm/bpabi.h ++++ b/src/gcc/config/arm/bpabi.h +@@ -60,6 +60,7 @@ + |mcpu=cortex-a7 \ + |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ + |mcpu=marvell-pj4 \ ++ |mcpu=cortex-a53 \ + |mcpu=generic-armv7-a \ + |march=armv7-m|mcpu=cortex-m3 \ + |march=armv7e-m|mcpu=cortex-m4 \ +@@ -71,6 +72,7 @@ + " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5 \ + |mcpu=cortex-a7 \ + |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ ++ |mcpu=cortex-a53 \ + |mcpu=marvell-pj4 \ + |mcpu=generic-armv7-a \ + |march=armv7-m|mcpu=cortex-m3 \ +--- a/src/gcc/config/arm/marvell-f-iwmmxt.md ++++ b/src/gcc/config/arm/marvell-f-iwmmxt.md +@@ -63,52 +63,62 @@ + ;; An attribute appended to instructions for classification + + (define_attr "wmmxt_shift" "yes,no" +- (if_then_else (eq_attr "wtype" "wror, wsll, wsra, wsrl") ++ (if_then_else (eq_attr "type" "wmmx_wror, wmmx_wsll, wmmx_wsra, wmmx_wsrl") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_pack" "yes,no" +- (if_then_else (eq_attr "wtype" "waligni, walignr, wmerge, wpack, wshufh, wunpckeh, wunpckih, wunpckel, wunpckil") ++ (if_then_else (eq_attr "type" "wmmx_waligni, wmmx_walignr, wmmx_wmerge,\ ++ wmmx_wpack, wmmx_wshufh, wmmx_wunpckeh,\ ++ wmmx_wunpckih, wmmx_wunpckel, wmmx_wunpckil") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_mult_c1" "yes,no" +- (if_then_else (eq_attr "wtype" "wmac, wmadd, wmiaxy, wmiawxy, wmulw, wqmiaxy, wqmulwm") ++ (if_then_else (eq_attr "type" "wmmx_wmac, wmmx_wmadd, wmmx_wmiaxy,\ ++ wmmx_wmiawxy, wmmx_wmulw, wmmx_wqmiaxy,\ ++ wmmx_wqmulwm") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_mult_c2" "yes,no" +- (if_then_else (eq_attr "wtype" "wmul, wqmulm") ++ (if_then_else (eq_attr "type" "wmmx_wmul, wmmx_wqmulm") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_alu_c1" "yes,no" +- (if_then_else (eq_attr "wtype" "wabs, wabsdiff, wand, wandn, wmov, wor, wxor") ++ (if_then_else (eq_attr "type" "wmmx_wabs, wmmx_wabsdiff, wmmx_wand,\ ++ wmmx_wandn, wmmx_wmov, wmmx_wor, wmmx_wxor") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_alu_c2" "yes,no" +- (if_then_else (eq_attr "wtype" "wacc, wadd, waddsubhx, wavg2, wavg4, wcmpeq, wcmpgt, wmax, wmin, wsub, waddbhus, wsubaddhx") ++ (if_then_else (eq_attr "type" "wmmx_wacc, wmmx_wadd, wmmx_waddsubhx,\ ++ wmmx_wavg2, wmmx_wavg4, wmmx_wcmpeq,\ ++ wmmx_wcmpgt, wmmx_wmax, wmmx_wmin,\ ++ wmmx_wsub, wmmx_waddbhus, wmmx_wsubaddhx") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_alu_c3" "yes,no" +- (if_then_else (eq_attr "wtype" "wsad") ++ (if_then_else (eq_attr "type" "wmmx_wsad") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_transfer_c1" "yes,no" +- (if_then_else (eq_attr "wtype" "tbcst, tinsr, tmcr, tmcrr") ++ (if_then_else (eq_attr "type" "wmmx_tbcst, wmmx_tinsr,\ ++ wmmx_tmcr, wmmx_tmcrr") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_transfer_c2" "yes,no" +- (if_then_else (eq_attr "wtype" "textrm, tmovmsk, tmrc, tmrrc") ++ (if_then_else (eq_attr "type" "wmmx_textrm, wmmx_tmovmsk,\ ++ wmmx_tmrc, wmmx_tmrrc") + (const_string "yes") (const_string "no")) + ) + + (define_attr "wmmxt_transfer_c3" "yes,no" +- (if_then_else (eq_attr "wtype" "tmia, tmiaph, tmiaxy") ++ (if_then_else (eq_attr "type" "wmmx_tmia, wmmx_tmiaph, wmmx_tmiaxy") + (const_string "yes") (const_string "no")) + ) + +@@ -169,11 +179,11 @@ + + (define_insn_reservation "marvell_f_iwmmxt_wstr" 0 + (and (eq_attr "marvell_f_iwmmxt" "yes") +- (eq_attr "wtype" "wstr")) ++ (eq_attr "type" "wmmx_wstr")) + "mf_iwmmxt_pipeline") + + ;There is a forwarding path from MW stage + (define_insn_reservation "marvell_f_iwmmxt_wldr" 5 + (and (eq_attr "marvell_f_iwmmxt" "yes") +- (eq_attr "wtype" "wldr")) ++ (eq_attr "type" "wmmx_wldr")) + "mf_iwmmxt_pipeline") +--- a/src/gcc/config/arm/iterators.md ++++ b/src/gcc/config/arm/iterators.md +@@ -496,3 +496,11 @@ + (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") + (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") + (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) ++;; Both kinds of return insn. ++(define_code_iterator returns [return simple_return]) ++(define_code_attr return_str [(return "") (simple_return "simple_")]) ++(define_code_attr return_simple_p [(return "false") (simple_return "true")]) ++(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") ++ (simple_return " && use_simple_return_p ()")]) ++(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") ++ (simple_return " && use_simple_return_p ()")]) +--- a/src/gcc/config/arm/sync.md ++++ b/src/gcc/config/arm/sync.md +@@ -65,6 +65,42 @@ + (set_attr "conds" "unconditional") + (set_attr "predicable" "no")]) + ++(define_insn "atomic_load" ++ [(set (match_operand:QHSI 0 "register_operand" "=r") ++ (unspec_volatile:QHSI ++ [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q") ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ VUNSPEC_LDA))] ++ "TARGET_HAVE_LDACQ" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[2]); ++ if (model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_RELEASE) ++ return \"ldr\\t%0, %1\"; ++ else ++ return \"lda\\t%0, %1\"; ++ } ++) ++ ++(define_insn "atomic_store" ++ [(set (match_operand:QHSI 0 "memory_operand" "=Q") ++ (unspec_volatile:QHSI ++ [(match_operand:QHSI 1 "general_operand" "r") ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ VUNSPEC_STL))] ++ "TARGET_HAVE_LDACQ" ++ { ++ enum memmodel model = (enum memmodel) INTVAL (operands[2]); ++ if (model == MEMMODEL_RELAXED ++ || model == MEMMODEL_CONSUME ++ || model == MEMMODEL_ACQUIRE) ++ return \"str\t%1, %0\"; ++ else ++ return \"stl\t%1, %0\"; ++ } ++) ++ + ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, + ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied + ;; with a store. +@@ -88,7 +124,8 @@ + UNSPEC_LL))] + "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN" + "ldrexd%?\t%0, %H0, %C1" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_expand "atomic_compare_and_swap" + [(match_operand:SI 0 "s_register_operand" "") ;; bool out +@@ -325,8 +362,20 @@ + VUNSPEC_LL)))] + "TARGET_HAVE_LDREXBH" + "ldrex%?\t%0, %C1" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + ++(define_insn "arm_load_acquire_exclusive" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (zero_extend:SI ++ (unspec_volatile:NARROW ++ [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")] ++ VUNSPEC_LAX)))] ++ "TARGET_HAVE_LDACQ" ++ "ldaex%?\\t%0, %C1" ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) ++ + (define_insn "arm_load_exclusivesi" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (unspec_volatile:SI +@@ -334,8 +383,19 @@ + VUNSPEC_LL))] + "TARGET_HAVE_LDREX" + "ldrex%?\t%0, %C1" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + ++(define_insn "arm_load_acquire_exclusivesi" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "mem_noofs_operand" "Ua")] ++ VUNSPEC_LAX))] ++ "TARGET_HAVE_LDACQ" ++ "ldaex%?\t%0, %C1" ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) ++ + (define_insn "arm_load_exclusivedi" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (unspec_volatile:DI +@@ -343,8 +403,19 @@ + VUNSPEC_LL))] + "TARGET_HAVE_LDREXD" + "ldrexd%?\t%0, %H0, %C1" +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + ++(define_insn "arm_load_acquire_exclusivedi" ++ [(set (match_operand:DI 0 "s_register_operand" "=r") ++ (unspec_volatile:DI ++ [(match_operand:DI 1 "mem_noofs_operand" "Ua")] ++ VUNSPEC_LAX))] ++ "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" ++ "ldaexd%?\t%0, %H0, %C1" ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) ++ + (define_insn "arm_store_exclusive" + [(set (match_operand:SI 0 "s_register_operand" "=&r") + (unspec_volatile:SI [(const_int 0)] VUNSPEC_SC)) +@@ -367,4 +438,35 @@ + } + return "strex%?\t%0, %2, %C1"; + } +- [(set_attr "predicable" "yes")]) ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) ++ ++(define_insn "arm_store_release_exclusivedi" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX)) ++ (set (match_operand:DI 1 "mem_noofs_operand" "=Ua") ++ (unspec_volatile:DI ++ [(match_operand:DI 2 "s_register_operand" "r")] ++ VUNSPEC_SLX))] ++ "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" ++ { ++ rtx value = operands[2]; ++ /* See comment in arm_store_exclusive above. */ ++ gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2); ++ operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); ++ return "stlexd%?\t%0, %2, %3, %C1"; ++ } ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) ++ ++(define_insn "arm_store_release_exclusive" ++ [(set (match_operand:SI 0 "s_register_operand" "=&r") ++ (unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX)) ++ (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua") ++ (unspec_volatile:QHSI ++ [(match_operand:QHSI 2 "s_register_operand" "r")] ++ VUNSPEC_SLX))] ++ "TARGET_HAVE_LDACQ" ++ "stlex%?\t%0, %2, %C1" ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) +--- a/src/gcc/config/arm/neon-testgen.ml ++++ b/src/gcc/config/arm/neon-testgen.ml +@@ -163,10 +163,12 @@ + match List.find (fun feature -> + match feature with Requires_feature _ -> true + | Requires_arch _ -> true ++ | Requires_FP_bit 1 -> true + | _ -> false) + features with + Requires_feature "FMA" -> "arm_neonv2" + | Requires_arch 8 -> "arm_v8_neon" ++ | Requires_FP_bit 1 -> "arm_neon_fp16" + | _ -> assert false + with Not_found -> "arm_neon" + +--- a/src/gcc/config/arm/fa726te.md ++++ b/src/gcc/config/arm/fa726te.md +@@ -78,15 +78,15 @@ + ;; Move instructions. + (define_insn_reservation "726te_shift_op" 1 + (and (eq_attr "tune" "fa726te") +- (eq_attr "insn" "mov,mvn")) ++ (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\ ++ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) + "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") + + ;; ALU operations with no shifted operand will finished in 1 cycle + ;; Other ALU instructions 2 cycles. + (define_insn_reservation "726te_alu_op" 1 + (and (eq_attr "tune" "fa726te") +- (and (eq_attr "type" "alu_reg,simple_alu_imm") +- (not (eq_attr "insn" "mov,mvn")))) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")) + "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") + + ;; ALU operations with a shift-by-register operand. +@@ -95,14 +95,12 @@ + ;; it takes 3 cycles. + (define_insn_reservation "726te_alu_shift_op" 3 + (and (eq_attr "tune" "fa726te") +- (and (eq_attr "type" "simple_alu_shift,alu_shift") +- (not (eq_attr "insn" "mov,mvn")))) ++ (eq_attr "type" "extend,arlo_shift")) + "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") + + (define_insn_reservation "726te_alu_shift_reg_op" 3 + (and (eq_attr "tune" "fa726te") +- (and (eq_attr "type" "alu_shift_reg") +- (not (eq_attr "insn" "mov,mvn")))) ++ (eq_attr "type" "arlo_shift_reg")) + "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ;; Multiplication Instructions +@@ -115,7 +113,7 @@ + + (define_insn_reservation "726te_mult_op" 3 + (and (eq_attr "tune" "fa726te") +- (eq_attr "insn" "smlalxy,mul,mla,muls,mlas,umull,umlal,smull,smlal,\ ++ (eq_attr "type" "smlalxy,mul,mla,muls,mlas,umull,umlal,smull,smlal,\ + umulls,umlals,smulls,smlals,smlawx,smulxy,smlaxy")) + "fa726te_issue+fa726te_mac_pipe") + +--- a/src/gcc/config/arm/arm.md ++++ b/src/gcc/config/arm/arm.md +@@ -74,6 +74,15 @@ + ; IS_THUMB1 is set to 'yes' iff we are generating Thumb-1 code. + (define_attr "is_thumb1" "no,yes" (const (symbol_ref "thumb1_code"))) + ++; We use this attribute to disable alternatives that can produce 32-bit ++; instructions inside an IT-block in Thumb2 state. ARMv8 deprecates IT blocks ++; that contain 32-bit instructions. ++(define_attr "enabled_for_depr_it" "no,yes" (const_string "yes")) ++ ++; This attribute is used to disable a predicated alternative when we have ++; arm_restrict_it. ++(define_attr "predicable_short_it" "no,yes" (const_string "yes")) + -+(define_insn_reservation "cortex_a53_fpmac" 8 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "fmacs,fmacd,ffmas,ffmad")) -+ "cortex_a53_slot0, nothing*3, cortex_a53_fpadd_pipe") + ;; Operand number of an input operand that is shifted. Zero if the + ;; given instruction does not shift one of its input operands. + (define_attr "shift" "" (const_int 0)) +@@ -84,6 +93,8 @@ + (define_attr "fpu" "none,vfp" + (const (symbol_ref "arm_fpu_attr"))) + ++(define_attr "predicated" "yes,no" (const_string "no")) + -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; Floating-point divide/square root instructions. -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; fsqrt really takes one cycle less, but that is not modelled. + ; LENGTH of an instruction (in bytes) + (define_attr "length" "" + (const_int 4)) +@@ -94,7 +105,7 @@ + ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without + ; arm_arch6. This attribute is used to compute attribute "enabled", + ; use type "any" to enable an alternative in all cases. +-(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8,iwmmxt,iwmmxt2" ++(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2" + (const_string "any")) + + (define_attr "arch_enabled" "no,yes" +@@ -129,24 +140,16 @@ + (match_test "TARGET_32BIT && !arm_arch6")) + (const_string "yes") + +- (and (eq_attr "arch" "onlya8") +- (eq_attr "tune" "cortexa8")) ++ (and (eq_attr "arch" "avoid_neon_for_64bits") ++ (match_test "TARGET_NEON") ++ (not (match_test "TARGET_PREFER_NEON_64BITS"))) + (const_string "yes") + +- (and (eq_attr "arch" "neon_onlya8") +- (eq_attr "tune" "cortexa8") +- (match_test "TARGET_NEON")) ++ (and (eq_attr "arch" "neon_for_64bits") ++ (match_test "TARGET_NEON") ++ (match_test "TARGET_PREFER_NEON_64BITS")) + (const_string "yes") + +- (and (eq_attr "arch" "nota8") +- (not (eq_attr "tune" "cortexa8"))) +- (const_string "yes") +- +- (and (eq_attr "arch" "neon_nota8") +- (not (eq_attr "tune" "cortexa8")) +- (match_test "TARGET_NEON")) +- (const_string "yes") +- + (and (eq_attr "arch" "iwmmxt2") + (match_test "TARGET_REALLY_IWMMXT2")) + (const_string "yes")] +@@ -179,6 +182,15 @@ + (cond [(eq_attr "insn_enabled" "no") + (const_string "no") + ++ (and (eq_attr "predicable_short_it" "no") ++ (and (eq_attr "predicated" "yes") ++ (match_test "arm_restrict_it"))) ++ (const_string "no") + -+(define_insn_reservation "cortex_a53_fdivs" 14 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "fdivs")) -+ "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 13") ++ (and (eq_attr "enabled_for_depr_it" "no") ++ (match_test "arm_restrict_it")) ++ (const_string "no") + -+(define_insn_reservation "cortex_a53_fdivd" 29 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "fdivd")) -+ "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 28") + (eq_attr "arch_enabled" "no") + (const_string "no") + +@@ -214,126 +226,340 @@ + (set_attr "length" "4") + (set_attr "pool_range" "250")]) + +-;; The instruction used to implement a particular pattern. This +-;; information is used by pipeline descriptions to provide accurate +-;; scheduling information. +- +-(define_attr "insn" +- "mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,sat,other" +- (const_string "other")) +- +-; TYPE attribute is used to detect floating point instructions which, if +-; running on a co-processor can run in parallel with other, basic instructions +-; If write-buffer scheduling is enabled then it can also be used in the +-; scheduling of writes. +- +-; Classification of each insn +-; Note: vfp.md has different meanings for some of these, and some further +-; types as well. See that file for details. +-; simple_alu_imm a simple alu instruction that doesn't hit memory or fp +-; regs or have a shifted source operand and has an immediate +-; operand. This currently only tracks very basic immediate +-; alu operations. +-; alu_reg any alu instruction that doesn't hit memory or fp +-; regs or have a shifted source operand +-; and does not have an immediate operand. This is +-; also the default +-; simple_alu_shift covers UXTH, UXTB, SXTH, SXTB +-; alu_shift any data instruction that doesn't hit memory or fp +-; regs, but has a source operand shifted by a constant +-; alu_shift_reg any data instruction that doesn't hit memory or fp +-; regs, but has a source operand shifted by a register value +-; mult a multiply instruction +-; block blockage insn, this blocks all functional units +-; float a floating point arithmetic operation (subject to expansion) +-; fdivd DFmode floating point division +-; fdivs SFmode floating point division +-; f_load[sd] A single/double load from memory. Used for VFP unit. +-; f_store[sd] A single/double store to memory. Used for VFP unit. +-; f_flag a transfer of co-processor flags to the CPSR +-; f_2_r transfer float to core (no memory needed) +-; r_2_f transfer core to float +-; f_cvt convert floating<->integral +-; branch a branch +-; call a subroutine call +-; load_byte load byte(s) from memory to arm registers +-; load1 load 1 word from memory to arm registers +-; load2 load 2 words from memory to arm registers +-; load3 load 3 words from memory to arm registers +-; load4 load 4 words from memory to arm registers +-; store store 1 word to memory from arm registers +-; store2 store 2 words +-; store3 store 3 words +-; store4 store 4 (or more) words ++; TYPE attribute is used to classify instructions for use in scheduling. + ; ++; Instruction classification: ++; ++; arlo_imm any arithmetic or logical instruction that doesn't have ++; a shifted operand and has an immediate operand. This ++; excludes MOV, MVN and RSB(S) immediate. ++; arlo_reg any arithmetic or logical instruction that doesn't have ++; a shifted or an immediate operand. This excludes ++; MOV and MVN but includes MOVT. This is also the default. ++; arlo_shift any arithmetic or logical instruction that has a source ++; operand shifted by a constant. This excludes ++; simple shifts. ++; arlo_shift_reg as arlo_shift, with the shift amount specified in a ++; register. ++; block blockage insn, this blocks all functional units. ++; branch branch. ++; call subroutine call. ++; clz count leading zeros (CLZ). ++; extend extend instruction (SXTB, SXTH, UXTB, UXTH). ++; f_2_r transfer from float to core (no memory needed). ++; f_cvt conversion between float and integral. ++; f_flag transfer of co-processor flags to the CPSR. ++; f_load[d,s] double/single load from memory. Used for VFP unit. ++; f_minmax[d,s] double/single floating point minimum/maximum. ++; f_rint[d,s] double/single floating point rount to integral. ++; f_sel[d,s] double/single floating byte select. ++; f_store[d,s] double/single store to memory. Used for VFP unit. ++; fadd[d,s] double/single floating-point scalar addition. ++; fcmp[d,s] double/single floating-point compare. ++; fconst[d,s] double/single load immediate. ++; fcpys single precision floating point cpy. ++; fdiv[d,s] double/single precision floating point division. ++; ffarith[d,s] double/single floating point abs/neg/cpy. ++; ffma[d,s] double/single floating point fused multiply-accumulate. ++; float floating point arithmetic operation. ++; fmac[d,s] double/single floating point multiply-accumulate. ++; fmul[d,s] double/single floating point multiply. ++; load_byte load byte(s) from memory to arm registers. ++; load1 load 1 word from memory to arm registers. ++; load2 load 2 words from memory to arm registers. ++; load3 load 3 words from memory to arm registers. ++; load4 load 4 words from memory to arm registers. ++; mla integer multiply accumulate. ++; mlas integer multiply accumulate, flag setting. ++; mov_imm simple MOV instruction that moves an immediate to ++; register. This includes MOVW, but not MOVT. ++; mov_reg simple MOV instruction that moves a register to another ++; register. This includes MOVW, but not MOVT. ++; mov_shift simple MOV instruction, shifted operand by a constant. ++; mov_shift_reg simple MOV instruction, shifted operand by a register. ++; mul integer multiply. ++; muls integer multiply, flag setting. ++; mvn_imm inverting move instruction, immediate. ++; mvn_reg inverting move instruction, register. ++; mvn_shift inverting move instruction, shifted operand by a constant. ++; mvn_shift_reg inverting move instruction, shifted operand by a register. ++; r_2_f transfer from core to float. ++; sdiv signed division. ++; shift simple shift operation (LSL, LSR, ASR, ROR) with an ++; immediate. ++; shift_reg simple shift by a register. ++; smlad signed multiply accumulate dual. ++; smladx signed multiply accumulate dual reverse. ++; smlal signed multiply accumulate long. ++; smlald signed multiply accumulate long dual. ++; smlals signed multiply accumulate long, flag setting. ++; smlalxy signed multiply accumulate, 16x16-bit, 64-bit accumulate. ++; smlawx signed multiply accumulate, 32x16-bit, 32-bit accumulate. ++; smlawy signed multiply accumulate wide, 32x16-bit, ++; 32-bit accumulate. ++; smlaxy signed multiply accumulate, 16x16-bit, 32-bit accumulate. ++; smlsd signed multiply subtract dual. ++; smlsdx signed multiply subtract dual reverse. ++; smlsld signed multiply subtract long dual. ++; smmla signed most significant word multiply accumulate. ++; smmul signed most significant word multiply. ++; smmulr signed most significant word multiply, rounded. ++; smuad signed dual multiply add. ++; smuadx signed dual multiply add reverse. ++; smull signed multiply long. ++; smulls signed multiply long, flag setting. ++; smulwy signed multiply wide, 32x16-bit, 32-bit accumulate. ++; smulxy signed multiply, 16x16-bit, 32-bit accumulate. ++; smusd signed dual multiply subtract. ++; smusdx signed dual multiply subtract reverse. ++; store1 store 1 word to memory from arm registers. ++; store2 store 2 words to memory from arm registers. ++; store3 store 3 words to memory from arm registers. ++; store4 store 4 (or more) words to memory from arm registers. ++; udiv unsigned division. ++; umaal unsigned multiply accumulate accumulate long. ++; umlal unsigned multiply accumulate long. ++; umlals unsigned multiply accumulate long, flag setting. ++; umull unsigned multiply long. ++; umulls unsigned multiply long, flag setting. ++; ++; The classification below is for instructions used by the Wireless MMX ++; Technology. Each attribute value is used to classify an instruction of the ++; same name or family. ++; ++; wmmx_tandc ++; wmmx_tbcst ++; wmmx_textrc ++; wmmx_textrm ++; wmmx_tinsr ++; wmmx_tmcr ++; wmmx_tmcrr ++; wmmx_tmia ++; wmmx_tmiaph ++; wmmx_tmiaxy ++; wmmx_tmrc ++; wmmx_tmrrc ++; wmmx_tmovmsk ++; wmmx_torc ++; wmmx_torvsc ++; wmmx_wabs ++; wmmx_wdiff ++; wmmx_wacc ++; wmmx_wadd ++; wmmx_waddbhus ++; wmmx_waddsubhx ++; wmmx_waligni ++; wmmx_walignr ++; wmmx_wand ++; wmmx_wandn ++; wmmx_wavg2 ++; wmmx_wavg4 ++; wmmx_wcmpeq ++; wmmx_wcmpgt ++; wmmx_wmac ++; wmmx_wmadd ++; wmmx_wmax ++; wmmx_wmerge ++; wmmx_wmiawxy ++; wmmx_wmiaxy ++; wmmx_wmin ++; wmmx_wmov ++; wmmx_wmul ++; wmmx_wmulw ++; wmmx_wldr ++; wmmx_wor ++; wmmx_wpack ++; wmmx_wqmiaxy ++; wmmx_wqmulm ++; wmmx_wqmulwm ++; wmmx_wror ++; wmmx_wsad ++; wmmx_wshufh ++; wmmx_wsll ++; wmmx_wsra ++; wmmx_wsrl ++; wmmx_wstr ++; wmmx_wsub ++; wmmx_wsubaddhx ++; wmmx_wunpckeh ++; wmmx_wunpckel ++; wmmx_wunpckih ++; wmmx_wunpckil ++; wmmx_wxor + + (define_attr "type" +- "simple_alu_imm,\ +- alu_reg,\ +- simple_alu_shift,\ +- alu_shift,\ +- alu_shift_reg,\ +- mult,\ ++ "arlo_imm,\ ++ arlo_reg,\ ++ arlo_shift,\ ++ arlo_shift_reg,\ + block,\ +- float,\ ++ branch,\ ++ call,\ ++ clz,\ ++ extend,\ ++ f_2_r,\ ++ f_cvt,\ ++ f_flag,\ ++ f_loadd,\ ++ f_loads,\ ++ f_minmaxd,\ ++ f_minmaxs,\ ++ f_rintd,\ ++ f_rints,\ ++ f_seld,\ ++ f_sels,\ ++ f_stored,\ ++ f_stores,\ ++ faddd,\ ++ fadds,\ ++ fcmpd,\ ++ fcmps,\ ++ fconstd,\ ++ fconsts,\ ++ fcpys,\ + fdivd,\ + fdivs,\ ++ ffarithd,\ ++ ffariths,\ ++ ffmad,\ ++ ffmas,\ ++ float,\ ++ fmacd,\ ++ fmacs,\ ++ fmuld,\ + fmuls,\ +- fmuld,\ +- fmacs,\ +- fmacd,\ +- ffmas,\ +- ffmad,\ +- f_rints,\ +- f_rintd,\ +- f_minmaxs,\ +- f_minmaxd,\ +- f_flag,\ +- f_loads,\ +- f_loadd,\ +- f_stores,\ +- f_stored,\ +- f_2_r,\ +- r_2_f,\ +- f_cvt,\ +- branch,\ +- call,\ + load_byte,\ + load1,\ + load2,\ + load3,\ + load4,\ ++ mla,\ ++ mlas,\ ++ mov_imm,\ ++ mov_reg,\ ++ mov_shift,\ ++ mov_shift_reg,\ ++ mul,\ ++ muls,\ ++ mvn_imm,\ ++ mvn_reg,\ ++ mvn_shift,\ ++ mvn_shift_reg,\ ++ r_2_f,\ ++ sdiv,\ ++ shift,\ ++ shift_reg,\ ++ smlad,\ ++ smladx,\ ++ smlal,\ ++ smlald,\ ++ smlals,\ ++ smlalxy,\ ++ smlawx,\ ++ smlawy,\ ++ smlaxy,\ ++ smlsd,\ ++ smlsdx,\ ++ smlsld,\ ++ smmla,\ ++ smmul,\ ++ smmulr,\ ++ smuad,\ ++ smuadx,\ ++ smull,\ ++ smulls,\ ++ smulwy,\ ++ smulxy,\ ++ smusd,\ ++ smusdx,\ + store1,\ + store2,\ + store3,\ + store4,\ +- fconsts,\ +- fconstd,\ +- fadds,\ +- faddd,\ +- ffariths,\ +- ffarithd,\ +- fcmps,\ +- fcmpd,\ +- fcpys" +- (if_then_else +- (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,\ +- umull,umulls,umlal,umlals,smull,smulls,smlal,smlals") +- (const_string "mult") +- (const_string "alu_reg"))) ++ udiv,\ ++ umaal,\ ++ umlal,\ ++ umlals,\ ++ umull,\ ++ umulls,\ ++ wmmx_tandc,\ ++ wmmx_tbcst,\ ++ wmmx_textrc,\ ++ wmmx_textrm,\ ++ wmmx_tinsr,\ ++ wmmx_tmcr,\ ++ wmmx_tmcrr,\ ++ wmmx_tmia,\ ++ wmmx_tmiaph,\ ++ wmmx_tmiaxy,\ ++ wmmx_tmrc,\ ++ wmmx_tmrrc,\ ++ wmmx_tmovmsk,\ ++ wmmx_torc,\ ++ wmmx_torvsc,\ ++ wmmx_wabs,\ ++ wmmx_wabsdiff,\ ++ wmmx_wacc,\ ++ wmmx_wadd,\ ++ wmmx_waddbhus,\ ++ wmmx_waddsubhx,\ ++ wmmx_waligni,\ ++ wmmx_walignr,\ ++ wmmx_wand,\ ++ wmmx_wandn,\ ++ wmmx_wavg2,\ ++ wmmx_wavg4,\ ++ wmmx_wcmpeq,\ ++ wmmx_wcmpgt,\ ++ wmmx_wmac,\ ++ wmmx_wmadd,\ ++ wmmx_wmax,\ ++ wmmx_wmerge,\ ++ wmmx_wmiawxy,\ ++ wmmx_wmiaxy,\ ++ wmmx_wmin,\ ++ wmmx_wmov,\ ++ wmmx_wmul,\ ++ wmmx_wmulw,\ ++ wmmx_wldr,\ ++ wmmx_wor,\ ++ wmmx_wpack,\ ++ wmmx_wqmiaxy,\ ++ wmmx_wqmulm,\ ++ wmmx_wqmulwm,\ ++ wmmx_wror,\ ++ wmmx_wsad,\ ++ wmmx_wshufh,\ ++ wmmx_wsll,\ ++ wmmx_wsra,\ ++ wmmx_wsrl,\ ++ wmmx_wstr,\ ++ wmmx_wsub,\ ++ wmmx_wsubaddhx,\ ++ wmmx_wunpckeh,\ ++ wmmx_wunpckel,\ ++ wmmx_wunpckih,\ ++ wmmx_wunpckil,\ ++ wmmx_wxor" ++ (const_string "arlo_reg")) + ++; Is this an (integer side) multiply with a 32-bit (or smaller) result? ++(define_attr "mul32" "no,yes" ++ (if_then_else ++ (eq_attr "type" ++ "smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\ ++ smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld") ++ (const_string "yes") ++ (const_string "no"))) ++ + ; Is this an (integer side) multiply with a 64-bit result? + (define_attr "mul64" "no,yes" + (if_then_else +- (eq_attr "insn" +- "smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals") ++ (eq_attr "type" ++ "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals") + (const_string "yes") + (const_string "no"))) + +-; wtype for WMMX insn scheduling purposes. +-(define_attr "wtype" +- "none,wor,wxor,wand,wandn,wmov,tmcrr,tmrrc,wldr,wstr,tmcr,tmrc,wadd,wsub,wmul,wmac,wavg2,tinsr,textrm,wshufh,wcmpeq,wcmpgt,wmax,wmin,wpack,wunpckih,wunpckil,wunpckeh,wunpckel,wror,wsra,wsrl,wsll,wmadd,tmia,tmiaph,tmiaxy,tbcst,tmovmsk,wacc,waligni,walignr,tandc,textrc,torc,torvsc,wsad,wabs,wabsdiff,waddsubhx,wsubaddhx,wavg4,wmulw,wqmulm,wqmulwm,waddbhus,wqmiaxy,wmiaxy,wmiawxy,wmerge" (const_string "none")) +- + ; Load scheduling, set from the arm_ld_sched variable + ; initialized by arm_option_override() + (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))) +@@ -458,9 +684,19 @@ + ; than one on the main cpu execution unit. + (define_attr "core_cycles" "single,multi" + (if_then_else (eq_attr "type" +- "simple_alu_imm,alu_reg,\ +- simple_alu_shift,alu_shift,\ +- float,fdivd,fdivs") ++ "arlo_imm, arlo_reg,\ ++ extend, shift, arlo_shift, float, fdivd, fdivs,\ ++ wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\ ++ wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\ ++ wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\ ++ wmmx_wshufh, wmmx_wcmpeq, wmmx_wcmpgt, wmmx_wmax, wmmx_wmin, wmmx_wpack,\ ++ wmmx_wunpckih, wmmx_wunpckil, wmmx_wunpckeh, wmmx_wunpckel, wmmx_wror,\ ++ wmmx_wsra, wmmx_wsrl, wmmx_wsll, wmmx_wmadd, wmmx_tmia, wmmx_tmiaph,\ ++ wmmx_tmiaxy, wmmx_tbcst, wmmx_tmovmsk, wmmx_wacc, wmmx_waligni,\ ++ wmmx_walignr, wmmx_tandc, wmmx_textrc, wmmx_torc, wmmx_torvsc, wmmx_wsad,\ ++ wmmx_wabs, wmmx_wabsdiff, wmmx_waddsubhx, wmmx_wsubaddhx, wmmx_wavg4,\ ++ wmmx_wmulw, wmmx_wqmulm, wmmx_wqmulwm, wmmx_waddbhus, wmmx_wqmiaxy,\ ++ wmmx_wmiaxy, wmmx_wmiawxy, wmmx_wmerge") + (const_string "single") + (const_string "multi"))) + +@@ -502,7 +738,7 @@ + + (define_attr "generic_sched" "yes,no" + (const (if_then_else +- (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexm4,marvell_pj4") ++ (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexa53,cortexm4,marvell_pj4") + (eq_attr "tune_cortexr4" "yes")) + (const_string "no") + (const_string "yes")))) +@@ -510,7 +746,7 @@ + (define_attr "generic_vfp" "yes,no" + (const (if_then_else + (and (eq_attr "fpu" "vfp") +- (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexm4,marvell_pj4") ++ (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexa53,cortexm4,marvell_pj4") + (eq_attr "tune_cortexr4" "no")) + (const_string "yes") + (const_string "no")))) +@@ -531,6 +767,7 @@ + (include "cortex-a8.md") + (include "cortex-a9.md") + (include "cortex-a15.md") ++(include "cortex-a53.md") + (include "cortex-r4.md") + (include "cortex-r4f.md") + (include "cortex-m4.md") +@@ -697,14 +934,17 @@ + ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will + ;; put the duplicated register first, and not try the commutative version. + (define_insn_and_split "*arm_addsi3" +- [(set (match_operand:SI 0 "s_register_operand" "=rk, r,k, r,r, k, r, k,k,r, k, r") +- (plus:SI (match_operand:SI 1 "s_register_operand" "%0, rk,k, r,rk,k, rk,k,r,rk,k, rk") +- (match_operand:SI 2 "reg_or_int_operand" "rk, rI,rI,k,Pj,Pj,L, L,L,PJ,PJ,?n")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r") ++ (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk") ++ (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))] + "TARGET_32BIT" + "@ + add%?\\t%0, %0, %2 + add%?\\t%0, %1, %2 + add%?\\t%0, %1, %2 ++ add%?\\t%0, %1, %2 ++ add%?\\t%0, %1, %2 ++ add%?\\t%0, %1, %2 + add%?\\t%0, %2, %1 + addw%?\\t%0, %1, %2 + addw%?\\t%0, %1, %2 +@@ -725,12 +965,13 @@ + operands[1], 0); + DONE; + " +- [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,16") ++ [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16") + (set_attr "predicable" "yes") +- (set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*") ++ (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") ++ (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") +- (const_string "simple_alu_imm") +- (const_string "alu_reg"))) ++ (const_string "arlo_imm") ++ (const_string "arlo_reg"))) + ] + ) + +@@ -811,7 +1052,7 @@ + sub%.\\t%0, %1, #%n2 + add%.\\t%0, %1, %2" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm, simple_alu_imm, *")] ++ (set_attr "type" "arlo_imm,arlo_imm,*")] + ) + + (define_insn "*addsi3_compare0_scratch" +@@ -827,24 +1068,27 @@ + cmn%?\\t%0, %1" + [(set_attr "conds" "set") + (set_attr "predicable" "yes") +- (set_attr "type" "simple_alu_imm, simple_alu_imm, *") ++ (set_attr "type" "arlo_imm,arlo_imm,*") + ] + ) + + (define_insn "*compare_negsi_si" + [(set (reg:CC_Z CC_REGNUM) + (compare:CC_Z +- (neg:SI (match_operand:SI 0 "s_register_operand" "r")) +- (match_operand:SI 1 "s_register_operand" "r")))] ++ (neg:SI (match_operand:SI 0 "s_register_operand" "l,r")) ++ (match_operand:SI 1 "s_register_operand" "l,r")))] + "TARGET_32BIT" + "cmn%?\\t%1, %0" + [(set_attr "conds" "set") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "arch" "t2,*") ++ (set_attr "length" "2,4") ++ (set_attr "predicable_short_it" "yes,no")] + ) + + ;; This is the canonicalization of addsi3_compare0_for_combiner when the + ;; addend is a constant. +-(define_insn "*cmpsi2_addneg" ++(define_insn "cmpsi2_addneg" + [(set (reg:CC CC_REGNUM) + (compare:CC + (match_operand:SI 1 "s_register_operand" "r,r") +@@ -914,7 +1158,7 @@ + sub%.\\t%0, %1, #%n2 + add%.\\t%0, %1, %2" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ++ (set_attr "type" "arlo_imm,arlo_imm,*")] + ) + + (define_insn "*addsi3_compare_op2" +@@ -931,63 +1175,84 @@ + add%.\\t%0, %1, %2 + sub%.\\t%0, %1, #%n2" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ++ (set_attr "type" "arlo_imm,arlo_imm,*")] + ) + + (define_insn "*compare_addsi2_op0" + [(set (reg:CC_C CC_REGNUM) +- (compare:CC_C +- (plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r") +- (match_operand:SI 1 "arm_add_operand" "I,L,r")) +- (match_dup 0)))] ++ (compare:CC_C ++ (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r") ++ (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r")) ++ (match_dup 0)))] + "TARGET_32BIT" + "@ ++ cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1 ++ cmn%?\\t%0, %1 + cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1" + [(set_attr "conds" "set") + (set_attr "predicable" "yes") +- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ++ (set_attr "arch" "t2,t2,*,*,*") ++ (set_attr "predicable_short_it" "yes,yes,no,no,no") ++ (set_attr "length" "2,2,4,4,4") ++ (set_attr "type" "arlo_imm,*,arlo_imm,arlo_imm,*")] + ) + + (define_insn "*compare_addsi2_op1" + [(set (reg:CC_C CC_REGNUM) +- (compare:CC_C +- (plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r") +- (match_operand:SI 1 "arm_add_operand" "I,L,r")) +- (match_dup 1)))] ++ (compare:CC_C ++ (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r") ++ (match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r")) ++ (match_dup 1)))] + "TARGET_32BIT" + "@ ++ cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1 ++ cmn%?\\t%0, %1 + cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1" + [(set_attr "conds" "set") + (set_attr "predicable" "yes") +- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] +-) ++ (set_attr "arch" "t2,t2,*,*,*") ++ (set_attr "predicable_short_it" "yes,yes,no,no,no") ++ (set_attr "length" "2,2,4,4,4") ++ (set_attr "type" ++ "arlo_imm,*,arlo_imm,arlo_imm,*")] ++ ) + + (define_insn "*addsi3_carryin_" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r,r") +- (match_operand:SI 2 "arm_not_operand" "rI,K")) +- (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] ++ [(set (match_operand:SI 0 "s_register_operand" "=l,r,r") ++ (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%l,r,r") ++ (match_operand:SI 2 "arm_not_operand" "0,rI,K")) ++ (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "@ + adc%?\\t%0, %1, %2 ++ adc%?\\t%0, %1, %2 + sbc%?\\t%0, %1, #%B2" +- [(set_attr "conds" "use")] ++ [(set_attr "conds" "use") ++ (set_attr "predicable" "yes") ++ (set_attr "arch" "t2,*,*") ++ (set_attr "length" "4") ++ (set_attr "predicable_short_it" "yes,no,no")] + ) + + (define_insn "*addsi3_carryin_alt2_" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (plus:SI (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) +- (match_operand:SI 1 "s_register_operand" "%r,r")) +- (match_operand:SI 2 "arm_rhs_operand" "rI,K")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=l,r,r") ++ (plus:SI (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) ++ (match_operand:SI 1 "s_register_operand" "%l,r,r")) ++ (match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))] + "TARGET_32BIT" + "@ + adc%?\\t%0, %1, %2 ++ adc%?\\t%0, %1, %2 + sbc%?\\t%0, %1, #%B2" +- [(set_attr "conds" "use")] ++ [(set_attr "conds" "use") ++ (set_attr "predicable" "yes") ++ (set_attr "arch" "t2,*,*") ++ (set_attr "length" "4") ++ (set_attr "predicable_short_it" "yes,no,no")] + ) + + (define_insn "*addsi3_carryin_shift_" +@@ -1001,9 +1266,11 @@ + "TARGET_32BIT" + "adc%?\\t%0, %1, %3%S2" + [(set_attr "conds" "use") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++ (const_string "arlo_shift") ++ (const_string "arlo_shift_reg")))] + ) + + (define_insn "*addsi3_carryin_clobercc_" +@@ -1017,26 +1284,89 @@ + [(set_attr "conds" "set")] + ) + +-(define_expand "incscc" ++(define_insn "*subsi3_carryin" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (plus:SI (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand:CC 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "s_register_operand" "0,?r")))] ++ (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I") ++ (match_operand:SI 2 "s_register_operand" "r,r")) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" +- "" ++ "@ ++ sbc%?\\t%0, %1, %2 ++ rsc%?\\t%0, %2, %1" ++ [(set_attr "conds" "use") ++ (set_attr "arch" "*,a") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + +-(define_insn "*arm_incscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (plus:SI (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand:CC 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "s_register_operand" "0,?r")))] ++(define_insn "*subsi3_carryin_const" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (minus:SI (plus:SI (match_operand:SI 1 "reg_or_int_operand" "r") ++ (match_operand:SI 2 "arm_not_operand" "K")) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ "TARGET_32BIT" ++ "sbc\\t%0, %1, #%B2" ++ [(set_attr "conds" "use")] ++) + -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; VFP to/from core transfers. -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++(define_insn "*subsi3_carryin_compare" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "s_register_operand" "r") ++ (match_operand:SI 2 "s_register_operand" "r"))) ++ (set (match_operand:SI 0 "s_register_operand" "=r") ++ (minus:SI (minus:SI (match_dup 1) ++ (match_dup 2)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ "TARGET_32BIT" ++ "sbcs\\t%0, %1, %2" ++ [(set_attr "conds" "set")] ++) + -+(define_insn_reservation "cortex_a53_r2f" 4 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "r_2_f")) -+ "cortex_a53_slot0") ++(define_insn "*subsi3_carryin_compare_const" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r") ++ (match_operand:SI 2 "arm_not_operand" "K"))) ++ (set (match_operand:SI 0 "s_register_operand" "=r") ++ (minus:SI (plus:SI (match_dup 1) ++ (match_dup 2)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ "TARGET_32BIT" ++ "sbcs\\t%0, %1, #%B2" ++ [(set_attr "conds" "set")] ++) + -+(define_insn_reservation "cortex_a53_f2r" 2 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "f_2_r")) -+ "cortex_a53_slot0") ++(define_insn "*subsi3_carryin_shift" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (minus:SI (minus:SI ++ (match_operand:SI 1 "s_register_operand" "r") ++ (match_operator:SI 2 "shift_operator" ++ [(match_operand:SI 3 "s_register_operand" "r") ++ (match_operand:SI 4 "reg_or_int_operand" "rM")])) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ "TARGET_32BIT" ++ "sbc%?\\t%0, %1, %3%S2" ++ [(set_attr "conds" "use") ++ (set_attr "predicable" "yes") ++ (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") ++ (const_string "arlo_shift") ++ (const_string "arlo_shift_reg")))] ++) + -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; VFP flag transfer. -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++(define_insn "*rsbsi3_carryin_shift" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (minus:SI (minus:SI ++ (match_operator:SI 2 "shift_operator" ++ [(match_operand:SI 3 "s_register_operand" "r") ++ (match_operand:SI 4 "reg_or_int_operand" "rM")]) ++ (match_operand:SI 1 "s_register_operand" "r")) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_ARM" +- "@ +- add%d2\\t%0, %1, #1 +- mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1" ++ "rsc%?\\t%0, %1, %3%S2" + [(set_attr "conds" "use") +- (set_attr "length" "4,8")] ++ (set_attr "predicable" "yes") ++ (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") ++ (const_string "arlo_shift") ++ (const_string "arlo_shift_reg")))] + ) + + ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. +@@ -1087,13 +1417,27 @@ + " + ) + +-(define_insn "*arm_subdi3" ++(define_insn_and_split "*arm_subdi3" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r") + (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") + (match_operand:DI 2 "s_register_operand" "r,0,0"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT && !TARGET_NEON" +- "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" ++ "#" ; "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) ++ (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[3] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[4] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ operands[5] = gen_highpart (SImode, operands[2]); ++ operands[2] = gen_lowpart (SImode, operands[2]); ++ } + [(set_attr "conds" "clob") + (set_attr "length" "8")] + ) +@@ -1108,55 +1452,113 @@ + [(set_attr "length" "4")] + ) + +-(define_insn "*subdi_di_zesidi" ++(define_insn_and_split "*subdi_di_zesidi" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (minus:DI (match_operand:DI 1 "s_register_operand" "0,r") + (zero_extend:DI + (match_operand:SI 2 "s_register_operand" "r,r")))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT" +- "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0" ++ "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0" ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) ++ (set (match_dup 3) (minus:SI (plus:SI (match_dup 4) (match_dup 5)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[3] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[4] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ operands[5] = GEN_INT (~0); ++ } + [(set_attr "conds" "clob") + (set_attr "length" "8")] + ) + +-(define_insn "*subdi_di_sesidi" ++(define_insn_and_split "*subdi_di_sesidi" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (minus:DI (match_operand:DI 1 "s_register_operand" "0,r") + (sign_extend:DI + (match_operand:SI 2 "s_register_operand" "r,r")))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT" +- "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31" ++ "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31" ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) ++ (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) ++ (ashiftrt:SI (match_dup 2) ++ (const_int 31))) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[3] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[4] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ } + [(set_attr "conds" "clob") + (set_attr "length" "8")] + ) + +-(define_insn "*subdi_zesidi_di" ++(define_insn_and_split "*subdi_zesidi_di" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (minus:DI (zero_extend:DI + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "0,r"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0" ++ "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0" ++ ; is equivalent to: ++ ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, #0" ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 2) (match_dup 1))) ++ (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))]) ++ (set (match_dup 3) (minus:SI (minus:SI (const_int 0) (match_dup 4)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[3] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[4] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ } + [(set_attr "conds" "clob") + (set_attr "length" "8")] + ) + +-(define_insn "*subdi_sesidi_di" ++(define_insn_and_split "*subdi_sesidi_di" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (minus:DI (sign_extend:DI + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "0,r"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31" ++ "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31" ++ ; is equivalent to: ++ ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, %2, asr #31" ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 2) (match_dup 1))) ++ (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))]) ++ (set (match_dup 3) (minus:SI (minus:SI ++ (ashiftrt:SI (match_dup 2) ++ (const_int 31)) ++ (match_dup 4)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[3] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[4] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ } + [(set_attr "conds" "clob") + (set_attr "length" "8")] + ) + +-(define_insn "*subdi_zesidi_zesidi" ++(define_insn_and_split "*subdi_zesidi_zesidi" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (minus:DI (zero_extend:DI + (match_operand:SI 1 "s_register_operand" "r")) +@@ -1164,7 +1566,17 @@ + (match_operand:SI 2 "s_register_operand" "r")))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT" +- "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1" ++ "#" ; "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1" ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) ++ (set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 1)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[3] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ } + [(set_attr "conds" "clob") + (set_attr "length" "8")] + ) +@@ -1201,12 +1613,16 @@ + + ; ??? Check Thumb-2 split length + (define_insn_and_split "*arm_subsi3_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,rk,r") +- (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,r,k,?n") +- (match_operand:SI 2 "reg_or_int_operand" "r,I,r,r, r")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r ,r,r,rk,r") ++ (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,rI,r,r,k ,?n") ++ (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r ,I,r,r ,r")))] + "TARGET_32BIT" + "@ ++ sub%?\\t%0, %1, %2 ++ sub%?\\t%0, %2 ++ sub%?\\t%0, %1, %2 + rsb%?\\t%0, %2, %1 ++ rsb%?\\t%0, %2, %1 + sub%?\\t%0, %1, %2 + sub%?\\t%0, %1, %2 + sub%?\\t%0, %1, %2 +@@ -1219,9 +1635,11 @@ + INTVAL (operands[1]), operands[0], operands[2], 0); + DONE; + " +- [(set_attr "length" "4,4,4,4,16") ++ [(set_attr "length" "4,4,4,4,4,4,4,4,16") ++ (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*") + (set_attr "predicable" "yes") +- (set_attr "type" "*,simple_alu_imm,*,*,*")] ++ (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no") ++ (set_attr "type" "*,*,*,*,arlo_imm,arlo_imm,*,*,arlo_imm")] + ) + + (define_peephole2 +@@ -1251,10 +1669,10 @@ + sub%.\\t%0, %1, %2 + rsb%.\\t%0, %2, %1" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,*,*")] ++ (set_attr "type" "arlo_imm,*,*")] + ) + +-(define_insn "*subsi3_compare" ++(define_insn "subsi3_compare" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,r,I") + (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))) +@@ -1266,32 +1684,9 @@ + sub%.\\t%0, %1, %2 + rsb%.\\t%0, %2, %1" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,*,*")] ++ (set_attr "type" "arlo_imm,*,*")] + ) + +-(define_expand "decscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") +- (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)])))] +- "TARGET_32BIT" +- "" +-) +- +-(define_insn "*arm_decscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") +- (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)])))] +- "TARGET_ARM" +- "@ +- sub%d2\\t%0, %1, #1 +- mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1" +- [(set_attr "conds" "use") +- (set_attr "length" "*,8") +- (set_attr "type" "simple_alu_imm,*")] +-) +- + (define_expand "subsf3" + [(set (match_operand:SF 0 "s_register_operand" "") + (minus:SF (match_operand:SF 1 "s_register_operand" "") +@@ -1311,6 +1706,20 @@ + + ;; Multiplication insns + ++(define_expand "mulhi3" ++ [(set (match_operand:HI 0 "s_register_operand" "") ++ (mult:HI (match_operand:HI 1 "s_register_operand" "") ++ (match_operand:HI 2 "s_register_operand" "")))] ++ "TARGET_DSP_MULTIPLY" ++ " ++ { ++ rtx result = gen_reg_rtx (SImode); ++ emit_insn (gen_mulhisi3 (result, operands[1], operands[2])); ++ emit_move_insn (operands[0], gen_lowpart (HImode, result)); ++ DONE; ++ }" ++) + -+(define_insn_reservation "cortex_a53_f_flags" 4 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "f_flag")) -+ "cortex_a53_slot0") + (define_expand "mulsi3" + [(set (match_operand:SI 0 "s_register_operand" "") + (mult:SI (match_operand:SI 2 "s_register_operand" "") +@@ -1326,18 +1735,21 @@ + (match_operand:SI 1 "s_register_operand" "%0,r")))] + "TARGET_32BIT && !arm_arch6" + "mul%?\\t%0, %2, %1" +- [(set_attr "insn" "mul") ++ [(set_attr "type" "mul") + (set_attr "predicable" "yes")] + ) + + (define_insn "*arm_mulsi3_v6" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (mult:SI (match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "s_register_operand" "r")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=l,l,r") ++ (mult:SI (match_operand:SI 1 "s_register_operand" "0,l,r") ++ (match_operand:SI 2 "s_register_operand" "l,0,r")))] + "TARGET_32BIT && arm_arch6" + "mul%?\\t%0, %1, %2" +- [(set_attr "insn" "mul") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "mul") ++ (set_attr "predicable" "yes") ++ (set_attr "arch" "t2,t2,*") ++ (set_attr "length" "4") ++ (set_attr "predicable_short_it" "yes,yes,no")] + ) + + ; Unfortunately with the Thumb the '&'/'0' trick can fails when operands +@@ -1357,7 +1769,7 @@ + return \"mul\\t%0, %2\"; + " + [(set_attr "length" "4,4,2") +- (set_attr "insn" "mul")] ++ (set_attr "type" "muls")] + ) + + (define_insn "*thumb_mulsi3_v6" +@@ -1370,7 +1782,7 @@ + mul\\t%0, %1 + mul\\t%0, %1" + [(set_attr "length" "2") +- (set_attr "insn" "mul")] ++ (set_attr "type" "muls")] + ) + + (define_insn "*mulsi3_compare0" +@@ -1384,7 +1796,7 @@ + "TARGET_ARM && !arm_arch6" + "mul%.\\t%0, %2, %1" + [(set_attr "conds" "set") +- (set_attr "insn" "muls")] ++ (set_attr "type" "muls")] + ) + + (define_insn "*mulsi3_compare0_v6" +@@ -1398,7 +1810,7 @@ + "TARGET_ARM && arm_arch6 && optimize_size" + "mul%.\\t%0, %2, %1" + [(set_attr "conds" "set") +- (set_attr "insn" "muls")] ++ (set_attr "type" "muls")] + ) + + (define_insn "*mulsi_compare0_scratch" +@@ -1411,7 +1823,7 @@ + "TARGET_ARM && !arm_arch6" + "mul%.\\t%0, %2, %1" + [(set_attr "conds" "set") +- (set_attr "insn" "muls")] ++ (set_attr "type" "muls")] + ) + + (define_insn "*mulsi_compare0_scratch_v6" +@@ -1424,7 +1836,7 @@ + "TARGET_ARM && arm_arch6 && optimize_size" + "mul%.\\t%0, %2, %1" + [(set_attr "conds" "set") +- (set_attr "insn" "muls")] ++ (set_attr "type" "muls")] + ) + + ;; Unnamed templates to match MLA instruction. +@@ -1437,7 +1849,7 @@ + (match_operand:SI 3 "s_register_operand" "r,r,0,0")))] + "TARGET_32BIT && !arm_arch6" + "mla%?\\t%0, %2, %1, %3" +- [(set_attr "insn" "mla") ++ [(set_attr "type" "mla") + (set_attr "predicable" "yes")] + ) + +@@ -1449,8 +1861,9 @@ + (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_32BIT && arm_arch6" + "mla%?\\t%0, %2, %1, %3" +- [(set_attr "insn" "mla") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "mla") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "*mulsi3addsi_compare0" +@@ -1467,7 +1880,7 @@ + "TARGET_ARM && arm_arch6" + "mla%.\\t%0, %2, %1, %3" + [(set_attr "conds" "set") +- (set_attr "insn" "mlas")] ++ (set_attr "type" "mlas")] + ) + + (define_insn "*mulsi3addsi_compare0_v6" +@@ -1484,7 +1897,7 @@ + "TARGET_ARM && arm_arch6 && optimize_size" + "mla%.\\t%0, %2, %1, %3" + [(set_attr "conds" "set") +- (set_attr "insn" "mlas")] ++ (set_attr "type" "mlas")] + ) + + (define_insn "*mulsi3addsi_compare0_scratch" +@@ -1499,7 +1912,7 @@ + "TARGET_ARM && !arm_arch6" + "mla%.\\t%0, %2, %1, %3" + [(set_attr "conds" "set") +- (set_attr "insn" "mlas")] ++ (set_attr "type" "mlas")] + ) + + (define_insn "*mulsi3addsi_compare0_scratch_v6" +@@ -1514,7 +1927,7 @@ + "TARGET_ARM && arm_arch6 && optimize_size" + "mla%.\\t%0, %2, %1, %3" + [(set_attr "conds" "set") +- (set_attr "insn" "mlas")] ++ (set_attr "type" "mlas")] + ) + + (define_insn "*mulsi3subsi" +@@ -1525,8 +1938,9 @@ + (match_operand:SI 1 "s_register_operand" "r"))))] + "TARGET_32BIT && arm_arch_thumb2" + "mls%?\\t%0, %2, %1, %3" +- [(set_attr "insn" "mla") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "mla") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_expand "maddsidi4" +@@ -1548,7 +1962,7 @@ + (match_operand:DI 1 "s_register_operand" "0")))] + "TARGET_32BIT && arm_arch3m && !arm_arch6" + "smlal%?\\t%Q0, %R0, %3, %2" +- [(set_attr "insn" "smlal") ++ [(set_attr "type" "smlal") + (set_attr "predicable" "yes")] + ) + +@@ -1561,8 +1975,9 @@ + (match_operand:DI 1 "s_register_operand" "0")))] + "TARGET_32BIT && arm_arch6" + "smlal%?\\t%Q0, %R0, %3, %2" +- [(set_attr "insn" "smlal") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smlal") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + ;; 32x32->64 widening multiply. +@@ -1587,7 +2002,7 @@ + (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] + "TARGET_32BIT && arm_arch3m && !arm_arch6" + "smull%?\\t%Q0, %R0, %1, %2" +- [(set_attr "insn" "smull") ++ [(set_attr "type" "smull") + (set_attr "predicable" "yes")] + ) + +@@ -1598,8 +2013,9 @@ + (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] + "TARGET_32BIT && arm_arch6" + "smull%?\\t%Q0, %R0, %1, %2" +- [(set_attr "insn" "smull") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smull") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_expand "umulsidi3" +@@ -1618,7 +2034,7 @@ + (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] + "TARGET_32BIT && arm_arch3m && !arm_arch6" + "umull%?\\t%Q0, %R0, %1, %2" +- [(set_attr "insn" "umull") ++ [(set_attr "type" "umull") + (set_attr "predicable" "yes")] + ) + +@@ -1629,8 +2045,9 @@ + (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] + "TARGET_32BIT && arm_arch6" + "umull%?\\t%Q0, %R0, %1, %2" +- [(set_attr "insn" "umull") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "umull") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_expand "umaddsidi4" +@@ -1652,7 +2069,7 @@ + (match_operand:DI 1 "s_register_operand" "0")))] + "TARGET_32BIT && arm_arch3m && !arm_arch6" + "umlal%?\\t%Q0, %R0, %3, %2" +- [(set_attr "insn" "umlal") ++ [(set_attr "type" "umlal") + (set_attr "predicable" "yes")] + ) + +@@ -1665,8 +2082,9 @@ + (match_operand:DI 1 "s_register_operand" "0")))] + "TARGET_32BIT && arm_arch6" + "umlal%?\\t%Q0, %R0, %3, %2" +- [(set_attr "insn" "umlal") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "umlal") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_expand "smulsi3_highpart" +@@ -1694,7 +2112,7 @@ + (clobber (match_scratch:SI 3 "=&r,&r"))] + "TARGET_32BIT && arm_arch3m && !arm_arch6" + "smull%?\\t%3, %0, %2, %1" +- [(set_attr "insn" "smull") ++ [(set_attr "type" "smull") + (set_attr "predicable" "yes")] + ) + +@@ -1709,8 +2127,9 @@ + (clobber (match_scratch:SI 3 "=r"))] + "TARGET_32BIT && arm_arch6" + "smull%?\\t%3, %0, %2, %1" +- [(set_attr "insn" "smull") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smull") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_expand "umulsi3_highpart" +@@ -1738,7 +2157,7 @@ + (clobber (match_scratch:SI 3 "=&r,&r"))] + "TARGET_32BIT && arm_arch3m && !arm_arch6" + "umull%?\\t%3, %0, %2, %1" +- [(set_attr "insn" "umull") ++ [(set_attr "type" "umull") + (set_attr "predicable" "yes")] + ) + +@@ -1753,8 +2172,9 @@ + (clobber (match_scratch:SI 3 "=r"))] + "TARGET_32BIT && arm_arch6" + "umull%?\\t%3, %0, %2, %1" +- [(set_attr "insn" "umull") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "umull") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "mulhisi3" +@@ -1765,7 +2185,7 @@ + (match_operand:HI 2 "s_register_operand" "r"))))] + "TARGET_DSP_MULTIPLY" + "smulbb%?\\t%0, %1, %2" +- [(set_attr "insn" "smulxy") ++ [(set_attr "type" "smulxy") + (set_attr "predicable" "yes")] + ) + +@@ -1778,8 +2198,9 @@ + (match_operand:HI 2 "s_register_operand" "r"))))] + "TARGET_DSP_MULTIPLY" + "smultb%?\\t%0, %1, %2" +- [(set_attr "insn" "smulxy") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smulxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "*mulhisi3bt" +@@ -1791,8 +2212,9 @@ + (const_int 16))))] + "TARGET_DSP_MULTIPLY" + "smulbt%?\\t%0, %1, %2" +- [(set_attr "insn" "smulxy") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smulxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "*mulhisi3tt" +@@ -1805,8 +2227,9 @@ + (const_int 16))))] + "TARGET_DSP_MULTIPLY" + "smultt%?\\t%0, %1, %2" +- [(set_attr "insn" "smulxy") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smulxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "maddhisi4" +@@ -1818,8 +2241,9 @@ + (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_DSP_MULTIPLY" + "smlabb%?\\t%0, %1, %2, %3" +- [(set_attr "insn" "smlaxy") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smlaxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + ;; Note: there is no maddhisi4ibt because this one is canonical form +@@ -1833,8 +2257,9 @@ + (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_DSP_MULTIPLY" + "smlatb%?\\t%0, %1, %2, %3" +- [(set_attr "insn" "smlaxy") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smlaxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "*maddhisi4tt" +@@ -1848,22 +2273,24 @@ + (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_DSP_MULTIPLY" + "smlatt%?\\t%0, %1, %2, %3" +- [(set_attr "insn" "smlaxy") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "smlaxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "maddhidi4" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (plus:DI + (mult:DI (sign_extend:DI +- (match_operand:HI 1 "s_register_operand" "r")) ++ (match_operand:HI 1 "s_register_operand" "r")) + (sign_extend:DI + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:DI 3 "s_register_operand" "0")))] + "TARGET_DSP_MULTIPLY" + "smlalbb%?\\t%Q0, %R0, %1, %2" +- [(set_attr "insn" "smlalxy") +- (set_attr "predicable" "yes")]) ++ [(set_attr "type" "smlalxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + ;; Note: there is no maddhidi4ibt because this one is canonical form + (define_insn "*maddhidi4tb" +@@ -1878,8 +2305,9 @@ + (match_operand:DI 3 "s_register_operand" "0")))] + "TARGET_DSP_MULTIPLY" + "smlaltb%?\\t%Q0, %R0, %1, %2" +- [(set_attr "insn" "smlalxy") +- (set_attr "predicable" "yes")]) ++ [(set_attr "type" "smlalxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*maddhidi4tt" + [(set (match_operand:DI 0 "s_register_operand" "=r") +@@ -1895,8 +2323,9 @@ + (match_operand:DI 3 "s_register_operand" "0")))] + "TARGET_DSP_MULTIPLY" + "smlaltt%?\\t%Q0, %R0, %1, %2" +- [(set_attr "insn" "smlalxy") +- (set_attr "predicable" "yes")]) ++ [(set_attr "type" "smlalxy") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_expand "mulsf3" + [(set (match_operand:SF 0 "s_register_operand" "") +@@ -2024,13 +2453,49 @@ + "" + ) + +-(define_insn "*anddi3_insn" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") +- (and:DI (match_operand:DI 1 "s_register_operand" "%0,r") +- (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" +- "#" +- [(set_attr "length" "8")] ++(define_insn_and_split "*anddi3_insn" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,w ,&r,&r,&r,&r,?w,?w") ++ (and:DI (match_operand:DI 1 "s_register_operand" "%w,0 ,0 ,r ,0 ,r ,w ,0") ++ (match_operand:DI 2 "arm_anddi_operand_neon" "w ,DL,r ,r ,De,De,w ,DL")))] ++ "TARGET_32BIT && !TARGET_IWMMXT" ++{ ++ switch (which_alternative) ++ { ++ case 0: /* fall through */ ++ case 6: return "vand\t%P0, %P1, %P2"; ++ case 1: /* fall through */ ++ case 7: return neon_output_logic_immediate ("vand", &operands[2], ++ DImode, 1, VALID_NEON_QREG_MODE (DImode)); ++ case 2: ++ case 3: ++ case 4: ++ case 5: /* fall through */ ++ return "#"; ++ default: gcc_unreachable (); ++ } ++} ++ "TARGET_32BIT && !TARGET_IWMMXT && reload_completed ++ && !(IS_VFP_REGNUM (REGNO (operands[0])))" ++ [(set (match_dup 3) (match_dup 4)) ++ (set (match_dup 5) (match_dup 6))] ++ " ++ { ++ operands[3] = gen_lowpart (SImode, operands[0]); ++ operands[5] = gen_highpart (SImode, operands[0]); + -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; VFP load/store. -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ operands[4] = simplify_gen_binary (AND, SImode, ++ gen_lowpart (SImode, operands[1]), ++ gen_lowpart (SImode, operands[2])); ++ operands[6] = simplify_gen_binary (AND, SImode, ++ gen_highpart (SImode, operands[1]), ++ gen_highpart_mode (SImode, DImode, operands[2])); + -+(define_insn_reservation "cortex_a53_f_loads" 4 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "f_loads")) -+ "cortex_a53_slot0") ++ }" ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") ++ (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*, ++ avoid_neon_for_64bits,avoid_neon_for_64bits") ++ (set_attr "length" "*,*,8,8,8,8,*,*") ++ ] + ) + + (define_insn_and_split "*anddi_zesidi_di" +@@ -2145,12 +2610,13 @@ + + ; ??? Check split length for Thumb-2 + (define_insn_and_split "*arm_andsi3_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") +- (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r,r") +- (match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r") ++ (and:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r") ++ (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))] + "TARGET_32BIT" + "@ + and%?\\t%0, %1, %2 ++ and%?\\t%0, %1, %2 + bic%?\\t%0, %1, #%B2 + and%?\\t%0, %1, %2 + #" +@@ -2164,9 +2630,11 @@ + INTVAL (operands[2]), operands[0], operands[1], 0); + DONE; + " +- [(set_attr "length" "4,4,4,16") ++ [(set_attr "length" "4,4,4,4,16") + (set_attr "predicable" "yes") +- (set_attr "type" "simple_alu_imm,simple_alu_imm,*,simple_alu_imm")] ++ (set_attr "predicable_short_it" "no,yes,no,no,no") ++ (set_attr "type" ++ "arlo_imm,arlo_imm,*,*,arlo_imm")] + ) + + (define_insn "*thumb1_andsi3_insn" +@@ -2176,7 +2644,7 @@ + "TARGET_THUMB1" + "and\\t%0, %2" + [(set_attr "length" "2") +- (set_attr "type" "simple_alu_imm") ++ (set_attr "type" "arlo_imm") + (set_attr "conds" "set")]) + + (define_insn "*andsi3_compare0" +@@ -2193,7 +2661,7 @@ + bic%.\\t%0, %1, #%B2 + and%.\\t%0, %1, %2" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ++ (set_attr "type" "arlo_imm,arlo_imm,*")] + ) + + (define_insn "*andsi3_compare0_scratch" +@@ -2209,14 +2677,14 @@ + bic%.\\t%2, %0, #%B1 + tst%?\\t%0, %1" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ++ (set_attr "type" "arlo_imm,arlo_imm,*")] + ) + + (define_insn "*zeroextractsi_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (zero_extract:SI + (match_operand:SI 0 "s_register_operand" "r") +- (match_operand 1 "const_int_operand" "n") ++ (match_operand 1 "const_int_operand" "n") + (match_operand 2 "const_int_operand" "n")) + (const_int 0)))] + "TARGET_32BIT +@@ -2232,7 +2700,8 @@ + " + [(set_attr "conds" "set") + (set_attr "predicable" "yes") +- (set_attr "type" "simple_alu_imm")] ++ (set_attr "predicable_short_it" "no") ++ (set_attr "type" "arlo_imm")] + ) + + (define_insn_and_split "*ne_zeroextractsi" +@@ -2659,7 +3128,8 @@ + "arm_arch_thumb2" + "bfc%?\t%0, %2, %1" + [(set_attr "length" "4") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "insv_t2" +@@ -2670,7 +3140,8 @@ + "arm_arch_thumb2" + "bfi%?\t%0, %3, %2, %1" + [(set_attr "length" "4") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + ; constants for op 2 will never be given to these patterns. +@@ -2697,7 +3168,7 @@ + [(set_attr "length" "8") + (set_attr "predicable" "yes")] + ) +- + -+(define_insn_reservation "cortex_a53_f_loadd" 5 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "f_loadd")) -+ "cortex_a53_slot0") + (define_insn_and_split "*anddi_notzesidi_di" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (and:DI (not:DI (zero_extend:DI +@@ -2722,9 +3193,10 @@ + operands[1] = gen_lowpart (SImode, operands[1]); + }" + [(set_attr "length" "4,8") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) +- + -+(define_insn_reservation "cortex_a53_f_stores" 0 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "f_stores")) -+ "cortex_a53_slot0") + (define_insn_and_split "*anddi_notsesidi_di" + [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") + (and:DI (not:DI (sign_extend:DI +@@ -2745,16 +3217,18 @@ + operands[1] = gen_lowpart (SImode, operands[1]); + }" + [(set_attr "length" "8") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) +- + -+(define_insn_reservation "cortex_a53_f_stored" 0 -+ (and (eq_attr "tune" "cortexa53") -+ (eq_attr "type" "f_stored")) -+ "cortex_a53_slot0") + (define_insn "andsi_notsi_si" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) + (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_32BIT" + "bic%?\\t%0, %1, %2" +- [(set_attr "predicable" "yes")] ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "thumb1_bicsi3" +@@ -2777,8 +3251,8 @@ + [(set_attr "predicable" "yes") + (set_attr "shift" "2") + (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++ (const_string "arlo_shift") ++ (const_string "arlo_shift_reg")))] + ) + + (define_insn "*andsi_notsi_si_compare0" +@@ -2814,14 +3288,47 @@ + "" + ) + +-(define_insn "*iordi3_insn" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") +- (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r") +- (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" +- "#" +- [(set_attr "length" "8") +- (set_attr "predicable" "yes")] ++(define_insn_and_split "*iordi3_insn" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,w ,&r,&r,&r,&r,?w,?w") ++ (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0 ,0 ,r ,0 ,r ,w ,0") ++ (match_operand:DI 2 "arm_iordi_operand_neon" "w ,Dl,r ,r ,Df,Df,w ,Dl")))] ++ "TARGET_32BIT && !TARGET_IWMMXT" ++ { ++ switch (which_alternative) ++ { ++ case 0: /* fall through */ ++ case 6: return "vorr\t%P0, %P1, %P2"; ++ case 1: /* fall through */ ++ case 7: return neon_output_logic_immediate ("vorr", &operands[2], ++ DImode, 0, VALID_NEON_QREG_MODE (DImode)); ++ case 2: ++ case 3: ++ case 4: ++ case 5: ++ return "#"; ++ default: gcc_unreachable (); ++ } ++ } ++ "TARGET_32BIT && !TARGET_IWMMXT && reload_completed ++ && !(IS_VFP_REGNUM (REGNO (operands[0])))" ++ [(set (match_dup 3) (match_dup 4)) ++ (set (match_dup 5) (match_dup 6))] ++ " ++ { ++ operands[3] = gen_lowpart (SImode, operands[0]); ++ operands[5] = gen_highpart (SImode, operands[0]); + -+;; Load-to-use for floating-point values has a penalty of one cycle, -+;; i.e. a latency of two. ++ operands[4] = simplify_gen_binary (IOR, SImode, ++ gen_lowpart (SImode, operands[1]), ++ gen_lowpart (SImode, operands[2])); ++ operands[6] = simplify_gen_binary (IOR, SImode, ++ gen_highpart (SImode, operands[1]), ++ gen_highpart_mode (SImode, DImode, operands[2])); + -+(define_bypass 2 "cortex_a53_f_loads" -+ "cortex_a53_fpalu, cortex_a53_fpmac, cortex_a53_fpmul,\ -+ cortex_a53_fdivs, cortex_a53_fdivd,\ -+ cortex_a53_f2r") ++ }" ++ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") ++ (set_attr "length" "*,*,8,8,8,8,*,*") ++ (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")] + ) + + (define_insn "*iordi_zesidi_di" +@@ -2834,7 +3341,8 @@ + orr%?\\t%Q0, %Q1, %2 + #" + [(set_attr "length" "4,8") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "*iordi_sesidi_di" +@@ -2879,12 +3387,13 @@ + ) + + (define_insn_and_split "*iorsi3_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") +- (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r,r") +- (match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r") ++ (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r") ++ (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))] + "TARGET_32BIT" + "@ + orr%?\\t%0, %1, %2 ++ orr%?\\t%0, %1, %2 + orn%?\\t%0, %1, #%B2 + orr%?\\t%0, %1, %2 + #" +@@ -2894,14 +3403,15 @@ + || (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))" + [(clobber (const_int 0))] + { +- arm_split_constant (IOR, SImode, curr_insn, ++ arm_split_constant (IOR, SImode, curr_insn, + INTVAL (operands[2]), operands[0], operands[1], 0); + DONE; + } +- [(set_attr "length" "4,4,4,16") +- (set_attr "arch" "32,t2,32,32") ++ [(set_attr "length" "4,4,4,4,16") ++ (set_attr "arch" "32,t2,t2,32,32") + (set_attr "predicable" "yes") +- (set_attr "type" "simple_alu_imm,simple_alu_imm,*,*")] ++ (set_attr "predicable_short_it" "no,yes,no,no,no") ++ (set_attr "type" "arlo_imm,*,arlo_imm,*,*")] + ) + + (define_insn "*thumb1_iorsi3_insn" +@@ -2936,7 +3446,7 @@ + "TARGET_32BIT" + "orr%.\\t%0, %1, %2" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,*")] ++ (set_attr "type" "arlo_imm,*")] + ) + + (define_insn "*iorsi3_compare0_scratch" +@@ -2948,25 +3458,55 @@ + "TARGET_32BIT" + "orr%.\\t%0, %1, %2" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm, *")] ++ (set_attr "type" "arlo_imm,*")] + ) + + (define_expand "xordi3" + [(set (match_operand:DI 0 "s_register_operand" "") + (xor:DI (match_operand:DI 1 "s_register_operand" "") +- (match_operand:DI 2 "s_register_operand" "")))] ++ (match_operand:DI 2 "arm_xordi_operand" "")))] + "TARGET_32BIT" + "" + ) + +-(define_insn "*xordi3_insn" +- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") +- (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r") +- (match_operand:DI 2 "s_register_operand" "r,r")))] +- "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" +- "#" +- [(set_attr "length" "8") +- (set_attr "predicable" "yes")] ++(define_insn_and_split "*xordi3_insn" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,&r,&r,&r,&r,?w") ++ (xor:DI (match_operand:DI 1 "s_register_operand" "w ,%0,r ,0 ,r ,w") ++ (match_operand:DI 2 "arm_xordi_operand" "w ,r ,r ,Dg,Dg,w")))] ++ "TARGET_32BIT && !TARGET_IWMMXT" ++{ ++ switch (which_alternative) ++ { ++ case 1: ++ case 2: ++ case 3: ++ case 4: /* fall through */ ++ return "#"; ++ case 0: /* fall through */ ++ case 5: return "veor\t%P0, %P1, %P2"; ++ default: gcc_unreachable (); ++ } ++} ++ "TARGET_32BIT && !TARGET_IWMMXT && reload_completed ++ && !(IS_VFP_REGNUM (REGNO (operands[0])))" ++ [(set (match_dup 3) (match_dup 4)) ++ (set (match_dup 5) (match_dup 6))] ++ " ++ { ++ operands[3] = gen_lowpart (SImode, operands[0]); ++ operands[5] = gen_highpart (SImode, operands[0]); + -+(define_bypass 2 "cortex_a53_f_loadd" -+ "cortex_a53_fpalu, cortex_a53_fpmac, cortex_a53_fpmul,\ -+ cortex_a53_fdivs, cortex_a53_fdivd,\ -+ cortex_a53_f2r") ++ operands[4] = simplify_gen_binary (XOR, SImode, ++ gen_lowpart (SImode, operands[1]), ++ gen_lowpart (SImode, operands[2])); ++ operands[6] = simplify_gen_binary (XOR, SImode, ++ gen_highpart (SImode, operands[1]), ++ gen_highpart_mode (SImode, DImode, operands[2])); + ---- a/src/gcc/config/arm/bpabi.h -+++ b/src/gcc/config/arm/bpabi.h -@@ -60,6 +60,7 @@ - |mcpu=cortex-a7 \ - |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ - |mcpu=marvell-pj4 \ -+ |mcpu=cortex-a53 \ - |mcpu=generic-armv7-a \ - |march=armv7-m|mcpu=cortex-m3 \ - |march=armv7e-m|mcpu=cortex-m4 \ -@@ -71,6 +72,7 @@ - " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5 \ - |mcpu=cortex-a7 \ - |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ -+ |mcpu=cortex-a53 \ - |mcpu=marvell-pj4 \ - |mcpu=generic-armv7-a \ - |march=armv7-m|mcpu=cortex-m3 \ ---- a/src/gcc/config/arm/sync.md -+++ b/src/gcc/config/arm/sync.md -@@ -65,6 +65,42 @@ - (set_attr "conds" "unconditional") - (set_attr "predicable" "no")]) ++ }" ++ [(set_attr "length" "*,8,8,8,8,*") ++ (set_attr "neon_type" "neon_int_1,*,*,*,*,neon_int_1") ++ (set_attr "arch" "neon_for_64bits,*,*,*,*,avoid_neon_for_64bits")] + ) + + (define_insn "*xordi_zesidi_di" +@@ -2979,7 +3519,8 @@ + eor%?\\t%Q0, %Q1, %2 + #" + [(set_attr "length" "4,8") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "*xordi_sesidi_di" +@@ -3022,13 +3563,14 @@ + ) + + (define_insn_and_split "*arm_xorsi3" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r,r") +- (match_operand:SI 2 "reg_or_int_operand" "I,r,?n")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r") ++ (xor:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r") ++ (match_operand:SI 2 "reg_or_int_operand" "I,l,r,?n")))] + "TARGET_32BIT" + "@ + eor%?\\t%0, %1, %2 + eor%?\\t%0, %1, %2 ++ eor%?\\t%0, %1, %2 + #" + "TARGET_32BIT + && CONST_INT_P (operands[2]) +@@ -3039,9 +3581,10 @@ + INTVAL (operands[2]), operands[0], operands[1], 0); + DONE; + } +- [(set_attr "length" "4,4,16") ++ [(set_attr "length" "4,4,4,16") + (set_attr "predicable" "yes") +- (set_attr "type" "simple_alu_imm,*,*")] ++ (set_attr "predicable_short_it" "no,yes,no,no") ++ (set_attr "type" "arlo_imm,*,*,*")] + ) + + (define_insn "*thumb1_xorsi3_insn" +@@ -3052,7 +3595,7 @@ + "eor\\t%0, %2" + [(set_attr "length" "2") + (set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm")] ++ (set_attr "type" "arlo_imm")] + ) + + (define_insn "*xorsi3_compare0" +@@ -3065,7 +3608,7 @@ + "TARGET_32BIT" + "eor%.\\t%0, %1, %2" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,*")] ++ (set_attr "type" "arlo_imm,*")] + ) + + (define_insn "*xorsi3_compare0_scratch" +@@ -3076,7 +3619,7 @@ + "TARGET_32BIT" + "teq%?\\t%0, %1" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm, *")] ++ (set_attr "type" "arlo_imm,*")] + ) + + ; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C), +@@ -3096,16 +3639,21 @@ + "" + ) + +-(define_insn "*andsi_iorsi3_notsi" ++(define_insn_and_split "*andsi_iorsi3_notsi" + [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") + (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r") + (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")) + (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))] + "TARGET_32BIT" +- "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3" ++ "#" ; "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3" ++ "&& reload_completed" ++ [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 0)))] ++ "" + [(set_attr "length" "8") + (set_attr "ce_count" "2") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + ; ??? Are these four splitters still beneficial when the Thumb-2 bitfield +@@ -3241,7 +3789,8 @@ + (const_int 0)))] + "TARGET_32BIT" + "bic%?\\t%0, %1, %1, asr #31" +- [(set_attr "predicable" "yes")] ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + + (define_insn "*smax_m1" +@@ -3250,18 +3799,27 @@ + (const_int -1)))] + "TARGET_32BIT" + "orr%?\\t%0, %1, %1, asr #31" +- [(set_attr "predicable" "yes")] ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + +-(define_insn "*arm_smax_insn" ++(define_insn_and_split "*arm_smax_insn" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r") + (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "@ +- cmp\\t%1, %2\;movlt\\t%0, %2 +- cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2" ++ "#" ++ ; cmp\\t%1, %2\;movlt\\t%0, %2 ++ ; cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2" ++ "TARGET_ARM" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) ++ (if_then_else:SI (ge:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (match_dup 1) ++ (match_dup 2)))] ++ "" + [(set_attr "conds" "clob") + (set_attr "length" "8,12")] + ) +@@ -3290,18 +3848,27 @@ + (const_int 0)))] + "TARGET_32BIT" + "and%?\\t%0, %1, %1, asr #31" +- [(set_attr "predicable" "yes")] ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) + +-(define_insn "*arm_smin_insn" ++(define_insn_and_split "*arm_smin_insn" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r") + (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "@ +- cmp\\t%1, %2\;movge\\t%0, %2 +- cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2" ++ "#" ++ ; cmp\\t%1, %2\;movge\\t%0, %2 ++ ; cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2" ++ "TARGET_ARM" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) ++ (if_then_else:SI (lt:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (match_dup 1) ++ (match_dup 2)))] ++ "" + [(set_attr "conds" "clob") + (set_attr "length" "8,12")] + ) +@@ -3316,16 +3883,24 @@ + "" + ) + +-(define_insn "*arm_umaxsi3" ++(define_insn_and_split "*arm_umaxsi3" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") + (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "@ +- cmp\\t%1, %2\;movcc\\t%0, %2 +- cmp\\t%1, %2\;movcs\\t%0, %1 +- cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2" ++ "#" ++ ; cmp\\t%1, %2\;movcc\\t%0, %2 ++ ; cmp\\t%1, %2\;movcs\\t%0, %1 ++ ; cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2" ++ "TARGET_ARM" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) ++ (if_then_else:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (match_dup 1) ++ (match_dup 2)))] ++ "" + [(set_attr "conds" "clob") + (set_attr "length" "8,8,12")] + ) +@@ -3340,16 +3915,24 @@ + "" + ) -+(define_insn "atomic_load" -+ [(set (match_operand:QHSI 0 "register_operand" "=r") -+ (unspec_volatile:QHSI -+ [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q") -+ (match_operand:SI 2 "const_int_operand")] ;; model -+ VUNSPEC_LDA))] -+ "TARGET_HAVE_LDACQ" -+ { -+ enum memmodel model = (enum memmodel) INTVAL (operands[2]); -+ if (model == MEMMODEL_RELAXED -+ || model == MEMMODEL_CONSUME -+ || model == MEMMODEL_RELEASE) -+ return \"ldr\\t%0, %1\"; -+ else -+ return \"lda\\t%0, %1\"; -+ } -+) +-(define_insn "*arm_uminsi3" ++(define_insn_and_split "*arm_uminsi3" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") + (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "@ +- cmp\\t%1, %2\;movcs\\t%0, %2 +- cmp\\t%1, %2\;movcc\\t%0, %1 +- cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2" ++ "#" ++ ; cmp\\t%1, %2\;movcs\\t%0, %2 ++ ; cmp\\t%1, %2\;movcc\\t%0, %1 ++ ; cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2" ++ "TARGET_ARM" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) ++ (if_then_else:SI (ltu:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (match_dup 1) ++ (match_dup 2)))] ++ "" + [(set_attr "conds" "clob") + (set_attr "length" "8,8,12")] + ) +@@ -3360,7 +3943,7 @@ + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")])) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT" ++ "TARGET_32BIT && optimize_insn_for_size_p()" + "* + operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode, + operands[1], operands[2]); +@@ -3389,7 +3972,7 @@ + (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) + (match_operand:SI 1 "s_register_operand" "0,?r")])) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT && !arm_eliminable_register (operands[1])" ++ "TARGET_32BIT && !arm_eliminable_register (operands[1]) && !arm_restrict_it" + "* + { + enum rtx_code code = GET_CODE (operands[4]); +@@ -3423,6 +4006,54 @@ + (const_int 12)))] + ) + ++; Reject the frame pointer in operand[1], since reloading this after ++; it has been eliminated can cause carnage. ++(define_insn_and_split "*minmax_arithsi_non_canon" ++ [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts") ++ (minus:SI ++ (match_operand:SI 1 "s_register_operand" "0,?Ts") ++ (match_operator:SI 4 "minmax_operator" ++ [(match_operand:SI 2 "s_register_operand" "Ts,Ts") ++ (match_operand:SI 3 "arm_rhs_operand" "TsI,TsI")]))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT && !arm_eliminable_register (operands[1]) ++ && !(arm_restrict_it && CONST_INT_P (operands[3]))" ++ "#" ++ "TARGET_32BIT && !arm_eliminable_register (operands[1]) && reload_completed" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 2) (match_dup 3))) + -+(define_insn "atomic_store" -+ [(set (match_operand:QHSI 0 "memory_operand" "=Q") -+ (unspec_volatile:QHSI -+ [(match_operand:QHSI 1 "general_operand" "r") -+ (match_operand:SI 2 "const_int_operand")] ;; model -+ VUNSPEC_STL))] -+ "TARGET_HAVE_LDACQ" ++ (cond_exec (match_op_dup 4 [(reg:CC CC_REGNUM) (const_int 0)]) ++ (set (match_dup 0) ++ (minus:SI (match_dup 1) ++ (match_dup 2)))) ++ (cond_exec (match_op_dup 5 [(reg:CC CC_REGNUM) (const_int 0)]) ++ (set (match_dup 0) ++ (match_dup 6)))] + { -+ enum memmodel model = (enum memmodel) INTVAL (operands[2]); -+ if (model == MEMMODEL_RELAXED -+ || model == MEMMODEL_CONSUME -+ || model == MEMMODEL_ACQUIRE) -+ return \"str\t%1, %0\"; -+ else -+ return \"stl\t%1, %0\"; ++ enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), ++ operands[2], operands[3]); ++ enum rtx_code rc = minmax_code (operands[4]); ++ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, ++ operands[2], operands[3]); ++ ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rc = reverse_condition_maybe_unordered (rc); ++ else ++ rc = reverse_condition (rc); ++ operands[5] = gen_rtx_fmt_ee (rc, SImode, operands[2], operands[3]); ++ if (CONST_INT_P (operands[3])) ++ operands[6] = plus_constant (SImode, operands[1], -INTVAL (operands[3])); ++ else ++ operands[6] = gen_rtx_MINUS (SImode, operands[1], operands[3]); + } ++ [(set_attr "conds" "clob") ++ (set (attr "length") ++ (if_then_else (eq_attr "is_thumb" "yes") ++ (const_int 14) ++ (const_int 12)))] +) + - ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, - ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied - ;; with a store. -@@ -88,7 +124,8 @@ - UNSPEC_LL))] - "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN" - "ldrexd%?\t%0, %H0, %C1" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) - - (define_expand "atomic_compare_and_swap" - [(match_operand:SI 0 "s_register_operand" "") ;; bool out -@@ -325,8 +362,20 @@ - VUNSPEC_LL)))] - "TARGET_HAVE_LDREXBH" - "ldrex%?\t%0, %C1" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) + (define_code_iterator SAT [smin smax]) + (define_code_iterator SATrev [smin smax]) + (define_code_attr SATlo [(smin "1") (smax "2")]) +@@ -3449,7 +4080,8 @@ + return "usat%?\t%0, %1, %3"; + } + [(set_attr "predicable" "yes") +- (set_attr "insn" "sat")]) ++ (set_attr "predicable_short_it" "no")] ++) -+(define_insn "arm_load_acquire_exclusive" -+ [(set (match_operand:SI 0 "s_register_operand" "=r") -+ (zero_extend:SI -+ (unspec_volatile:NARROW -+ [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")] -+ VUNSPEC_LAX)))] -+ "TARGET_HAVE_LDACQ" -+ "ldaex%?\\t%0, %C1" -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) -+ - (define_insn "arm_load_exclusivesi" + (define_insn "*satsi__shift" [(set (match_operand:SI 0 "s_register_operand" "=r") - (unspec_volatile:SI -@@ -334,8 +383,19 @@ - VUNSPEC_LL))] - "TARGET_HAVE_LDREX" - "ldrex%?\t%0, %C1" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) +@@ -3474,9 +4106,9 @@ + return "usat%?\t%0, %1, %4%S3"; + } + [(set_attr "predicable" "yes") +- (set_attr "insn" "sat") ++ (set_attr "predicable_short_it" "no") + (set_attr "shift" "3") +- (set_attr "type" "alu_shift")]) ++ (set_attr "type" "arlo_shift")]) + + ;; Shift and rotation insns -+(define_insn "arm_load_acquire_exclusivesi" -+ [(set (match_operand:SI 0 "s_register_operand" "=r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "mem_noofs_operand" "Ua")] -+ VUNSPEC_LAX))] -+ "TARGET_HAVE_LDACQ" -+ "ldaex%?\t%0, %C1" -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) -+ - (define_insn "arm_load_exclusivedi" - [(set (match_operand:DI 0 "s_register_operand" "=r") - (unspec_volatile:DI -@@ -343,8 +403,19 @@ - VUNSPEC_LL))] - "TARGET_HAVE_LDREXD" - "ldrexd%?\t%0, %H0, %C1" -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) +@@ -3566,6 +4198,7 @@ + "TARGET_THUMB1" + "lsl\\t%0, %1, %2" + [(set_attr "length" "2") ++ (set_attr "type" "shift,shift_reg") + (set_attr "conds" "set")]) + + (define_expand "ashrdi3" +@@ -3623,7 +4256,6 @@ + "TARGET_32BIT" + "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" + [(set_attr "conds" "clob") +- (set_attr "insn" "mov") + (set_attr "length" "8")] + ) + +@@ -3646,6 +4278,7 @@ + "TARGET_THUMB1" + "asr\\t%0, %1, %2" + [(set_attr "length" "2") ++ (set_attr "type" "shift,shift_reg") + (set_attr "conds" "set")]) + + (define_expand "lshrdi3" +@@ -3703,7 +4336,6 @@ + "TARGET_32BIT" + "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" + [(set_attr "conds" "clob") +- (set_attr "insn" "mov") + (set_attr "length" "8")] + ) + +@@ -3729,6 +4361,7 @@ + "TARGET_THUMB1" + "lsr\\t%0, %1, %2" + [(set_attr "length" "2") ++ (set_attr "type" "shift,shift_reg") + (set_attr "conds" "set")]) + + (define_expand "rotlsi3" +@@ -3774,51 +4407,52 @@ + (match_operand:SI 2 "register_operand" "l")))] + "TARGET_THUMB1" + "ror\\t%0, %0, %2" +- [(set_attr "length" "2")] ++ [(set_attr "type" "shift_reg") ++ (set_attr "length" "2")] + ) + + (define_insn "*arm_shiftsi3" +- [(set (match_operand:SI 0 "s_register_operand" "=r") ++ [(set (match_operand:SI 0 "s_register_operand" "=l,r,r") + (match_operator:SI 3 "shift_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "reg_or_int_operand" "rM")]))] ++ [(match_operand:SI 1 "s_register_operand" "0,r,r") ++ (match_operand:SI 2 "reg_or_int_operand" "l,M,r")]))] + "TARGET_32BIT" + "* return arm_output_shift(operands, 0);" + [(set_attr "predicable" "yes") ++ (set_attr "arch" "t2,*,*") ++ (set_attr "predicable_short_it" "yes,no,no") ++ (set_attr "length" "4") + (set_attr "shift" "1") +- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++ (set_attr "type" "arlo_shift_reg,arlo_shift,arlo_shift_reg")] + ) + + (define_insn "*shiftsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (match_operator:SI 3 "shift_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rM")]) ++ [(match_operand:SI 1 "s_register_operand" "r,r") ++ (match_operand:SI 2 "arm_rhs_operand" "M,r")]) + (const_int 0))) +- (set (match_operand:SI 0 "s_register_operand" "=r") ++ (set (match_operand:SI 0 "s_register_operand" "=r,r") + (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] + "TARGET_32BIT" + "* return arm_output_shift(operands, 1);" + [(set_attr "conds" "set") + (set_attr "shift" "1") +- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++ (set_attr "type" "arlo_shift,arlo_shift_reg")] + ) + + (define_insn "*shiftsi3_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (match_operator:SI 3 "shift_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rM")]) ++ [(match_operand:SI 1 "s_register_operand" "r,r") ++ (match_operand:SI 2 "arm_rhs_operand" "M,r")]) + (const_int 0))) +- (clobber (match_scratch:SI 0 "=r"))] ++ (clobber (match_scratch:SI 0 "=r,r"))] + "TARGET_32BIT" + "* return arm_output_shift(operands, 1);" + [(set_attr "conds" "set") +- (set_attr "shift" "1")] ++ (set_attr "shift" "1") ++ (set_attr "type" "shift,shift_reg")] + ) + + (define_insn "*not_shiftsi" +@@ -3829,10 +4463,10 @@ + "TARGET_32BIT" + "mvn%?\\t%0, %1%S3" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "shift" "1") +- (set_attr "insn" "mvn") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "mvn_shift,mvn_shift_reg")]) + + (define_insn "*not_shiftsi_compare0" + [(set (reg:CC_NOOV CC_REGNUM) +@@ -3847,9 +4481,8 @@ + "mvn%.\\t%0, %1%S3" + [(set_attr "conds" "set") + (set_attr "shift" "1") +- (set_attr "insn" "mvn") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "mvn_shift,mvn_shift_reg")]) + + (define_insn "*not_shiftsi_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) +@@ -3863,9 +4496,8 @@ + "mvn%.\\t%0, %1%S3" + [(set_attr "conds" "set") + (set_attr "shift" "1") +- (set_attr "insn" "mvn") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "mvn_shift,mvn_shift_reg")]) + + ;; We don't really have extzv, but defining this using shifts helps + ;; to reduce register pressure later on. +@@ -4042,6 +4674,7 @@ + [(set_attr "arch" "t2,any") + (set_attr "length" "2,4") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no") + (set_attr "type" "load1")]) + + (define_insn "unaligned_loadhis" +@@ -4054,6 +4687,7 @@ + [(set_attr "arch" "t2,any") + (set_attr "length" "2,4") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no") + (set_attr "type" "load_byte")]) + + (define_insn "unaligned_loadhiu" +@@ -4066,6 +4700,7 @@ + [(set_attr "arch" "t2,any") + (set_attr "length" "2,4") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no") + (set_attr "type" "load_byte")]) + + (define_insn "unaligned_storesi" +@@ -4077,6 +4712,7 @@ + [(set_attr "arch" "t2,any") + (set_attr "length" "2,4") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no") + (set_attr "type" "store1")]) + + (define_insn "unaligned_storehi" +@@ -4088,8 +4724,67 @@ + [(set_attr "arch" "t2,any") + (set_attr "length" "2,4") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no") + (set_attr "type" "store1")]) -+(define_insn "arm_load_acquire_exclusivedi" -+ [(set (match_operand:DI 0 "s_register_operand" "=r") -+ (unspec_volatile:DI -+ [(match_operand:DI 1 "mem_noofs_operand" "Ua")] -+ VUNSPEC_LAX))] -+ "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" -+ "ldaexd%?\t%0, %H0, %C1" -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) ++;; Unaligned double-word load and store. ++;; Split after reload into two unaligned single-word accesses. ++;; It prevents lower_subreg from splitting some other aligned ++;; double-word accesses too early. Used for internal memcpy. + - (define_insn "arm_store_exclusive" - [(set (match_operand:SI 0 "s_register_operand" "=&r") - (unspec_volatile:SI [(const_int 0)] VUNSPEC_SC)) -@@ -367,4 +438,35 @@ - } - return "strex%?\t%0, %2, %C1"; - } -- [(set_attr "predicable" "yes")]) -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) ++(define_insn_and_split "unaligned_loaddi" ++ [(set (match_operand:DI 0 "s_register_operand" "=l,r") ++ (unspec:DI [(match_operand:DI 1 "memory_operand" "o,o")] ++ UNSPEC_UNALIGNED_LOAD))] ++ "unaligned_access && TARGET_32BIT" ++ "#" ++ "&& reload_completed" ++ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_UNALIGNED_LOAD)) ++ (set (match_dup 2) (unspec:SI [(match_dup 3)] UNSPEC_UNALIGNED_LOAD))] ++ { ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[3] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); + -+(define_insn "arm_store_release_exclusivedi" -+ [(set (match_operand:SI 0 "s_register_operand" "=&r") -+ (unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX)) -+ (set (match_operand:DI 1 "mem_noofs_operand" "=Ua") -+ (unspec_volatile:DI -+ [(match_operand:DI 2 "s_register_operand" "r")] -+ VUNSPEC_SLX))] -+ "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN" ++ /* If the first destination register overlaps with the base address, ++ swap the order in which the loads are emitted. */ ++ if (reg_overlap_mentioned_p (operands[0], operands[1])) ++ { ++ rtx tmp = operands[1]; ++ operands[1] = operands[3]; ++ operands[3] = tmp; ++ tmp = operands[0]; ++ operands[0] = operands[2]; ++ operands[2] = tmp; ++ } ++ } ++ [(set_attr "arch" "t2,any") ++ (set_attr "length" "4,8") ++ (set_attr "predicable" "yes") ++ (set_attr "type" "load2")]) ++ ++(define_insn_and_split "unaligned_storedi" ++ [(set (match_operand:DI 0 "memory_operand" "=o,o") ++ (unspec:DI [(match_operand:DI 1 "s_register_operand" "l,r")] ++ UNSPEC_UNALIGNED_STORE))] ++ "unaligned_access && TARGET_32BIT" ++ "#" ++ "&& reload_completed" ++ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_UNALIGNED_STORE)) ++ (set (match_dup 2) (unspec:SI [(match_dup 3)] UNSPEC_UNALIGNED_STORE))] + { -+ rtx value = operands[2]; -+ /* See comment in arm_store_exclusive above. */ -+ gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2); -+ operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1); -+ return "stlexd%?\t%0, %2, %3, %C1"; ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[3] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); + } -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) ++ [(set_attr "arch" "t2,any") ++ (set_attr "length" "4,8") ++ (set_attr "predicable" "yes") ++ (set_attr "type" "store2")]) + -+(define_insn "arm_store_release_exclusive" -+ [(set (match_operand:SI 0 "s_register_operand" "=&r") -+ (unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX)) -+ (set (match_operand:QHSI 1 "mem_noofs_operand" "=Ua") -+ (unspec_volatile:QHSI -+ [(match_operand:QHSI 2 "s_register_operand" "r")] -+ VUNSPEC_SLX))] -+ "TARGET_HAVE_LDACQ" -+ "stlex%?\t%0, %2, %C1" -+ [(set_attr "predicable" "yes") -+ (set_attr "predicable_short_it" "no")]) ---- a/src/gcc/config/arm/neon-testgen.ml -+++ b/src/gcc/config/arm/neon-testgen.ml -@@ -163,10 +163,12 @@ - match List.find (fun feature -> - match feature with Requires_feature _ -> true - | Requires_arch _ -> true -+ | Requires_FP_bit 1 -> true - | _ -> false) - features with - Requires_feature "FMA" -> "arm_neonv2" - | Requires_arch 8 -> "arm_v8_neon" -+ | Requires_FP_bit 1 -> "arm_neon_fp16" - | _ -> assert false - with Not_found -> "arm_neon" ++ + (define_insn "*extv_reg" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") +@@ -4098,7 +4793,8 @@ + "arm_arch_thumb2" + "sbfx%?\t%0, %1, %3, %2" + [(set_attr "length" "4") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) ---- a/src/gcc/config/arm/arm.md -+++ b/src/gcc/config/arm/arm.md -@@ -74,6 +74,15 @@ - ; IS_THUMB1 is set to 'yes' iff we are generating Thumb-1 code. - (define_attr "is_thumb1" "no,yes" (const (symbol_ref "thumb1_code"))) + (define_insn "extzv_t2" +@@ -4109,7 +4805,8 @@ + "arm_arch_thumb2" + "ubfx%?\t%0, %1, %3, %2" + [(set_attr "length" "4") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] + ) -+; We use this attribute to disable alternatives that can produce 32-bit -+; instructions inside an IT-block in Thumb2 state. ARMv8 deprecates IT blocks -+; that contain 32-bit instructions. -+(define_attr "enabled_for_depr_it" "no,yes" (const_string "yes")) -+ -+; This attribute is used to disable a predicated alternative when we have -+; arm_restrict_it. -+(define_attr "predicable_short_it" "no,yes" (const_string "yes")) -+ - ;; Operand number of an input operand that is shifted. Zero if the - ;; given instruction does not shift one of its input operands. - (define_attr "shift" "" (const_int 0)) -@@ -84,6 +93,8 @@ - (define_attr "fpu" "none,vfp" - (const (symbol_ref "arm_fpu_attr"))) -+(define_attr "predicated" "yes,no" (const_string "no")) -+ - ; LENGTH of an instruction (in bytes) - (define_attr "length" "" - (const_int 4)) -@@ -94,7 +105,7 @@ - ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without - ; arm_arch6. This attribute is used to compute attribute "enabled", - ; use type "any" to enable an alternative in all cases. --(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,onlya8,neon_onlya8,nota8,neon_nota8,iwmmxt,iwmmxt2" -+(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2" - (const_string "any")) +@@ -4121,7 +4818,8 @@ + "TARGET_IDIV" + "sdiv%?\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "insn" "sdiv")] ++ (set_attr "predicable_short_it" "no") ++ (set_attr "type" "sdiv")] + ) - (define_attr "arch_enabled" "no,yes" -@@ -129,24 +140,16 @@ - (match_test "TARGET_32BIT && !arm_arch6")) - (const_string "yes") + (define_insn "udivsi3" +@@ -4131,7 +4829,8 @@ + "TARGET_IDIV" + "udiv%?\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "insn" "udiv")] ++ (set_attr "predicable_short_it" "no") ++ (set_attr "type" "udiv")] + ) -- (and (eq_attr "arch" "onlya8") -- (eq_attr "tune" "cortexa8")) -+ (and (eq_attr "arch" "avoid_neon_for_64bits") -+ (match_test "TARGET_NEON") -+ (not (match_test "TARGET_PREFER_NEON_64BITS"))) - (const_string "yes") + +@@ -4154,12 +4853,24 @@ -- (and (eq_attr "arch" "neon_onlya8") -- (eq_attr "tune" "cortexa8") -- (match_test "TARGET_NEON")) -+ (and (eq_attr "arch" "neon_for_64bits") -+ (match_test "TARGET_NEON") -+ (match_test "TARGET_PREFER_NEON_64BITS")) - (const_string "yes") + ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). + ;; The first alternative allows the common case of a *full* overlap. +-(define_insn "*arm_negdi2" ++(define_insn_and_split "*arm_negdi2" + [(set (match_operand:DI 0 "s_register_operand" "=r,&r") + (neg:DI (match_operand:DI 1 "s_register_operand" "0,r"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0" ++ "#" ; "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0" ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (const_int 0) (match_dup 1))) ++ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))]) ++ (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[3] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ } + [(set_attr "conds" "clob") + (set_attr "length" "8")] + ) +@@ -4181,11 +4892,14 @@ + ) -- (and (eq_attr "arch" "nota8") -- (not (eq_attr "tune" "cortexa8"))) -- (const_string "yes") -- -- (and (eq_attr "arch" "neon_nota8") -- (not (eq_attr "tune" "cortexa8")) -- (match_test "TARGET_NEON")) -- (const_string "yes") -- - (and (eq_attr "arch" "iwmmxt2") - (match_test "TARGET_REALLY_IWMMXT2")) - (const_string "yes")] -@@ -179,6 +182,15 @@ - (cond [(eq_attr "insn_enabled" "no") - (const_string "no") + (define_insn "*arm_negsi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (neg:SI (match_operand:SI 1 "s_register_operand" "r")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=l,r") ++ (neg:SI (match_operand:SI 1 "s_register_operand" "l,r")))] + "TARGET_32BIT" + "rsb%?\\t%0, %1, #0" +- [(set_attr "predicable" "yes")] ++ [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "yes,no") ++ (set_attr "arch" "t2,*") ++ (set_attr "length" "4")] + ) -+ (and (eq_attr "predicable_short_it" "no") -+ (and (eq_attr "predicated" "yes") -+ (match_test "arm_restrict_it"))) -+ (const_string "no") + (define_insn "*thumb1_negsi2" +@@ -4209,6 +4923,73 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + "") + ++;; Negate an extended 32-bit value. ++(define_insn_and_split "*negdi_extendsidi" ++ [(set (match_operand:DI 0 "s_register_operand" "=r,&r,l,&l") ++ (neg:DI (sign_extend:DI (match_operand:SI 1 "s_register_operand" "0,r,0,l")))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT" ++ "#" ; rsb\\t%Q0, %1, #0\;asr\\t%R0, %Q0, #31 ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ rtx tmp = gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_MINUS (SImode, ++ const0_rtx, ++ operands[1])); ++ if (TARGET_ARM) ++ { ++ emit_insn (tmp); ++ } ++ else ++ { ++ /* Set the flags, to emit the short encoding in Thumb2. */ ++ rtx flags = gen_rtx_SET (VOIDmode, ++ gen_rtx_REG (CCmode, CC_REGNUM), ++ gen_rtx_COMPARE (CCmode, ++ const0_rtx, ++ operands[1])); ++ emit_insn (gen_rtx_PARALLEL (VOIDmode, ++ gen_rtvec (2, ++ flags, ++ tmp))); ++ } ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[2], ++ gen_rtx_ASHIFTRT (SImode, ++ operands[0], ++ GEN_INT (31)))); ++ DONE; ++ } ++ [(set_attr "length" "8,8,4,4") ++ (set_attr "arch" "a,a,t2,t2")] ++) + -+ (and (eq_attr "enabled_for_depr_it" "no") -+ (match_test "arm_restrict_it")) -+ (const_string "no") ++(define_insn_and_split "*negdi_zero_extendsidi" ++ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") ++ (neg:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r")))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT" ++ "#" ; "rsbs\\t%Q0, %1, #0\;sbc\\t%R0,%R0,%R0" ++ ;; Don't care what register is input to sbc, ++ ;; since we just just need to propagate the carry. ++ "&& reload_completed" ++ [(parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (const_int 0) (match_dup 1))) ++ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))]) ++ (set (match_dup 2) (minus:SI (minus:SI (match_dup 2) (match_dup 2)) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] ++ { ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ } ++ [(set_attr "conds" "clob") ++ (set_attr "length" "8")] ;; length in thumb is 4 ++) + - (eq_attr "arch_enabled" "no") - (const_string "no") + ;; abssi2 doesn't really clobber the condition codes if a different register + ;; is being set. To keep things simple, assume during rtl manipulations that + ;; it does, but tell the final scan operator the truth. Similarly for +@@ -4227,14 +5008,67 @@ + operands[2] = gen_rtx_REG (CCmode, CC_REGNUM); + ") -@@ -296,6 +308,8 @@ - f_2_r,\ - r_2_f,\ - f_cvt,\ -+ f_sels,\ -+ f_seld,\ - branch,\ - call,\ - load_byte,\ -@@ -502,7 +516,7 @@ +-(define_insn "*arm_abssi2" ++(define_insn_and_split "*arm_abssi2" + [(set (match_operand:SI 0 "s_register_operand" "=r,&r") + (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "@ +- cmp\\t%0, #0\;rsblt\\t%0, %0, #0 +- eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ /* if (which_alternative == 0) */ ++ if (REGNO(operands[0]) == REGNO(operands[1])) ++ { ++ /* Emit the pattern: ++ cmp\\t%0, #0\;rsblt\\t%0, %0, #0 ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 0) (const_int 0))) ++ (cond_exec (lt:CC (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1))))] ++ */ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ gen_rtx_REG (CCmode, CC_REGNUM), ++ gen_rtx_COMPARE (CCmode, operands[0], const0_rtx))); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ (gen_rtx_LT (SImode, ++ gen_rtx_REG (CCmode, CC_REGNUM), ++ const0_rtx)), ++ (gen_rtx_SET (VOIDmode, ++ operands[0], ++ (gen_rtx_MINUS (SImode, ++ const0_rtx, ++ operands[1])))))); ++ DONE; ++ } ++ else ++ { ++ /* Emit the pattern: ++ alt1: eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31 ++ [(set (match_dup 0) ++ (xor:SI (match_dup 1) ++ (ashiftrt:SI (match_dup 1) (const_int 31)))) ++ (set (match_dup 0) ++ (minus:SI (match_dup 0) ++ (ashiftrt:SI (match_dup 1) (const_int 31))))] ++ */ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_XOR (SImode, ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31)), ++ operands[1]))); ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_MINUS (SImode, ++ operands[0], ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31))))); ++ DONE; ++ } ++ } + [(set_attr "conds" "clob,*") + (set_attr "shift" "1") + (set_attr "predicable" "no, yes") +@@ -4255,14 +5089,56 @@ + [(set_attr "length" "6")] + ) - (define_attr "generic_sched" "yes,no" - (const (if_then_else -- (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexm4,marvell_pj4") -+ (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexa53,cortexm4,marvell_pj4") - (eq_attr "tune_cortexr4" "yes")) - (const_string "no") - (const_string "yes")))) -@@ -510,7 +524,7 @@ - (define_attr "generic_vfp" "yes,no" - (const (if_then_else - (and (eq_attr "fpu" "vfp") -- (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexm4,marvell_pj4") -+ (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexa53,cortexm4,marvell_pj4") - (eq_attr "tune_cortexr4" "no")) - (const_string "yes") - (const_string "no")))) -@@ -531,6 +545,7 @@ - (include "cortex-a8.md") - (include "cortex-a9.md") - (include "cortex-a15.md") -+(include "cortex-a53.md") - (include "cortex-r4.md") - (include "cortex-r4f.md") - (include "cortex-m4.md") -@@ -844,7 +859,7 @@ +-(define_insn "*arm_neg_abssi2" ++(define_insn_and_split "*arm_neg_abssi2" + [(set (match_operand:SI 0 "s_register_operand" "=r,&r") + (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "@ +- cmp\\t%0, #0\;rsbgt\\t%0, %0, #0 +- eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++ { ++ /* if (which_alternative == 0) */ ++ if (REGNO (operands[0]) == REGNO (operands[1])) ++ { ++ /* Emit the pattern: ++ cmp\\t%0, #0\;rsbgt\\t%0, %0, #0 ++ */ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ gen_rtx_REG (CCmode, CC_REGNUM), ++ gen_rtx_COMPARE (CCmode, operands[0], const0_rtx))); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ gen_rtx_GT (SImode, ++ gen_rtx_REG (CCmode, CC_REGNUM), ++ const0_rtx), ++ gen_rtx_SET (VOIDmode, ++ operands[0], ++ (gen_rtx_MINUS (SImode, ++ const0_rtx, ++ operands[1]))))); ++ } ++ else ++ { ++ /* Emit the pattern: ++ eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31 ++ */ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_XOR (SImode, ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31)), ++ operands[1]))); ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_MINUS (SImode, ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31)), ++ operands[0]))); ++ } ++ DONE; ++ } + [(set_attr "conds" "clob,*") + (set_attr "shift" "1") + (set_attr "predicable" "no, yes") +@@ -4330,7 +5206,7 @@ + [(set_attr "length" "*,8,8,*") + (set_attr "predicable" "no,yes,yes,no") + (set_attr "neon_type" "neon_int_1,*,*,neon_int_1") +- (set_attr "arch" "neon_nota8,*,*,neon_onlya8")] ++ (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] + ) - ;; This is the canonicalization of addsi3_compare0_for_combiner when the - ;; addend is a constant. --(define_insn "*cmpsi2_addneg" -+(define_insn "cmpsi2_addneg" - [(set (reg:CC CC_REGNUM) - (compare:CC - (match_operand:SI 1 "s_register_operand" "r,r") -@@ -975,7 +990,8 @@ - "@ - adc%?\\t%0, %1, %2 - sbc%?\\t%0, %1, #%B2" -- [(set_attr "conds" "use")] -+ [(set_attr "conds" "use") -+ (set_attr "predicable" "yes")] + (define_expand "one_cmplsi2" +@@ -4341,12 +5217,15 @@ ) - (define_insn "*addsi3_carryin_alt2_" -@@ -987,7 +1003,8 @@ - "@ - adc%?\\t%0, %1, %2 - sbc%?\\t%0, %1, #%B2" -- [(set_attr "conds" "use")] -+ [(set_attr "conds" "use") -+ (set_attr "predicable" "yes")] + (define_insn "*arm_one_cmplsi2" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (not:SI (match_operand:SI 1 "s_register_operand" "r")))] ++ [(set (match_operand:SI 0 "s_register_operand" "=l,r") ++ (not:SI (match_operand:SI 1 "s_register_operand" "l,r")))] + "TARGET_32BIT" + "mvn%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "insn" "mvn")] ++ (set_attr "predicable_short_it" "yes,no") ++ (set_attr "arch" "t2,*") ++ (set_attr "length" "4") ++ (set_attr "type" "mvn_reg")] ) - (define_insn "*addsi3_carryin_shift_" -@@ -1001,6 +1018,7 @@ + (define_insn "*thumb1_one_cmplsi2" +@@ -4355,7 +5234,7 @@ + "TARGET_THUMB1" + "mvn\\t%0, %1" + [(set_attr "length" "2") +- (set_attr "insn" "mvn")] ++ (set_attr "type" "mvn_reg")] + ) + + (define_insn "*notsi_compare0" +@@ -4367,7 +5246,7 @@ "TARGET_32BIT" - "adc%?\\t%0, %1, %3%S2" - [(set_attr "conds" "use") -+ (set_attr "predicable" "yes") - (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "alu_shift") - (const_string "alu_shift_reg")))] -@@ -1017,26 +1035,88 @@ - [(set_attr "conds" "set")] + "mvn%.\\t%0, %1" + [(set_attr "conds" "set") +- (set_attr "insn" "mvn")] ++ (set_attr "type" "mvn_reg")] + ) + + (define_insn "*notsi_compare0_scratch" +@@ -4378,7 +5257,7 @@ + "TARGET_32BIT" + "mvn%.\\t%0, %1" + [(set_attr "conds" "set") +- (set_attr "insn" "mvn")] ++ (set_attr "type" "mvn_reg")] + ) + + ;; Fixed <--> Floating conversion insns +@@ -4498,7 +5377,7 @@ + "TARGET_32BIT " + "#" + [(set_attr "length" "8,4,8,8") +- (set_attr "arch" "neon_nota8,*,*,neon_onlya8") ++ (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits") + (set_attr "ce_count" "2") + (set_attr "predicable" "yes")] + ) +@@ -4513,7 +5392,7 @@ + (set_attr "ce_count" "2") + (set_attr "shift" "1") + (set_attr "predicable" "yes") +- (set_attr "arch" "neon_nota8,*,a,t,neon_onlya8")] ++ (set_attr "arch" "neon_for_64bits,*,a,t,avoid_neon_for_64bits")] + ) + + ;; Splits for all extensions to DImode +@@ -4639,7 +5518,7 @@ + [(if_then_else (eq_attr "is_arch6" "yes") + (const_int 2) (const_int 4)) + (const_int 4)]) +- (set_attr "type" "simple_alu_shift, load_byte")] ++ (set_attr "type" "extend,load_byte")] ) --(define_expand "incscc" -+(define_insn "*subsi3_carryin" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") -- (plus:SI (match_operator:SI 2 "arm_comparison_operator" -- [(match_operand:CC 3 "cc_register" "") (const_int 0)]) -- (match_operand:SI 1 "s_register_operand" "0,?r")))] -+ (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I") -+ (match_operand:SI 2 "s_register_operand" "r,r")) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] - "TARGET_32BIT" -- "" -+ "@ -+ sbc%?\\t%0, %1, %2 -+ rsc%?\\t%0, %2, %1" -+ [(set_attr "conds" "use") -+ (set_attr "arch" "*,a") -+ (set_attr "predicable" "yes")] + (define_insn "*arm_zero_extendhisi2" +@@ -4649,7 +5528,7 @@ + "@ + # + ldr%(h%)\\t%0, %1" +- [(set_attr "type" "alu_shift,load_byte") ++ [(set_attr "type" "arlo_shift,load_byte") + (set_attr "predicable" "yes")] ) --(define_insn "*arm_incscc" -- [(set (match_operand:SI 0 "s_register_operand" "=r,r") -- (plus:SI (match_operator:SI 2 "arm_comparison_operator" -- [(match_operand:CC 3 "cc_register" "") (const_int 0)]) -- (match_operand:SI 1 "s_register_operand" "0,?r")))] -+(define_insn "*subsi3_carryin_const" -+ [(set (match_operand:SI 0 "s_register_operand" "=r") -+ (minus:SI (plus:SI (match_operand:SI 1 "reg_or_int_operand" "r") -+ (match_operand:SI 2 "arm_not_operand" "K")) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ "TARGET_32BIT" -+ "sbc\\t%0, %1, #%B2" -+ [(set_attr "conds" "use")] -+) -+ -+(define_insn "*subsi3_carryin_compare" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_operand:SI 1 "s_register_operand" "r") -+ (match_operand:SI 2 "s_register_operand" "r"))) -+ (set (match_operand:SI 0 "s_register_operand" "=r") -+ (minus:SI (minus:SI (match_dup 1) -+ (match_dup 2)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ "TARGET_32BIT" -+ "sbcs\\t%0, %1, %2" -+ [(set_attr "conds" "set")] -+) -+ -+(define_insn "*subsi3_carryin_compare_const" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r") -+ (match_operand:SI 2 "arm_not_operand" "K"))) -+ (set (match_operand:SI 0 "s_register_operand" "=r") -+ (minus:SI (plus:SI (match_dup 1) -+ (match_dup 2)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ "TARGET_32BIT" -+ "sbcs\\t%0, %1, #%B2" -+ [(set_attr "conds" "set")] -+) -+ -+(define_insn "*subsi3_carryin_shift" -+ [(set (match_operand:SI 0 "s_register_operand" "=r") -+ (minus:SI (minus:SI -+ (match_operand:SI 1 "s_register_operand" "r") -+ (match_operator:SI 2 "shift_operator" -+ [(match_operand:SI 3 "s_register_operand" "r") -+ (match_operand:SI 4 "reg_or_int_operand" "rM")])) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ "TARGET_32BIT" -+ "sbc%?\\t%0, %1, %3%S2" -+ [(set_attr "conds" "use") -+ (set_attr "predicable" "yes") -+ (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") -+ (const_string "alu_shift") -+ (const_string "alu_shift_reg")))] -+) -+ -+(define_insn "*rsbsi3_carryin_shift" -+ [(set (match_operand:SI 0 "s_register_operand" "=r") -+ (minus:SI (minus:SI -+ (match_operator:SI 2 "shift_operator" -+ [(match_operand:SI 3 "s_register_operand" "r") -+ (match_operand:SI 4 "reg_or_int_operand" "rM")]) -+ (match_operand:SI 1 "s_register_operand" "r")) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] - "TARGET_ARM" -- "@ -- add%d2\\t%0, %1, #1 -- mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1" -+ "rsc%?\\t%0, %1, %3%S2" - [(set_attr "conds" "use") -- (set_attr "length" "4,8")] +@@ -4661,7 +5540,7 @@ + uxth%?\\t%0, %1 + ldr%(h%)\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "type" "simple_alu_shift,load_byte")] ++ (set_attr "type" "extend,load_byte")] + ) + + (define_insn "*arm_zero_extendhisi2addsi" +@@ -4670,8 +5549,9 @@ + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "uxtah%?\\t%0, %2, %1" +- [(set_attr "type" "alu_shift") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "arlo_shift") + (set_attr "predicable" "yes") -+ (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") -+ (const_string "alu_shift") -+ (const_string "alu_shift_reg")))] ++ (set_attr "predicable_short_it" "no")] ) - ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. -@@ -1087,13 +1167,27 @@ - " + (define_expand "zero_extendqisi2" +@@ -4719,7 +5599,7 @@ + # + ldrb\\t%0, %1" + [(set_attr "length" "4,2") +- (set_attr "type" "alu_shift,load_byte") ++ (set_attr "type" "arlo_shift,load_byte") + (set_attr "pool_range" "*,32")] + ) + +@@ -4731,7 +5611,7 @@ + uxtb\\t%0, %1 + ldrb\\t%0, %1" + [(set_attr "length" "2") +- (set_attr "type" "simple_alu_shift,load_byte")] ++ (set_attr "type" "extend,load_byte")] + ) + + (define_insn "*arm_zero_extendqisi2" +@@ -4742,7 +5622,7 @@ + # + ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" + [(set_attr "length" "8,4") +- (set_attr "type" "alu_shift,load_byte") ++ (set_attr "type" "arlo_shift,load_byte") + (set_attr "predicable" "yes")] ) --(define_insn "*arm_subdi3" -+(define_insn_and_split "*arm_subdi3" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r") - (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") - (match_operand:DI 2 "s_register_operand" "r,0,0"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT && !TARGET_NEON" -- "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" -+ "#" ; "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) -+ (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[3] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[2]); -+ operands[2] = gen_lowpart (SImode, operands[2]); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] +@@ -4753,7 +5633,7 @@ + "@ + uxtb%(%)\\t%0, %1 + ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" +- [(set_attr "type" "simple_alu_shift,load_byte") ++ [(set_attr "type" "extend,load_byte") + (set_attr "predicable" "yes")] ) -@@ -1108,55 +1202,113 @@ - [(set_attr "length" "4")] + +@@ -4764,8 +5644,8 @@ + "TARGET_INT_SIMD" + "uxtab%?\\t%0, %2, %1" + [(set_attr "predicable" "yes") +- (set_attr "insn" "xtab") +- (set_attr "type" "alu_shift")] ++ (set_attr "predicable_short_it" "no") ++ (set_attr "type" "arlo_shift")] ) --(define_insn "*subdi_di_zesidi" -+(define_insn_and_split "*subdi_di_zesidi" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") - (minus:DI (match_operand:DI 1 "s_register_operand" "0,r") - (zero_extend:DI - (match_operand:SI 2 "s_register_operand" "r,r")))) - (clobber (reg:CC CC_REGNUM))] + (define_split +@@ -4816,7 +5696,8 @@ "TARGET_32BIT" -- "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0" -+ "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) -+ (set (match_dup 3) (minus:SI (plus:SI (match_dup 4) (match_dup 5)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[3] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ operands[5] = GEN_INT (~0); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] + "tst%?\\t%0, #255" + [(set_attr "conds" "set") +- (set_attr "predicable" "yes")] ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] ) --(define_insn "*subdi_di_sesidi" -+(define_insn_and_split "*subdi_di_sesidi" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") - (minus:DI (match_operand:DI 1 "s_register_operand" "0,r") - (sign_extend:DI - (match_operand:SI 2 "s_register_operand" "r,r")))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT" -- "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31" -+ "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) -+ (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31))) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[3] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] + (define_expand "extendhisi2" +@@ -4927,7 +5808,7 @@ + [(if_then_else (eq_attr "is_arch6" "yes") + (const_int 2) (const_int 4)) + (const_int 4)]) +- (set_attr "type" "simple_alu_shift,load_byte") ++ (set_attr "type" "extend,load_byte") + (set_attr "pool_range" "*,1018")] + ) + +@@ -4986,7 +5867,7 @@ + # + ldr%(sh%)\\t%0, %1" + [(set_attr "length" "8,4") +- (set_attr "type" "alu_shift,load_byte") ++ (set_attr "type" "arlo_shift,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] +@@ -5000,8 +5881,9 @@ + "@ + sxth%?\\t%0, %1 + ldr%(sh%)\\t%0, %1" +- [(set_attr "type" "simple_alu_shift,load_byte") ++ [(set_attr "type" "extend,load_byte") + (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] + ) +@@ -5086,7 +5968,7 @@ + # + ldr%(sb%)\\t%0, %1" + [(set_attr "length" "8,4") +- (set_attr "type" "alu_shift,load_byte") ++ (set_attr "type" "arlo_shift,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] +@@ -5100,7 +5982,7 @@ + "@ + sxtb%?\\t%0, %1 + ldr%(sb%)\\t%0, %1" +- [(set_attr "type" "simple_alu_shift,load_byte") ++ [(set_attr "type" "extend,load_byte") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,256") + (set_attr "neg_pool_range" "*,244")] +@@ -5112,9 +5994,9 @@ + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_INT_SIMD" + "sxtab%?\\t%0, %2, %1" +- [(set_attr "type" "alu_shift") +- (set_attr "insn" "xtab") +- (set_attr "predicable" "yes")] ++ [(set_attr "type" "arlo_shift") ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")] ) --(define_insn "*subdi_zesidi_di" -+(define_insn_and_split "*subdi_zesidi_di" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") - (minus:DI (zero_extend:DI - (match_operand:SI 2 "s_register_operand" "r,r")) - (match_operand:DI 1 "s_register_operand" "0,r"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" -- "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0" -+ "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0" -+ ; is equivalent to: -+ ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, #0" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 2) (match_dup 1))) -+ (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))]) -+ (set (match_dup 3) (minus:SI (minus:SI (const_int 0) (match_dup 4)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[3] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] + (define_split +@@ -5213,7 +6095,7 @@ + (const_int 2) + (if_then_else (eq_attr "is_arch6" "yes") + (const_int 4) (const_int 6))]) +- (set_attr "type" "simple_alu_shift,load_byte,load_byte")] ++ (set_attr "type" "extend,load_byte,load_byte")] ) --(define_insn "*subdi_sesidi_di" -+(define_insn_and_split "*subdi_sesidi_di" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") - (minus:DI (sign_extend:DI - (match_operand:SI 2 "s_register_operand" "r,r")) - (match_operand:DI 1 "s_register_operand" "0,r"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" -- "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31" -+ "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31" -+ ; is equivalent to: -+ ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, %2, asr #31" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 2) (match_dup 1))) -+ (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))]) -+ (set (match_dup 3) (minus:SI (minus:SI -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31)) -+ (match_dup 4)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[3] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] + (define_expand "extendsfdf2" +@@ -5313,8 +6195,8 @@ + ) + + (define_insn "*arm_movdi" +- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") +- (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] ++ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, q, m") ++ (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,q"))] + "TARGET_32BIT + && !(TARGET_HARD_FLOAT && TARGET_VFP) + && !TARGET_IWMMXT +@@ -5472,8 +6354,7 @@ + } + }" + [(set_attr "length" "4,4,6,2,2,6,4,4") +- (set_attr "type" "*,*,*,load2,store2,load2,store2,*") +- (set_attr "insn" "*,mov,*,*,*,*,*,mov") ++ (set_attr "type" "*,mov_reg,*,load2,store2,load2,store2,mov_reg") + (set_attr "pool_range" "*,*,*,*,*,1018,*,*")] ) --(define_insn "*subdi_zesidi_zesidi" -+(define_insn_and_split "*subdi_zesidi_zesidi" - [(set (match_operand:DI 0 "s_register_operand" "=r") - (minus:DI (zero_extend:DI - (match_operand:SI 1 "s_register_operand" "r")) -@@ -1164,7 +1316,17 @@ - (match_operand:SI 2 "s_register_operand" "r")))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT" -- "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1" -+ "#" ; "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) -+ (set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 1)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[3] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] +@@ -5570,6 +6451,7 @@ + "arm_arch_thumb2" + "movt%?\t%0, #:upper16:%c2" + [(set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no") + (set_attr "length" "4")] ) -@@ -1254,7 +1416,7 @@ - (set_attr "type" "simple_alu_imm,*,*")] + +@@ -5587,8 +6469,7 @@ + movw%?\\t%0, %1 + ldr%?\\t%0, %1 + str%?\\t%1, %0" +- [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1,store1") +- (set_attr "insn" "mov,mov,mvn,mov,*,*") ++ [(set_attr "type" "mov_reg,mov_imm,mvn_imm,mov_imm,load1,store1") + (set_attr "predicable" "yes") + (set_attr "pool_range" "*,*,*,*,4096,*") + (set_attr "neg_pool_range" "*,*,*,*,4084,*")] +@@ -5890,7 +6771,7 @@ + cmp%?\\t%0, #0 + sub%.\\t%0, %1, #0" + [(set_attr "conds" "set") +- (set_attr "type" "simple_alu_imm,simple_alu_imm")] ++ (set_attr "type" "arlo_imm,arlo_imm")] ) --(define_insn "*subsi3_compare" -+(define_insn "subsi3_compare" - [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,r,I") - (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))) -@@ -1269,29 +1431,6 @@ - (set_attr "type" "simple_alu_imm,*,*")] + ;; Subroutine to store a half word from a register into memory. +@@ -6304,14 +7185,13 @@ + str%(h%)\\t%1, %0\\t%@ movhi + ldr%(h%)\\t%0, %1\\t%@ movhi" + [(set_attr "predicable" "yes") +- (set_attr "insn" "mov,mvn,*,*") + (set_attr "pool_range" "*,*,*,256") + (set_attr "neg_pool_range" "*,*,*,244") + (set_attr_alternative "type" + [(if_then_else (match_operand 1 "const_int_operand" "") +- (const_string "simple_alu_imm" ) +- (const_string "*")) +- (const_string "simple_alu_imm") ++ (const_string "mov_imm" ) ++ (const_string "mov_reg")) ++ (const_string "mvn_imm") + (const_string "store1") + (const_string "load1")])] + ) +@@ -6325,8 +7205,7 @@ + mov%?\\t%0, %1\\t%@ movhi + mvn%?\\t%0, #%B1\\t%@ movhi" + [(set_attr "predicable" "yes") +- (set_attr "insn" "mov, mov,mvn") +- (set_attr "type" "simple_alu_imm,*,simple_alu_imm")] ++ (set_attr "type" "mov_imm,mov_reg,mvn_imm")] + ) + + (define_expand "thumb_movhi_clobber" +@@ -6449,26 +7328,27 @@ + " ) --(define_expand "decscc" -- [(set (match_operand:SI 0 "s_register_operand" "=r,r") -- (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") -- (match_operator:SI 2 "arm_comparison_operator" -- [(match_operand 3 "cc_register" "") (const_int 0)])))] -- "TARGET_32BIT" -- "" --) -- --(define_insn "*arm_decscc" -- [(set (match_operand:SI 0 "s_register_operand" "=r,r") -- (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") -- (match_operator:SI 2 "arm_comparison_operator" -- [(match_operand 3 "cc_register" "") (const_int 0)])))] -- "TARGET_ARM" -- "@ -- sub%d2\\t%0, %1, #1 -- mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1" -- [(set_attr "conds" "use") -- (set_attr "length" "*,8") -- (set_attr "type" "simple_alu_imm,*")] --) - - (define_expand "subsf3" - [(set (match_operand:SF 0 "s_register_operand" "") - (minus:SF (match_operand:SF 1 "s_register_operand" "") -@@ -2024,13 +2163,49 @@ - "" + (define_insn "*arm_movqi_insn" +- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,Uu,r,m") +- (match_operand:QI 1 "general_operand" "r,I,K,Uu,l,m,r"))] ++ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m") ++ (match_operand:QI 1 "general_operand" "r,r,I,Py,K,Uu,l,m,r"))] + "TARGET_32BIT + && ( register_operand (operands[0], QImode) + || register_operand (operands[1], QImode))" + "@ + mov%?\\t%0, %1 + mov%?\\t%0, %1 ++ mov%?\\t%0, %1 ++ mov%?\\t%0, %1 + mvn%?\\t%0, #%B1 + ldr%(b%)\\t%0, %1 + str%(b%)\\t%1, %0 + ldr%(b%)\\t%0, %1 + str%(b%)\\t%1, %0" +- [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,load1, store1, load1, store1") +- (set_attr "insn" "mov,mov,mvn,*,*,*,*") ++ [(set_attr "type" "mov_reg,mov_reg,mov_imm,mov_imm,mvn_imm,load1,store1,load1,store1") + (set_attr "predicable" "yes") +- (set_attr "arch" "any,any,any,t2,t2,any,any") +- (set_attr "length" "4,4,4,2,2,4,4")] ++ (set_attr "predicable_short_it" "yes,yes,yes,no,no,no,no,no,no") ++ (set_attr "arch" "t2,any,any,t2,any,t2,t2,any,any") ++ (set_attr "length" "2,4,4,2,4,2,2,4,4")] + ) + + (define_insn "*thumb1_movqi_insn" +@@ -6485,8 +7365,7 @@ + mov\\t%0, %1 + mov\\t%0, %1" + [(set_attr "length" "2") +- (set_attr "type" "simple_alu_imm,load1,store1,*,*,simple_alu_imm") +- (set_attr "insn" "*,*,*,mov,mov,mov") ++ (set_attr "type" "arlo_imm,load1,store1,mov_reg,mov_imm,mov_imm") + (set_attr "pool_range" "*,32,*,*,*,*") + (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")]) + +@@ -6515,7 +7394,7 @@ + (define_insn "*arm32_movhf" + [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r") + (match_operand:HF 1 "general_operand" " m,r,r,F"))] +- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16) ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16) && !arm_restrict_it + && ( s_register_operand (operands[0], HFmode) + || s_register_operand (operands[1], HFmode))" + "* +@@ -6551,8 +7430,7 @@ + } + " + [(set_attr "conds" "unconditional") +- (set_attr "type" "load1,store1,*,*") +- (set_attr "insn" "*,*,mov,mov") ++ (set_attr "type" "load1,store1,mov_reg,mov_reg") + (set_attr "length" "4,4,4,8") + (set_attr "predicable" "yes")] + ) +@@ -6587,8 +7465,7 @@ + } + " + [(set_attr "length" "2") +- (set_attr "type" "*,load1,store1,*,*") +- (set_attr "insn" "mov,*,*,mov,mov") ++ (set_attr "type" "mov_reg,load1,store1,mov_reg,mov_reg") + (set_attr "pool_range" "*,1018,*,*,*") + (set_attr "conds" "clob,nocond,nocond,nocond,nocond")]) + +@@ -6642,8 +7519,8 @@ + ldr%?\\t%0, %1\\t%@ float + str%?\\t%1, %0\\t%@ float" + [(set_attr "predicable" "yes") +- (set_attr "type" "*,load1,store1") +- (set_attr "insn" "mov,*,*") ++ (set_attr "predicable_short_it" "no") ++ (set_attr "type" "mov_reg,load1,store1") + (set_attr "arm_pool_range" "*,4096,*") + (set_attr "thumb2_pool_range" "*,4094,*") + (set_attr "arm_neg_pool_range" "*,4084,*") +@@ -6666,9 +7543,8 @@ + mov\\t%0, %1 + mov\\t%0, %1" + [(set_attr "length" "2") +- (set_attr "type" "*,load1,store1,load1,store1,*,*") ++ (set_attr "type" "*,load1,store1,load1,store1,mov_reg,mov_reg") + (set_attr "pool_range" "*,*,*,1018,*,*,*") +- (set_attr "insn" "*,*,*,*,*,mov,mov") + (set_attr "conds" "clob,nocond,nocond,nocond,nocond,nocond,nocond")] ) --(define_insn "*anddi3_insn" -- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") -- (and:DI (match_operand:DI 1 "s_register_operand" "%0,r") -- (match_operand:DI 2 "s_register_operand" "r,r")))] -- "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" -- "#" -- [(set_attr "length" "8")] -+(define_insn_and_split "*anddi3_insn" -+ [(set (match_operand:DI 0 "s_register_operand" "=w,w ,&r,&r,&r,&r,?w,?w") -+ (and:DI (match_operand:DI 1 "s_register_operand" "%w,0 ,0 ,r ,0 ,r ,w ,0") -+ (match_operand:DI 2 "arm_anddi_operand_neon" "w ,DL,r ,r ,De,De,w ,DL")))] -+ "TARGET_32BIT && !TARGET_IWMMXT" -+{ -+ switch (which_alternative) -+ { -+ case 0: /* fall through */ -+ case 6: return "vand\t%P0, %P1, %P2"; -+ case 1: /* fall through */ -+ case 7: return neon_output_logic_immediate ("vand", &operands[2], -+ DImode, 1, VALID_NEON_QREG_MODE (DImode)); -+ case 2: -+ case 3: -+ case 4: -+ case 5: /* fall through */ -+ return "#"; -+ default: gcc_unreachable (); -+ } -+} -+ "TARGET_32BIT && !TARGET_IWMMXT && reload_completed -+ && !(IS_VFP_REGNUM (REGNO (operands[0])))" -+ [(set (match_dup 3) (match_dup 4)) -+ (set (match_dup 5) (match_dup 6))] -+ " -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ -+ operands[4] = simplify_gen_binary (AND, SImode, -+ gen_lowpart (SImode, operands[1]), -+ gen_lowpart (SImode, operands[2])); -+ operands[6] = simplify_gen_binary (AND, SImode, -+ gen_highpart (SImode, operands[1]), -+ gen_highpart_mode (SImode, DImode, operands[2])); +@@ -6738,8 +7614,8 @@ + ) + + (define_insn "*movdf_soft_insn" +- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m") +- (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))] ++ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,q,m") ++ (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,q"))] + "TARGET_32BIT && TARGET_SOFT_FLOAT + && ( register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" +@@ -6799,8 +7675,7 @@ + } + " + [(set_attr "length" "4,2,2,6,4,4") +- (set_attr "type" "*,load2,store2,load2,store2,*") +- (set_attr "insn" "*,*,*,*,*,mov") ++ (set_attr "type" "*,load2,store2,load2,store2,mov_reg") + (set_attr "pool_range" "*,*,*,1018,*,*")] + ) + +@@ -6869,10 +7744,18 @@ + (match_operand:BLK 1 "general_operand" "") + (match_operand:SI 2 "const_int_operand" "") + (match_operand:SI 3 "const_int_operand" "")] +- "TARGET_EITHER" ++ "" + " + if (TARGET_32BIT) + { ++ if (TARGET_LDRD && current_tune->prefer_ldrd_strd ++ && !optimize_function_for_size_p (cfun)) ++ { ++ if (gen_movmem_ldrd_strd (operands)) ++ DONE; ++ FAIL; ++ } + -+ }" -+ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1") -+ (set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*, -+ avoid_neon_for_64bits,avoid_neon_for_64bits") -+ (set_attr "length" "*,*,8,8,8,8,*,*") -+ ] + if (arm_gen_movmemqi (operands)) + DONE; + FAIL; +@@ -7568,7 +8451,7 @@ + (set_attr "arch" "t2,t2,any,any") + (set_attr "length" "2,2,4,4") + (set_attr "predicable" "yes") +- (set_attr "type" "*,*,*,simple_alu_imm")] ++ (set_attr "type" "*,*,*,arlo_imm")] ) - (define_insn_and_split "*anddi_zesidi_di" -@@ -3096,13 +3271,17 @@ - "" + (define_insn "*cmpsi_shiftsi" +@@ -7582,7 +8465,7 @@ + [(set_attr "conds" "set") + (set_attr "shift" "1") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "arlo_shift,arlo_shift_reg")]) + + (define_insn "*cmpsi_shiftsi_swp" + [(set (reg:CC_SWP CC_REGNUM) +@@ -7595,7 +8478,7 @@ + [(set_attr "conds" "set") + (set_attr "shift" "1") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "arlo_shift,arlo_shift_reg")]) + + (define_insn "*arm_cmpsi_negshiftsi_si" + [(set (reg:CC_Z CC_REGNUM) +@@ -7608,8 +8491,8 @@ + "cmn%?\\t%0, %2%S1" + [(set_attr "conds" "set") + (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg"))) ++ (const_string "arlo_shift") ++ (const_string "arlo_shift_reg"))) + (set_attr "predicable" "yes")] ) --(define_insn "*andsi_iorsi3_notsi" -+(define_insn_and_split "*andsi_iorsi3_notsi" - [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") - (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r") - (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")) - (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))] +@@ -7617,25 +8500,69 @@ + ;; if-conversion can not reduce to a conditional compare, so we do + ;; that directly. + +-(define_insn "*arm_cmpdi_insn" ++(define_insn_and_split "*arm_cmpdi_insn" + [(set (reg:CC_NCV CC_REGNUM) + (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r") + (match_operand:DI 1 "arm_di_operand" "rDi"))) + (clobber (match_scratch:SI 2 "=r"))] "TARGET_32BIT" -- "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3" -+ "#" ; "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3" +- "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1" ++ "#" ; "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1" + "&& reload_completed" -+ [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 0)))] -+ "" - [(set_attr "length" "8") - (set_attr "ce_count" "2") - (set_attr "predicable" "yes")] -@@ -3253,15 +3432,23 @@ - [(set_attr "predicable" "yes")] ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 0) (match_dup 1))) ++ (parallel [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 3) (match_dup 4))) ++ (set (match_dup 2) ++ (minus:SI (match_dup 5) ++ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])] ++ { ++ operands[3] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ if (CONST_INT_P (operands[1])) ++ { ++ operands[4] = GEN_INT (~INTVAL (gen_highpart_mode (SImode, ++ DImode, ++ operands[1]))); ++ operands[5] = gen_rtx_PLUS (SImode, operands[3], operands[4]); ++ } ++ else ++ { ++ operands[4] = gen_highpart (SImode, operands[1]); ++ operands[5] = gen_rtx_MINUS (SImode, operands[3], operands[4]); ++ } ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ operands[2] = gen_lowpart (SImode, operands[2]); ++ } + [(set_attr "conds" "set") + (set_attr "length" "8")] ) --(define_insn "*arm_smax_insn" -+(define_insn_and_split "*arm_smax_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r") - (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" -- "@ -- cmp\\t%1, %2\;movlt\\t%0, %2 -- cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2" -+ "#" -+ ; cmp\\t%1, %2\;movlt\\t%0, %2 -+ ; cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2" -+ "TARGET_ARM" +-(define_insn "*arm_cmpdi_unsigned" ++(define_insn_and_split "*arm_cmpdi_unsigned" + [(set (reg:CC_CZ CC_REGNUM) +- (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r") +- (match_operand:DI 1 "arm_di_operand" "rDi")))] ++ (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "l,r,r") ++ (match_operand:DI 1 "arm_di_operand" "Py,r,rDi")))] ++ + "TARGET_32BIT" +- "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1" ++ "#" ; "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1" ++ "&& reload_completed" + [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) -+ (if_then_else:SI (ge:SI (reg:CC CC_REGNUM) (const_int 0)) -+ (match_dup 1) -+ (match_dup 2)))] -+ "" - [(set_attr "conds" "clob") - (set_attr "length" "8,12")] ++ (compare:CC (match_dup 2) (match_dup 3))) ++ (cond_exec (eq:SI (reg:CC CC_REGNUM) (const_int 0)) ++ (set (reg:CC CC_REGNUM) ++ (compare:CC (match_dup 0) (match_dup 1))))] ++ { ++ operands[2] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ if (CONST_INT_P (operands[1])) ++ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); ++ else ++ operands[3] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ } + [(set_attr "conds" "set") +- (set_attr "length" "8")] ++ (set_attr "enabled_for_depr_it" "yes,yes,no") ++ (set_attr "arch" "t2,t2,*") ++ (set_attr "length" "6,6,8")] ) -@@ -3293,15 +3480,23 @@ - [(set_attr "predicable" "yes")] + + (define_insn "*arm_cmpdi_zero" +@@ -7758,36 +8685,56 @@ + operands[3] = const0_rtx;" ) --(define_insn "*arm_smin_insn" -+(define_insn_and_split "*arm_smin_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r") - (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) - (clobber (reg:CC CC_REGNUM))] +-(define_insn "*mov_scc" ++(define_insn_and_split "*mov_scc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]))] "TARGET_ARM" -- "@ -- cmp\\t%1, %2\;movge\\t%0, %2 -- cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2" -+ "#" -+ ; cmp\\t%1, %2\;movge\\t%0, %2 -+ ; cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2" +- "mov%D1\\t%0, #0\;mov%d1\\t%0, #1" ++ "#" ; "mov%D1\\t%0, #0\;mov%d1\\t%0, #1" + "TARGET_ARM" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) -+ (if_then_else:SI (lt:SI (reg:CC CC_REGNUM) (const_int 0)) -+ (match_dup 1) -+ (match_dup 2)))] ++ [(set (match_dup 0) ++ (if_then_else:SI (match_dup 1) ++ (const_int 1) ++ (const_int 0)))] + "" - [(set_attr "conds" "clob") - (set_attr "length" "8,12")] - ) -@@ -3316,16 +3511,24 @@ - "" + [(set_attr "conds" "use") +- (set_attr "insn" "mov") + (set_attr "length" "8")] ) --(define_insn "*arm_umaxsi3" -+(define_insn_and_split "*arm_umaxsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") - (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) - (clobber (reg:CC CC_REGNUM))] +-(define_insn "*mov_negscc" ++(define_insn_and_split "*mov_negscc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (neg:SI (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])))] "TARGET_ARM" -- "@ -- cmp\\t%1, %2\;movcc\\t%0, %2 -- cmp\\t%1, %2\;movcs\\t%0, %1 -- cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2" -+ "#" -+ ; cmp\\t%1, %2\;movcc\\t%0, %2 -+ ; cmp\\t%1, %2\;movcs\\t%0, %1 -+ ; cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2" +- "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" ++ "#" ; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" + "TARGET_ARM" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) -+ (if_then_else:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0)) -+ (match_dup 1) -+ (match_dup 2)))] -+ "" - [(set_attr "conds" "clob") - (set_attr "length" "8,8,12")] - ) -@@ -3340,16 +3543,24 @@ - "" ++ [(set (match_dup 0) ++ (if_then_else:SI (match_dup 1) ++ (match_dup 3) ++ (const_int 0)))] ++ { ++ operands[3] = GEN_INT (~0); ++ } + [(set_attr "conds" "use") +- (set_attr "insn" "mov") + (set_attr "length" "8")] ) --(define_insn "*arm_uminsi3" -+(define_insn_and_split "*arm_uminsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") - (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) - (clobber (reg:CC CC_REGNUM))] +-(define_insn "*mov_notscc" ++(define_insn_and_split "*mov_notscc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (not:SI (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])))] "TARGET_ARM" -- "@ -- cmp\\t%1, %2\;movcs\\t%0, %2 -- cmp\\t%1, %2\;movcc\\t%0, %1 -- cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2" -+ "#" -+ ; cmp\\t%1, %2\;movcs\\t%0, %2 -+ ; cmp\\t%1, %2\;movcc\\t%0, %1 -+ ; cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2" +- "mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1" ++ "#" ; "mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1" + "TARGET_ARM" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 1) (match_dup 2))) -+ (set (match_dup 0) -+ (if_then_else:SI (ltu:SI (reg:CC CC_REGNUM) (const_int 0)) -+ (match_dup 1) -+ (match_dup 2)))] -+ "" - [(set_attr "conds" "clob") - (set_attr "length" "8,8,12")] ++ [(set (match_dup 0) ++ (if_then_else:SI (match_dup 1) ++ (match_dup 3) ++ (match_dup 4)))] ++ { ++ operands[3] = GEN_INT (~1); ++ operands[4] = GEN_INT (~0); ++ } + [(set_attr "conds" "use") +- (set_attr "insn" "mov") + (set_attr "length" "8")] ) -@@ -3360,7 +3571,7 @@ - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "s_register_operand" "r")])) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_32BIT" -+ "TARGET_32BIT && optimize_insn_for_size_p()" - "* - operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode, - operands[1], operands[2]); -@@ -3423,6 +3634,50 @@ - (const_int 12)))] + +@@ -8069,7 +9016,7 @@ + + (define_expand "movsfcc" + [(set (match_operand:SF 0 "s_register_operand" "") +- (if_then_else:SF (match_operand 1 "expandable_comparison_operator" "") ++ (if_then_else:SF (match_operand 1 "arm_cond_move_operator" "") + (match_operand:SF 2 "s_register_operand" "") + (match_operand:SF 3 "s_register_operand" "")))] + "TARGET_32BIT && TARGET_HARD_FLOAT" +@@ -8091,7 +9038,7 @@ + + (define_expand "movdfcc" + [(set (match_operand:DF 0 "s_register_operand" "") +- (if_then_else:DF (match_operand 1 "expandable_comparison_operator" "") ++ (if_then_else:DF (match_operand 1 "arm_cond_move_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "s_register_operand" "")))] + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" +@@ -8110,7 +9057,40 @@ + }" ) -+; Reject the frame pointer in operand[1], since reloading this after -+; it has been eliminated can cause carnage. -+(define_insn_and_split "*minmax_arithsi_non_canon" -+ [(set (match_operand:SI 0 "s_register_operand" "=r,r") -+ (minus:SI -+ (match_operand:SI 1 "s_register_operand" "0,?r") -+ (match_operator:SI 4 "minmax_operator" -+ [(match_operand:SI 2 "s_register_operand" "r,r") -+ (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) -+ (clobber (reg:CC CC_REGNUM))] -+ "TARGET_32BIT && !arm_eliminable_register (operands[1])" -+ "#" -+ "TARGET_32BIT && !arm_eliminable_register (operands[1]) && reload_completed" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 2) (match_dup 3))) +-(define_insn "*movsicc_insn" ++(define_insn "*cmov" ++ [(set (match_operand:SDF 0 "s_register_operand" "=") ++ (if_then_else:SDF (match_operator 1 "arm_vsel_comparison_operator" ++ [(match_operand 2 "cc_register" "") (const_int 0)]) ++ (match_operand:SDF 3 "s_register_operand" ++ "") ++ (match_operand:SDF 4 "s_register_operand" ++ "")))] ++ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " ++ "* ++ { ++ enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]); ++ switch (code) ++ { ++ case ARM_GE: ++ case ARM_GT: ++ case ARM_EQ: ++ case ARM_VS: ++ return \"vsel%d1.\\t%0, %3, %4\"; ++ case ARM_LT: ++ case ARM_LE: ++ case ARM_NE: ++ case ARM_VC: ++ return \"vsel%D1.\\t%0, %4, %3\"; ++ default: ++ gcc_unreachable (); ++ } ++ return \"\"; ++ }" ++ [(set_attr "conds" "use") ++ (set_attr "type" "f_sel")] ++) + -+ (cond_exec (match_op_dup 4 [(reg:CC CC_REGNUM) (const_int 0)]) -+ (set (match_dup 0) -+ (minus:SI (match_dup 1) -+ (match_dup 2)))) -+ (cond_exec (match_op_dup 5 [(reg:CC CC_REGNUM) (const_int 0)]) -+ (set (match_dup 0) -+ (minus:SI (match_dup 1) -+ (match_dup 3))))] ++(define_insn_and_split "*movsicc_insn" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") + (if_then_else:SI + (match_operator 3 "arm_comparison_operator" +@@ -8123,26 +9103,60 @@ + mvn%D3\\t%0, #%B2 + mov%d3\\t%0, %1 + mvn%d3\\t%0, #%B1 +- mov%d3\\t%0, %1\;mov%D3\\t%0, %2 +- mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 +- mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 +- mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" ++ # ++ # ++ # ++ #" ++ ; alt4: mov%d3\\t%0, %1\;mov%D3\\t%0, %2 ++ ; alt5: mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 ++ ; alt6: mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 ++ ; alt7: mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" ++ "&& reload_completed" ++ [(const_int 0)] + { -+ enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), -+ operands[2], operands[3]); -+ enum rtx_code rc = minmax_code (operands[4]); -+ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, -+ operands[2], operands[3]); ++ enum rtx_code rev_code; ++ enum machine_mode mode; ++ rtx rev_cond; + -+ if (mode == CCFPmode || mode == CCFPEmode) -+ rc = reverse_condition_maybe_unordered (rc); -+ else -+ rc = reverse_condition (rc); -+ operands[5] = gen_rtx_fmt_ee (rc, SImode, operands[2], operands[3]); -+ } -+ [(set_attr "conds" "clob") -+ (set (attr "length") -+ (if_then_else (eq_attr "is_thumb" "yes") -+ (const_int 14) -+ (const_int 12)))] -+) ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ operands[3], ++ gen_rtx_SET (VOIDmode, ++ operands[0], ++ operands[1]))); + - (define_code_iterator SAT [smin smax]) - (define_code_iterator SATrev [smin smax]) - (define_code_attr SATlo [(smin "1") (smax "2")]) -@@ -3533,13 +3788,26 @@ - " ++ rev_code = GET_CODE (operands[3]); ++ mode = GET_MODE (operands[4]); ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rev_code = reverse_condition_maybe_unordered (rev_code); ++ else ++ rev_code = reverse_condition (rev_code); ++ ++ rev_cond = gen_rtx_fmt_ee (rev_code, ++ VOIDmode, ++ operands[4], ++ const0_rtx); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ rev_cond, ++ gen_rtx_SET (VOIDmode, ++ operands[0], ++ operands[2]))); ++ DONE; ++ } + [(set_attr "length" "4,4,4,4,8,8,8,8") + (set_attr "conds" "use") +- (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn") + (set_attr_alternative "type" + [(if_then_else (match_operand 2 "const_int_operand" "") +- (const_string "simple_alu_imm") +- (const_string "*")) +- (const_string "simple_alu_imm") ++ (const_string "mov_imm") ++ (const_string "mov_reg")) ++ (const_string "mvn_imm") + (if_then_else (match_operand 1 "const_int_operand" "") +- (const_string "simple_alu_imm") +- (const_string "*")) +- (const_string "simple_alu_imm") +- (const_string "*") +- (const_string "*") +- (const_string "*") +- (const_string "*")])] ++ (const_string "mov_imm") ++ (const_string "mov_reg")) ++ (const_string "mvn_imm") ++ (const_string "mov_reg") ++ (const_string "mov_reg") ++ (const_string "mov_reg") ++ (const_string "mov_reg")])] + ) + + (define_insn "*movsfcc_soft_insn" +@@ -8156,7 +9170,7 @@ + mov%D3\\t%0, %2 + mov%d3\\t%0, %1" + [(set_attr "conds" "use") +- (set_attr "insn" "mov")] ++ (set_attr "type" "mov_reg")] ) --(define_insn "arm_ashldi3_1bit" -+(define_insn_and_split "arm_ashldi3_1bit" - [(set (match_operand:DI 0 "s_register_operand" "=r,&r") - (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") - (const_int 1))) - (clobber (reg:CC CC_REGNUM))] + +@@ -8255,7 +9269,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && arm_arch5" ++ "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" + "blx%?\\t%0" + [(set_attr "type" "call")] + ) +@@ -8265,7 +9279,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && !arm_arch5" ++ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" + "* + return output_call (operands); + " +@@ -8284,7 +9298,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && !arm_arch5" ++ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" + "* + return output_call_mem (operands); + " +@@ -8297,7 +9311,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_THUMB1 && arm_arch5" ++ "TARGET_THUMB1 && arm_arch5 && !SIBLING_CALL_P (insn)" + "blx\\t%0" + [(set_attr "length" "2") + (set_attr "type" "call")] +@@ -8308,7 +9322,7 @@ + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_THUMB1 && !arm_arch5" ++ "TARGET_THUMB1 && !arm_arch5 && !SIBLING_CALL_P (insn)" + "* + { + if (!TARGET_CALLER_INTERWORKING) +@@ -8367,7 +9381,7 @@ + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && arm_arch5" ++ "TARGET_ARM && arm_arch5 && !SIBLING_CALL_P (insn)" + "blx%?\\t%1" + [(set_attr "type" "call")] + ) +@@ -8378,7 +9392,7 @@ + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && !arm_arch5" ++ "TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)" + "* + return output_call (&operands[1]); + " +@@ -8394,7 +9408,8 @@ + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] +- "TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))" ++ "TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ++ && !SIBLING_CALL_P (insn)" + "* + return output_call_mem (&operands[1]); + " +@@ -8444,6 +9459,7 @@ + (use (match_operand 2 "" "")) + (clobber (reg:SI LR_REGNUM))] + "TARGET_32BIT ++ && !SIBLING_CALL_P (insn) + && (GET_CODE (operands[0]) == SYMBOL_REF) + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" + "* +@@ -8460,6 +9476,7 @@ + (use (match_operand 3 "" "")) + (clobber (reg:SI LR_REGNUM))] + "TARGET_32BIT ++ && !SIBLING_CALL_P (insn) + && (GET_CODE (operands[1]) == SYMBOL_REF) + && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" + "* +@@ -8505,6 +9522,10 @@ "TARGET_32BIT" -- "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" -+ "#" ; "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (ashift:SI (match_dup 1) (const_int 1)) -+ (const_int 0))) -+ (set (match_dup 0) (ashift:SI (match_dup 1) (const_int 1)))]) -+ (set (match_dup 2) (plus:SI (plus:SI (match_dup 3) (match_dup 3)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] + " + { ++ if (!REG_P (XEXP (operands[0], 0)) ++ && (GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)) ++ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); ++ + if (operands[2] == NULL_RTX) + operands[2] = const0_rtx; + }" +@@ -8519,47 +9540,67 @@ + "TARGET_32BIT" + " + { ++ if (!REG_P (XEXP (operands[1], 0)) && ++ (GET_CODE (XEXP (operands[1],0)) != SYMBOL_REF)) ++ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); ++ + if (operands[3] == NULL_RTX) + operands[3] = const0_rtx; + }" ) -@@ -3615,18 +3883,43 @@ + + (define_insn "*sibcall_insn" +- [(call (mem:SI (match_operand:SI 0 "" "X")) ++ [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "Cs, US")) + (match_operand 1 "" "")) + (return) + (use (match_operand 2 "" ""))] +- "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF" ++ "TARGET_32BIT && SIBLING_CALL_P (insn)" + "* +- return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; ++ if (which_alternative == 1) ++ return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; ++ else ++ { ++ if (arm_arch5 || arm_arch4t) ++ return \"bx%?\\t%0\\t%@ indirect register sibling call\"; ++ else ++ return \"mov%?\\t%|pc, %0\\t%@ indirect register sibling call\"; ++ } " + [(set_attr "type" "call")] ) --(define_insn "arm_ashrdi3_1bit" -+(define_insn_and_split "arm_ashrdi3_1bit" - [(set (match_operand:DI 0 "s_register_operand" "=r,&r") - (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") - (const_int 1))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT" -- "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" -+ "#" ; "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (ashiftrt:SI (match_dup 3) (const_int 1)) -+ (const_int 0))) -+ (set (match_dup 2) (ashiftrt:SI (match_dup 3) (const_int 1)))]) -+ (set (match_dup 0) (unspec:SI [(match_dup 1) -+ (reg:CC_C CC_REGNUM)] -+ UNSPEC_RRX))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } - [(set_attr "conds" "clob") -- (set_attr "insn" "mov") - (set_attr "length" "8")] + (define_insn "*sibcall_value_insn" + [(set (match_operand 0 "" "") +- (call (mem:SI (match_operand:SI 1 "" "X")) ++ (call (mem:SI (match_operand:SI 1 "call_insn_operand" "Cs,US")) + (match_operand 2 "" ""))) + (return) + (use (match_operand 3 "" ""))] +- "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF" ++ "TARGET_32BIT && SIBLING_CALL_P (insn)" + "* +- return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; ++ if (which_alternative == 1) ++ return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; ++ else ++ { ++ if (arm_arch5 || arm_arch4t) ++ return \"bx%?\\t%1\"; ++ else ++ return \"mov%?\\t%|pc, %1\\t@ indirect sibling call \"; ++ } + " + [(set_attr "type" "call")] ) -+(define_insn "*rrx" -+ [(set (match_operand:SI 0 "s_register_operand" "=r") -+ (unspec:SI [(match_operand:SI 1 "s_register_operand" "r") -+ (reg:CC_C CC_REGNUM)] -+ UNSPEC_RRX))] -+ "TARGET_32BIT" -+ "mov\\t%0, %1, rrx" -+ [(set_attr "conds" "use") -+ (set_attr "insn" "mov") -+ (set_attr "type" "alu_shift")] -+) -+ - (define_expand "ashrsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") -@@ -3695,15 +3988,28 @@ +-(define_expand "return" +- [(return)] ++(define_expand "return" ++ [(returns)] + "(TARGET_ARM || (TARGET_THUMB2 + && ARM_FUNC_TYPE (arm_current_func_type ()) == ARM_FT_NORMAL + && !IS_STACKALIGN (arm_current_func_type ()))) +- && USE_RETURN_INSN (FALSE)" ++ " " + { + if (TARGET_THUMB2) + { +- thumb2_expand_return (); ++ thumb2_expand_return (); + DONE; + } + } +@@ -8584,13 +9625,13 @@ + (set_attr "predicable" "yes")] ) --(define_insn "arm_lshrdi3_1bit" -+(define_insn_and_split "arm_lshrdi3_1bit" - [(set (match_operand:DI 0 "s_register_operand" "=r,&r") - (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") - (const_int 1))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT" -- "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" -+ "#" ; "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" +-(define_insn "*cond_return" ++(define_insn "*cond_return" + [(set (pc) + (if_then_else (match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") (const_int 0)]) +- (return) ++ (returns) + (pc)))] +- "TARGET_ARM && USE_RETURN_INSN (TRUE)" ++ "TARGET_ARM " + "* + { + if (arm_ccfsm_state == 2) +@@ -8598,20 +9639,21 @@ + arm_ccfsm_state += 2; + return \"\"; + } +- return output_return_instruction (operands[0], true, false, false); ++ return output_return_instruction (operands[0], true, false, ++ ); + }" + [(set_attr "conds" "use") + (set_attr "length" "12") + (set_attr "type" "load1")] + ) + +-(define_insn "*cond_return_inverted" ++(define_insn "*cond_return_inverted" + [(set (pc) + (if_then_else (match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") (const_int 0)]) + (pc) +- (return)))] +- "TARGET_ARM && USE_RETURN_INSN (TRUE)" ++ (returns)))] ++ "TARGET_ARM " + "* + { + if (arm_ccfsm_state == 2) +@@ -8619,7 +9661,8 @@ + arm_ccfsm_state += 2; + return \"\"; + } +- return output_return_instruction (operands[0], true, true, false); ++ return output_return_instruction (operands[0], true, true, ++ ); + }" + [(set_attr "conds" "use") + (set_attr "length" "12") +@@ -8991,7 +10034,7 @@ + (if_then_else + (match_operand:SI 3 "mult_operator" "") + (const_string "no") (const_string "yes"))]) +- (set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")]) ++ (set_attr "type" "arlo_shift,arlo_shift,arlo_shift,arlo_shift_reg")]) + + (define_split + [(set (match_operand:SI 0 "s_register_operand" "") +@@ -9028,7 +10071,7 @@ + [(set_attr "conds" "set") + (set_attr "shift" "4") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "arlo_shift,arlo_shift_reg")]) + + (define_insn "*arith_shiftsi_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) +@@ -9045,7 +10088,7 @@ + [(set_attr "conds" "set") + (set_attr "shift" "4") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "arlo_shift,arlo_shift_reg")]) + + (define_insn "*sub_shiftsi" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") +@@ -9058,7 +10101,7 @@ + [(set_attr "predicable" "yes") + (set_attr "shift" "3") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "arlo_shift,arlo_shift_reg")]) + + (define_insn "*sub_shiftsi_compare0" + [(set (reg:CC_NOOV CC_REGNUM) +@@ -9076,7 +10119,7 @@ + [(set_attr "conds" "set") + (set_attr "shift" "3") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "arlo_shift,arlo_shift_reg")]) + + (define_insn "*sub_shiftsi_compare0_scratch" + [(set (reg:CC_NOOV CC_REGNUM) +@@ -9092,30 +10135,67 @@ + [(set_attr "conds" "set") + (set_attr "shift" "3") + (set_attr "arch" "32,a") +- (set_attr "type" "alu_shift,alu_shift_reg")]) ++ (set_attr "type" "arlo_shift,arlo_shift_reg")]) + + +-(define_insn "*and_scc" ++(define_insn_and_split "*and_scc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (and:SI (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 2 "s_register_operand" "r")))] ++ [(match_operand 2 "cc_register" "") (const_int 0)]) ++ (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_ARM" +- "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" ++ "#" ; "mov%D1\\t%0, #0\;and%d1\\t%0, %3, #1" + "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (lshiftrt:SI (match_dup 3) (const_int 1)) -+ (const_int 0))) -+ (set (match_dup 2) (lshiftrt:SI (match_dup 3) (const_int 1)))]) -+ (set (match_dup 0) (unspec:SI [(match_dup 1) -+ (reg:CC_C CC_REGNUM)] -+ UNSPEC_RRX))] ++ [(cond_exec (match_dup 5) (set (match_dup 0) (const_int 0))) ++ (cond_exec (match_dup 4) (set (match_dup 0) ++ (and:SI (match_dup 3) (const_int 1))))] + { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); ++ enum machine_mode mode = GET_MODE (operands[2]); ++ enum rtx_code rc = GET_CODE (operands[1]); ++ ++ /* Note that operands[4] is the same as operands[1], ++ but with VOIDmode as the result. */ ++ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rc = reverse_condition_maybe_unordered (rc); ++ else ++ rc = reverse_condition (rc); ++ operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); + } - [(set_attr "conds" "clob") + [(set_attr "conds" "use") - (set_attr "insn" "mov") ++ (set_attr "type" "mov_reg") (set_attr "length" "8")] ) -@@ -3791,6 +4097,23 @@ - (const_string "alu_shift_reg")))] +-(define_insn "*ior_scc" ++(define_insn_and_split "*ior_scc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (ior:SI (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "s_register_operand" "0,?r")))] ++ (ior:SI (match_operator:SI 1 "arm_comparison_operator" ++ [(match_operand 2 "cc_register" "") (const_int 0)]) ++ (match_operand:SI 3 "s_register_operand" "0,?r")))] + "TARGET_ARM" + "@ +- orr%d2\\t%0, %1, #1 +- mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" ++ orr%d1\\t%0, %3, #1 ++ #" ++ "&& reload_completed ++ && REGNO (operands [0]) != REGNO (operands[3])" ++ ;; && which_alternative == 1 ++ ; mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1 ++ [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3))) ++ (cond_exec (match_dup 4) (set (match_dup 0) ++ (ior:SI (match_dup 3) (const_int 1))))] ++ { ++ enum machine_mode mode = GET_MODE (operands[2]); ++ enum rtx_code rc = GET_CODE (operands[1]); ++ ++ /* Note that operands[4] is the same as operands[1], ++ but with VOIDmode as the result. */ ++ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); ++ if (mode == CCFPmode || mode == CCFPEmode) ++ rc = reverse_condition_maybe_unordered (rc); ++ else ++ rc = reverse_condition (rc); ++ operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); ++ } + [(set_attr "conds" "use") + (set_attr "length" "4,8")] ) - -+(define_insn "*shiftsi3_compare" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_operator:SI 3 "shift_operator" -+ [(match_operand:SI 1 "s_register_operand" "r") -+ (match_operand:SI 2 "arm_rhs_operand" "rM")]) -+ (const_int 0))) -+ (set (match_operand:SI 0 "s_register_operand" "=r") -+ (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] -+ "TARGET_32BIT" -+ "* return arm_output_shift(operands, 1);" -+ [(set_attr "conds" "set") -+ (set_attr "shift" "1") -+ (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") -+ (const_string "alu_shift") -+ (const_string "alu_shift_reg")))] +@@ -9144,6 +10224,16 @@ + (eq:SI (match_operand:SI 1 "s_register_operand" "") + (const_int 0))) + (clobber (reg:CC CC_REGNUM))] ++ "arm_arch5 && TARGET_32BIT" ++ [(set (match_dup 0) (clz:SI (match_dup 1))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] +) + - (define_insn "*shiftsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (match_operator:SI 3 "shift_operator" -@@ -4090,6 +4413,64 @@ - (set_attr "predicable" "yes") - (set_attr "type" "store1")]) ++(define_split ++ [(set (match_operand:SI 0 "s_register_operand" "") ++ (eq:SI (match_operand:SI 1 "s_register_operand" "") ++ (const_int 0))) ++ (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT && reload_completed" + [(parallel + [(set (reg:CC CC_REGNUM) +@@ -9184,7 +10274,7 @@ + (set (match_dup 0) (const_int 1)))]) -+;; Unaligned double-word load and store. -+;; Split after reload into two unaligned single-word accesses. -+;; It prevents lower_subreg from splitting some other aligned -+;; double-word accesses too early. Used for internal memcpy. -+ -+(define_insn_and_split "unaligned_loaddi" -+ [(set (match_operand:DI 0 "s_register_operand" "=l,r") -+ (unspec:DI [(match_operand:DI 1 "memory_operand" "o,o")] -+ UNSPEC_UNALIGNED_LOAD))] -+ "unaligned_access && TARGET_32BIT" -+ "#" -+ "&& reload_completed" -+ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_UNALIGNED_LOAD)) -+ (set (match_dup 2) (unspec:SI [(match_dup 3)] UNSPEC_UNALIGNED_LOAD))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); + (define_insn_and_split "*compare_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++ [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts") + (match_operator:SI 1 "arm_comparison_operator" + [(match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "arm_add_operand" "rI,L")])) +@@ -9213,29 +10303,93 @@ + + ;; Attempt to improve the sequence generated by the compare_scc splitters + ;; not to use conditional execution. ++ ++;; Rd = (eq (reg1) (const_int0)) // ARMv5 ++;; clz Rd, reg1 ++;; lsr Rd, Rd, #5 + (define_peephole2 + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "register_operand" "") ++ (const_int 0))) ++ (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "") (const_int 0))) ++ (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1)))] ++ "arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" ++ [(set (match_dup 0) (clz:SI (match_dup 1))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] ++) + -+ /* If the first destination register overlaps with the base address, -+ swap the order in which the loads are emitted. */ -+ if (reg_overlap_mentioned_p (operands[0], operands[1])) -+ { -+ rtx tmp = operands[1]; -+ operands[1] = operands[3]; -+ operands[3] = tmp; -+ tmp = operands[0]; -+ operands[0] = operands[2]; -+ operands[2] = tmp; -+ } -+ } -+ [(set_attr "arch" "t2,any") -+ (set_attr "length" "4,8") -+ (set_attr "predicable" "yes") -+ (set_attr "type" "load2")]) ++;; Rd = (eq (reg1) (const_int0)) // !ARMv5 ++;; negs Rd, reg1 ++;; adc Rd, Rd, reg1 ++(define_peephole2 ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "register_operand" "") ++ (const_int 0))) ++ (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "") (const_int 0))) ++ (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1))) ++ (match_scratch:SI 2 "r")] ++ "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" ++ [(parallel ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (const_int 0) (match_dup 1))) ++ (set (match_dup 2) (minus:SI (const_int 0) (match_dup 1)))]) ++ (set (match_dup 0) ++ (plus:SI (plus:SI (match_dup 1) (match_dup 2)) ++ (geu:SI (reg:CC CC_REGNUM) (const_int 0))))] ++) + -+(define_insn_and_split "unaligned_storedi" -+ [(set (match_operand:DI 0 "memory_operand" "=o,o") -+ (unspec:DI [(match_operand:DI 1 "s_register_operand" "l,r")] -+ UNSPEC_UNALIGNED_STORE))] -+ "unaligned_access && TARGET_32BIT" -+ "#" -+ "&& reload_completed" -+ [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_UNALIGNED_STORE)) -+ (set (match_dup 2) (unspec:SI [(match_dup 3)] UNSPEC_UNALIGNED_STORE))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } -+ [(set_attr "arch" "t2,any") -+ (set_attr "length" "4,8") -+ (set_attr "predicable" "yes") -+ (set_attr "type" "store2")]) ++;; Rd = (eq (reg1) (reg2/imm)) // ARMv5 and optimising for speed. ++;; sub Rd, Reg1, reg2 ++;; clz Rd, Rd ++;; lsr Rd, Rd, #5 ++(define_peephole2 ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "arm_rhs_operand" ""))) + (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) + (set (match_operand:SI 0 "register_operand" "") (const_int 0))) + (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_dup 0) (const_int 1)))] ++ "arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM) ++ && !(TARGET_THUMB2 && optimize_insn_for_size_p ())" ++ [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2))) ++ (set (match_dup 0) (clz:SI (match_dup 0))) ++ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))] ++) + + - (define_insn "*extv_reg" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") -@@ -4154,12 +4535,24 @@ ++;; Rd = (eq (reg1) (reg2)) // ! ARMv5 or optimising for size. ++;; sub T1, Reg1, reg2 ++;; negs Rd, T1 ++;; adc Rd, Rd, T1 ++(define_peephole2 ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 1 "register_operand" "") ++ (match_operand:SI 2 "arm_rhs_operand" ""))) ++ (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "") (const_int 0))) ++ (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) + (set (match_dup 0) (const_int 1))) + (match_scratch:SI 3 "r")] +- "TARGET_32BIT" +- [(parallel +- [(set (reg:CC CC_REGNUM) +- (compare:CC (match_dup 1) (match_dup 2))) +- (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))]) ++ "TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)" ++ [(set (match_dup 3) (match_dup 4)) + (parallel + [(set (reg:CC CC_REGNUM) + (compare:CC (const_int 0) (match_dup 3))) + (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))]) +- (parallel +- [(set (match_dup 0) +- (plus:SI (plus:SI (match_dup 0) (match_dup 3)) +- (geu:SI (reg:CC CC_REGNUM) (const_int 0)))) +- (clobber (reg:CC CC_REGNUM))])]) ++ (set (match_dup 0) ++ (plus:SI (plus:SI (match_dup 0) (match_dup 3)) ++ (geu:SI (reg:CC CC_REGNUM) (const_int 0))))] ++ " ++ if (CONST_INT_P (operands[2])) ++ operands[4] = plus_constant (SImode, operands[1], -INTVAL (operands[2])); ++ else ++ operands[4] = gen_rtx_MINUS (SImode, operands[1], operands[2]); ++ ") - ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). - ;; The first alternative allows the common case of a *full* overlap. --(define_insn "*arm_negdi2" -+(define_insn_and_split "*arm_negdi2" - [(set (match_operand:DI 0 "s_register_operand" "=r,&r") - (neg:DI (match_operand:DI 1 "s_register_operand" "0,r"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" -- "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0" -+ "#" ; "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0" -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (const_int 0) (match_dup 1))) -+ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))]) -+ (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } - [(set_attr "conds" "clob") - (set_attr "length" "8")] + (define_insn "*cond_move" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +@@ -9262,7 +10416,7 @@ + return \"\"; + " + [(set_attr "conds" "use") +- (set_attr "insn" "mov") ++ (set_attr "type" "mov_reg") + (set_attr "length" "4,4,8")] ) -@@ -4209,6 +4602,73 @@ - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" + +@@ -9636,7 +10790,7 @@ + ) + + (define_insn_and_split "*ior_scc_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") ++ [(set (match_operand:SI 0 "s_register_operand" "=Ts") + (ior:SI (match_operator:SI 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_add_operand" "rIL")]) +@@ -9674,7 +10828,7 @@ + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "arm_add_operand" "rIL")])) + (const_int 0))) +- (set (match_operand:SI 7 "s_register_operand" "=r") ++ (set (match_operand:SI 7 "s_register_operand" "=Ts") + (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] + "TARGET_32BIT" +@@ -9692,7 +10846,7 @@ + (set_attr "length" "16")]) + + (define_insn_and_split "*and_scc_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") ++ [(set (match_operand:SI 0 "s_register_operand" "=Ts") + (and:SI (match_operator:SI 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_add_operand" "rIL")]) +@@ -9732,7 +10886,7 @@ + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "arm_add_operand" "rIL")])) + (const_int 0))) +- (set (match_operand:SI 7 "s_register_operand" "=r") ++ (set (match_operand:SI 7 "s_register_operand" "=Ts") + (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] + "TARGET_32BIT" +@@ -9754,7 +10908,7 @@ + ;; need only zero the value if false (if true, then the value is already + ;; correct). + (define_insn_and_split "*and_scc_scc_nodom" +- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") ++ [(set (match_operand:SI 0 "s_register_operand" "=&Ts,&Ts,&Ts") + (and:SI (match_operator:SI 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r,r,0") + (match_operand:SI 2 "arm_add_operand" "rIL,0,rIL")]) +@@ -9822,28 +10976,117 @@ "") + ;; ??? The conditional patterns above need checking for Thumb-2 usefulness -+;; Negate an extended 32-bit value. -+(define_insn_and_split "*negdi_extendsidi" -+ [(set (match_operand:DI 0 "s_register_operand" "=r,&r,l,&l") -+ (neg:DI (sign_extend:DI (match_operand:SI 1 "s_register_operand" "0,r,0,l")))) -+ (clobber (reg:CC CC_REGNUM))] -+ "TARGET_32BIT" -+ "#" ; rsb\\t%Q0, %1, #0\;asr\\t%R0, %Q0, #31 +-(define_insn "*negscc" ++(define_insn_and_split "*negscc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (neg:SI (match_operator 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_rhs_operand" "rI")]))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" +- "* +- if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx) +- return \"mov\\t%0, %1, asr #31\"; ++ "#" + "&& reload_completed" + [(const_int 0)] + { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ rtx tmp = gen_rtx_SET (VOIDmode, -+ operands[0], -+ gen_rtx_MINUS (SImode, -+ const0_rtx, -+ operands[1])); -+ if (TARGET_ARM) ++ rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); + +- if (GET_CODE (operands[3]) == NE) +- return \"subs\\t%0, %1, %2\;mvnne\\t%0, #0\"; ++ if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx) + { -+ emit_insn (tmp); ++ /* Emit mov\\t%0, %1, asr #31 */ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ operands[0], ++ gen_rtx_ASHIFTRT (SImode, ++ operands[1], ++ GEN_INT (31)))); ++ DONE; + } -+ else ++ else if (GET_CODE (operands[3]) == NE) + { -+ /* Set the flags, to emit the short encoding in Thumb2. */ -+ rtx flags = gen_rtx_SET (VOIDmode, -+ gen_rtx_REG (CCmode, CC_REGNUM), -+ gen_rtx_COMPARE (CCmode, -+ const0_rtx, -+ operands[1])); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, -+ gen_rtvec (2, -+ flags, -+ tmp))); -+ } -+ emit_insn (gen_rtx_SET (VOIDmode, -+ operands[2], -+ gen_rtx_ASHIFTRT (SImode, -+ operands[0], -+ GEN_INT (31)))); -+ DONE; -+ } -+ [(set_attr "length" "8,8,4,4") -+ (set_attr "arch" "a,a,t2,t2")] -+) ++ /* Emit subs\\t%0, %1, %2\;mvnne\\t%0, #0 */ ++ if (CONST_INT_P (operands[2])) ++ emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2], ++ GEN_INT (- INTVAL (operands[2])))); ++ else ++ emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2])); + +- output_asm_insn (\"cmp\\t%1, %2\", operands); +- output_asm_insn (\"mov%D3\\t%0, #0\", operands); +- return \"mvn%d3\\t%0, #0\"; +- " ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ gen_rtx_NE (SImode, ++ cc_reg, ++ const0_rtx), ++ gen_rtx_SET (SImode, ++ operands[0], ++ GEN_INT (~0)))); ++ DONE; ++ } ++ else ++ { ++ /* Emit: cmp\\t%1, %2\;mov%D3\\t%0, #0\;mvn%d3\\t%0, #0 */ ++ emit_insn (gen_rtx_SET (VOIDmode, ++ cc_reg, ++ gen_rtx_COMPARE (CCmode, operands[1], operands[2]))); ++ enum rtx_code rc = GET_CODE (operands[3]); + -+(define_insn_and_split "*negdi_zero_extendsidi" -+ [(set (match_operand:DI 0 "s_register_operand" "=r,&r") -+ (neg:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "0,r")))) -+ (clobber (reg:CC CC_REGNUM))] -+ "TARGET_32BIT" -+ "#" ; "rsbs\\t%Q0, %1, #0\;sbc\\t%R0,%R0,%R0" -+ ;; Don't care what register is input to sbc, -+ ;; since we just just need to propagate the carry. -+ "&& reload_completed" -+ [(parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (const_int 0) (match_dup 1))) -+ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))]) -+ (set (match_dup 2) (minus:SI (minus:SI (match_dup 2) (match_dup 2)) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); ++ rc = reverse_condition (rc); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ gen_rtx_fmt_ee (rc, ++ VOIDmode, ++ cc_reg, ++ const0_rtx), ++ gen_rtx_SET (VOIDmode, operands[0], const0_rtx))); ++ rc = GET_CODE (operands[3]); ++ emit_insn (gen_rtx_COND_EXEC (VOIDmode, ++ gen_rtx_fmt_ee (rc, ++ VOIDmode, ++ cc_reg, ++ const0_rtx), ++ gen_rtx_SET (VOIDmode, ++ operands[0], ++ GEN_INT (~0)))); ++ DONE; ++ } ++ FAIL; + } -+ [(set_attr "conds" "clob") -+ (set_attr "length" "8")] ;; length in thumb is 4 -+) -+ - ;; abssi2 doesn't really clobber the condition codes if a different register - ;; is being set. To keep things simple, assume during rtl manipulations that - ;; it does, but tell the final scan operator the truth. Similarly for -@@ -4227,14 +4687,67 @@ - operands[2] = gen_rtx_REG (CCmode, CC_REGNUM); - ") + [(set_attr "conds" "clob") + (set_attr "length" "12")] + ) --(define_insn "*arm_abssi2" -+(define_insn_and_split "*arm_abssi2" - [(set (match_operand:SI 0 "s_register_operand" "=r,&r") - (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" -- "@ -- cmp\\t%0, #0\;rsblt\\t%0, %0, #0 -- eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31" -+ "#" -+ "&& reload_completed" -+ [(const_int 0)] ++(define_insn_and_split "movcond_addsi" ++ [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") ++ (if_then_else:SI ++ (match_operator 5 "comparison_operator" ++ [(plus:SI (match_operand:SI 3 "s_register_operand" "r,r,r") ++ (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")) ++ (const_int 0)]) ++ (match_operand:SI 1 "arm_rhs_operand" "rI,rPy,r") ++ (match_operand:SI 2 "arm_rhs_operand" "rI,rPy,r"))) ++ (clobber (reg:CC CC_REGNUM))] ++ "TARGET_32BIT" ++ "#" ++ "&& reload_completed" ++ [(set (reg:CC_NOOV CC_REGNUM) ++ (compare:CC_NOOV ++ (plus:SI (match_dup 3) ++ (match_dup 4)) ++ (const_int 0))) ++ (set (match_dup 0) (match_dup 1)) ++ (cond_exec (match_dup 6) ++ (set (match_dup 0) (match_dup 2)))] ++ " + { -+ /* if (which_alternative == 0) */ -+ if (REGNO(operands[0]) == REGNO(operands[1])) -+ { -+ /* Emit the pattern: -+ cmp\\t%0, #0\;rsblt\\t%0, %0, #0 -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 0) (const_int 0))) -+ (cond_exec (lt:CC (reg:CC CC_REGNUM) (const_int 0)) -+ (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1))))] -+ */ -+ emit_insn (gen_rtx_SET (VOIDmode, -+ gen_rtx_REG (CCmode, CC_REGNUM), -+ gen_rtx_COMPARE (CCmode, operands[0], const0_rtx))); -+ emit_insn (gen_rtx_COND_EXEC (VOIDmode, -+ (gen_rtx_LT (SImode, -+ gen_rtx_REG (CCmode, CC_REGNUM), -+ const0_rtx)), -+ (gen_rtx_SET (VOIDmode, -+ operands[0], -+ (gen_rtx_MINUS (SImode, -+ const0_rtx, -+ operands[1])))))); -+ DONE; -+ } -+ else -+ { -+ /* Emit the pattern: -+ alt1: eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31 -+ [(set (match_dup 0) -+ (xor:SI (match_dup 1) -+ (ashiftrt:SI (match_dup 1) (const_int 31)))) -+ (set (match_dup 0) -+ (minus:SI (match_dup 0) -+ (ashiftrt:SI (match_dup 1) (const_int 31))))] -+ */ -+ emit_insn (gen_rtx_SET (VOIDmode, -+ operands[0], -+ gen_rtx_XOR (SImode, -+ gen_rtx_ASHIFTRT (SImode, -+ operands[1], -+ GEN_INT (31)), -+ operands[1]))); -+ emit_insn (gen_rtx_SET (VOIDmode, -+ operands[0], -+ gen_rtx_MINUS (SImode, -+ operands[0], -+ gen_rtx_ASHIFTRT (SImode, -+ operands[1], -+ GEN_INT (31))))); -+ DONE; -+ } ++ enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[5]), ++ operands[3], operands[4]); ++ enum rtx_code rc = GET_CODE (operands[5]); ++ ++ operands[6] = gen_rtx_REG (mode, CC_REGNUM); ++ gcc_assert (!(mode == CCFPmode || mode == CCFPEmode)); ++ rc = reverse_condition (rc); ++ ++ operands[6] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx); + } - [(set_attr "conds" "clob,*") ++ " ++ [(set_attr "conds" "clob") ++ (set_attr "enabled_for_depr_it" "no,yes,yes")] ++) ++ + (define_insn "movcond" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (if_then_else:SI +@@ -9944,9 +11187,9 @@ + (set_attr "length" "4,4,8,8") + (set_attr_alternative "type" + [(if_then_else (match_operand 3 "const_int_operand" "") +- (const_string "simple_alu_imm" ) ++ (const_string "arlo_imm" ) + (const_string "*")) +- (const_string "simple_alu_imm") ++ (const_string "arlo_imm") + (const_string "*") + (const_string "*")])] + ) +@@ -9986,9 +11229,9 @@ + (set_attr "length" "4,4,8,8") + (set_attr_alternative "type" + [(if_then_else (match_operand 3 "const_int_operand" "") +- (const_string "simple_alu_imm" ) ++ (const_string "arlo_imm" ) + (const_string "*")) +- (const_string "simple_alu_imm") ++ (const_string "arlo_imm") + (const_string "*") + (const_string "*")])] + ) +@@ -10174,7 +11417,7 @@ + mov%d4\\t%0, %1\;mvn%D4\\t%0, %2 + mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2" + [(set_attr "conds" "use") +- (set_attr "insn" "mvn") ++ (set_attr "type" "mvn_reg") + (set_attr "length" "4,8,8")] + ) + +@@ -10207,7 +11450,7 @@ + mov%D4\\t%0, %1\;mvn%d4\\t%0, %2 + mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2" + [(set_attr "conds" "use") +- (set_attr "insn" "mvn") ++ (set_attr "type" "mvn_reg") + (set_attr "length" "4,8,8")] + ) + +@@ -10245,10 +11488,9 @@ + [(set_attr "conds" "use") + (set_attr "shift" "2") + (set_attr "length" "4,8,8") +- (set_attr "insn" "mov") + (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++ (const_string "mov_shift") ++ (const_string "mov_shift_reg")))] + ) + + (define_insn "*ifcompare_move_shift" +@@ -10285,10 +11527,9 @@ + [(set_attr "conds" "use") + (set_attr "shift" "2") + (set_attr "length" "4,8,8") +- (set_attr "insn" "mov") + (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++ (const_string "mov_shift") ++ (const_string "mov_shift_reg")))] + ) + + (define_insn "*ifcompare_shift_shift" +@@ -10326,12 +11567,11 @@ + [(set_attr "conds" "use") (set_attr "shift" "1") - (set_attr "predicable" "no, yes") -@@ -4255,14 +4768,56 @@ - [(set_attr "length" "6")] + (set_attr "length" "8") +- (set_attr "insn" "mov") + (set (attr "type") (if_then_else + (and (match_operand 2 "const_int_operand" "") + (match_operand 4 "const_int_operand" "")) +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++ (const_string "mov_shift") ++ (const_string "mov_shift_reg")))] ) --(define_insn "*arm_neg_abssi2" -+(define_insn_and_split "*arm_neg_abssi2" - [(set (match_operand:SI 0 "s_register_operand" "=r,&r") - (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))) - (clobber (reg:CC CC_REGNUM))] + (define_insn "*ifcompare_not_arith" +@@ -10363,7 +11603,7 @@ "TARGET_ARM" -- "@ -- cmp\\t%0, #0\;rsbgt\\t%0, %0, #0 -- eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31" -+ "#" -+ "&& reload_completed" -+ [(const_int 0)] -+ { -+ /* if (which_alternative == 0) */ -+ if (REGNO (operands[0]) == REGNO (operands[1])) -+ { -+ /* Emit the pattern: -+ cmp\\t%0, #0\;rsbgt\\t%0, %0, #0 -+ */ -+ emit_insn (gen_rtx_SET (VOIDmode, -+ gen_rtx_REG (CCmode, CC_REGNUM), -+ gen_rtx_COMPARE (CCmode, operands[0], const0_rtx))); -+ emit_insn (gen_rtx_COND_EXEC (VOIDmode, -+ gen_rtx_GT (SImode, -+ gen_rtx_REG (CCmode, CC_REGNUM), -+ const0_rtx), -+ gen_rtx_SET (VOIDmode, -+ operands[0], -+ (gen_rtx_MINUS (SImode, -+ const0_rtx, -+ operands[1]))))); -+ } -+ else -+ { -+ /* Emit the pattern: -+ eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31 -+ */ -+ emit_insn (gen_rtx_SET (VOIDmode, -+ operands[0], -+ gen_rtx_XOR (SImode, -+ gen_rtx_ASHIFTRT (SImode, -+ operands[1], -+ GEN_INT (31)), -+ operands[1]))); -+ emit_insn (gen_rtx_SET (VOIDmode, -+ operands[0], -+ gen_rtx_MINUS (SImode, -+ gen_rtx_ASHIFTRT (SImode, -+ operands[1], -+ GEN_INT (31)), -+ operands[0]))); -+ } -+ DONE; -+ } - [(set_attr "conds" "clob,*") - (set_attr "shift" "1") - (set_attr "predicable" "no, yes") -@@ -4330,7 +4885,7 @@ - [(set_attr "length" "*,8,8,*") - (set_attr "predicable" "no,yes,yes,no") - (set_attr "neon_type" "neon_int_1,*,*,neon_int_1") -- (set_attr "arch" "neon_nota8,*,*,neon_onlya8")] -+ (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits")] + "mvn%d5\\t%0, %1\;%I6%D5\\t%0, %2, %3" + [(set_attr "conds" "use") +- (set_attr "insn" "mvn") ++ (set_attr "type" "mvn_reg") + (set_attr "length" "8")] ) - (define_expand "one_cmplsi2" -@@ -4498,7 +5053,7 @@ - "TARGET_32BIT " - "#" - [(set_attr "length" "8,4,8,8") -- (set_attr "arch" "neon_nota8,*,*,neon_onlya8") -+ (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits") - (set_attr "ce_count" "2") - (set_attr "predicable" "yes")] +@@ -10396,7 +11636,7 @@ + "TARGET_ARM" + "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3" + [(set_attr "conds" "use") +- (set_attr "insn" "mvn") ++ (set_attr "type" "mvn_reg") + (set_attr "length" "8")] ) -@@ -4513,7 +5068,7 @@ - (set_attr "ce_count" "2") - (set_attr "shift" "1") - (set_attr "predicable" "yes") -- (set_attr "arch" "neon_nota8,*,a,t,neon_onlya8")] -+ (set_attr "arch" "neon_for_64bits,*,a,t,avoid_neon_for_64bits")] + +@@ -10844,7 +12084,7 @@ + mvn%D4\\t%0, %2 + mov%d4\\t%0, %1\;mvn%D4\\t%0, %2" + [(set_attr "conds" "use") +- (set_attr "insn" "mvn") ++ (set_attr "type" "mvn_reg") + (set_attr "length" "4,8")] ) - ;; Splits for all extensions to DImode -@@ -5313,8 +5868,8 @@ +@@ -11239,7 +12479,7 @@ + "TARGET_32BIT && arm_arch5" + "clz%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "insn" "clz")]) ++ (set_attr "type" "clz")]) + + (define_insn "rbitsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") +@@ -11247,7 +12487,7 @@ + "TARGET_32BIT && arm_arch_thumb2" + "rbit%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "insn" "clz")]) ++ (set_attr "type" "clz")]) + + (define_expand "ctzsi2" + [(set (match_operand:SI 0 "s_register_operand" "") +@@ -11280,6 +12520,7 @@ + (const_int 0)])] + "TARGET_32BIT" + "" ++[(set_attr "predicated" "yes")] ) - (define_insn "*arm_movdi" -- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") -- (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] -+ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, q, m") -+ (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,q"))] - "TARGET_32BIT - && !(TARGET_HARD_FLOAT && TARGET_VFP) - && !TARGET_IWMMXT -@@ -6738,8 +7293,8 @@ + (define_insn "force_register_use" +@@ -11399,7 +12640,8 @@ + "arm_arch_thumb2" + "movt%?\t%0, %L1" + [(set_attr "predicable" "yes") +- (set_attr "length" "4")] ++ (set_attr "predicable_short_it" "no") ++ (set_attr "length" "4")] ) - (define_insn "*movdf_soft_insn" -- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m") -- (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))] -+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,q,m") -+ (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,q"))] - "TARGET_32BIT && TARGET_SOFT_FLOAT - && ( register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" -@@ -6869,10 +7424,18 @@ - (match_operand:BLK 1 "general_operand" "") - (match_operand:SI 2 "const_int_operand" "") - (match_operand:SI 3 "const_int_operand" "")] -- "TARGET_EITHER" -+ "" - " - if (TARGET_32BIT) - { -+ if (TARGET_LDRD && current_tune->prefer_ldrd_strd -+ && !optimize_function_for_size_p (cfun)) -+ { -+ if (gen_movmem_ldrd_strd (operands)) -+ DONE; -+ FAIL; -+ } + (define_insn "*arm_rev" +@@ -11550,7 +12792,8 @@ + false, true))" + "ldrd%?\t%0, %3, [%1, %2]" + [(set_attr "type" "load2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb2_ldrd_base" + [(set (match_operand:SI 0 "s_register_operand" "=r") +@@ -11564,7 +12807,8 @@ + operands[1], 0, false, true))" + "ldrd%?\t%0, %2, [%1]" + [(set_attr "type" "load2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb2_ldrd_base_neg" + [(set (match_operand:SI 0 "s_register_operand" "=r") +@@ -11578,7 +12822,8 @@ + operands[1], -4, false, true))" + "ldrd%?\t%0, %2, [%1, #-4]" + [(set_attr "type" "load2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb2_strd" + [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk") +@@ -11595,7 +12840,8 @@ + false, false))" + "strd%?\t%2, %4, [%0, %1]" + [(set_attr "type" "store2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb2_strd_base" + [(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk")) +@@ -11609,7 +12855,8 @@ + operands[0], 0, false, false))" + "strd%?\t%1, %2, [%0]" + [(set_attr "type" "store2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + (define_insn "*thumb2_strd_base_neg" + [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk") +@@ -11623,9 +12870,13 @@ + operands[0], -4, false, false))" + "strd%?\t%1, %2, [%0, #-4]" + [(set_attr "type" "store2") +- (set_attr "predicable" "yes")]) ++ (set_attr "predicable" "yes") ++ (set_attr "predicable_short_it" "no")]) + + ++;; Load the load/store double peephole optimizations. ++(include "ldrdstrd.md") + - if (arm_gen_movmemqi (operands)) - DONE; - FAIL; -@@ -7617,23 +8180,64 @@ - ;; if-conversion can not reduce to a conditional compare, so we do - ;; that directly. + ;; Load the load/store multiple patterns + (include "ldmstm.md") + +--- a/src/gcc/config/arm/fmp626.md ++++ b/src/gcc/config/arm/fmp626.md +@@ -63,12 +63,15 @@ + ;; ALU operations + (define_insn_reservation "mp626_alu_op" 1 + (and (eq_attr "tune" "fmp626") +- (eq_attr "type" "alu_reg,simple_alu_imm")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg")) + "fmp626_core") + + (define_insn_reservation "mp626_alu_shift_op" 2 + (and (eq_attr "tune" "fmp626") +- (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) ++ (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\ ++ mov_shift,mov_shift_reg,\ ++ mvn_shift,mvn_shift_reg")) + "fmp626_core") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +@@ -77,22 +80,22 @@ + + (define_insn_reservation "mp626_mult1" 2 + (and (eq_attr "tune" "fmp626") +- (eq_attr "insn" "smulwy,smlawy,smulxy,smlaxy")) ++ (eq_attr "type" "smulwy,smlawy,smulxy,smlaxy")) + "fmp626_core") + + (define_insn_reservation "mp626_mult2" 2 + (and (eq_attr "tune" "fmp626") +- (eq_attr "insn" "mul,mla")) ++ (eq_attr "type" "mul,mla")) + "fmp626_core") + + (define_insn_reservation "mp626_mult3" 3 + (and (eq_attr "tune" "fmp626") +- (eq_attr "insn" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx")) ++ (eq_attr "type" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx")) + "fmp626_core*2") + + (define_insn_reservation "mp626_mult4" 4 + (and (eq_attr "tune" "fmp626") +- (eq_attr "insn" "smulls,smlals,umulls,umlals")) ++ (eq_attr "type" "smulls,smlals,umulls,umlals")) + "fmp626_core*3") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/fa526.md ++++ b/src/gcc/config/arm/fa526.md +@@ -62,12 +62,15 @@ + ;; ALU operations + (define_insn_reservation "526_alu_op" 1 + (and (eq_attr "tune" "fa526") +- (eq_attr "type" "alu_reg,simple_alu_imm")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg")) + "fa526_core") + + (define_insn_reservation "526_alu_shift_op" 2 + (and (eq_attr "tune" "fa526") +- (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) ++ (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\ ++ mov_shift,mov_shift_reg,\ ++ mvn_shift,mvn_shift_reg")) + "fa526_core") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +@@ -76,12 +79,12 @@ + + (define_insn_reservation "526_mult1" 2 + (and (eq_attr "tune" "fa526") +- (eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy")) ++ (eq_attr "type" "smlalxy,smulxy,smlaxy,smlalxy")) + "fa526_core") + + (define_insn_reservation "526_mult2" 5 + (and (eq_attr "tune" "fa526") +- (eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\ ++ (eq_attr "type" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\ + umlals,smulls,smlals,smlawx")) + "fa526_core*4") + +--- a/src/gcc/config/arm/arm-generic.md ++++ b/src/gcc/config/arm/arm-generic.md +@@ -114,7 +114,9 @@ + + (define_insn_reservation "mult" 16 + (and (eq_attr "generic_sched" "yes") +- (and (eq_attr "ldsched" "no") (eq_attr "type" "mult"))) ++ (and (eq_attr "ldsched" "no") ++ (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes")))) + "core*16") + + (define_insn_reservation "mult_ldsched_strongarm" 3 +@@ -122,7 +124,8 @@ + (and (eq_attr "ldsched" "yes") + (and (eq_attr "tune" + "strongarm,strongarm110,strongarm1100,strongarm1110") +- (eq_attr "type" "mult")))) ++ (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes"))))) + "core*2") + + (define_insn_reservation "mult_ldsched" 4 +@@ -130,13 +133,17 @@ + (and (eq_attr "ldsched" "yes") + (and (eq_attr "tune" + "!strongarm,strongarm110,strongarm1100,strongarm1110") +- (eq_attr "type" "mult")))) ++ (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes"))))) + "core*4") + + (define_insn_reservation "multi_cycle" 32 + (and (eq_attr "generic_sched" "yes") + (and (eq_attr "core_cycles" "multi") +- (eq_attr "type" "!mult,load_byte,load1,load2,load3,load4,store1,store2,store3,store4"))) ++ (and (eq_attr "type" "!load_byte,load1,load2,load3,load4,\ ++ store1,store2,store3,store4") ++ (not (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes")))))) + "core*32") + + (define_insn_reservation "single_cycle" 1 +--- a/src/gcc/config/arm/iwmmxt2.md ++++ b/src/gcc/config/arm/iwmmxt2.md +@@ -24,7 +24,7 @@ + "TARGET_REALLY_IWMMXT" + "wabs%?\\t%0, %1" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wabs")] ++ (set_attr "type" "wmmx_wabs")] + ) + + (define_insn "iwmmxt_wabsdiffb" +@@ -37,7 +37,7 @@ + "TARGET_REALLY_IWMMXT" + "wabsdiffb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wabsdiff")] ++ (set_attr "type" "wmmx_wabsdiff")] + ) + + (define_insn "iwmmxt_wabsdiffh" +@@ -50,7 +50,7 @@ + "TARGET_REALLY_IWMMXT" + "wabsdiffh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wabsdiff")] ++ (set_attr "type" "wmmx_wabsdiff")] + ) + + (define_insn "iwmmxt_wabsdiffw" +@@ -63,7 +63,7 @@ + "TARGET_REALLY_IWMMXT" + "wabsdiffw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wabsdiff")] ++ (set_attr "type" "wmmx_wabsdiff")] + ) + + (define_insn "iwmmxt_waddsubhx" +@@ -81,7 +81,7 @@ + "TARGET_REALLY_IWMMXT" + "waddsubhx%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "waddsubhx")] ++ (set_attr "type" "wmmx_waddsubhx")] + ) + + (define_insn "iwmmxt_wsubaddhx" +@@ -99,7 +99,7 @@ + "TARGET_REALLY_IWMMXT" + "wsubaddhx%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wsubaddhx")] ++ (set_attr "type" "wmmx_wsubaddhx")] + ) + + (define_insn "addc3" +@@ -111,7 +111,7 @@ + "TARGET_REALLY_IWMMXT" + "waddc%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wadd")] ++ (set_attr "type" "wmmx_wadd")] + ) + + (define_insn "iwmmxt_avg4" +@@ -143,7 +143,7 @@ + "TARGET_REALLY_IWMMXT" + "wavg4%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wavg4")] ++ (set_attr "type" "wmmx_wavg4")] + ) + + (define_insn "iwmmxt_avg4r" +@@ -175,7 +175,7 @@ + "TARGET_REALLY_IWMMXT" + "wavg4r%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wavg4")] ++ (set_attr "type" "wmmx_wavg4")] + ) + + (define_insn "iwmmxt_wmaddsx" +@@ -194,7 +194,7 @@ + "TARGET_REALLY_IWMMXT" + "wmaddsx%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmadd")] ++ (set_attr "type" "wmmx_wmadd")] + ) + + (define_insn "iwmmxt_wmaddux" +@@ -213,7 +213,7 @@ + "TARGET_REALLY_IWMMXT" + "wmaddux%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmadd")] ++ (set_attr "type" "wmmx_wmadd")] + ) + + (define_insn "iwmmxt_wmaddsn" +@@ -232,7 +232,7 @@ + "TARGET_REALLY_IWMMXT" + "wmaddsn%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmadd")] ++ (set_attr "type" "wmmx_wmadd")] + ) + + (define_insn "iwmmxt_wmaddun" +@@ -251,7 +251,7 @@ + "TARGET_REALLY_IWMMXT" + "wmaddun%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmadd")] ++ (set_attr "type" "wmmx_wmadd")] + ) + + (define_insn "iwmmxt_wmulwsm" +@@ -265,7 +265,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulwsm%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmulw")] ++ (set_attr "type" "wmmx_wmulw")] + ) + + (define_insn "iwmmxt_wmulwum" +@@ -279,7 +279,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulwum%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmulw")] ++ (set_attr "type" "wmmx_wmulw")] + ) + + (define_insn "iwmmxt_wmulsmr" +@@ -297,7 +297,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulsmr%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmul")] ++ (set_attr "type" "wmmx_wmul")] + ) + + (define_insn "iwmmxt_wmulumr" +@@ -316,7 +316,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulumr%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmul")] ++ (set_attr "type" "wmmx_wmul")] + ) + + (define_insn "iwmmxt_wmulwsmr" +@@ -333,7 +333,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulwsmr%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmul")] ++ (set_attr "type" "wmmx_wmul")] + ) + + (define_insn "iwmmxt_wmulwumr" +@@ -350,7 +350,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulwumr%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmulw")] ++ (set_attr "type" "wmmx_wmulw")] + ) + + (define_insn "iwmmxt_wmulwl" +@@ -361,7 +361,7 @@ + "TARGET_REALLY_IWMMXT" + "wmulwl%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmulw")] ++ (set_attr "type" "wmmx_wmulw")] + ) + + (define_insn "iwmmxt_wqmulm" +@@ -371,7 +371,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmulm%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmulm")] ++ (set_attr "type" "wmmx_wqmulm")] + ) + + (define_insn "iwmmxt_wqmulwm" +@@ -381,7 +381,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmulwm%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmulwm")] ++ (set_attr "type" "wmmx_wqmulwm")] + ) + + (define_insn "iwmmxt_wqmulmr" +@@ -391,7 +391,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmulmr%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmulm")] ++ (set_attr "type" "wmmx_wqmulm")] + ) + + (define_insn "iwmmxt_wqmulwmr" +@@ -401,7 +401,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmulwmr%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmulwm")] ++ (set_attr "type" "wmmx_wqmulwm")] + ) + + (define_insn "iwmmxt_waddbhusm" +@@ -417,7 +417,7 @@ + "TARGET_REALLY_IWMMXT" + "waddbhusm%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "waddbhus")] ++ (set_attr "type" "wmmx_waddbhus")] + ) + + (define_insn "iwmmxt_waddbhusl" +@@ -433,7 +433,7 @@ + "TARGET_REALLY_IWMMXT" + "waddbhusl%?\\t%0, %1, %2" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "waddbhus")] ++ (set_attr "type" "wmmx_waddbhus")] + ) --(define_insn "*arm_cmpdi_insn" -+(define_insn_and_split "*arm_cmpdi_insn" - [(set (reg:CC_NCV CC_REGNUM) - (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r") - (match_operand:DI 1 "arm_di_operand" "rDi"))) - (clobber (match_scratch:SI 2 "=r"))] - "TARGET_32BIT" -- "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1" -+ "#" ; "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1" -+ "&& reload_completed" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 0) (match_dup 1))) -+ (parallel [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 3) (match_dup 4))) -+ (set (match_dup 2) -+ (minus:SI (match_dup 5) -+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))])] -+ { -+ operands[3] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ if (CONST_INT_P (operands[1])) -+ { -+ operands[4] = GEN_INT (~INTVAL (gen_highpart_mode (SImode, -+ DImode, -+ operands[1]))); -+ operands[5] = gen_rtx_PLUS (SImode, operands[3], operands[4]); -+ } -+ else -+ { -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[5] = gen_rtx_MINUS (SImode, operands[3], operands[4]); -+ } -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ operands[2] = gen_lowpart (SImode, operands[2]); -+ } - [(set_attr "conds" "set") - (set_attr "length" "8")] + (define_insn "iwmmxt_wqmiabb" +@@ -446,7 +446,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmiabb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmiaxy")] ++ (set_attr "type" "wmmx_wqmiaxy")] ) --(define_insn "*arm_cmpdi_unsigned" -+(define_insn_and_split "*arm_cmpdi_unsigned" - [(set (reg:CC_CZ CC_REGNUM) - (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r") - (match_operand:DI 1 "arm_di_operand" "rDi")))] - "TARGET_32BIT" -- "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1" -+ "#" ; "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1" -+ "&& reload_completed" -+ [(set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 2) (match_dup 3))) -+ (cond_exec (eq:SI (reg:CC CC_REGNUM) (const_int 0)) -+ (set (reg:CC CC_REGNUM) -+ (compare:CC (match_dup 0) (match_dup 1))))] -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[0] = gen_lowpart (SImode, operands[0]); -+ if (CONST_INT_P (operands[1])) -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ else -+ operands[3] = gen_highpart (SImode, operands[1]); -+ operands[1] = gen_lowpart (SImode, operands[1]); -+ } - [(set_attr "conds" "set") - (set_attr "length" "8")] + (define_insn "iwmmxt_wqmiabt" +@@ -459,7 +459,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmiabt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmiaxy")] ++ (set_attr "type" "wmmx_wqmiaxy")] ) -@@ -7758,36 +8362,56 @@ - operands[3] = const0_rtx;" + + (define_insn "iwmmxt_wqmiatb" +@@ -472,7 +472,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmiatb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmiaxy")] ++ (set_attr "type" "wmmx_wqmiaxy")] ) --(define_insn "*mov_scc" -+(define_insn_and_split "*mov_scc" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (match_operator:SI 1 "arm_comparison_operator" - [(match_operand 2 "cc_register" "") (const_int 0)]))] - "TARGET_ARM" -- "mov%D1\\t%0, #0\;mov%d1\\t%0, #1" -+ "#" ; "mov%D1\\t%0, #0\;mov%d1\\t%0, #1" -+ "TARGET_ARM" -+ [(set (match_dup 0) -+ (if_then_else:SI (match_dup 1) -+ (const_int 1) -+ (const_int 0)))] -+ "" - [(set_attr "conds" "use") -- (set_attr "insn" "mov") - (set_attr "length" "8")] + (define_insn "iwmmxt_wqmiatt" +@@ -485,7 +485,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmiatt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmiaxy")] ++ (set_attr "type" "wmmx_wqmiaxy")] ) --(define_insn "*mov_negscc" -+(define_insn_and_split "*mov_negscc" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (neg:SI (match_operator:SI 1 "arm_comparison_operator" - [(match_operand 2 "cc_register" "") (const_int 0)])))] - "TARGET_ARM" -- "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" -+ "#" ; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" -+ "TARGET_ARM" -+ [(set (match_dup 0) -+ (if_then_else:SI (match_dup 1) -+ (match_dup 3) -+ (const_int 0)))] -+ { -+ operands[3] = GEN_INT (~0); -+ } - [(set_attr "conds" "use") -- (set_attr "insn" "mov") - (set_attr "length" "8")] + (define_insn "iwmmxt_wqmiabbn" +@@ -498,7 +498,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmiabbn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmiaxy")] ++ (set_attr "type" "wmmx_wqmiaxy")] ) --(define_insn "*mov_notscc" -+(define_insn_and_split "*mov_notscc" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (not:SI (match_operator:SI 1 "arm_comparison_operator" - [(match_operand 2 "cc_register" "") (const_int 0)])))] - "TARGET_ARM" -- "mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1" -+ "#" ; "mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1" -+ "TARGET_ARM" -+ [(set (match_dup 0) -+ (if_then_else:SI (match_dup 1) -+ (match_dup 3) -+ (match_dup 4)))] -+ { -+ operands[3] = GEN_INT (~1); -+ operands[4] = GEN_INT (~0); -+ } - [(set_attr "conds" "use") -- (set_attr "insn" "mov") - (set_attr "length" "8")] + (define_insn "iwmmxt_wqmiabtn" +@@ -511,7 +511,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmiabtn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmiaxy")] ++ (set_attr "type" "wmmx_wqmiaxy")] ) -@@ -8110,7 +8734,40 @@ - }" + (define_insn "iwmmxt_wqmiatbn" +@@ -524,7 +524,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmiatbn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmiaxy")] ++ (set_attr "type" "wmmx_wqmiaxy")] ) --(define_insn "*movsicc_insn" -+(define_insn "*cmov" -+ [(set (match_operand:SDF 0 "s_register_operand" "=") -+ (if_then_else:SDF (match_operator 1 "arm_vsel_comparison_operator" -+ [(match_operand 2 "cc_register" "") (const_int 0)]) -+ (match_operand:SDF 3 "s_register_operand" -+ "") -+ (match_operand:SDF 4 "s_register_operand" -+ "")))] -+ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " -+ "* -+ { -+ enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]); -+ switch (code) -+ { -+ case ARM_GE: -+ case ARM_GT: -+ case ARM_EQ: -+ case ARM_VS: -+ return \"vsel%d1.\\t%0, %3, %4\"; -+ case ARM_LT: -+ case ARM_LE: -+ case ARM_NE: -+ case ARM_VC: -+ return \"vsel%D1.\\t%0, %4, %3\"; -+ default: -+ gcc_unreachable (); -+ } -+ return \"\"; -+ }" -+ [(set_attr "conds" "use") -+ (set_attr "type" "f_sel")] -+) -+ -+(define_insn_and_split "*movsicc_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") - (if_then_else:SI - (match_operator 3 "arm_comparison_operator" -@@ -8123,10 +8780,45 @@ - mvn%D3\\t%0, #%B2 - mov%d3\\t%0, %1 - mvn%d3\\t%0, #%B1 -- mov%d3\\t%0, %1\;mov%D3\\t%0, %2 -- mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 -- mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 -- mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" -+ # -+ # -+ # -+ #" -+ ; alt4: mov%d3\\t%0, %1\;mov%D3\\t%0, %2 -+ ; alt5: mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 -+ ; alt6: mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 -+ ; alt7: mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" -+ "&& reload_completed" -+ [(const_int 0)] -+ { -+ enum rtx_code rev_code; -+ enum machine_mode mode; -+ rtx rev_cond; -+ -+ emit_insn (gen_rtx_COND_EXEC (VOIDmode, -+ operands[3], -+ gen_rtx_SET (VOIDmode, -+ operands[0], -+ operands[1]))); -+ -+ rev_code = GET_CODE (operands[3]); -+ mode = GET_MODE (operands[4]); -+ if (mode == CCFPmode || mode == CCFPEmode) -+ rev_code = reverse_condition_maybe_unordered (rev_code); -+ else -+ rev_code = reverse_condition (rev_code); -+ -+ rev_cond = gen_rtx_fmt_ee (rev_code, -+ VOIDmode, -+ operands[4], -+ const0_rtx); -+ emit_insn (gen_rtx_COND_EXEC (VOIDmode, -+ rev_cond, -+ gen_rtx_SET (VOIDmode, -+ operands[0], -+ operands[2]))); -+ DONE; -+ } - [(set_attr "length" "4,4,4,4,8,8,8,8") - (set_attr "conds" "use") - (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn") -@@ -9095,27 +9787,64 @@ - (set_attr "type" "alu_shift,alu_shift_reg")]) - + (define_insn "iwmmxt_wqmiattn" +@@ -537,7 +537,7 @@ + "TARGET_REALLY_IWMMXT" + "wqmiattn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wqmiaxy")] ++ (set_attr "type" "wmmx_wqmiaxy")] + ) --(define_insn "*and_scc" -+(define_insn_and_split "*and_scc" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (and:SI (match_operator:SI 1 "arm_comparison_operator" -- [(match_operand 3 "cc_register" "") (const_int 0)]) -- (match_operand:SI 2 "s_register_operand" "r")))] -+ [(match_operand 2 "cc_register" "") (const_int 0)]) -+ (match_operand:SI 3 "s_register_operand" "r")))] - "TARGET_ARM" -- "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" -+ "#" ; "mov%D1\\t%0, #0\;and%d1\\t%0, %3, #1" -+ "&& reload_completed" -+ [(cond_exec (match_dup 5) (set (match_dup 0) (const_int 0))) -+ (cond_exec (match_dup 4) (set (match_dup 0) -+ (and:SI (match_dup 3) (const_int 1))))] -+ { -+ enum machine_mode mode = GET_MODE (operands[2]); -+ enum rtx_code rc = GET_CODE (operands[1]); -+ -+ /* Note that operands[4] is the same as operands[1], -+ but with VOIDmode as the result. */ -+ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); -+ if (mode == CCFPmode || mode == CCFPEmode) -+ rc = reverse_condition_maybe_unordered (rc); -+ else -+ rc = reverse_condition (rc); -+ operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); -+ } - [(set_attr "conds" "use") - (set_attr "insn" "mov") - (set_attr "length" "8")] + (define_insn "iwmmxt_wmiabb" +@@ -561,7 +561,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiabb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiaxy")] ++ (set_attr "type" "wmmx_wmiaxy")] + ) + + (define_insn "iwmmxt_wmiabt" +@@ -585,7 +585,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiabt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiaxy")] ++ (set_attr "type" "wmmx_wmiaxy")] + ) + + (define_insn "iwmmxt_wmiatb" +@@ -609,7 +609,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiatb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiaxy")] ++ (set_attr "type" "wmmx_wmiaxy")] + ) + + (define_insn "iwmmxt_wmiatt" +@@ -633,7 +633,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiatt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiaxy")] ++ (set_attr "type" "wmmx_wmiaxy")] ) --(define_insn "*ior_scc" -+(define_insn_and_split "*ior_scc" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") -- (ior:SI (match_operator:SI 2 "arm_comparison_operator" -- [(match_operand 3 "cc_register" "") (const_int 0)]) -- (match_operand:SI 1 "s_register_operand" "0,?r")))] -+ (ior:SI (match_operator:SI 1 "arm_comparison_operator" -+ [(match_operand 2 "cc_register" "") (const_int 0)]) -+ (match_operand:SI 3 "s_register_operand" "0,?r")))] - "TARGET_ARM" - "@ -- orr%d2\\t%0, %1, #1 -- mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" -+ orr%d1\\t%0, %3, #1 -+ #" -+ "&& reload_completed -+ && REGNO (operands [0]) != REGNO (operands[3])" -+ ;; && which_alternative == 1 -+ ; mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1 -+ [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3))) -+ (cond_exec (match_dup 4) (set (match_dup 0) -+ (ior:SI (match_dup 3) (const_int 1))))] -+ { -+ enum machine_mode mode = GET_MODE (operands[2]); -+ enum rtx_code rc = GET_CODE (operands[1]); -+ -+ /* Note that operands[4] is the same as operands[1], -+ but with VOIDmode as the result. */ -+ operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); -+ if (mode == CCFPmode || mode == CCFPEmode) -+ rc = reverse_condition_maybe_unordered (rc); -+ else -+ rc = reverse_condition (rc); -+ operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx); -+ } - [(set_attr "conds" "use") - (set_attr "length" "4,8")] + (define_insn "iwmmxt_wmiabbn" +@@ -657,7 +657,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiabbn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiaxy")] ++ (set_attr "type" "wmmx_wmiaxy")] ) -@@ -9822,24 +10551,75 @@ - "") - ;; ??? The conditional patterns above need checking for Thumb-2 usefulness --(define_insn "*negscc" -+(define_insn_and_split "*negscc" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (neg:SI (match_operator 3 "arm_comparison_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rI")]))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" -- "* -- if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx) -- return \"mov\\t%0, %1, asr #31\"; -+ "#" -+ "&& reload_completed" -+ [(const_int 0)] -+ { -+ rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); + (define_insn "iwmmxt_wmiabtn" +@@ -681,7 +681,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiabtn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiaxy")] ++ (set_attr "type" "wmmx_wmiaxy")] + ) -- if (GET_CODE (operands[3]) == NE) -- return \"subs\\t%0, %1, %2\;mvnne\\t%0, #0\"; -+ if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx) -+ { -+ /* Emit mov\\t%0, %1, asr #31 */ -+ emit_insn (gen_rtx_SET (VOIDmode, -+ operands[0], -+ gen_rtx_ASHIFTRT (SImode, -+ operands[1], -+ GEN_INT (31)))); -+ DONE; -+ } -+ else if (GET_CODE (operands[3]) == NE) -+ { -+ /* Emit subs\\t%0, %1, %2\;mvnne\\t%0, #0 */ -+ if (CONST_INT_P (operands[2])) -+ emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2], -+ GEN_INT (- INTVAL (operands[2])))); -+ else -+ emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2])); + (define_insn "iwmmxt_wmiatbn" +@@ -705,7 +705,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiatbn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiaxy")] ++ (set_attr "type" "wmmx_wmiaxy")] + ) -- output_asm_insn (\"cmp\\t%1, %2\", operands); -- output_asm_insn (\"mov%D3\\t%0, #0\", operands); -- return \"mvn%d3\\t%0, #0\"; -- " -+ emit_insn (gen_rtx_COND_EXEC (VOIDmode, -+ gen_rtx_NE (SImode, -+ cc_reg, -+ const0_rtx), -+ gen_rtx_SET (SImode, -+ operands[0], -+ GEN_INT (~0)))); -+ DONE; -+ } -+ else -+ { -+ /* Emit: cmp\\t%1, %2\;mov%D3\\t%0, #0\;mvn%d3\\t%0, #0 */ -+ emit_insn (gen_rtx_SET (VOIDmode, -+ cc_reg, -+ gen_rtx_COMPARE (CCmode, operands[1], operands[2]))); -+ enum rtx_code rc = GET_CODE (operands[3]); -+ -+ rc = reverse_condition (rc); -+ emit_insn (gen_rtx_COND_EXEC (VOIDmode, -+ gen_rtx_fmt_ee (rc, -+ VOIDmode, -+ cc_reg, -+ const0_rtx), -+ gen_rtx_SET (VOIDmode, operands[0], const0_rtx))); -+ rc = GET_CODE (operands[3]); -+ emit_insn (gen_rtx_COND_EXEC (VOIDmode, -+ gen_rtx_fmt_ee (rc, -+ VOIDmode, -+ cc_reg, -+ const0_rtx), -+ gen_rtx_SET (VOIDmode, -+ operands[0], -+ GEN_INT (~0)))); -+ DONE; -+ } -+ FAIL; -+ } - [(set_attr "conds" "clob") - (set_attr "length" "12")] + (define_insn "iwmmxt_wmiattn" +@@ -729,7 +729,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiattn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiaxy")] ++ (set_attr "type" "wmmx_wmiaxy")] ) -@@ -11280,6 +12060,7 @@ - (const_int 0)])] - "TARGET_32BIT" - "" -+[(set_attr "predicated" "yes")] + + (define_insn "iwmmxt_wmiawbb" +@@ -742,7 +742,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiawbb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiawxy")] ++ (set_attr "type" "wmmx_wmiawxy")] ) - (define_insn "force_register_use" -@@ -11626,6 +12407,9 @@ - (set_attr "predicable" "yes")]) + (define_insn "iwmmxt_wmiawbt" +@@ -755,7 +755,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiawbt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiawxy")] ++ (set_attr "type" "wmmx_wmiawxy")] + ) + (define_insn "iwmmxt_wmiawtb" +@@ -768,7 +768,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiawtb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiawxy")] ++ (set_attr "type" "wmmx_wmiawxy")] + ) -+;; Load the load/store double peephole optimizations. -+(include "ldrdstrd.md") -+ - ;; Load the load/store multiple patterns - (include "ldmstm.md") + (define_insn "iwmmxt_wmiawtt" +@@ -781,7 +781,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiawtt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiawxy")] ++ (set_attr "type" "wmmx_wmiawxy")] + ) + + (define_insn "iwmmxt_wmiawbbn" +@@ -794,7 +794,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiawbbn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiawxy")] ++ (set_attr "type" "wmmx_wmiawxy")] + ) + + (define_insn "iwmmxt_wmiawbtn" +@@ -807,7 +807,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiawbtn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiawxy")] ++ (set_attr "type" "wmmx_wmiawxy")] + ) + + (define_insn "iwmmxt_wmiawtbn" +@@ -820,7 +820,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiawtbn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiawxy")] ++ (set_attr "type" "wmmx_wmiawxy")] + ) + + (define_insn "iwmmxt_wmiawttn" +@@ -833,7 +833,7 @@ + "TARGET_REALLY_IWMMXT" + "wmiawttn%?\\t%0, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmiawxy")] ++ (set_attr "type" "wmmx_wmiawxy")] + ) + + (define_insn "iwmmxt_wmerge" +@@ -858,7 +858,7 @@ + "TARGET_REALLY_IWMMXT" + "wmerge%?\\t%0, %1, %2, %3" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "wmerge")] ++ (set_attr "type" "wmmx_wmerge")] + ) + + (define_insn "iwmmxt_tandc3" +@@ -868,7 +868,7 @@ + "TARGET_REALLY_IWMMXT" + "tandc%?\\t r15" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "tandc")] ++ (set_attr "type" "wmmx_tandc")] + ) + + (define_insn "iwmmxt_torc3" +@@ -878,7 +878,7 @@ + "TARGET_REALLY_IWMMXT" + "torc%?\\t r15" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "torc")] ++ (set_attr "type" "wmmx_torc")] + ) + + (define_insn "iwmmxt_torvsc3" +@@ -888,7 +888,7 @@ + "TARGET_REALLY_IWMMXT" + "torvsc%?\\t r15" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "torvsc")] ++ (set_attr "type" "wmmx_torvsc")] + ) + (define_insn "iwmmxt_textrc3" +@@ -899,5 +899,5 @@ + "TARGET_REALLY_IWMMXT" + "textrc%?\\t r15, %0" + [(set_attr "predicable" "yes") +- (set_attr "wtype" "textrc")] ++ (set_attr "type" "wmmx_textrc")] + ) +--- a/src/gcc/config/arm/cortex-a5.md ++++ b/src/gcc/config/arm/cortex-a5.md +@@ -58,12 +58,15 @@ + + (define_insn_reservation "cortex_a5_alu" 2 + (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "alu_reg,simple_alu_imm")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg")) + "cortex_a5_ex1") + + (define_insn_reservation "cortex_a5_alu_shift" 2 + (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) ++ (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\ ++ mov_shift,mov_shift_reg,\ ++ mvn_shift,mvn_shift_reg")) + "cortex_a5_ex1") + + ;; Forwarding path for unshifted operands. +@@ -80,7 +83,8 @@ + + (define_insn_reservation "cortex_a5_mul" 2 + (and (eq_attr "tune" "cortexa5") +- (eq_attr "type" "mult")) ++ (ior (eq_attr "mul32" "yes") ++ (eq_attr "mul64" "yes"))) + "cortex_a5_ex1") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/fa606te.md ++++ b/src/gcc/config/arm/fa606te.md +@@ -62,7 +62,10 @@ + ;; ALU operations + (define_insn_reservation "606te_alu_op" 1 + (and (eq_attr "tune" "fa606te") +- (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg, ++ extend,arlo_shift,arlo_shift_reg,\ ++ mov_imm,mov_reg,mov_shift,mov_shift_reg,\ ++ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) + "fa606te_core") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +@@ -71,22 +74,22 @@ + + (define_insn_reservation "606te_mult1" 2 + (and (eq_attr "tune" "fa606te") +- (eq_attr "insn" "smlalxy")) ++ (eq_attr "type" "smlalxy")) + "fa606te_core") + + (define_insn_reservation "606te_mult2" 3 + (and (eq_attr "tune" "fa606te") +- (eq_attr "insn" "smlaxy,smulxy,smulwy,smlawy")) ++ (eq_attr "type" "smlaxy,smulxy,smulwy,smlawy")) + "fa606te_core*2") + + (define_insn_reservation "606te_mult3" 4 + (and (eq_attr "tune" "fa606te") +- (eq_attr "insn" "mul,mla,muls,mlas")) ++ (eq_attr "type" "mul,mla,muls,mlas")) + "fa606te_core*3") + + (define_insn_reservation "606te_mult4" 5 + (and (eq_attr "tune" "fa606te") +- (eq_attr "insn" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals")) ++ (eq_attr "type" "umull,umlal,smull,smlal,umulls,umlals,smulls,smlals")) + "fa606te_core*4") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +--- a/src/gcc/config/arm/cortex-a9.md ++++ b/src/gcc/config/arm/cortex-a9.md +@@ -80,18 +80,17 @@ + ;; which can go down E2 without any problem. + (define_insn_reservation "cortex_a9_dp" 2 + (and (eq_attr "tune" "cortexa9") +- (ior (and (eq_attr "type" "alu_reg,simple_alu_imm") +- (eq_attr "neon_type" "none")) +- (and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift") +- (eq_attr "insn" "mov")) +- (eq_attr "neon_type" "none")))) ++ (and (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg,\ ++ mov_shift_reg,mov_shift") ++ (eq_attr "neon_type" "none"))) + "cortex_a9_p0_default|cortex_a9_p1_default") + + ;; An instruction using the shifter will go down E1. + (define_insn_reservation "cortex_a9_dp_shift" 3 + (and (eq_attr "tune" "cortexa9") +- (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift") +- (not (eq_attr "insn" "mov")))) ++ (eq_attr "type" "arlo_shift_reg,extend,arlo_shift,\ ++ mvn_shift,mvn_shift_reg")) + "cortex_a9_p0_shift | cortex_a9_p1_shift") + + ;; Loads have a latency of 4 cycles. +@@ -130,29 +129,29 @@ + ;; We get 16*16 multiply / mac results in 3 cycles. + (define_insn_reservation "cortex_a9_mult16" 3 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "insn" "smulxy")) ++ (eq_attr "type" "smulxy")) + "cortex_a9_mult16") + + ;; The 16*16 mac is slightly different that it + ;; reserves M1 and M2 in the same cycle. + (define_insn_reservation "cortex_a9_mac16" 3 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "insn" "smlaxy")) ++ (eq_attr "type" "smlaxy")) + "cortex_a9_mac16") + + (define_insn_reservation "cortex_a9_multiply" 4 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "insn" "mul,smmul,smmulr")) ++ (eq_attr "type" "mul,smmul,smmulr")) + "cortex_a9_mult") + + (define_insn_reservation "cortex_a9_mac" 4 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "insn" "mla,smmla")) ++ (eq_attr "type" "mla,smmla")) + "cortex_a9_mac") + + (define_insn_reservation "cortex_a9_multiply_long" 5 + (and (eq_attr "tune" "cortexa9") +- (eq_attr "insn" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals")) ++ (eq_attr "type" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals")) + "cortex_a9_mult_long") + + ;; An instruction with a result in E2 can be forwarded +--- a/src/gcc/config/arm/fa626te.md ++++ b/src/gcc/config/arm/fa626te.md +@@ -68,12 +68,15 @@ + ;; ALU operations + (define_insn_reservation "626te_alu_op" 1 + (and (eq_attr "tune" "fa626,fa626te") +- (eq_attr "type" "alu_reg,simple_alu_imm")) ++ (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\ ++ mov_imm,mov_reg,mvn_imm,mvn_reg")) + "fa626te_core") + + (define_insn_reservation "626te_alu_shift_op" 2 + (and (eq_attr "tune" "fa626,fa626te") +- (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) ++ (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\ ++ mov_shift,mov_shift_reg,\ ++ mvn_shift,mvn_shift_reg")) + "fa626te_core") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +@@ -82,22 +85,22 @@ + + (define_insn_reservation "626te_mult1" 2 + (and (eq_attr "tune" "fa626,fa626te") +- (eq_attr "insn" "smulwy,smlawy,smulxy,smlaxy")) ++ (eq_attr "type" "smulwy,smlawy,smulxy,smlaxy")) + "fa626te_core") + + (define_insn_reservation "626te_mult2" 2 + (and (eq_attr "tune" "fa626,fa626te") +- (eq_attr "insn" "mul,mla")) ++ (eq_attr "type" "mul,mla")) + "fa626te_core") + + (define_insn_reservation "626te_mult3" 3 + (and (eq_attr "tune" "fa626,fa626te") +- (eq_attr "insn" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx")) ++ (eq_attr "type" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx")) + "fa626te_core*2") + + (define_insn_reservation "626te_mult4" 4 + (and (eq_attr "tune" "fa626,fa626te") +- (eq_attr "insn" "smulls,smlals,umulls,umlals")) ++ (eq_attr "type" "smulls,smlals,umulls,umlals")) + "fa626te_core*3") + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; --- a/src/gcc/config/arm/neon-gen.ml +++ b/src/gcc/config/arm/neon-gen.ml @@ -121,6 +121,7 @@ @@ -23199,9 +38353,36 @@ "__builtin_neon_sf", "float", 32, 2; "__builtin_neon_poly8", "poly", 8, 8; "__builtin_neon_poly16", "poly", 16, 4; +--- a/src/gcc/config/mips/linux-common.h ++++ b/src/gcc/config/mips/linux-common.h +@@ -44,7 +44,7 @@ + #undef LIB_SPEC + #define LIB_SPEC \ + LINUX_OR_ANDROID_LD (GNU_USER_TARGET_LIB_SPEC, \ +- GNU_USER_TARGET_LIB_SPEC " " ANDROID_LIB_SPEC) ++ GNU_USER_TARGET_NO_PTHREADS_LIB_SPEC " " ANDROID_LIB_SPEC) + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ --- a/src/libobjc/ChangeLog.linaro +++ b/src/libobjc/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -23215,7 +38396,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libgfortran/ChangeLog.linaro +++ b/src/libgfortran/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -23229,7 +38426,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libada/ChangeLog.linaro +++ b/src/libada/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -23243,7 +38456,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libffi/ChangeLog.linaro +++ b/src/libffi/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -23257,7 +38486,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libssp/ChangeLog.linaro +++ b/src/libssp/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -23269,12 +38514,62 @@ +2013-04-09 Matthew Gretton-Dann + + * GCC Linaro 4.8-2013.04 released. +--- a/src/libcpp/configure ++++ b/src/libcpp/configure +@@ -7152,9 +7152,7 @@ + case $target in + aarch64*-*-* | \ + alpha*-*-* | \ +- arm*-*-*eabi* | \ +- arm*-*-rtems* | \ +- arm*-*-symbianelf* | \ ++ arm*-*-* | \ + x86_64-*-* | \ + ia64-*-* | \ + hppa*64*-*-* | \ +--- a/src/libcpp/configure.ac ++++ b/src/libcpp/configure.ac +@@ -184,9 +184,7 @@ + case $target in + aarch64*-*-* | \ + alpha*-*-* | \ +- arm*-*-*eabi* | \ +- arm*-*-rtems* | \ +- arm*-*-symbianelf* | \ ++ arm*-*-* | \ + x86_64-*-* | \ + ia64-*-* | \ + hppa*64*-*-* | \ --- a/src/libcpp/ChangeLog.linaro +++ b/src/libcpp/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,35 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-09-05 Yvan Roux ++ ++ Backport from trunk r201566. ++ 2013-08-07 Richard Earnshaw ++ ++ * configure.ac: Set need_64bit_hwint for all arm targets. ++ * configure: Regenerated. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + -+ GCC Linaro gcc-linaro-4.8-2013.06 released. ++ GCC Linaro gcc-linaro-4.8-2013.06 released. + +2013-05-14 Matthew Gretton-Dann + @@ -23285,7 +38580,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/libcpp/po/ChangeLog.linaro +++ b/src/libcpp/po/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. @@ -23299,7 +38610,23 @@ + * GCC Linaro 4.8-2013.04 released. --- a/src/fixincludes/ChangeLog.linaro +++ b/src/fixincludes/ChangeLog.linaro -@@ -0,0 +1,11 @@ +@@ -0,0 +1,27 @@ ++2013-09-10 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.09 released. ++ ++2013-08-14 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.08 released. ++ ++2013-07-19 Matthew Gretton-Dann ++ ++ GCC Linaro 4.8-2013.07-1 released. ++ ++2013-07-05 Christophe Lyon ++ ++ GCC Linaro 4.8-2013.07 released. ++ +2013-06-11 Rob Savoye + + GCC Linaro gcc-linaro-4.8-2013.06 released. diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-multiarch.diff gcc-4.8-4.8.2/debian/patches/gcc-multiarch.diff --- gcc-4.8-4.8.1/debian/patches/gcc-multiarch.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-multiarch.diff 2013-10-17 15:57:25.000000000 +0000 @@ -13,6 +13,31 @@ * config/s390/t-linux64: Set MULTIARCH_DIRNAME. * config/sparc/t-linux64: Set MULTIARCH_DIRNAME. +--- a/src/libstdc++-v3/python/hook.in ++++ b/src/libstdc++-v3/python/hook.in +@@ -47,14 +47,18 @@ + libdir = libdir[len (prefix):] + + # Compute the ".."s needed to get from libdir to the prefix. +- dotdots = ('..' + os.sep) * len (libdir.split (os.sep)) ++ backdirs = len (libdir.split (os.sep)) ++ if not os.path.basename(os.path.dirname(__file__)).startswith('lib'): ++ backdirs += 1 # multiarch subdir ++ dotdots = ('..' + os.sep) * backdirs + + objfile = gdb.current_objfile ().filename + dir_ = os.path.join (os.path.dirname (objfile), dotdots, pythondir) + +- if not dir_ in sys.path: ++ if not objfile.startswith('/usr/lib/debug/') and not dir_ in sys.path: + sys.path.insert(0, dir_) + + # Load the pretty-printers. +-from libstdcxx.v6.printers import register_libstdcxx_printers +-register_libstdcxx_printers (gdb.current_objfile ()) ++if gdb.current_objfile () is None or not gdb.current_objfile ().filename.startswith ('/usr/lib/debug/'): ++ from libstdcxx.v6.printers import register_libstdcxx_printers ++ register_libstdcxx_printers (gdb.current_objfile ()) Index: b/src/gcc/config/sh/t-linux =================================================================== --- a/src/gcc/config/sh/t-linux @@ -98,29 +123,24 @@ MULTILIB_OSDIRNAMES := $(filter-out mx32=%,$(subst linux,$(KFREEBSD_OS),$(MULTILIB_OSDIRNAMES))) + +MULTIARCH_DIRNAME := $(subst linux,$(KFREEBSD_OS),$(MULTIARCH_DIRNAME)) -Index: b/src/gcc/config/mips/t-linux64 -=================================================================== ---- a/src/gcc/config/mips/t-linux64 -+++ b/src/gcc/config/mips/t-linux64 -@@ -24,3 +24,13 @@ - ../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \ - ../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \ - ../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) -+ -+ifneq (,$(findstring abin32,$(target))) -+MULTIARCH_DIRNAME = $(call if_multiarch,mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) -+else -+ifneq (,$(findstring abi64,$(target))) -+MULTIARCH_DIRNAME = $(call if_multiarch,mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) -+else -+MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) -+endif -+endif Index: b/src/gcc/config.gcc =================================================================== --- a/src/gcc/config.gcc +++ b/src/gcc/config.gcc -@@ -3707,7 +3707,7 @@ +@@ -1799,8 +1799,11 @@ + mips64*-*-linux* | mipsisa64*-*-linux*) + tm_file="dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} mips/gnu-user.h mips/gnu-user64.h mips/linux64.h mips/linux-common.h" + tmake_file="${tmake_file} mips/t-linux64" +- tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_N32" ++ tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_64" + case ${target} in ++ *gnuabin32*) ++ tm_defines=$(echo ${tm_defines}| sed 's/MIPS_ABI_DEFAULT=ABI_64/MIPS_ABI_DEFAULT=ABI_N32/g') ++ ;; + mips64el-st-linux-gnu) + tm_file="${tm_file} mips/st.h" + tmake_file="${tmake_file} mips/t-st" +@@ -3709,7 +3712,7 @@ i[34567]86-*-darwin* | x86_64-*-darwin*) ;; i[34567]86-*-linux* | x86_64-*-linux*) @@ -156,7 +176,7 @@ =================================================================== --- a/src/gcc/Makefile.in +++ b/src/gcc/Makefile.in -@@ -1838,7 +1838,7 @@ +@@ -1829,7 +1829,7 @@ "$(MULTILIB_EXCLUSIONS)" \ "$(MULTILIB_OSDIRNAMES)" \ "$(MULTILIB_REQUIRED)" \ diff -Nru gcc-4.8-4.8.1/debian/patches/gcc-multilib-multiarch.diff gcc-4.8-4.8.2/debian/patches/gcc-multilib-multiarch.diff --- gcc-4.8-4.8.1/debian/patches/gcc-multilib-multiarch.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/gcc-multilib-multiarch.diff 2013-10-17 15:57:25.000000000 +0000 @@ -79,3 +79,36 @@ ifneq (,$(findstring x86_64,$(target))) ifneq (,$(findstring biarchx32.h,$(tm_include_list))) +Index: b/src/gcc/config/mips/t-linux64 +=================================================================== +--- a/src/gcc/config/mips/t-linux64 ++++ b/src/gcc/config/mips/t-linux64 +@@ -20,7 +20,28 @@ + MULTILIB_DIRNAMES = n32 32 64 + MIPS_EL = $(if $(filter %el, $(firstword $(subst -, ,$(target)))),el) + MIPS_SOFT = $(if $(strip $(filter MASK_SOFT_FLOAT_ABI, $(target_cpu_default)) $(filter soft, $(with_float))),soft) ++ ++ifneq (,$(findstring gnuabi64,$(target))) ++MULTILIB_OSDIRNAMES = \ ++ ../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \ ++ ../libo32$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \ ++ ../lib$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) ++else ifneq (,$(findstring gnuabin32,$(target))) ++MULTILIB_OSDIRNAMES = \ ++ ../lib$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \ ++ ../libo32$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \ ++ ../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) ++else + MULTILIB_OSDIRNAMES = \ + ../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \ + ../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \ + ../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) ++endif ++ ++ifneq (,$(findstring gnuabi64,$(target))) ++ MULTIARCH_DIRNAME = $(call if_multiarch,mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) ++else ifneq (,$(findstring gnuabin32,$(target))) ++ MULTIARCH_DIRNAME = $(call if_multiarch,mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) ++else ++ MULTIARCH_DIRNAME = $(call if_multiarch,mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) ++endif diff -Nru gcc-4.8-4.8.1/debian/patches/libffi-m68k.diff gcc-4.8-4.8.2/debian/patches/libffi-m68k.diff --- gcc-4.8-4.8.1/debian/patches/libffi-m68k.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/libffi-m68k.diff 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,141 @@ +# DP: Apply #660525 fix to in-tree libffi + +--- a/src/libffi/src/m68k/sysv.S ++++ b/src/libffi/src/m68k/sysv.S +@@ -2,9 +2,10 @@ + + sysv.S - Copyright (c) 2012 Alan Hourihane + Copyright (c) 1998, 2012 Andreas Schwab +- Copyright (c) 2008 Red Hat, Inc. +- +- m68k Foreign Function Interface ++ Copyright (c) 2008 Red Hat, Inc. ++ Copyright (c) 2012 Thorsten Glaser ++ ++ m68k Foreign Function Interface + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the +@@ -168,8 +169,28 @@ retstruct1: + + retstruct2: + btst #7,%d2 +- jbeq noretval ++ jbeq retsint8 + move.w %d0,(%a1) ++ jbra epilogue ++ ++retsint8: ++ btst #8,%d2 ++ jbeq retsint16 ++ | NOTE: On the mc68000, extb is not supported. 8->16, then 16->32. ++#if !defined(__mc68020__) && !defined(__mc68030__) && !defined(__mc68040__) && !defined(__mc68060__) && !defined(__mcoldfire__) ++ ext.w %d0 ++ ext.l %d0 ++#else ++ extb.l %d0 ++#endif ++ move.l %d0,(%a1) ++ jbra epilogue ++ ++retsint16: ++ btst #9,%d2 ++ jbeq noretval ++ ext.l %d0 ++ move.l %d0,(%a1) + + noretval: + epilogue: +@@ -201,8 +222,10 @@ CALLFUNC(ffi_closure_SYSV): + lsr.l #1,%d0 + jne 1f + jcc .Lcls_epilogue ++ | CIF_FLAGS_INT + move.l -12(%fp),%d0 + .Lcls_epilogue: ++ | no CIF_FLAGS_* + unlk %fp + rts + 1: +@@ -210,6 +233,7 @@ CALLFUNC(ffi_closure_SYSV): + lsr.l #2,%d0 + jne 1f + jcs .Lcls_ret_float ++ | CIF_FLAGS_DINT + move.l (%a0)+,%d0 + move.l (%a0),%d1 + jra .Lcls_epilogue +@@ -224,6 +248,7 @@ CALLFUNC(ffi_closure_SYSV): + lsr.l #2,%d0 + jne 1f + jcs .Lcls_ret_ldouble ++ | CIF_FLAGS_DOUBLE + #if defined(__MC68881__) || defined(__HAVE_68881__) + fmove.d (%a0),%fp0 + #else +@@ -242,17 +267,37 @@ CALLFUNC(ffi_closure_SYSV): + jra .Lcls_epilogue + 1: + lsr.l #2,%d0 +- jne .Lcls_ret_struct2 ++ jne 1f + jcs .Lcls_ret_struct1 ++ | CIF_FLAGS_POINTER + move.l (%a0),%a0 + move.l %a0,%d0 + jra .Lcls_epilogue + .Lcls_ret_struct1: + move.b (%a0),%d0 + jra .Lcls_epilogue +-.Lcls_ret_struct2: ++1: ++ lsr.l #2,%d0 ++ jne 1f ++ jcs .Lcls_ret_sint8 ++ | CIF_FLAGS_STRUCT2 + move.w (%a0),%d0 + jra .Lcls_epilogue ++.Lcls_ret_sint8: ++ move.l (%a0),%d0 ++ | NOTE: On the mc68000, extb is not supported. 8->16, then 16->32. ++#if !defined(__mc68020__) && !defined(__mc68030__) && !defined(__mc68040__) && !defined(__mc68060__) && !defined(__mcoldfire__) ++ ext.w %d0 ++ ext.l %d0 ++#else ++ extb.l %d0 ++#endif ++ jra .Lcls_epilogue ++1: ++ | CIF_FLAGS_SINT16 ++ move.l (%a0),%d0 ++ ext.l %d0 ++ jra .Lcls_epilogue + CFI_ENDPROC() + + .size CALLFUNC(ffi_closure_SYSV),.-CALLFUNC(ffi_closure_SYSV) +--- a/src/libffi/src/m68k/ffi.c ++++ b/src/libffi/src/m68k/ffi.c +@@ -123,6 +123,8 @@ ffi_prep_args (void *stack, extended_cif + #define CIF_FLAGS_POINTER 32 + #define CIF_FLAGS_STRUCT1 64 + #define CIF_FLAGS_STRUCT2 128 ++#define CIF_FLAGS_SINT8 256 ++#define CIF_FLAGS_SINT16 512 + + /* Perform machine dependent cif processing */ + ffi_status +@@ -200,6 +202,14 @@ ffi_prep_cif_machdep (ffi_cif *cif) + cif->flags = CIF_FLAGS_DINT; + break; + ++ case FFI_TYPE_SINT16: ++ cif->flags = CIF_FLAGS_SINT16; ++ break; ++ ++ case FFI_TYPE_SINT8: ++ cif->flags = CIF_FLAGS_SINT8; ++ break; ++ + default: + cif->flags = CIF_FLAGS_INT; + break; diff -Nru gcc-4.8-4.8.1/debian/patches/libjava-testsuite.diff gcc-4.8-4.8.2/debian/patches/libjava-testsuite.diff --- gcc-4.8-4.8.1/debian/patches/libjava-testsuite.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/libjava-testsuite.diff 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,6 @@ +# DP: Mark libjava sourcelocation test as failing. PR libjava/55637 + +--- a/src/libjava/testsuite/libjava.lang/sourcelocation.xfail ++++ b/src/libjava/testsuite/libjava.lang/sourcelocation.xfail +@@ -0,0 +1 @@ ++xfail-output diff -Nru gcc-4.8-4.8.1/debian/patches/libstdc++-no-testsuite.diff gcc-4.8-4.8.2/debian/patches/libstdc++-no-testsuite.diff --- gcc-4.8-4.8.1/debian/patches/libstdc++-no-testsuite.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/libstdc++-no-testsuite.diff 2013-10-17 15:57:25.000000000 +0000 @@ -7,7 +7,7 @@ # Run the testsuite in normal mode. check-DEJAGNU $(check_DEJAGNU_normal_targets): check-DEJAGNU%: site.exp -+ case "$(target)" in arm*|hppa*|ia64*|mipsel*) exit 0;; esac; \ ++ case "$(target)" in hppa*|ia64*|mipsel*) exit 0;; esac; \ AR="$(AR)"; export AR; \ RANLIB="$(RANLIB)"; export RANLIB; \ if [ -z "$*$(filter-out --target_board=%, $(RUNTESTFLAGS))" ] \ diff -Nru gcc-4.8-4.8.1/debian/patches/libstdc++-python3.diff gcc-4.8-4.8.2/debian/patches/libstdc++-python3.diff --- gcc-4.8-4.8.1/debian/patches/libstdc++-python3.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/libstdc++-python3.diff 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,167 @@ +# DP: Make the libstdc++-v3 pretty printer compatible with Python3. + +--- a/src/libstdc++-v3/python/libstdcxx/v6/printers.py ++++ b/src/libstdc++-v3/python/libstdcxx/v6/printers.py +@@ -51,7 +51,7 @@ + # anything fancier here. + field = typ.fields()[0] + if not field.is_base_class: +- raise ValueError, "Cannot find type %s::%s" % (str(orig), name) ++ raise ValueError("Cannot find type %s::%s" % (str(orig), name)) + typ = field.type + + class SharedPointerPrinter: +@@ -97,7 +97,7 @@ + def __iter__(self): + return self + +- def next(self): ++ def __next__(self): + if self.base == self.head: + raise StopIteration + elt = self.base.cast(self.nodetype).dereference() +@@ -144,7 +144,7 @@ + def __iter__(self): + return self + +- def next(self): ++ def __next__(self): + if self.base == 0: + raise StopIteration + elt = self.base.cast(self.nodetype).dereference() +@@ -198,7 +198,7 @@ + def __iter__(self): + return self + +- def next(self): ++ def __next__(self): + count = self.count + self.count = self.count + 1 + if self.bitvec: +@@ -276,20 +276,20 @@ + # Set the actual head to the first pair. + self.head = self.head.cast (nodes[0].type) + elif len (nodes) != 0: +- raise ValueError, "Top of tuple tree does not consist of a single node." ++ raise ValueError("Top of tuple tree does not consist of a single node.") + self.count = 0 + + def __iter__ (self): + return self + +- def next (self): ++ def __next__ (self): + nodes = self.head.type.fields () + # Check for further recursions in the inheritance tree. + if len (nodes) == 0: + raise StopIteration + # Check that this iteration has an expected structure. + if len (nodes) != 2: +- raise ValueError, "Cannot parse more than 2 nodes in a tuple tree." ++ raise ValueError("Cannot parse more than 2 nodes in a tuple tree.") + + # - Left node is the next recursion parent. + # - Right node is the actual class contained in the tuple. +@@ -353,7 +353,7 @@ + def __len__(self): + return int (self.size) + +- def next(self): ++ def __next__(self): + if self.count == self.size: + raise StopIteration + result = self.node +@@ -414,9 +414,9 @@ + def __iter__(self): + return self + +- def next(self): ++ def __next__(self): + if self.count % 2 == 0: +- n = self.rbiter.next() ++ n = next(self.rbiter) + n = n.cast(self.type).dereference()['_M_value_field'] + self.pair = n + item = n['first'] +@@ -456,8 +456,8 @@ + def __iter__(self): + return self + +- def next(self): +- item = self.rbiter.next() ++ def __next__(self): ++ item = next(self.rbiter) + item = item.cast(self.type).dereference()['_M_value_field'] + # FIXME: this is weird ... what to do? + # Maybe a 'set' display hint? +@@ -534,7 +534,7 @@ + def __iter__(self): + return self + +- def next(self): ++ def __next__(self): + if self.p == self.last: + raise StopIteration + +@@ -572,7 +572,7 @@ + + size = self.buffer_size * delta_n + delta_s + delta_e + +- return '%s with %d elements' % (self.typename, long (size)) ++ return '%s with %d elements' % (self.typename, int (size)) + + def children(self): + start = self.val['_M_impl']['_M_start'] +@@ -627,7 +627,7 @@ + def __iter__ (self): + return self + +- def next (self): ++ def __next__ (self): + if self.node == 0: + raise StopIteration + node = self.node.cast(self.node_type) +@@ -655,8 +655,8 @@ + return '[%d]' % i + + def children (self): +- counter = itertools.imap (self.format_count, itertools.count()) +- return itertools.izip (counter, Tr1HashtableIterator (self.hashtable())) ++ counter = map (self.format_count, itertools.count()) ++ return zip (counter, Tr1HashtableIterator (self.hashtable())) + + class Tr1UnorderedMapPrinter: + "Print a tr1::unordered_map" +@@ -688,11 +688,11 @@ + return '[%d]' % i + + def children (self): +- counter = itertools.imap (self.format_count, itertools.count()) ++ counter = map (self.format_count, itertools.count()) + # Map over the hash table and flatten the result. +- data = self.flatten (itertools.imap (self.format_one, Tr1HashtableIterator (self.hashtable()))) ++ data = self.flatten (map (self.format_one, Tr1HashtableIterator (self.hashtable()))) + # Zip the two iterators together. +- return itertools.izip (counter, data) ++ return zip (counter, data) + + def display_hint (self): + return 'map' +@@ -709,7 +709,7 @@ + def __iter__(self): + return self + +- def next(self): ++ def __next__(self): + if self.base == 0: + raise StopIteration + elt = self.base.cast(self.nodetype).dereference() +@@ -764,7 +764,7 @@ + # A small sanity check. + # FIXME + if not self.compiled_rx.match(name + '<>'): +- raise ValueError, 'libstdc++ programming error: "%s" does not match' % name ++ raise ValueError('libstdc++ programming error: "%s" does not match' % name) + printer = RxPrinter(name, function) + self.subprinters.append(printer) + self.lookup[name] = printer diff -Nru gcc-4.8-4.8.1/debian/patches/m68k-revert-pr45144.diff gcc-4.8-4.8.2/debian/patches/m68k-revert-pr45144.diff --- gcc-4.8-4.8.1/debian/patches/m68k-revert-pr45144.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/m68k-revert-pr45144.diff 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,18 @@ +[revert the minor PR45144 missed-optimization fix because it + results in miscompilation of gnat on m68k with gcc-4.6 and 4.5; + with gcc-4.7 other changes mask the issue ] + + PR ada/48835 + +--- a/src/gcc/tree-sra.c ++++ b/src/gcc/tree-sra.c +@@ -916,9 +916,6 @@ type_consists_of_records_p (tree type) + { + tree ft = TREE_TYPE (fld); + +- if (DECL_BIT_FIELD (fld)) +- return false; +- + if (!is_gimple_reg_type (ft) + && !type_consists_of_records_p (ft)) + return false; diff -Nru gcc-4.8-4.8.1/debian/patches/pr49847.diff gcc-4.8-4.8.2/debian/patches/pr49847.diff --- gcc-4.8-4.8.1/debian/patches/pr49847.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/pr49847.diff 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,28 @@ +gcc/ + +2012-02-26 Mikael Pettersson + + PR rtl-optimization/49847 + * cse.c (fold_rtx) : If prev_insn_cc0 is zero + don't call equiv_constant on it. + +--- a/src/gcc/cse.c ++++ b/src/gcc/cse.c +@@ -3194,9 +3194,14 @@ fold_rtx (rtx x, rtx insn) + + #ifdef HAVE_cc0 + case CC0: +- folded_arg = prev_insn_cc0; +- mode_arg = prev_insn_cc0_mode; +- const_arg = equiv_constant (folded_arg); ++ if (!prev_insn_cc0) ++ const_arg = 0; ++ else ++ { ++ folded_arg = prev_insn_cc0; ++ mode_arg = prev_insn_cc0_mode; ++ const_arg = equiv_constant (folded_arg); ++ } + break; + #endif + diff -Nru gcc-4.8-4.8.1/debian/patches/pr52714.diff gcc-4.8-4.8.2/debian/patches/pr52714.diff --- gcc-4.8-4.8.1/debian/patches/pr52714.diff 1970-01-01 00:00:00.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/pr52714.diff 2013-10-17 15:57:25.000000000 +0000 @@ -0,0 +1,68 @@ +# DP: Proposed fix for PR rtl-optimization/52714: +# DP: Revert gcc 4.8 to gcc the 4.5 version of the PR rtl-optimization/45695 fix: + +--- a/src/gcc/combine.c ++++ b/src/gcc/combine.c +@@ -3690,41 +3690,42 @@ try_combine (rtx i3, rtx i2, rtx i1, rtx + && GET_CODE (XVECEXP (newpat, 0, 1)) == SET + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT + && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART ++ && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), ++ DF_INSN_LUID (i2)) + && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), + XVECEXP (newpat, 0, 0)) + && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), + XVECEXP (newpat, 0, 1)) + && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) +- && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) ++ && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))) ++#ifdef HAVE_cc0 ++ /* We cannot split the parallel into two sets if both sets ++ reference cc0. */ ++ && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)) ++ && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))) ++#endif ++ ) + { + /* Normally, it doesn't matter which of the two is done first, +- but the one that references cc0 can't be the second, and +- one which uses any regs/memory set in between i2 and i3 can't ++ but it does if one references cc0. In that case, it has to + be first. */ +- if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), +- DF_INSN_LUID (i2)) +-#ifdef HAVE_cc0 +- && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)) +-#endif +- ) +- { +- newi2pat = XVECEXP (newpat, 0, 1); +- newpat = XVECEXP (newpat, 0, 0); +- } +- else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)), +- DF_INSN_LUID (i2)) + #ifdef HAVE_cc0 +- && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)) +-#endif +- ) ++ if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) + { ++ if (use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)), ++ DF_INSN_LUID (i2))) ++ { ++ undo_all (); ++ return 0; ++ } + newi2pat = XVECEXP (newpat, 0, 0); + newpat = XVECEXP (newpat, 0, 1); + } + else ++#endif + { +- undo_all (); +- return 0; ++ newi2pat = XVECEXP (newpat, 0, 1); ++ newpat = XVECEXP (newpat, 0, 0); + } + + i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); diff -Nru gcc-4.8-4.8.1/debian/patches/pr57878.diff gcc-4.8-4.8.2/debian/patches/pr57878.diff --- gcc-4.8-4.8.1/debian/patches/pr57878.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/pr57878.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,303 +0,0 @@ -gcc/ - -2013-07-19 Wei Mi - - Backport from mainline: - 2013-07-18 Vladimir Makarov - Wei Mi - - PR rtl-optimization/57878 - * lra-assigns.c (assign_by_spills): Move non_reload_pseudos to the - top. Promote lra_assert to gcc_assert. - (reload_pseudo_compare_func): Check regs first for reload pseudos. - -gcc/testsuite/ - -2013-07-19 Wei Mi - - Backport from mainline: - 2013-07-18 Wei Mi - - PR rtl-optimization/57878 - * g++.dg/pr57518.C: New test. - -Index: gcc/lra-assigns.c -=================================================================== ---- a/src/gcc/lra-assigns.c (revision 201067) -+++ a/src/gcc/lra-assigns.c (revision 201068) -@@ -116,6 +116,11 @@ - /* Map regno to the corresponding regno assignment info. */ - static struct regno_assign_info *regno_assign_info; - -+/* All inherited, subreg or optional pseudos created before last spill -+ sub-pass. Such pseudos are permitted to get memory instead of hard -+ regs. */ -+static bitmap_head non_reload_pseudos; -+ - /* Process a pseudo copy with execution frequency COPY_FREQ connecting - REGNO1 and REGNO2 to form threads. */ - static void -@@ -194,6 +199,15 @@ - if ((diff = (ira_class_hard_regs_num[cl1] - - ira_class_hard_regs_num[cl2])) != 0) - return diff; -+ if ((diff -+ = (ira_reg_class_max_nregs[cl2][lra_reg_info[r2].biggest_mode] -+ - ira_reg_class_max_nregs[cl1][lra_reg_info[r1].biggest_mode])) != 0 -+ /* The code below executes rarely as nregs == 1 in most cases. -+ So we should not worry about using faster data structures to -+ check reload pseudos. */ -+ && ! bitmap_bit_p (&non_reload_pseudos, r1) -+ && ! bitmap_bit_p (&non_reload_pseudos, r2)) -+ return diff; - if ((diff = (regno_assign_info[regno_assign_info[r2].first].freq - - regno_assign_info[regno_assign_info[r1].first].freq)) != 0) - return diff; -@@ -1156,7 +1170,6 @@ - rtx insn; - basic_block bb; - bitmap_head changed_insns, do_not_assign_nonreload_pseudos; -- bitmap_head non_reload_pseudos; - unsigned int u; - bitmap_iterator bi; - bool reload_p; -@@ -1265,7 +1278,7 @@ - } - } - } -- lra_assert (asm_p); -+ gcc_assert (asm_p); - break; - } - /* This is a very rare event. We can not assign a hard -Index: gcc/testsuite/g++.dg/pr57878.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/pr57878.C (revision 0) -+++ a/src/gcc/testsuite/g++.dg/pr57878.C (revision 201068) -@@ -0,0 +1,226 @@ -+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -+/* { dg-options "-m32 -O2 -fno-omit-frame-pointer -fPIC -std=gnu++11" } */ -+ -+typedef int int32; -+typedef long long int64; -+typedef unsigned int uint32; -+typedef unsigned long long uint64; -+namespace std { -+ typedef unsigned int size_t; -+ template -+ struct char_traits; -+ template -+ inline _Tp* __addressof(_Tp& __r) noexcept { -+ return reinterpret_cast<_Tp*> (&const_cast(reinterpret_cast(__r))); -+ } -+ template -+ struct remove_reference { -+ typedef _Tp type; -+ }; -+ template -+ constexpr _Tp&& forward(typename std::remove_reference<_Tp>::type& __t) noexcept { -+ return static_cast<_Tp&&>(__t); -+ } -+} -+typedef unsigned int size_t; -+extern "C++" { -+ inline void* operator new(std::size_t, void* __p) noexcept { -+ return __p; -+ } -+} -+namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) { -+ template -+ class new_allocator { -+ public: -+ typedef size_t size_type; -+ typedef _Tp* pointer; -+ }; -+} -+namespace std { -+ template -+ using __allocator_base = __gnu_cxx::new_allocator<_Tp>; -+ template -+ class allocator -+ : public __allocator_base<_Tp> { -+ public: -+ typedef size_t size_type; -+ template -+ struct rebind { -+ typedef allocator<_Tp1> other; -+ }; -+ }; -+} -+namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) { -+ template -+ class __sso_string_base; -+ template, typename _Alloc = std::allocator<_CharT>, template class _Base = __sso_string_base> -+ class __versa_string; -+ template -+ struct __vstring_utility { -+ typedef typename _Alloc::template rebind<_CharT>::other _CharT_alloc_type; -+ template -+ struct _Alloc_hider -+ : public _Alloc1 { -+ _Alloc_hider(const _Alloc1& __a, _CharT* __ptr) -+ : _Alloc1(__a), _M_p(__ptr) { -+ } -+ _CharT* _M_p; -+ }; -+ }; -+ template -+ class __sso_string_base -+ : protected __vstring_utility<_CharT, _Traits, _Alloc> { -+ typedef __vstring_utility<_CharT, _Traits, _Alloc> _Util_Base; -+ typedef typename _Util_Base::_CharT_alloc_type _CharT_alloc_type; -+ typedef typename _CharT_alloc_type::size_type size_type; -+ private: -+ typename _Util_Base::template _Alloc_hider<_CharT_alloc_type> -+ _M_dataplus; -+ size_type _M_string_length; -+ enum { -+ _S_local_capacity = 15 }; -+ union { -+ _CharT _M_local_data[_S_local_capacity + 1]; -+ }; -+ template -+ void _M_construct(_InIterator __beg, _InIterator __end); -+ public: -+ size_type _M_max_size() const; -+ _CharT* _M_data() const { -+ return _M_dataplus._M_p; -+ } -+ size_type _M_length() const { -+ return _M_string_length; -+ } -+ __sso_string_base(const __sso_string_base& __rcs); -+ const _CharT_alloc_type& _M_get_allocator() const { -+ } -+ }; -+ template -+ __sso_string_base<_CharT, _Traits, _Alloc>:: __sso_string_base(const __sso_string_base& __rcs) -+ : _M_dataplus(__rcs._M_get_allocator(), _M_local_data) { -+ _M_construct(__rcs._M_data(), __rcs._M_data() + __rcs._M_length()); -+ } -+ template class _Base> -+ class __versa_string -+ : private _Base<_CharT, _Traits, _Alloc> { -+ }; -+} -+template, typename _Alloc = std::allocator<_CharT> > -+class basic_string -+ : public __gnu_cxx::__versa_string<_CharT, _Traits, _Alloc> { -+}; -+typedef basic_string string; -+namespace std __attribute__ ((__visibility__ ("default"))) { -+ template -+ class __alloctr_rebind_helper { -+ public: -+ static const bool __value = true; -+ }; -+ template::__value> -+ struct __alloctr_rebind; -+ template struct __alloctr_rebind<_Alloc, _Tp, true> -+ { -+ typedef typename _Alloc::template rebind<_Tp>::other __type; -+ }; -+ template -+ struct allocator_traits { -+ private: -+ template -+ static typename _Tp::pointer _S_pointer_helper(_Tp*); -+ typedef decltype(_S_pointer_helper((_Alloc*)0)) __pointer; -+ public: -+ typedef __pointer pointer; -+ template -+ using rebind_alloc = typename __alloctr_rebind<_Alloc, _Tp>::__type; -+ }; -+} -+namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) { -+ template struct __alloc_traits -+ : std::allocator_traits<_Alloc> -+ { -+ typedef std::allocator_traits<_Alloc> _Base_type; -+ template -+ struct rebind { -+ typedef typename _Base_type::template rebind_alloc<_Tp> -+ other; -+ }; -+ }; -+} -+namespace std __attribute__ ((__visibility__ ("default"))) { -+ template -+ inline void _Construct(_T1* __p, _Args&&... __args) { -+ ::new(static_cast(__p)) _T1(std::forward<_Args>(__args)...); -+ } -+ template -+ struct _Vector_base { -+ typedef typename __gnu_cxx::__alloc_traits<_Alloc>::template rebind<_Tp>::other _Tp_alloc_type; -+ typedef typename __gnu_cxx::__alloc_traits<_Tp_alloc_type>::pointer pointer; -+ struct _Vector_impl -+ : public _Tp_alloc_type { -+ pointer _M_start; -+ pointer _M_finish; -+ }; -+ public: -+ _Vector_impl _M_impl; -+ }; -+ template > -+ class vector -+ : protected _Vector_base<_Tp, _Alloc> { -+ typedef _Vector_base<_Tp, _Alloc> _Base; -+ public: -+ typedef _Tp value_type; -+ typedef typename _Base::pointer pointer; -+ typedef size_t size_type; -+ size_type size() const; -+ void push_back(const value_type& __x) { -+ _M_emplace_back_aux(__x); -+ } -+ template -+ void _M_emplace_back_aux(_Args&&... __args); -+ size_type _M_check_len(); -+ }; -+ template template -+ void vector<_Tp, _Alloc>:: _M_emplace_back_aux(_Args&&... __args) { -+ const size_type __len = _M_check_len(); -+ pointer __new_start(static_cast(::operator new(__len * sizeof(_Tp)))); -+ pointer __new_temp(__new_start + size()); -+ ::new((void *)__new_temp) _Tp(std::forward<_Args>(__args)...); -+ pointer __cur = __new_start; -+ pointer __first = this->_M_impl._M_start; -+ pointer __last = this->_M_impl._M_finish; -+ for (; -+ __first != __last; -+ ++__first, ++__cur) std::_Construct(std::__addressof(*__cur), *__first); -+ } -+} -+using std::vector; -+class DL { -+public: -+ struct ChunkId { -+ int64 disk_id; -+ uint64 handle; -+ uint64 version; -+ string capability; -+ ChunkId(); -+ }; -+ struct ChunkInfo { -+ ChunkId id; -+ uint64 mtime; -+ uint32 length; -+ int32 space_used; -+ }; -+}; -+class FDB { -+ void CollectChunk(const DL::ChunkInfo& chunk, const int& location); -+private: -+ struct ChunkData { -+ int location; -+ DL::ChunkInfo chunk_info; -+ }; -+ vector chunk_data_; -+}; -+void FDB::CollectChunk(const DL::ChunkInfo& chunk, const int& location) { -+ ChunkData chunk_data; -+ chunk_data_.push_back( chunk_data); -+} diff -Nru gcc-4.8-4.8.1/debian/patches/pr57909.diff gcc-4.8-4.8.2/debian/patches/pr57909.diff --- gcc-4.8-4.8.1/debian/patches/pr57909.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/pr57909.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,30 +0,0 @@ -2013-07-19 Matthew Gretton-Dann - - Backport from trunk r201005. - 2013-07-17 Yvan Roux - - PR target/57909 - * config/arm/arm.c (gen_movmem_ldrd_strd): Fix unaligned load/store - usage in HI mode. - ---- a/src/gcc/config/arm/arm.c -+++ b/src/gcc/config/arm/arm.c -@@ -11965,8 +11965,16 @@ - dst = adjust_address (dst, HImode, 0); - src = adjust_address (src, HImode, 0); - reg0 = gen_reg_rtx (SImode); -- emit_insn (gen_unaligned_loadhiu (reg0, src)); -- emit_insn (gen_unaligned_storehi (dst, gen_lowpart (HImode, reg0))); -+ if (src_aligned) -+ emit_insn (gen_zero_extendhisi2 (reg0, src)); -+ else -+ emit_insn (gen_unaligned_loadhiu (reg0, src)); -+ -+ if (dst_aligned) -+ emit_insn (gen_movhi (dst, gen_lowpart(HImode, reg0))); -+ else -+ emit_insn (gen_unaligned_storehi (dst, gen_lowpart (HImode, reg0))); -+ - src = next_consecutive_mem (src); - dst = next_consecutive_mem (dst); - if (len == 2) diff -Nru gcc-4.8-4.8.1/debian/patches/svn-updates.diff gcc-4.8-4.8.2/debian/patches/svn-updates.diff --- gcc-4.8-4.8.1/debian/patches/svn-updates.diff 2013-10-17 15:57:22.000000000 +0000 +++ gcc-4.8-4.8.2/debian/patches/svn-updates.diff 2013-10-17 15:57:25.000000000 +0000 @@ -1,272617 +1,2093 @@ -# DP: updates from the 4.8 branch upto 20130717 (r200995). +# DP: updates from the 4.8 branch upto 20131017 (r203751). last_updated() { cat > ${dir}LAST_UPDATED </dev/null -+ @cd ${host_builddir}/../ext && {\ -+ $(LN_S) ${ext_host_headers} . || true ;\ -+ } 2>/dev/null - $(STAMP) stamp-host - - # Host includes dynamic. -@@ -1688,9 +1690,12 @@ - for file in ${profile_impl_headers}; do \ - $(INSTALL_DATA) $${file} $(DESTDIR)${gxx_include_dir}/${profile_impl_builddir}; done - $(mkinstalldirs) $(DESTDIR)${host_installdir} -- for file in ${host_headers} ${host_headers_extra} \ -+ for file in ${host_headers} ${bits_host_headers} ${host_headers_extra} \ - ${thread_host_headers}; do \ - $(INSTALL_DATA) $${file} $(DESTDIR)${host_installdir}; done -+ $(mkinstalldirs) $(DESTDIR)${host_installdir}/../ext -+ for file in ${ext_host_headers}; do \ -+ $(INSTALL_DATA) $${file} $(DESTDIR)${host_installdir}/../ext; done - - # To remove directories. - clean-local: -Index: libstdc++-v3/include/std/valarray -=================================================================== ---- a/src/libstdc++-v3/include/std/valarray (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/std/valarray (.../branches/gcc-4_8-branch) -@@ -819,8 +819,21 @@ - inline valarray<_Tp>& - valarray<_Tp>::operator=(const _Expr<_Dom, _Tp>& __e) - { -- _GLIBCXX_DEBUG_ASSERT(_M_size == __e.size()); -- std::__valarray_copy(__e, _M_size, _Array<_Tp>(_M_data)); -+ // _GLIBCXX_RESOLVE_LIB_DEFECTS -+ // 630. arrays of valarray. -+ if (_M_size == __e.size()) -+ std::__valarray_copy(__e, _M_size, _Array<_Tp>(_M_data)); -+ else -+ { -+ if (_M_data) -+ { -+ std::__valarray_destroy_elements(_M_data, _M_data + _M_size); -+ std::__valarray_release_memory(_M_data); -+ } -+ _M_size = __e.size(); -+ _M_data = __valarray_get_storage<_Tp>(_M_size); -+ std::__valarray_copy_construct(__e, _M_size, _Array<_Tp>(_M_data)); -+ } - return *this; - } - -Index: libstdc++-v3/include/std/complex +--- a/src/libstdc++-v3/include/debug/functions.h (.../tags/gcc_4_8_2_release) ++++ b/src/libstdc++-v3/include/debug/functions.h (.../branches/gcc-4_8-branch) +@@ -345,11 +345,13 @@ + return __check_sorted_set_aux(__first, __last, __pred, _SameType()); + } + ++ // _GLIBCXX_RESOLVE_LIB_DEFECTS ++ // 270. Binary search requirements overly strict ++ // Determine if a sequence is partitioned w.r.t. this element. + template + inline bool +- __check_partitioned_lower_aux(_ForwardIterator __first, +- _ForwardIterator __last, const _Tp& __value, +- std::forward_iterator_tag) ++ __check_partitioned_lower(_ForwardIterator __first, ++ _ForwardIterator __last, const _Tp& __value) + { + while (__first != __last && *__first < __value) + ++__first; +@@ -362,38 +364,11 @@ + return __first == __last; + } + +- // For performance reason, as the iterator range has been validated, check on +- // random access safe iterators is done using the base iterator. +- template +- inline bool +- __check_partitioned_lower_aux( +- const _Safe_iterator<_Iterator, _Sequence>& __first, +- const _Safe_iterator<_Iterator, _Sequence>& __last, +- const _Tp& __value, +- std::random_access_iterator_tag __tag) +- { +- return __check_partitioned_lower_aux(__first.base(), __last.base(), +- __value, __tag); +- } +- +- // _GLIBCXX_RESOLVE_LIB_DEFECTS +- // 270. Binary search requirements overly strict +- // Determine if a sequence is partitioned w.r.t. this element. + template + inline bool +- __check_partitioned_lower(_ForwardIterator __first, ++ __check_partitioned_upper(_ForwardIterator __first, + _ForwardIterator __last, const _Tp& __value) + { +- return __check_partitioned_lower_aux(__first, __last, __value, +- std::__iterator_category(__first)); +- } +- +- template +- inline bool +- __check_partitioned_upper_aux(_ForwardIterator __first, +- _ForwardIterator __last, const _Tp& __value, +- std::forward_iterator_tag) +- { + while (__first != __last && !(__value < *__first)) + ++__first; + if (__first != __last) +@@ -405,35 +380,12 @@ + return __first == __last; + } + +- // For performance reason, as the iterator range has been validated, check on +- // random access safe iterators is done using the base iterator. +- template +- inline bool +- __check_partitioned_upper_aux( +- const _Safe_iterator<_Iterator, _Sequence>& __first, +- const _Safe_iterator<_Iterator, _Sequence>& __last, +- const _Tp& __value, +- std::random_access_iterator_tag __tag) +- { +- return __check_partitioned_upper_aux(__first.base(), __last.base(), +- __value, __tag); +- } +- +- template +- inline bool +- __check_partitioned_upper(_ForwardIterator __first, +- _ForwardIterator __last, const _Tp& __value) +- { +- return __check_partitioned_upper_aux(__first, __last, __value, +- std::__iterator_category(__first)); +- } +- ++ // Determine if a sequence is partitioned w.r.t. this element. + template + inline bool +- __check_partitioned_lower_aux(_ForwardIterator __first, +- _ForwardIterator __last, const _Tp& __value, +- _Pred __pred, +- std::forward_iterator_tag) ++ __check_partitioned_lower(_ForwardIterator __first, ++ _ForwardIterator __last, const _Tp& __value, ++ _Pred __pred) + { + while (__first != __last && bool(__pred(*__first, __value))) + ++__first; +@@ -446,39 +398,12 @@ + return __first == __last; + } + +- // For performance reason, as the iterator range has been validated, check on +- // random access safe iterators is done using the base iterator. +- template +- inline bool +- __check_partitioned_lower_aux( +- const _Safe_iterator<_Iterator, _Sequence>& __first, +- const _Safe_iterator<_Iterator, _Sequence>& __last, +- const _Tp& __value, _Pred __pred, +- std::random_access_iterator_tag __tag) +- { +- return __check_partitioned_lower_aux(__first.base(), __last.base(), +- __value, __pred, __tag); +- } +- +- // Determine if a sequence is partitioned w.r.t. this element. + template + inline bool +- __check_partitioned_lower(_ForwardIterator __first, ++ __check_partitioned_upper(_ForwardIterator __first, + _ForwardIterator __last, const _Tp& __value, + _Pred __pred) + { +- return __check_partitioned_lower_aux(__first, __last, __value, __pred, +- std::__iterator_category(__first)); +- } +- +- template +- inline bool +- __check_partitioned_upper_aux(_ForwardIterator __first, +- _ForwardIterator __last, const _Tp& __value, +- _Pred __pred, +- std::forward_iterator_tag) +- { + while (__first != __last && !bool(__pred(__value, *__first))) + ++__first; + if (__first != __last) +@@ -490,31 +415,6 @@ + return __first == __last; + } + +- // For performance reason, as the iterator range has been validated, check on +- // random access safe iterators is done using the base iterator. +- template +- inline bool +- __check_partitioned_upper_aux( +- const _Safe_iterator<_Iterator, _Sequence>& __first, +- const _Safe_iterator<_Iterator, _Sequence>& __last, +- const _Tp& __value, _Pred __pred, +- std::random_access_iterator_tag __tag) +- { +- return __check_partitioned_upper_aux(__first.base(), __last.base(), +- __value, __pred, __tag); +- } +- +- template +- inline bool +- __check_partitioned_upper(_ForwardIterator __first, +- _ForwardIterator __last, const _Tp& __value, +- _Pred __pred) +- { +- return __check_partitioned_upper_aux(__first, __last, __value, __pred, +- std::__iterator_category(__first)); +- } +- + // Helper struct to detect random access safe iterators. + template + struct __is_safe_random_iterator +Index: libstdc++-v3/include/debug/macros.h +=================================================================== +--- a/src/libstdc++-v3/include/debug/macros.h (.../tags/gcc_4_8_2_release) ++++ b/src/libstdc++-v3/include/debug/macros.h (.../branches/gcc-4_8-branch) +@@ -261,8 +261,9 @@ + w.r.t. the value _Value. */ + #define __glibcxx_check_partitioned_lower(_First,_Last,_Value) \ + __glibcxx_check_valid_range(_First,_Last); \ +-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower(_First, _Last, \ +- _Value), \ ++_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower( \ ++ __gnu_debug::__base(_First), \ ++ __gnu_debug::__base(_Last), _Value), \ + _M_message(__gnu_debug::__msg_unpartitioned) \ + ._M_iterator(_First, #_First) \ + ._M_iterator(_Last, #_Last) \ +@@ -270,8 +271,9 @@ + + #define __glibcxx_check_partitioned_upper(_First,_Last,_Value) \ + __glibcxx_check_valid_range(_First,_Last); \ +-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper(_First, _Last, \ +- _Value), \ ++_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper( \ ++ __gnu_debug::__base(_First), \ ++ __gnu_debug::__base(_Last), _Value), \ + _M_message(__gnu_debug::__msg_unpartitioned) \ + ._M_iterator(_First, #_First) \ + ._M_iterator(_Last, #_Last) \ +@@ -281,8 +283,9 @@ + w.r.t. the value _Value and predicate _Pred. */ + #define __glibcxx_check_partitioned_lower_pred(_First,_Last,_Value,_Pred) \ + __glibcxx_check_valid_range(_First,_Last); \ +-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower(_First, _Last, \ +- _Value, _Pred), \ ++_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_lower( \ ++ __gnu_debug::__base(_First), \ ++ __gnu_debug::__base(_Last), _Value, _Pred), \ + _M_message(__gnu_debug::__msg_unpartitioned_pred) \ + ._M_iterator(_First, #_First) \ + ._M_iterator(_Last, #_Last) \ +@@ -293,8 +296,9 @@ + w.r.t. the value _Value and predicate _Pred. */ + #define __glibcxx_check_partitioned_upper_pred(_First,_Last,_Value,_Pred) \ + __glibcxx_check_valid_range(_First,_Last); \ +-_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper(_First, _Last, \ +- _Value, _Pred), \ ++_GLIBCXX_DEBUG_VERIFY(__gnu_debug::__check_partitioned_upper( \ ++ __gnu_debug::__base(_First), \ ++ __gnu_debug::__base(_Last), _Value, _Pred), \ + _M_message(__gnu_debug::__msg_unpartitioned_pred) \ + ._M_iterator(_First, #_First) \ + ._M_iterator(_Last, #_Last) \ +Index: libstdc++-v3/ChangeLog =================================================================== ---- a/src/libstdc++-v3/include/std/complex (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/std/complex (.../branches/gcc-4_8-branch) -@@ -142,11 +142,11 @@ - #if __cplusplus >= 201103L - // _GLIBCXX_RESOLVE_LIB_DEFECTS - // DR 387. std::complex over-encapsulated. -- __attribute ((__abi_tag__ ("cxx11"))) -+ _GLIBCXX_ABI_TAG_CXX11 - constexpr _Tp - real() { return _M_real; } +--- a/src/libstdc++-v3/ChangeLog (.../tags/gcc_4_8_2_release) ++++ b/src/libstdc++-v3/ChangeLog (.../branches/gcc-4_8-branch) +@@ -1,3 +1,16 @@ ++2013-10-16 François Dumont ++ ++ PR libstdc++/58191 ++ * include/debug/macros.h (__glibcxx_check_partitioned_lower): Add ++ __gnu_debug::__base calls on iterators passed to internal debug ++ check. ++ (__glibcxx_check_partitioned_lower_pred): Likewise. ++ (__glibcxx_check_partitioned_upper): Likewise. ++ (__glibcxx_check_partitioned_upper_pred): Likewise. ++ * include/debug/functions.h (__check_partitioned_lower): ++ Remove code to detect safe iterators. ++ (__check_partitioned_upper): Likewise. ++ + 2013-10-16 Release Manager -- __attribute ((__abi_tag__ ("cxx11"))) -+ _GLIBCXX_ABI_TAG_CXX11 - constexpr _Tp - imag() { return _M_imag; } - #else -Index: libstdc++-v3/include/ext/random + * GCC 4.8.2 released. +Index: gcc/DATESTAMP =================================================================== ---- a/src/libstdc++-v3/include/ext/random (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/ext/random (.../branches/gcc-4_8-branch) -@@ -2848,7 +2848,7 @@ - _GLIBCXX_END_NAMESPACE_VERSION - } // namespace __gnu_cxx - --#include "opt_random.h" -+#include "ext/opt_random.h" - #include "random.tcc" - - #endif // _GLIBCXX_USE_C99_STDINT_TR1 -Index: libstdc++-v3/include/profile/vector +--- a/src/gcc/DATESTAMP (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/DATESTAMP (.../branches/gcc-4_8-branch) +@@ -1 +1 @@ +-20131016 ++20131017 +Index: gcc/ChangeLog =================================================================== ---- a/src/libstdc++-v3/include/profile/vector (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/profile/vector (.../branches/gcc-4_8-branch) -@@ -374,6 +374,16 @@ - return iterator(__res, this); - } - -+ template -+ iterator -+ emplace(iterator __position, _Args&&... __args) -+ { -+ typename _Base::iterator __res -+ = _Base::emplace(__position.base(), -+ std::forward<_Args>(__args)...); -+ return iterator(__res, this); -+ } +--- a/src/gcc/ChangeLog (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/ChangeLog (.../branches/gcc-4_8-branch) +@@ -1,3 +1,12 @@ ++2013-10-16 Ganesh Gopalasubramanian + - void - insert(iterator __position, initializer_list __l) - { this->insert(__position, __l.begin(), __l.end()); } -Index: libstdc++-v3/include/bits/stl_map.h -=================================================================== ---- a/src/libstdc++-v3/include/bits/stl_map.h (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/stl_map.h (.../branches/gcc-4_8-branch) -@@ -690,7 +690,8 @@ - erase(const_iterator __position) - { return _M_t.erase(__position); } ++ Backport from mainline ++ 2013-10-16 Ganesh Gopalasubramanian ++ ++ ++ * config/i386/i386.c (ix86_option_override_internal): Enable FMA4 ++ for AMD bdver3. ++ + 2013-10-16 Release Manager -- // LWG 2059. -+ // LWG 2059 -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(iterator __position) - { return _M_t.erase(__position); } -Index: libstdc++-v3/include/bits/stl_set.h -=================================================================== ---- a/src/libstdc++-v3/include/bits/stl_set.h (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/stl_set.h (.../branches/gcc-4_8-branch) -@@ -546,6 +546,7 @@ - * touched in any way. Managing the pointer is the user's - * responsibility. - */ -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(const_iterator __position) - { return _M_t.erase(__position); } -@@ -597,6 +598,7 @@ - * the element is itself a pointer, the pointed-to memory is not touched - * in any way. Managing the pointer is the user's responsibility. - */ -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(const_iterator __first, const_iterator __last) - { return _M_t.erase(__first, __last); } -Index: libstdc++-v3/include/bits/stl_multimap.h + * GCC 4.8.2 released. +Index: gcc/testsuite/ChangeLog =================================================================== ---- a/src/libstdc++-v3/include/bits/stl_multimap.h (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/stl_multimap.h (.../branches/gcc-4_8-branch) -@@ -596,6 +596,7 @@ - { return _M_t.erase(__position); } +--- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-4_8-branch) +@@ -1,3 +1,9 @@ ++2013-10-16 Paolo Carlini ++ ++ PR c++/58633 ++ * g++.dg/cpp0x/decltype57.C: New. ++ * g++.dg/cpp0x/enum18.C: Revert r174385 changes. ++ + 2013-10-16 Release Manager - // LWG 2059. -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(iterator __position) - { return _M_t.erase(__position); } -Index: libstdc++-v3/include/bits/unordered_map.h + * GCC 4.8.2 released. +Index: gcc/testsuite/g++.dg/cpp0x/enum18.C =================================================================== ---- a/src/libstdc++-v3/include/bits/unordered_map.h (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/unordered_map.h (.../branches/gcc-4_8-branch) -@@ -367,7 +367,7 @@ - _Pair&&>::value>::type> - std::pair - insert(_Pair&& __x) -- { return _M_h.insert(std::move(__x)); } -+ { return _M_h.insert(std::forward<_Pair>(__x)); } - //@} - - //@{ -@@ -401,7 +401,7 @@ - _Pair&&>::value>::type> - iterator - insert(const_iterator __hint, _Pair&& __x) -- { return _M_h.insert(__hint, std::move(__x)); } -+ { return _M_h.insert(__hint, std::forward<_Pair>(__x)); } - //@} - - /** -@@ -1032,7 +1032,7 @@ - _Pair&&>::value>::type> - iterator - insert(_Pair&& __x) -- { return _M_h.insert(std::move(__x)); } -+ { return _M_h.insert(std::forward<_Pair>(__x)); } - //@} - - //@{ -@@ -1064,7 +1064,7 @@ - _Pair&&>::value>::type> - iterator - insert(const_iterator __hint, _Pair&& __x) -- { return _M_h.insert(__hint, std::move(__x)); } -+ { return _M_h.insert(__hint, std::forward<_Pair>(__x)); } - //@} - - /** -Index: libstdc++-v3/include/bits/stl_multiset.h +--- a/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/g++.dg/cpp0x/enum18.C (.../branches/gcc-4_8-branch) +@@ -4,5 +4,5 @@ + int main(void) { + enum e {}; + e ev; +- ev.e::~e_u(); // { dg-error "e_u. has not been declared" } ++ ev.e::~e_u(); // { dg-error "" } + } +Index: gcc/testsuite/g++.dg/cpp0x/decltype57.C =================================================================== ---- a/src/libstdc++-v3/include/bits/stl_multiset.h (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/stl_multiset.h (.../branches/gcc-4_8-branch) -@@ -532,6 +532,7 @@ - * not touched in any way. Managing the pointer is the user's - * responsibility. - */ -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(const_iterator __position) - { return _M_t.erase(__position); } -@@ -583,6 +584,7 @@ - * touched in any way. Managing the pointer is the user's - * responsibility. - */ -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(const_iterator __first, const_iterator __last) - { return _M_t.erase(__first, __last); } -Index: libstdc++-v3/include/bits/c++config +--- a/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/g++.dg/cpp0x/decltype57.C (.../branches/gcc-4_8-branch) +@@ -0,0 +1,8 @@ ++// PR c++/58633 ++// { dg-do compile { target c++11 } } ++ ++void foo(int i) ++{ ++ typedef int I; ++ decltype(i.I::~I())* p; ++} +Index: gcc/cp/ChangeLog =================================================================== ---- a/src/libstdc++-v3/include/bits/c++config (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/c++config (.../branches/gcc-4_8-branch) -@@ -84,6 +84,12 @@ - # define _GLIBCXX_DEPRECATED - #endif - -+// Macros for ABI tag attributes. -+#ifndef _GLIBCXX_ABI_TAG_CXX11 -+# define _GLIBCXX_ABI_TAG_CXX11 __attribute ((__abi_tag__ ("cxx11"))) -+#endif +--- a/src/gcc/cp/ChangeLog (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/cp/ChangeLog (.../branches/gcc-4_8-branch) +@@ -1,3 +1,14 @@ ++2013-10-16 Paolo Carlini + ++ PR c++/58633 ++ * parser.c (cp_parser_pseudo_destructor_name): Revert r174385 changes. + - #if __cplusplus - - // Macro for constexpr, to support in mixed 03/0x mode. -Index: libstdc++-v3/include/bits/random.tcc -=================================================================== ---- a/src/libstdc++-v3/include/bits/random.tcc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/random.tcc (.../branches/gcc-4_8-branch) -@@ -1648,7 +1648,8 @@ - template - typename binomial_distribution<_IntType>::result_type - binomial_distribution<_IntType>:: -- _M_waiting(_UniformRandomNumberGenerator& __urng, _IntType __t) -+ _M_waiting(_UniformRandomNumberGenerator& __urng, -+ _IntType __t, double __q) - { - _IntType __x = 0; - double __sum = 0.0; -@@ -1663,7 +1664,7 @@ - __sum += __e / (__t - __x); - __x += 1; - } -- while (__sum <= _M_param._M_q); -+ while (__sum <= __q); - - return __x - 1; - } -@@ -1784,12 +1785,13 @@ - - __x += __np + __naf; - -- const _IntType __z = _M_waiting(__urng, __t - _IntType(__x)); -+ const _IntType __z = _M_waiting(__urng, __t - _IntType(__x), -+ __param._M_q); - __ret = _IntType(__x) + __z; - } - else - #endif -- __ret = _M_waiting(__urng, __t); -+ __ret = _M_waiting(__urng, __t, __param._M_q); ++2013-10-16 Jason Merrill ++ ++ PR c++/57850 ++ * decl2.c (dump_tu): Split out from... ++ (cp_write_global_declarations): ...here. Call it in PCH mode. ++ + 2013-10-16 Release Manager - if (__p12 != __p) - __ret = __t - __ret; -Index: libstdc++-v3/include/bits/random.h + * GCC 4.8.2 released. +Index: gcc/cp/decl2.c =================================================================== ---- a/src/libstdc++-v3/include/bits/random.h (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/random.h (.../branches/gcc-4_8-branch) -@@ -3978,7 +3978,8 @@ +--- a/src/gcc/cp/decl2.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/cp/decl2.c (.../branches/gcc-4_8-branch) +@@ -3960,6 +3960,22 @@ + expand_or_defer_fn (finish_function (0)); + } - template - result_type -- _M_waiting(_UniformRandomNumberGenerator& __urng, _IntType __t); -+ _M_waiting(_UniformRandomNumberGenerator& __urng, -+ _IntType __t, double __q); ++/* The entire file is now complete. If requested, dump everything ++ to a file. */ ++ ++static void ++dump_tu (void) ++{ ++ int flags; ++ FILE *stream = dump_begin (TDI_tu, &flags); ++ ++ if (stream) ++ { ++ dump_node (global_namespace, flags & ~TDF_SLIM, stream); ++ dump_end (TDI_tu, stream); ++ } ++} ++ + /* This routine is called at the end of compilation. + Its job is to create all the code needed to initialize and + destroy the global aggregates. We do the destruction +@@ -3990,6 +4006,7 @@ + if (pch_file) + { + c_common_write_pch (); ++ dump_tu (); + return; + } - param_type _M_param; +@@ -4359,17 +4376,8 @@ -Index: libstdc++-v3/include/bits/stl_tree.h + /* The entire file is now complete. If requested, dump everything + to a file. */ +- { +- int flags; +- FILE *stream = dump_begin (TDI_tu, &flags); ++ dump_tu (); + +- if (stream) +- { +- dump_node (global_namespace, flags & ~TDF_SLIM, stream); +- dump_end (TDI_tu, stream); +- } +- } +- + if (flag_detailed_statistics) + { + dump_tree_statistics (); +Index: gcc/cp/parser.c =================================================================== ---- a/src/libstdc++-v3/include/bits/stl_tree.h (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/bits/stl_tree.h (.../branches/gcc-4_8-branch) -@@ -336,21 +336,21 @@ - _Node_allocator; - - protected: -- typedef _Rb_tree_node_base* _Base_ptr; -- typedef const _Rb_tree_node_base* _Const_Base_ptr; -+ typedef _Rb_tree_node_base* _Base_ptr; -+ typedef const _Rb_tree_node_base* _Const_Base_ptr; - - public: -- typedef _Key key_type; -- typedef _Val value_type; -- typedef value_type* pointer; -- typedef const value_type* const_pointer; -- typedef value_type& reference; -- typedef const value_type& const_reference; -- typedef _Rb_tree_node<_Val>* _Link_type; -- typedef const _Rb_tree_node<_Val>* _Const_Link_type; -- typedef size_t size_type; -- typedef ptrdiff_t difference_type; -- typedef _Alloc allocator_type; -+ typedef _Key key_type; -+ typedef _Val value_type; -+ typedef value_type* pointer; -+ typedef const value_type* const_pointer; -+ typedef value_type& reference; -+ typedef const value_type& const_reference; -+ typedef _Rb_tree_node<_Val>* _Link_type; -+ typedef const _Rb_tree_node<_Val>* _Const_Link_type; -+ typedef size_t size_type; -+ typedef ptrdiff_t difference_type; -+ typedef _Alloc allocator_type; - - _Node_allocator& - _M_get_Node_allocator() _GLIBCXX_NOEXCEPT -@@ -800,6 +800,7 @@ - #if __cplusplus >= 201103L - // _GLIBCXX_RESOLVE_LIB_DEFECTS - // DR 130. Associative erase should return an iterator. -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(const_iterator __position) - { -@@ -810,6 +811,7 @@ - } - - // LWG 2059. -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(iterator __position) - { -@@ -833,6 +835,7 @@ - #if __cplusplus >= 201103L - // _GLIBCXX_RESOLVE_LIB_DEFECTS - // DR 130. Associative erase should return an iterator. -+ _GLIBCXX_ABI_TAG_CXX11 - iterator - erase(const_iterator __first, const_iterator __last) - { -Index: libstdc++-v3/include/Makefile.am +--- a/src/gcc/cp/parser.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/cp/parser.c (.../branches/gcc-4_8-branch) +@@ -6421,10 +6421,6 @@ + /* Look for the `~'. */ + cp_parser_require (parser, CPP_COMPL, RT_COMPL); + +- /* Once we see the ~, this has to be a pseudo-destructor. */ +- if (!processing_template_decl && !cp_parser_error_occurred (parser)) +- cp_parser_commit_to_tentative_parse (parser); +- + /* Look for the type-name again. We are not responsible for + checking that it matches the first type-name. */ + *type = cp_parser_nonclass_name (parser); +Index: gcc/go/go-gcc.cc =================================================================== ---- a/src/libstdc++-v3/include/Makefile.am (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/include/Makefile.am (.../branches/gcc-4_8-branch) -@@ -172,8 +172,7 @@ - ${bits_srcdir}/valarray_array.tcc \ - ${bits_srcdir}/valarray_before.h \ - ${bits_srcdir}/valarray_after.h \ -- ${bits_srcdir}/vector.tcc \ -- ${bits_host_headers} -+ ${bits_srcdir}/vector.tcc - - bits_host_headers = \ - ${glibcxx_srcdir}/${CPU_OPT_BITS_RANDOM} -@@ -535,8 +534,7 @@ - ${ext_srcdir}/vstring.tcc \ - ${ext_srcdir}/vstring_fwd.h \ - ${ext_srcdir}/vstring_util.h \ -- ${ext_compat_headers} \ -- ${ext_host_headers} -+ ${ext_compat_headers} +--- a/src/gcc/go/go-gcc.cc (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/go/go-gcc.cc (.../branches/gcc-4_8-branch) +@@ -232,6 +232,9 @@ + Bexpression* + convert_expression(Btype* type, Bexpression* expr, Location); - ext_compat_headers = \ - ${backward_srcdir}/hash_set \ -@@ -1048,13 +1046,14 @@ ++ Bexpression* ++ function_code_expression(Bfunction*, Location); ++ + // Statements. - stamp-${host_alias}: - @-mkdir -p ${host_builddir} -+ @-mkdir -p ${host_builddir}/../ext - @$(STAMP) stamp-${host_alias} + Bstatement* +@@ -334,6 +337,17 @@ + Bexpression* + label_address(Blabel*, Location); + ++ // Functions. ++ ++ Bfunction* ++ error_function() ++ { return this->make_function(error_mark_node); } ++ ++ Bfunction* ++ function(Btype* fntype, const std::string& name, const std::string& asm_name, ++ bool is_visible, bool is_declaration, bool is_inlinable, ++ bool disable_split_stack, bool in_unique_section, Location); ++ + private: + // Make a Bexpression from a tree. + Bexpression* +@@ -350,6 +364,10 @@ + make_type(tree t) + { return new Btype(t); } - # Host includes static. - # XXX Missing dependency info for {host_headers_extra} --stamp-host: ${host_headers} ${host_headers_noinst} stamp-${host_alias} -+stamp-host: ${host_headers} ${bits_host_headers} ${ext_host_headers} ${host_headers_noinst} stamp-${host_alias} - @cd ${host_builddir} && {\ -- $(LN_S) ${host_headers} . || true ;\ -+ $(LN_S) ${host_headers} ${bits_host_headers} . || true ;\ - $(LN_S) ${glibcxx_srcdir}/$(BASIC_FILE_H) basic_file.h || true ;\ - $(LN_S) ${glibcxx_srcdir}/$(ALLOCATOR_H) c++allocator.h || true ;\ - $(LN_S) ${glibcxx_srcdir}/$(CSTDIO_H) c++io.h || true ;\ -@@ -1064,6 +1063,9 @@ - $(LN_S) ${glibcxx_srcdir}/$(CMESSAGES_H) messages_members.h || true ;\ - $(LN_S) ${glibcxx_srcdir}/$(CTIME_H) time_members.h || true;\ - } 2>/dev/null -+ @cd ${host_builddir}/../ext && {\ -+ $(LN_S) ${ext_host_headers} . || true ;\ -+ } 2>/dev/null - $(STAMP) stamp-host ++ Bfunction* ++ make_function(tree t) ++ { return new Bfunction(t); } ++ + Btype* + fill_in_struct(Btype*, const std::vector&); - # Host includes dynamic. -@@ -1290,9 +1292,12 @@ - for file in ${profile_impl_headers}; do \ - $(INSTALL_DATA) $${file} $(DESTDIR)${gxx_include_dir}/${profile_impl_builddir}; done - $(mkinstalldirs) $(DESTDIR)${host_installdir} -- for file in ${host_headers} ${host_headers_extra} \ -+ for file in ${host_headers} ${bits_host_headers} ${host_headers_extra} \ - ${thread_host_headers}; do \ - $(INSTALL_DATA) $${file} $(DESTDIR)${host_installdir}; done -+ $(mkinstalldirs) $(DESTDIR)${host_installdir}/../ext -+ for file in ${ext_host_headers}; do \ -+ $(INSTALL_DATA) $${file} $(DESTDIR)${host_installdir}/../ext; done +@@ -966,6 +984,19 @@ + return tree_to_expr(ret); + } - # By adding these files here, automake will remove them for 'make clean' - CLEANFILES = ${pch_output} ${pch_output_anchors} stamp-host -Index: libstdc++-v3/ChangeLog -=================================================================== ---- a/src/libstdc++-v3/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,104 @@ -+2013-06-27 Paolo Carlini -+ -+ * include/profile/vector (emplace(iterator, _Args&&...)): Define. -+ -+2013-06-25 Paolo Carlini -+ -+ * testsuite/23_containers/map/modifiers/erase/abi_tag.cc: Avoid -+ spurious fails with check-debug. -+ * testsuite/23_containers/multimap/modifiers/erase/abi_tag.cc: -+ Likewise. -+ * testsuite/23_containers/set/modifiers/erase/abi_tag.cc: Likewise. -+ * testsuite/23_containers/multiset/modifiers/erase/abi_tag.cc: -+ Likewise. -+ -+2013-06-22 Paolo Carlini -+ -+ PR libstdc++/57674 -+ * include/bits/random.h (binomial_distribution<>::_M_waiting): -+ Add double parameter. -+ * include/bits/random.tcc (binomial_distribution<>::operator() -+ (_UniformRandomNumberGenerator&, const param_type&)): Pass -+ __param._M_q to _M_waiting. -+ (_M_waiting): Adjust. -+ * testsuite/26_numerics/random/binomial_distribution/ -+ operators/values.cc: Add tests. -+ -+2013-06-21 Paolo Carlini -+ -+ PR libstdc++/57666 -+ * include/std/valarray (valarray<>::operator=(const _Expr<>&)): -+ Implement correctly C++11 26.6.2.3/1. -+ * testsuite/26_numerics/valarray/dr630-3.C: New. ++// Get the address of a function. + -+2013-06-19 Alan Modra -+ -+ Apply mainline patch -+ 2013-06-14 Alan Modra -+ * configure.host (abi_baseline_pair): Match powerpc64*. ++Bexpression* ++Gcc_backend::function_code_expression(Bfunction* bfunc, Location location) ++{ ++ tree func = bfunc->get_tree(); ++ if (func == error_mark_node) ++ return this->error_expression(); + -+2013-06-15 Paolo Carlini ++ tree ret = build_fold_addr_expr_loc(location.gcc_location(), func); ++ return this->make_expression(ret); ++} + -+ PR libstdc++/57619 -+ * include/bits/unordered_map.h (unordered_map<>::insert, -+ unordered_multimap<>::insert): Use std::forward, not std::move. -+ * testsuite/23_containers/unordered_map/insert/57619.C: New. -+ * testsuite/23_containers/unordered_multimap/insert/57619.C: Likewise. + // An expression as a statement. + + Bstatement* +@@ -1724,6 +1755,56 @@ + return this->make_expression(ret); + } + ++// Declare or define a new function. + -+2013-06-12 Benjamin Kosnik ++Bfunction* ++Gcc_backend::function(Btype* fntype, const std::string& name, ++ const std::string& asm_name, bool is_visible, ++ bool is_declaration, bool is_inlinable, ++ bool disable_split_stack, bool in_unique_section, ++ Location location) ++{ ++ tree functype = fntype->get_tree(); ++ if (functype != error_mark_node) ++ { ++ gcc_assert(FUNCTION_POINTER_TYPE_P(functype)); ++ functype = TREE_TYPE(functype); ++ } ++ tree id = get_identifier_from_string(name); ++ if (functype == error_mark_node || id == error_mark_node) ++ return this->error_function(); + -+ * include/bits/c++config (_GLIBCXX_ABI_TAG_CXX11): Add. -+ * include/bits/stl_map.h (erase): Use abi_tag when C++11. -+ * include/bits/stl_multimap.h: Same. -+ * include/bits/stl_multiset.h: Same. -+ * include/bits/stl_set.h: Same. -+ * include/bits/stl_tree.h: Same. -+ * include/std/complex (real, imag): Use macro for abi_tag. ++ tree decl = build_decl(location.gcc_location(), FUNCTION_DECL, id, functype); ++ if (!asm_name.empty()) ++ SET_DECL_ASSEMBLER_NAME(decl, get_identifier_from_string(asm_name)); ++ if (is_visible) ++ TREE_PUBLIC(decl) = 1; ++ if (is_declaration) ++ DECL_EXTERNAL(decl) = 1; ++ else ++ { ++ tree restype = TREE_TYPE(functype); ++ tree resdecl = ++ build_decl(location.gcc_location(), RESULT_DECL, NULL_TREE, restype); ++ DECL_ARTIFICIAL(resdecl) = 1; ++ DECL_IGNORED_P(resdecl) = 1; ++ DECL_CONTEXT(resdecl) = decl; ++ DECL_RESULT(decl) = resdecl; ++ } ++ if (!is_inlinable) ++ DECL_UNINLINABLE(decl) = 1; ++ if (disable_split_stack) ++ { ++ tree attr = get_identifier("__no_split_stack__"); ++ DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE); ++ } ++ if (in_unique_section) ++ resolve_unique_section(decl, 0, 1); + -+ * testsuite/lib/libstdc++.exp: Disable inlinling with -fno-inline. -+ * testsuite/util/testsuite_containers.h (erase_external): New -+ declarations. -+ (erase_external_iterators): Same. -+ (linkage_check_cxx98_cxx11_erase): Same. -+ (linkage_check_cxx98_cxx11_erase_iterators): Same. -+ * testsuite/util/testsuite_shared.cc: Define. -+ * testsuite/23_containers/map/modifiers/erase/abi_tag.cc: New. -+ * testsuite/23_containers/map/modifiers/erase/ -+ dr130-linkage-check.cc: New. -+ * testsuite/23_containers/multimap/modifiers/erase/abi_tag.cc: New. -+ * testsuite/23_containers/multimap/modifiers/erase/ -+ dr130-linkage-check.cc: New. -+ * testsuite/23_containers/multiset/modifiers/erase/abi_tag.cc: New. -+ * testsuite/23_containers/multiset/modifiers/erase/ -+ dr130-linkage-check.cc: New. -+ * testsuite/23_containers/set/modifiers/erase/abi_tag.cc: New. -+ * testsuite/23_containers/set/modifiers/erase/dr130-linkage-check.cc: -+ New. -+ * testsuite/ext/profile/mutex_extensions_neg.cc: Adjust line number. ++ go_preserve_from_gc(decl); ++ return new Bfunction(decl); ++} + -+ * testsuite/23_containers/map/dr130.cc: Move... -+ * testsuite/23_containers/map/modifiers/dr130.cc: ...here. -+ * testsuite/23_containers/multimap/dr130.cc: Move ... -+ * testsuite/23_containers/multimap/modifiers/dr130.cc: ...here. -+ * testsuite/23_containers/multiset/dr130.cc: Move... -+ * testsuite/23_containers/multiset/modifiers/dr130.cc: ...here. -+ * testsuite/23_containers/set/dr130.cc: Move... -+ * testsuite/23_containers/set/modifiers/dr130.cc: ...here. + // The single backend. + + static Gcc_backend gcc_backend; +@@ -1799,3 +1880,9 @@ + { + return bv->get_tree(); + } + -+2013-06-11 Matthias Klose ++tree ++function_to_tree(Bfunction* bf) ++{ ++ return bf->get_tree(); ++} +Index: gcc/go/ChangeLog +=================================================================== +--- a/src/gcc/go/ChangeLog (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/go/ChangeLog (.../branches/gcc-4_8-branch) +@@ -1,3 +1,17 @@ ++2013-10-16 Ian Lance Taylor + -+ * include/Makefile.am (bits_headers): Remove ${bits_host_headers}. -+ (ext_headers): Remove ${ext_host_headers}. -+ (stamp-${host_alias}): Create ${host_builddir}/../ext. -+ (stamp-host): Link ${bits_host_headers} and ${ext_host_headers}. -+ (install-headers): Install ${bits_host_headers} and ${ext_host_headers}. -+ * include/Makefile.in: Regenerate. -+ * include/ext/random: Include ext/opt_random.h. ++ Bring in from mainline: + -+2013-06-07 Uros Bizjak ++ 2013-10-11 Chris Manghane ++ * go-gcc.cc (Gcc_backend::function_code_expression): New ++ function. + -+ * config/abi/post/alpha-linux-gnu/baseline_symbols.txt: Update. ++ 2013-10-10 Chris Manghane ++ * go-gcc.cc (Backend::error_function): New function. ++ (Backend::function): New function. ++ (Backend::make_function): New function. ++ (function_to_tree): New function. + - 2013-05-31 Release Manager + 2013-10-16 Release Manager - * GCC 4.8.1 released. -Index: libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/operators/values.cc + * GCC 4.8.2 released. +Index: gcc/go/gofrontend/gogo.cc =================================================================== ---- a/src/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/operators/values.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/operators/values.cc (.../branches/gcc-4_8-branch) -@@ -43,6 +43,17 @@ - std::binomial_distribution<> bd3(10, 0.75); - auto bbd3 = std::bind(bd3, eng); - testDiscreteDist(bbd3, [](int n) { return binomial_pdf(n, 10, 0.75); } ); +--- a/src/gcc/go/gofrontend/gogo.cc (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/go/gofrontend/gogo.cc (.../branches/gcc-4_8-branch) +@@ -3320,7 +3320,8 @@ + closure_var_(NULL), block_(block), location_(location), labels_(), + local_type_count_(0), descriptor_(NULL), fndecl_(NULL), defer_stack_(NULL), + is_sink_(false), results_are_named_(false), nointerface_(false), +- calls_recover_(false), is_recover_thunk_(false), has_recover_thunk_(false), ++ is_unnamed_type_stub_method_(false), calls_recover_(false), ++ is_recover_thunk_(false), has_recover_thunk_(false), + in_unique_section_(false) + { + } +@@ -3819,6 +3820,81 @@ + *presults = results; + } + ++// Get the backend representation. ++ ++Bfunction* ++Function::get_or_make_decl(Gogo* gogo, Named_object* no) ++{ ++ if (this->fndecl_ == NULL) ++ { ++ std::string asm_name; ++ bool is_visible = false; ++ if (no->package() != NULL) ++ ; ++ else if (this->enclosing_ != NULL || Gogo::is_thunk(no)) ++ ; ++ else if (Gogo::unpack_hidden_name(no->name()) == "init" ++ && !this->type_->is_method()) ++ ; ++ else if (Gogo::unpack_hidden_name(no->name()) == "main" ++ && gogo->is_main_package()) ++ is_visible = true; ++ // Methods have to be public even if they are hidden because ++ // they can be pulled into type descriptors when using ++ // anonymous fields. ++ else if (!Gogo::is_hidden_name(no->name()) ++ || this->type_->is_method()) ++ { ++ if (!this->is_unnamed_type_stub_method_) ++ is_visible = true; ++ std::string pkgpath = gogo->pkgpath_symbol(); ++ if (this->type_->is_method() ++ && Gogo::is_hidden_name(no->name()) ++ && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath()) ++ { ++ // This is a method we created for an unexported ++ // method of an imported embedded type. We need to ++ // use the pkgpath of the imported package to avoid ++ // a possible name collision. See bug478 for a test ++ // case. ++ pkgpath = Gogo::hidden_name_pkgpath(no->name()); ++ pkgpath = Gogo::pkgpath_for_symbol(pkgpath); ++ } ++ ++ asm_name = pkgpath; ++ asm_name.append(1, '.'); ++ asm_name.append(Gogo::unpack_hidden_name(no->name())); ++ if (this->type_->is_method()) ++ { ++ asm_name.append(1, '.'); ++ Type* rtype = this->type_->receiver()->type(); ++ asm_name.append(rtype->mangled_name(gogo)); ++ } ++ } + -+ // libstdc++/57674 -+ std::binomial_distribution<> bd4(1, 0.8); -+ const std::binomial_distribution<>::param_type pm4(1, 0.3); -+ auto bbd4 = std::bind(bd4, eng, pm4); -+ testDiscreteDist(bbd4, [](int n) { return binomial_pdf(n, 1, 0.3); } ); ++ // If a function calls the predeclared recover function, we ++ // can't inline it, because recover behaves differently in a ++ // function passed directly to defer. If this is a recover ++ // thunk that we built to test whether a function can be ++ // recovered, we can't inline it, because that will mess up ++ // our return address comparison. ++ bool is_inlinable = !(this->calls_recover_ || this->is_recover_thunk_); ++ ++ // If this is a thunk created to call a function which calls ++ // the predeclared recover function, we need to disable ++ // stack splitting for the thunk. ++ bool disable_split_stack = this->is_recover_thunk_; ++ ++ Btype* functype = this->type_->get_backend_fntype(gogo); ++ this->fndecl_ = ++ gogo->backend()->function(functype, no->get_id(gogo), asm_name, ++ is_visible, false, is_inlinable, ++ disable_split_stack, ++ this->in_unique_section_, this->location()); ++ } ++ return this->fndecl_; ++} + -+ std::binomial_distribution<> bd5(100, 0.3); -+ const std::binomial_distribution<>::param_type pm5(100, 0.8); -+ auto bbd5 = std::bind(bd5, eng, pm5); -+ testDiscreteDist(bbd5, [](int n) { return binomial_pdf(n, 100, 0.8); } ); + // Class Block. + + Block::Block(Block* enclosing, Location location) +@@ -5110,6 +5186,75 @@ + go_unreachable(); } - int main() -Index: libstdc++-v3/testsuite/26_numerics/valarray/dr630-3.C -=================================================================== ---- a/src/libstdc++-v3/testsuite/26_numerics/valarray/dr630-3.C (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/26_numerics/valarray/dr630-3.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,37 @@ -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. + -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. ++// Return the external identifier for this object. + -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+#include -+ -+// libstdc++/57666 -+void test01() ++std::string ++Named_object::get_id(Gogo* gogo) +{ -+ bool test __attribute__((unused)) = true; ++ go_assert(!this->is_variable() && !this->is_result_variable()); ++ std::string decl_name; ++ if (this->is_function_declaration() ++ && !this->func_declaration_value()->asm_name().empty()) ++ decl_name = this->func_declaration_value()->asm_name(); ++ else if (this->is_type() ++ && Linemap::is_predeclared_location(this->type_value()->location())) ++ { ++ // We don't need the package name for builtin types. ++ decl_name = Gogo::unpack_hidden_name(this->name_); ++ } ++ else ++ { ++ std::string package_name; ++ if (this->package_ == NULL) ++ package_name = gogo->package_name(); ++ else ++ package_name = this->package_->package_name(); + -+ std::valarray a(3), b(3), d1, d2; -+ d1 = a; -+ VERIFY( d1.size() == 3 ); -+ d2 = a + b; -+ VERIFY( d2.size() == 3 ); ++ // Note that this will be misleading if this is an unexported ++ // method generated for an embedded imported type. In that case ++ // the unexported method should have the package name of the ++ // package from which it is imported, but we are going to give ++ // it our package name. Fixing this would require knowing the ++ // package name, but we only know the package path. It might be ++ // better to use package paths here anyhow. This doesn't affect ++ // the assembler code, because we always set that name in ++ // Function::get_or_make_decl anyhow. FIXME. ++ ++ decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_); ++ ++ Function_type* fntype; ++ if (this->is_function()) ++ fntype = this->func_value()->type(); ++ else if (this->is_function_declaration()) ++ fntype = this->func_declaration_value()->type(); ++ else ++ fntype = NULL; ++ if (fntype != NULL && fntype->is_method()) ++ { ++ decl_name.push_back('.'); ++ decl_name.append(fntype->receiver()->type()->mangled_name(gogo)); ++ } ++ } ++ if (this->is_type()) ++ { ++ unsigned int index; ++ const Named_object* in_function = this->type_value()->in_function(&index); ++ if (in_function != NULL) ++ { ++ decl_name += '$' + Gogo::unpack_hidden_name(in_function->name()); ++ if (index > 0) ++ { ++ char buf[30]; ++ snprintf(buf, sizeof buf, "%u", index); ++ decl_name += '$'; ++ decl_name += buf; ++ } ++ } ++ } ++ return decl_name; +} + -+int main() -+{ -+ test01(); -+ return 0; -+} -Index: libstdc++-v3/testsuite/ext/profile/mutex_extensions_neg.cc + // Class Bindings. + + Bindings::Bindings(Bindings* enclosing) +Index: gcc/go/gofrontend/runtime.def =================================================================== ---- a/src/libstdc++-v3/testsuite/ext/profile/mutex_extensions_neg.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/ext/profile/mutex_extensions_neg.cc (.../branches/gcc-4_8-branch) -@@ -25,4 +25,4 @@ +--- a/src/gcc/go/gofrontend/runtime.def (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/go/gofrontend/runtime.def (.../branches/gcc-4_8-branch) +@@ -68,6 +68,12 @@ + P1(STRING), R1(SLICE)) - #include --// { dg-error "multiple inlined namespaces" "" { target *-*-* } 269 } -+// { dg-error "multiple inlined namespaces" "" { target *-*-* } 275 } -Index: libstdc++-v3/testsuite/lib/libstdc++.exp -=================================================================== ---- a/src/libstdc++-v3/testsuite/lib/libstdc++.exp (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/lib/libstdc++.exp (.../branches/gcc-4_8-branch) -@@ -626,7 +626,7 @@ - # Compile with "-w" so that warnings issued by the compiler - # do not prevent compilation. - if { [v3_target_compile $srcdir/util/$f $object_file "sharedlib" \ -- [list "incdir=$srcdir" "additional_flags=-w -shared -fPIC -DPIC"]] -+ [list "incdir=$srcdir" "additional_flags=-fno-inline -w -shared -fPIC -DPIC"]] - != "" } { - error "could not compile $f" - } -Index: libstdc++-v3/testsuite/23_containers/unordered_map/insert/57619.C ++// Complex division. ++DEF_GO_RUNTIME(COMPLEX64_DIV, "__go_complex64_div", ++ P2(COMPLEX64, COMPLEX64), R1(COMPLEX64)) ++DEF_GO_RUNTIME(COMPLEX128_DIV, "__go_complex128_div", ++ P2(COMPLEX128, COMPLEX128), R1(COMPLEX128)) ++ + // Make a slice. + DEF_GO_RUNTIME(MAKESLICE1, "__go_make_slice1", P2(TYPE, UINTPTR), R1(SLICE)) + DEF_GO_RUNTIME(MAKESLICE2, "__go_make_slice2", P3(TYPE, UINTPTR, UINTPTR), +Index: gcc/go/gofrontend/gogo.h =================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/unordered_map/insert/57619.C (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/unordered_map/insert/57619.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,51 @@ -+// { dg-options "-std=gnu++11" } -+// -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+// -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+// -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+#include -+#include -+ -+void test01() -+{ -+ bool test __attribute__((unused)) = true; -+ +--- a/src/gcc/go/gofrontend/gogo.h (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/go/gofrontend/gogo.h (.../branches/gcc-4_8-branch) +@@ -48,6 +48,7 @@ + class Bblock; + class Bvariable; + class Blabel; ++class Bfunction; + + // This file declares the basic classes used to hold the internal + // representation of Go which is built by the parser. +@@ -952,6 +953,15 @@ + this->nointerface_ = true; + } + ++ // Record that this function is a stub method created for an unnamed ++ // type. ++ void ++ set_is_unnamed_type_stub_method() + { -+ std::unordered_map mymap; -+ std::pair mypair{std::string("key"), -+ std::string("value")}; -+ mymap.insert(mypair); -+ -+ VERIFY( mypair.first.length() && mypair.second.length() ); ++ go_assert(this->is_method()); ++ this->is_unnamed_type_stub_method_ = true; + } + -+ { -+ std::unordered_map mymap; -+ std::pair mypair{std::string("key"), -+ std::string("value")}; -+ mymap.insert(mymap.begin(), mypair); + // Add a new field to the closure variable. + void + add_closure_field(Named_object* var, Location loc) +@@ -1089,17 +1099,13 @@ + this->descriptor_ = descriptor; + } + +- // Return the function's decl given an identifier. +- tree +- get_or_make_decl(Gogo*, Named_object*, tree id); ++ // Return the backend representation. ++ Bfunction* ++ get_or_make_decl(Gogo*, Named_object*); + + // Return the function's decl after it has been built. + tree +- get_decl() const +- { +- go_assert(this->fndecl_ != NULL); +- return this->fndecl_; +- } ++ get_decl() const; + + // Set the function decl to hold a tree of the function code. + void +@@ -1170,7 +1176,7 @@ + // The function descriptor, if any. + Expression* descriptor_; + // The function decl. +- tree fndecl_; ++ Bfunction* fndecl_; + // The defer stack variable. A pointer to this variable is used to + // distinguish the defer stack for one function from another. This + // is NULL unless we actually need a defer stack. +@@ -1181,6 +1187,9 @@ + bool results_are_named_ : 1; + // True if this method should not be included in the type descriptor. + bool nointerface_ : 1; ++ // True if this function is a stub method created for an unnamed ++ // type. ++ bool is_unnamed_type_stub_method_ : 1; + // True if this function calls the predeclared recover function. + bool calls_recover_ : 1; + // True if this a thunk built for a function which calls recover. +@@ -1265,9 +1274,9 @@ + has_descriptor() const + { return this->descriptor_ != NULL; } + +- // Return a decl for the function given an identifier. +- tree +- get_or_make_decl(Gogo*, Named_object*, tree id); ++ // Return a backend representation. ++ Bfunction* ++ get_or_make_decl(Gogo*, Named_object*); + + // If there is a descriptor, build it into the backend + // representation. +@@ -1290,7 +1299,7 @@ + // The function descriptor, if any. + Expression* descriptor_; + // The function decl if needed. +- tree fndecl_; ++ Bfunction* fndecl_; + }; + + // A variable. +@@ -2181,8 +2190,8 @@ + Bvariable* + get_backend_variable(Gogo*, Named_object* function); + +- // Return a tree for the external identifier for this object. +- tree ++ // Return the external identifier for this object. ++ std::string + get_id(Gogo*); + + // Return a tree representing this object. +Index: gcc/go/gofrontend/types.h +=================================================================== +--- a/src/gcc/go/gofrontend/types.h (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/go/gofrontend/types.h (.../branches/gcc-4_8-branch) +@@ -1717,7 +1717,8 @@ + Typed_identifier_list* results, Location location) + : Type(TYPE_FUNCTION), + receiver_(receiver), parameters_(parameters), results_(results), +- location_(location), is_varargs_(false), is_builtin_(false) ++ location_(location), is_varargs_(false), is_builtin_(false), ++ fnbtype_(NULL) + { } + + // Get the receiver. +@@ -1798,6 +1799,11 @@ + static Type* + make_function_type_descriptor_type(); + ++ // Return the backend representation of this function type. This is used ++ // as the real type of a backend function declaration or defintion. ++ Btype* ++ get_backend_fntype(Gogo*); + -+ VERIFY( mypair.first.length() && mypair.second.length() ); -+ } -+} + protected: + int + do_traverse(Traverse*); +@@ -1851,6 +1857,9 @@ + // Whether this is a special builtin function which can not simply + // be called. This is used for len, cap, etc. + bool is_builtin_; ++ // The backend representation of this type for backend function ++ // declarations and definitions. ++ Btype* fnbtype_; + }; + + // The type of a pointer. +Index: gcc/go/gofrontend/parse.cc +=================================================================== +--- a/src/gcc/go/gofrontend/parse.cc (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/go/gofrontend/parse.cc (.../branches/gcc-4_8-branch) +@@ -744,6 +744,8 @@ + return NULL; + + Parse::Names names; ++ if (receiver != NULL) ++ names[receiver->name()] = receiver; + if (params != NULL) + this->check_signature_names(params, &names); + if (results != NULL) +Index: gcc/go/gofrontend/import.h +=================================================================== +--- a/src/gcc/go/gofrontend/import.h (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/go/gofrontend/import.h (.../branches/gcc-4_8-branch) +@@ -149,6 +149,11 @@ + location() const + { return this->location_; } + ++ // Return the package we are importing. ++ Package* ++ package() const ++ { return this->package_; } + -+int main() -+{ -+ test01(); -+ return 0; -+} -Index: libstdc++-v3/testsuite/23_containers/multimap/dr130.cc + // Return the next character. + int + peek_char() +Index: gcc/go/gofrontend/runtime.cc =================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/multimap/dr130.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/multimap/dr130.cc (.../branches/gcc-4_8-branch) -@@ -1,87 +0,0 @@ --// { dg-options "-std=gnu++0x" } -- --// Copyright (C) 2009-2013 Free Software Foundation, Inc. --// --// This file is part of the GNU ISO C++ Library. This library is free --// software; you can redistribute it and/or modify it under the --// terms of the GNU General Public License as published by the --// Free Software Foundation; either version 3, or (at your option) --// any later version. -- --// This library is distributed in the hope that it will be useful, --// but WITHOUT ANY WARRANTY; without even the implied warranty of --// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --// GNU General Public License for more details. -- --// You should have received a copy of the GNU General Public License along --// with this library; see the file COPYING3. If not see --// . -- -- --// NOTE: This makes use of the fact that we know how moveable --// is implemented on multiset (via swap). If the implementation changed --// this test may begin to fail. -- --#include --#include --#include -- --using namespace std; -- --void --test01() --{ -- bool test __attribute__((unused)) = true; -- using namespace std; -- -- multimap mm0; -- typedef multimap::iterator iterator; -- typedef multimap::const_iterator const_iterator; -- typedef multimap::value_type value_type; -- typedef iterator insert_return_type; -- -- vector irt; -- for (int i = 1; i <= 4; ++i) -- for (int j = 1; j <= i; ++j) -- irt.push_back( mm0.insert( value_type( i, i ) ) ); -- -- iterator pos1 = mm0.erase(irt[1]); -- VERIFY( pos1 == irt[2] ); -- -- iterator pos2 = mm0.erase(irt[2]); -- VERIFY( pos2 == irt[3] ); -- -- iterator pos3 = mm0.erase(irt[9]); -- VERIFY( pos3 == mm0.end() ); --} -- --void --test02() --{ -- bool test __attribute__((unused)) = true; -- using namespace std; -- -- multimap mm0; -- typedef multimap::iterator iterator; -- typedef multimap::const_iterator const_iterator; -- typedef multimap::value_type value_type; -- typedef iterator insert_return_type; -- -- vector irt; -- for (int i = 1; i <= 4; ++i) -- for (int j = 1; j <= i; ++j) -- irt.push_back( mm0.insert( value_type( i, i ) ) ); -- -- iterator pos1 = mm0.erase(irt[3], irt[6]); -- VERIFY( pos1 == irt[6] ); -- -- iterator pos2 = mm0.erase(irt[6], ++irt[9]); -- VERIFY( pos2 == mm0.end() ); --} -- --int --main() --{ -- test01(); -- test02(); --} -Index: libstdc++-v3/testsuite/23_containers/multimap/modifiers/erase/dr130-linkage-check.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/multimap/modifiers/erase/dr130-linkage-check.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/multimap/modifiers/erase/dr130-linkage-check.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,40 @@ -+// { dg-require-effective-target ia32 } -+// { dg-require-sharedlib "" } -+// { dg-options "-fno-inline -std=gnu++11 ./testsuite_shared.so" } -+// 2013-06-03 Benjamin Kosnik -+// -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+// -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+// -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+ -+int main() -+{ -+ typedef std::multimap container_type; -+ -+ { -+ container_type s { {0,0} , {1,1} , {2,2} }; -+ __gnu_test::linkage_check_cxx98_cxx11_erase(s); -+ } -+ -+ { -+ container_type s { {0,0} , {1,1} , {2,2} }; -+ __gnu_test::linkage_check_cxx98_cxx11_erase_iterators(s); -+ } -+ -+ return 0; -+} -Index: libstdc++-v3/testsuite/23_containers/multimap/modifiers/erase/abi_tag.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/multimap/modifiers/erase/abi_tag.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/multimap/modifiers/erase/abi_tag.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,36 @@ -+// { dg-do compile } -+// { dg-options -std=c++11 } -+// { dg-require-normal-mode "" } -+ -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+ -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+ -+// Under Section 7 of GPL version 3, you are granted additional -+// permissions described in the GCC Runtime Library Exception, version -+// 3.1, as published by the Free Software Foundation. -+ -+// You should have received a copy of the GNU General Public License and -+// a copy of the GCC Runtime Library Exception along with this program; -+// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+// . -+ -+// Test that the C++11 variants have an ABI tag -+ -+#include -+ -+using container = std::multimap; -+using iterator = typename container::iterator; -+using const_iterator = typename container::const_iterator; -+ -+// { dg-final { scan-assembler "_ZNSt8multimapIiiSt4lessIiESaISt4pairIKiiEEE5eraseB5cxx11ESt17_Rb_tree_iteratorIS4_E" } } -+iterator (container::*p1)(iterator) = &container::erase; -Index: libstdc++-v3/testsuite/23_containers/multimap/modifiers/dr130.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/multimap/modifiers/dr130.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/multimap/modifiers/dr130.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,87 @@ -+// { dg-options "-std=gnu++0x" } -+ -+// Copyright (C) 2009-2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+ -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+ -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+ -+// NOTE: This makes use of the fact that we know how moveable -+// is implemented on multiset (via swap). If the implementation changed -+// this test may begin to fail. -+ -+#include -+#include -+#include -+ -+using namespace std; -+ -+void -+test01() -+{ -+ bool test __attribute__((unused)) = true; -+ using namespace std; -+ -+ multimap mm0; -+ typedef multimap::iterator iterator; -+ typedef multimap::const_iterator const_iterator; -+ typedef multimap::value_type value_type; -+ typedef iterator insert_return_type; -+ -+ vector irt; -+ for (int i = 1; i <= 4; ++i) -+ for (int j = 1; j <= i; ++j) -+ irt.push_back( mm0.insert( value_type( i, i ) ) ); -+ -+ iterator pos1 = mm0.erase(irt[1]); -+ VERIFY( pos1 == irt[2] ); -+ -+ iterator pos2 = mm0.erase(irt[2]); -+ VERIFY( pos2 == irt[3] ); -+ -+ iterator pos3 = mm0.erase(irt[9]); -+ VERIFY( pos3 == mm0.end() ); -+} -+ -+void -+test02() -+{ -+ bool test __attribute__((unused)) = true; -+ using namespace std; -+ -+ multimap mm0; -+ typedef multimap::iterator iterator; -+ typedef multimap::const_iterator const_iterator; -+ typedef multimap::value_type value_type; -+ typedef iterator insert_return_type; -+ -+ vector irt; -+ for (int i = 1; i <= 4; ++i) -+ for (int j = 1; j <= i; ++j) -+ irt.push_back( mm0.insert( value_type( i, i ) ) ); -+ -+ iterator pos1 = mm0.erase(irt[3], irt[6]); -+ VERIFY( pos1 == irt[6] ); -+ -+ iterator pos2 = mm0.erase(irt[6], ++irt[9]); -+ VERIFY( pos2 == mm0.end() ); -+} -+ -+int -+main() -+{ -+ test01(); -+ test02(); -+} -Index: libstdc++-v3/testsuite/23_containers/set/dr130.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/set/dr130.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/set/dr130.cc (.../branches/gcc-4_8-branch) -@@ -1,75 +0,0 @@ --// { dg-options "-std=gnu++0x" } --// 2008-07-22 Edward Smith-Rowland <3dw4rd@verizon.net> --// --// Copyright (C) 2009-2013 Free Software Foundation, Inc. --// --// This file is part of the GNU ISO C++ Library. This library is free --// software; you can redistribute it and/or modify it under the --// terms of the GNU General Public License as published by the --// Free Software Foundation; either version 3, or (at your option) --// any later version. --// --// This library is distributed in the hope that it will be useful, --// but WITHOUT ANY WARRANTY; without even the implied warranty of --// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --// GNU General Public License for more details. --// --// You should have received a copy of the GNU General Public License along --// with this library; see the file COPYING3. If not see --// . -- --#include --#include -- --// DR 130. Associative erase should return an iterator. --void --test01() --{ -- bool test __attribute__((unused)) = true; -- using namespace std; -- -- set s0; -- typedef set::iterator iterator; -- typedef set::const_iterator const_iterator; -- typedef pair insert_return_type; -- -- s0.insert(1); -- insert_return_type irt1 = s0.insert(2); -- insert_return_type irt2 = s0.insert(3); -- -- iterator pos1 = s0.erase(irt1.first); -- VERIFY( pos1 == irt2.first ); -- -- iterator pos2 = s0.erase(irt2.first); -- VERIFY( pos2 == s0.end() ); --} -- --void --test02() --{ -- bool test __attribute__((unused)) = true; -- using namespace std; -- -- set s0; -- typedef set::iterator iterator; -- typedef set::const_iterator const_iterator; -- typedef pair insert_return_type; -- -- insert_return_type irt0 = s0.insert(1); -- s0.insert(2); -- insert_return_type irt2 = s0.insert(3); -- insert_return_type irt3 = s0.insert(4); -- -- iterator pos1 = s0.erase(irt0.first, irt2.first); -- VERIFY( pos1 == irt2.first ); -- -- iterator pos2 = s0.erase(irt2.first, ++irt3.first); -- VERIFY( pos2 == s0.end() ); --} -- --int --main() --{ -- test01(); -- test02(); --} -Index: libstdc++-v3/testsuite/23_containers/set/modifiers/erase/dr130-linkage-check.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/set/modifiers/erase/dr130-linkage-check.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/set/modifiers/erase/dr130-linkage-check.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,40 @@ -+// { dg-require-effective-target ia32 } -+// { dg-require-sharedlib "" } -+// { dg-options "-fno-inline -std=gnu++11 ./testsuite_shared.so" } -+// 2013-06-03 Benjamin Kosnik -+// -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+// -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+// -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+ -+int main() -+{ -+ typedef std::set container_type; -+ -+ { -+ container_type s { 0, 1, 2 }; -+ __gnu_test::linkage_check_cxx98_cxx11_erase(s); -+ } -+ -+ { -+ container_type s { 0, 1, 2 }; -+ __gnu_test::linkage_check_cxx98_cxx11_erase_iterators(s); -+ } -+ -+ return 0; -+} -Index: libstdc++-v3/testsuite/23_containers/set/modifiers/erase/abi_tag.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/set/modifiers/erase/abi_tag.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/set/modifiers/erase/abi_tag.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,39 @@ -+// { dg-do compile } -+// { dg-options -std=c++11 } -+// { dg-require-normal-mode "" } -+ -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+ -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+ -+// Under Section 7 of GPL version 3, you are granted additional -+// permissions described in the GCC Runtime Library Exception, version -+// 3.1, as published by the Free Software Foundation. -+ -+// You should have received a copy of the GNU General Public License and -+// a copy of the GCC Runtime Library Exception along with this program; -+// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+// . -+ -+// Test that the C++11 variants have an ABI tag -+ -+#include -+ -+using container = std::set; -+using iterator = typename container::iterator; -+using const_iterator = typename container::const_iterator; -+ -+// { dg-final { scan-assembler "_ZNSt3setIiSt4lessIiESaIiEE5eraseB5cxx11ESt23_Rb_tree_const_iteratorIiE" } } -+iterator (container::*p1)(const_iterator) = &container::erase; -+ -+// { dg-final { scan-assembler "_ZNSt3setIiSt4lessIiESaIiEE5eraseB5cxx11ESt23_Rb_tree_const_iteratorIiES5_" } } -+iterator (container::*p2)(const_iterator, const_iterator) = &container::erase; -Index: libstdc++-v3/testsuite/23_containers/set/modifiers/dr130.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/set/modifiers/dr130.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/set/modifiers/dr130.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,75 @@ -+// { dg-options "-std=gnu++0x" } -+// 2008-07-22 Edward Smith-Rowland <3dw4rd@verizon.net> -+// -+// Copyright (C) 2009-2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+// -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+// -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+#include -+ -+// DR 130. Associative erase should return an iterator. -+void -+test01() -+{ -+ bool test __attribute__((unused)) = true; -+ using namespace std; -+ -+ set s0; -+ typedef set::iterator iterator; -+ typedef set::const_iterator const_iterator; -+ typedef pair insert_return_type; -+ -+ s0.insert(1); -+ insert_return_type irt1 = s0.insert(2); -+ insert_return_type irt2 = s0.insert(3); -+ -+ iterator pos1 = s0.erase(irt1.first); -+ VERIFY( pos1 == irt2.first ); -+ -+ iterator pos2 = s0.erase(irt2.first); -+ VERIFY( pos2 == s0.end() ); -+} -+ -+void -+test02() -+{ -+ bool test __attribute__((unused)) = true; -+ using namespace std; -+ -+ set s0; -+ typedef set::iterator iterator; -+ typedef set::const_iterator const_iterator; -+ typedef pair insert_return_type; -+ -+ insert_return_type irt0 = s0.insert(1); -+ s0.insert(2); -+ insert_return_type irt2 = s0.insert(3); -+ insert_return_type irt3 = s0.insert(4); -+ -+ iterator pos1 = s0.erase(irt0.first, irt2.first); -+ VERIFY( pos1 == irt2.first ); -+ -+ iterator pos2 = s0.erase(irt2.first, ++irt3.first); -+ VERIFY( pos2 == s0.end() ); -+} -+ -+int -+main() -+{ -+ test01(); -+ test02(); -+} -Index: libstdc++-v3/testsuite/23_containers/unordered_multimap/insert/57619.C -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/unordered_multimap/insert/57619.C (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/unordered_multimap/insert/57619.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,51 @@ -+// { dg-options "-std=gnu++11" } -+// -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+// -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+// -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+#include -+#include -+ -+void test01() -+{ -+ bool test __attribute__((unused)) = true; -+ -+ { -+ std::unordered_multimap mymmap; -+ std::pair mypair{std::string("key"), -+ std::string("value")}; -+ mymmap.insert(mypair); -+ -+ VERIFY( mypair.first.length() && mypair.second.length() ); -+ } -+ -+ { -+ std::unordered_multimap mymmap; -+ std::pair mypair{std::string("key"), -+ std::string("value")}; -+ mymmap.insert(mymmap.begin(), mypair); -+ -+ VERIFY( mypair.first.length() && mypair.second.length() ); -+ } -+} -+ -+int main() -+{ -+ test01(); -+ return 0; -+} -Index: libstdc++-v3/testsuite/23_containers/multiset/dr130.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/multiset/dr130.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/multiset/dr130.cc (.../branches/gcc-4_8-branch) -@@ -1,85 +0,0 @@ --// { dg-options "-std=gnu++0x" } -- --// Copyright (C) 2009-2013 Free Software Foundation, Inc. --// --// This file is part of the GNU ISO C++ Library. This library is free --// software; you can redistribute it and/or modify it under the --// terms of the GNU General Public License as published by the --// Free Software Foundation; either version 3, or (at your option) --// any later version. -- --// This library is distributed in the hope that it will be useful, --// but WITHOUT ANY WARRANTY; without even the implied warranty of --// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --// GNU General Public License for more details. -- --// You should have received a copy of the GNU General Public License along --// with this library; see the file COPYING3. If not see --// . -- -- --// NOTE: This makes use of the fact that we know how moveable --// is implemented on multiset (via swap). If the implementation changed --// this test may begin to fail. -- --#include --#include --#include -- --using namespace std; -- --void --test01() --{ -- bool test __attribute__((unused)) = true; -- using namespace std; -- -- multiset ms0; -- typedef multiset::iterator iterator; -- typedef multiset::const_iterator const_iterator; -- typedef iterator insert_return_type; -- -- vector irt; -- for ( int i = 1; i <= 4; ++i ) -- for (int j = 1; j <= i; ++j) -- irt.push_back( ms0.insert( i ) ); -- -- iterator pos1 = ms0.erase(irt[1]); -- VERIFY( pos1 == irt[2] ); -- -- iterator pos2 = ms0.erase(irt[2]); -- VERIFY( pos2 == irt[3] ); -- -- iterator pos3 = ms0.erase(irt[9]); -- VERIFY( pos3 == ms0.end() ); --} -- --void --test02() --{ -- bool test __attribute__((unused)) = true; -- using namespace std; -- -- multiset ms0; -- typedef multiset::iterator iterator; -- typedef multiset::const_iterator const_iterator; -- typedef iterator insert_return_type; -- -- vector irt; -- for ( int i = 1; i <= 4; ++i ) -- for (int j = 1; j <= i; ++j) -- irt.push_back( ms0.insert( i ) ); -- -- iterator pos1 = ms0.erase(irt[3], irt[6]); -- VERIFY( pos1 == irt[6] ); -- -- iterator pos2 = ms0.erase(irt[6], ++irt[9]); -- VERIFY( pos2 == ms0.end() ); --} -- --int --main() --{ -- test01(); -- test02(); --} -Index: libstdc++-v3/testsuite/23_containers/multiset/modifiers/erase/dr130-linkage-check.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/multiset/modifiers/erase/dr130-linkage-check.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/multiset/modifiers/erase/dr130-linkage-check.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,40 @@ -+// { dg-require-effective-target ia32 } -+// { dg-require-sharedlib "" } -+// { dg-options "-fno-inline -std=gnu++11 ./testsuite_shared.so" } -+// 2013-06-03 Benjamin Kosnik -+// -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+// -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+// -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+ -+int main() -+{ -+ typedef std::multiset container_type; -+ -+ { -+ container_type s { 0, 1, 2 }; -+ __gnu_test::linkage_check_cxx98_cxx11_erase(s); -+ } -+ -+ { -+ container_type s { 0, 1, 2 }; -+ __gnu_test::linkage_check_cxx98_cxx11_erase_iterators(s); -+ } -+ -+ return 0; -+} -Index: libstdc++-v3/testsuite/23_containers/multiset/modifiers/erase/abi_tag.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/multiset/modifiers/erase/abi_tag.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/multiset/modifiers/erase/abi_tag.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,39 @@ -+// { dg-do compile } -+// { dg-options -std=c++11 } -+// { dg-require-normal-mode "" } -+ -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+ -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+ -+// Under Section 7 of GPL version 3, you are granted additional -+// permissions described in the GCC Runtime Library Exception, version -+// 3.1, as published by the Free Software Foundation. -+ -+// You should have received a copy of the GNU General Public License and -+// a copy of the GCC Runtime Library Exception along with this program; -+// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+// . -+ -+// Test that the C++11 variants have an ABI tag -+ -+#include -+ -+using container = std::multiset; -+using iterator = typename container::iterator; -+using const_iterator = typename container::const_iterator; -+ -+// { dg-final { scan-assembler "_ZNSt8multisetIiSt4lessIiESaIiEE5eraseB5cxx11ESt23_Rb_tree_const_iteratorIiE" } } -+iterator (container::*p1)(const_iterator) = &container::erase; -+ -+// { dg-final { scan-assembler "_ZNSt8multisetIiSt4lessIiESaIiEE5eraseB5cxx11ESt23_Rb_tree_const_iteratorIiES5_" } } -+iterator (container::*p2)(const_iterator, const_iterator) = &container::erase; -Index: libstdc++-v3/testsuite/23_containers/multiset/modifiers/dr130.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/multiset/modifiers/dr130.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/multiset/modifiers/dr130.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,85 @@ -+// { dg-options "-std=gnu++0x" } -+ -+// Copyright (C) 2009-2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+ -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+ -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+ -+// NOTE: This makes use of the fact that we know how moveable -+// is implemented on multiset (via swap). If the implementation changed -+// this test may begin to fail. -+ -+#include -+#include -+#include -+ -+using namespace std; -+ -+void -+test01() -+{ -+ bool test __attribute__((unused)) = true; -+ using namespace std; -+ -+ multiset ms0; -+ typedef multiset::iterator iterator; -+ typedef multiset::const_iterator const_iterator; -+ typedef iterator insert_return_type; -+ -+ vector irt; -+ for ( int i = 1; i <= 4; ++i ) -+ for (int j = 1; j <= i; ++j) -+ irt.push_back( ms0.insert( i ) ); -+ -+ iterator pos1 = ms0.erase(irt[1]); -+ VERIFY( pos1 == irt[2] ); -+ -+ iterator pos2 = ms0.erase(irt[2]); -+ VERIFY( pos2 == irt[3] ); -+ -+ iterator pos3 = ms0.erase(irt[9]); -+ VERIFY( pos3 == ms0.end() ); -+} -+ -+void -+test02() -+{ -+ bool test __attribute__((unused)) = true; -+ using namespace std; -+ -+ multiset ms0; -+ typedef multiset::iterator iterator; -+ typedef multiset::const_iterator const_iterator; -+ typedef iterator insert_return_type; -+ -+ vector irt; -+ for ( int i = 1; i <= 4; ++i ) -+ for (int j = 1; j <= i; ++j) -+ irt.push_back( ms0.insert( i ) ); -+ -+ iterator pos1 = ms0.erase(irt[3], irt[6]); -+ VERIFY( pos1 == irt[6] ); -+ -+ iterator pos2 = ms0.erase(irt[6], ++irt[9]); -+ VERIFY( pos2 == ms0.end() ); -+} -+ -+int -+main() -+{ -+ test01(); -+ test02(); -+} -Index: libstdc++-v3/testsuite/23_containers/map/dr130.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/map/dr130.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/map/dr130.cc (.../branches/gcc-4_8-branch) -@@ -1,77 +0,0 @@ --// { dg-options "-std=gnu++0x" } --// 2008-07-22 Edward Smith-Rowland <3dw4rd@verizon.net> --// --// Copyright (C) 2009-2013 Free Software Foundation, Inc. --// --// This file is part of the GNU ISO C++ Library. This library is free --// software; you can redistribute it and/or modify it under the --// terms of the GNU General Public License as published by the --// Free Software Foundation; either version 3, or (at your option) --// any later version. --// --// This library is distributed in the hope that it will be useful, --// but WITHOUT ANY WARRANTY; without even the implied warranty of --// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --// GNU General Public License for more details. --// --// You should have received a copy of the GNU General Public License along --// with this library; see the file COPYING3. If not see --// . -- --#include --#include -- --// DR 130. Associative erase should return an iterator. --void --test01() --{ -- bool test __attribute__((unused)) = true; -- using namespace std; -- -- map m0; -- typedef map::iterator iterator; -- typedef map::const_iterator const_iterator; -- typedef map::value_type value_type; -- typedef pair insert_return_type; -- -- m0.insert(value_type(1, 1)); -- insert_return_type irt1 = m0.insert(value_type(2, 2)); -- insert_return_type irt2 = m0.insert(value_type(3, 3)); -- -- iterator pos1 = m0.erase(irt1.first); -- VERIFY( pos1 == irt2.first ); -- -- iterator pos2 = m0.erase(irt2.first); -- VERIFY( pos2 == m0.end() ); --} -- --void --test02() --{ -- bool test __attribute__((unused)) = true; -- using namespace std; -- -- map m0; -- typedef map::iterator iterator; -- typedef map::const_iterator const_iterator; -- typedef map::value_type value_type; -- typedef pair insert_return_type; -- -- insert_return_type irt0 = m0.insert(value_type(1, 1)); -- m0.insert(value_type(2, 2)); -- insert_return_type irt2 = m0.insert(value_type(3, 3)); -- insert_return_type irt3 = m0.insert(value_type(4, 4)); -- -- iterator pos1 = m0.erase(irt0.first, irt2.first); -- VERIFY( pos1 == irt2.first ); -- -- iterator pos2 = m0.erase(irt2.first, ++irt3.first); -- VERIFY( pos2 == m0.end() ); --} -- --int --main() --{ -- test01(); -- test02(); --} -Index: libstdc++-v3/testsuite/23_containers/map/modifiers/erase/dr130-linkage-check.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/map/modifiers/erase/dr130-linkage-check.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/map/modifiers/erase/dr130-linkage-check.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,40 @@ -+// { dg-require-effective-target ia32 } -+// { dg-require-sharedlib "" } -+// { dg-options "-fno-inline -std=gnu++11 ./testsuite_shared.so" } -+// 2013-06-03 Benjamin Kosnik -+// -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+// -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+// -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+ -+int main() -+{ -+ typedef std::map container_type; -+ -+ { -+ container_type s { {0,0} , {1,1} , {2,2} }; -+ __gnu_test::linkage_check_cxx98_cxx11_erase(s); -+ } -+ -+ { -+ container_type s { {0,0} , {1,1} , {2,2} }; -+ __gnu_test::linkage_check_cxx98_cxx11_erase_iterators(s); -+ } -+ -+ return 0; -+} -Index: libstdc++-v3/testsuite/23_containers/map/modifiers/erase/abi_tag.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/map/modifiers/erase/abi_tag.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/map/modifiers/erase/abi_tag.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,36 @@ -+// { dg-do compile } -+// { dg-options -std=c++11 } -+// { dg-require-normal-mode "" } -+ -+// Copyright (C) 2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+ -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+ -+// Under Section 7 of GPL version 3, you are granted additional -+// permissions described in the GCC Runtime Library Exception, version -+// 3.1, as published by the Free Software Foundation. -+ -+// You should have received a copy of the GNU General Public License and -+// a copy of the GCC Runtime Library Exception along with this program; -+// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+// . -+ -+// Test that the C++11 variants have an ABI tag -+ -+#include -+ -+using container = std::map; -+using iterator = typename container::iterator; -+using const_iterator = typename container::const_iterator; -+ -+// { dg-final { scan-assembler "_ZNSt3mapIiiSt4lessIiESaISt4pairIKiiEEE5eraseB5cxx11ESt17_Rb_tree_iteratorIS4_E" } } -+iterator (container::*p1)(iterator) = &container::erase; -Index: libstdc++-v3/testsuite/23_containers/map/modifiers/dr130.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/23_containers/map/modifiers/dr130.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/23_containers/map/modifiers/dr130.cc (.../branches/gcc-4_8-branch) -@@ -0,0 +1,77 @@ -+// { dg-options "-std=gnu++0x" } -+// 2008-07-22 Edward Smith-Rowland <3dw4rd@verizon.net> -+// -+// Copyright (C) 2009-2013 Free Software Foundation, Inc. -+// -+// This file is part of the GNU ISO C++ Library. This library is free -+// software; you can redistribute it and/or modify it under the -+// terms of the GNU General Public License as published by the -+// Free Software Foundation; either version 3, or (at your option) -+// any later version. -+// -+// This library is distributed in the hope that it will be useful, -+// but WITHOUT ANY WARRANTY; without even the implied warranty of -+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+// GNU General Public License for more details. -+// -+// You should have received a copy of the GNU General Public License along -+// with this library; see the file COPYING3. If not see -+// . -+ -+#include -+#include -+ -+// DR 130. Associative erase should return an iterator. -+void -+test01() -+{ -+ bool test __attribute__((unused)) = true; -+ using namespace std; -+ -+ map m0; -+ typedef map::iterator iterator; -+ typedef map::const_iterator const_iterator; -+ typedef map::value_type value_type; -+ typedef pair insert_return_type; -+ -+ m0.insert(value_type(1, 1)); -+ insert_return_type irt1 = m0.insert(value_type(2, 2)); -+ insert_return_type irt2 = m0.insert(value_type(3, 3)); -+ -+ iterator pos1 = m0.erase(irt1.first); -+ VERIFY( pos1 == irt2.first ); -+ -+ iterator pos2 = m0.erase(irt2.first); -+ VERIFY( pos2 == m0.end() ); -+} -+ -+void -+test02() -+{ -+ bool test __attribute__((unused)) = true; -+ using namespace std; -+ -+ map m0; -+ typedef map::iterator iterator; -+ typedef map::const_iterator const_iterator; -+ typedef map::value_type value_type; -+ typedef pair insert_return_type; -+ -+ insert_return_type irt0 = m0.insert(value_type(1, 1)); -+ m0.insert(value_type(2, 2)); -+ insert_return_type irt2 = m0.insert(value_type(3, 3)); -+ insert_return_type irt3 = m0.insert(value_type(4, 4)); -+ -+ iterator pos1 = m0.erase(irt0.first, irt2.first); -+ VERIFY( pos1 == irt2.first ); -+ -+ iterator pos2 = m0.erase(irt2.first, ++irt3.first); -+ VERIFY( pos2 == m0.end() ); -+} -+ -+int -+main() -+{ -+ test01(); -+ test02(); -+} -Index: libstdc++-v3/testsuite/util/testsuite_containers.h -=================================================================== ---- a/src/libstdc++-v3/testsuite/util/testsuite_containers.h (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/util/testsuite_containers.h (.../branches/gcc-4_8-branch) -@@ -223,7 +223,59 @@ - template - _Tp citerator<_Tp>::_S_container; - -+ // DR 130 vs. C++98 vs. C++11. -+ // Defined in testsuite_shared.cc. -+ void -+ erase_external(std::set& s); - -+ void -+ erase_external(std::multiset& s); -+ -+ void -+ erase_external(std::map& s); -+ -+ void -+ erase_external(std::multimap& s); -+ -+ void -+ erase_external_iterators(std::set& s); -+ -+ void -+ erase_external_iterators(std::multiset& s); -+ -+ void -+ erase_external_iterators(std::map& s); -+ -+ void -+ erase_external_iterators(std::multimap& s); -+ -+// NB: "must be compiled with C++11" -+#if __cplusplus >= 201103L -+template -+ void -+ linkage_check_cxx98_cxx11_erase(_Tp& container) -+ { -+ // Crashing when exteral reference and internal reference symbols are -+ // equivalently mangled but have different size return types in C++98 -+ // and C++11 signatures. -+ erase_external(container); // C++98 -+ container.erase(container.begin()); // C++11 -+ } -+ -+template -+ void -+ linkage_check_cxx98_cxx11_erase_iterators(_Tp& container) -+ { -+ // Crashing when exteral reference and internal reference symbols are -+ // equivalently mangled but have different size return types in C++98 -+ // and C++11 signatures. -+ erase_external_iterators(container);// C++98 -+ -+ auto iter = container.begin(); -+ container.erase(iter, ++iter); // C++11 -+ } -+#endif -+ - } // namespace __gnu_test - - #endif -Index: libstdc++-v3/testsuite/util/testsuite_shared.cc -=================================================================== ---- a/src/libstdc++-v3/testsuite/util/testsuite_shared.cc (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/testsuite/util/testsuite_shared.cc (.../branches/gcc-4_8-branch) -@@ -19,9 +19,13 @@ - #include - #include - #include -+#include -+#include - #include - #include - -+namespace __gnu_test -+{ - // libstdc++/22309 - extern "C" void - try_allocation() -@@ -70,3 +74,57 @@ - // Randomly throw. See if other threads cleanup. - std::__throw_bad_exception(); - } -+ -+#if __cplusplus < 201103L -+// "must be compiled with C++98" -+ void -+ erase_external(std::set& s) -+ { s.erase(s.begin()); } -+ -+ void -+ erase_external(std::multiset& s) -+ { s.erase(s.begin()); } -+ -+ void -+ erase_external(std::map& s) -+ { s.erase(s.begin()); } -+ -+ void -+ erase_external(std::multimap& s) -+ { s.erase(s.begin()); } -+ -+ void -+ erase_external_iterators(std::set& s) -+ { -+ typedef typename std::set::iterator iterator_type; -+ iterator_type iter = s.begin(); -+ s.erase(iter, ++iter); -+ } -+ -+ void -+ erase_external_iterators(std::multiset& s) -+ { -+ typedef typename std::multiset::iterator iterator_type; -+ iterator_type iter = s.begin(); -+ s.erase(iter, ++iter); -+ } -+ -+ void -+ erase_external_iterators(std::map& s) -+ { -+ typedef typename std::map::iterator iterator_type; -+ iterator_type iter = s.begin(); -+ s.erase(iter, ++iter); -+ } -+ -+ -+ void -+ erase_external_iterators(std::multimap& s) -+ { -+ typedef typename std::multimap::iterator iterator_type; -+ iterator_type iter = s.begin(); -+ s.erase(iter, ++iter); -+ } -+#endif -+ -+} // end namepace __gnu_test -Index: libstdc++-v3/config/abi/post/alpha-linux-gnu/baseline_symbols.txt -=================================================================== ---- a/src/libstdc++-v3/config/abi/post/alpha-linux-gnu/baseline_symbols.txt (.../tags/gcc_4_8_1_release) -+++ b/src/libstdc++-v3/config/abi/post/alpha-linux-gnu/baseline_symbols.txt (.../branches/gcc-4_8-branch) -@@ -543,6 +543,7 @@ - FUNC:_ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE8__do_putES4_bRSt8ios_basewd@@GLIBCXX_LDBL_3.4 - FUNC:_ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb0EEES4_S4_RSt8ios_basewRKSbIwS3_SaIwEE@@GLIBCXX_LDBL_3.4 - FUNC:_ZNKSt17__gnu_cxx_ldbl1289money_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE9_M_insertILb1EEES4_S4_RSt8ios_basewRKSbIwS3_SaIwEE@@GLIBCXX_LDBL_3.4 -+FUNC:_ZNKSt17bad_function_call4whatEv@@GLIBCXX_3.4.18 - FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4 - FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@@GLIBCXX_3.4 - FUNC:_ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4 -@@ -732,6 +733,8 @@ - FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewm@@GLIBCXX_3.4 - FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewx@@GLIBCXX_3.4 - FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewy@@GLIBCXX_3.4 -+FUNC:_ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEm@@GLIBCXX_3.4.18 -+FUNC:_ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEmmm@@GLIBCXX_3.4.18 - FUNC:_ZNKSt8bad_cast4whatEv@@GLIBCXX_3.4.9 - FUNC:_ZNKSt8ios_base7failure4whatEv@@GLIBCXX_3.4 - FUNC:_ZNKSt8messagesIcE18_M_convert_to_charERKSs@@GLIBCXX_3.4 -@@ -1353,6 +1356,7 @@ - FUNC:_ZNSt11regex_errorD0Ev@@GLIBCXX_3.4.15 - FUNC:_ZNSt11regex_errorD1Ev@@GLIBCXX_3.4.15 - FUNC:_ZNSt11regex_errorD2Ev@@GLIBCXX_3.4.15 -+FUNC:_ZNSt11this_thread11__sleep_forENSt6chrono8durationIlSt5ratioILl1ELl1EEEENS1_IlS2_ILl1ELl1000000000EEEE@@GLIBCXX_3.4.18 - FUNC:_ZNSt12__basic_fileIcE2fdEv@@GLIBCXX_3.4 - FUNC:_ZNSt12__basic_fileIcE4fileEv@@GLIBCXX_3.4.1 - FUNC:_ZNSt12__basic_fileIcE4openEPKcSt13_Ios_Openmodei@@GLIBCXX_3.4 -@@ -1635,6 +1639,11 @@ - FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEt@@GLIBCXX_3.4 - FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEx@@GLIBCXX_3.4 - FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEy@@GLIBCXX_3.4 -+FUNC:_ZNSt13random_device14_M_init_pretr1ERKSs@@GLIBCXX_3.4.18 -+FUNC:_ZNSt13random_device16_M_getval_pretr1Ev@@GLIBCXX_3.4.18 -+FUNC:_ZNSt13random_device7_M_finiEv@@GLIBCXX_3.4.18 -+FUNC:_ZNSt13random_device7_M_initERKSs@@GLIBCXX_3.4.18 -+FUNC:_ZNSt13random_device9_M_getvalEv@@GLIBCXX_3.4.18 - FUNC:_ZNSt13runtime_errorC1ERKSs@@GLIBCXX_3.4 - FUNC:_ZNSt13runtime_errorC2ERKSs@@GLIBCXX_3.4 - FUNC:_ZNSt13runtime_errorD0Ev@@GLIBCXX_3.4 -@@ -2119,6 +2128,8 @@ - FUNC:_ZNSt6__norm15_List_node_base8transferEPS0_S1_@@GLIBCXX_3.4.9 - FUNC:_ZNSt6__norm15_List_node_base9_M_unhookEv@@GLIBCXX_3.4.14 - FUNC:_ZNSt6chrono12system_clock3nowEv@@GLIBCXX_3.4.11 -+FUNC:_ZNSt6chrono3_V212steady_clock3nowEv@@GLIBCXX_3.4.19 -+FUNC:_ZNSt6chrono3_V212system_clock3nowEv@@GLIBCXX_3.4.19 - FUNC:_ZNSt6gslice8_IndexerC1EmRKSt8valarrayImES4_@@GLIBCXX_3.4 - FUNC:_ZNSt6gslice8_IndexerC2EmRKSt8valarrayImES4_@@GLIBCXX_3.4 - FUNC:_ZNSt6locale11_M_coalesceERKS_S1_i@@GLIBCXX_3.4 -@@ -2678,6 +2689,7 @@ - FUNC:__cxa_guard_release@@CXXABI_1.3 - FUNC:__cxa_pure_virtual@@CXXABI_1.3 - FUNC:__cxa_rethrow@@CXXABI_1.3 -+FUNC:__cxa_thread_atexit@@CXXABI_1.3.7 - FUNC:__cxa_throw@@CXXABI_1.3 - FUNC:__cxa_tm_cleanup@@CXXABI_TM_1 - FUNC:__cxa_vec_cctor@@CXXABI_1.3 -@@ -2724,6 +2736,7 @@ - OBJECT:0:CXXABI_1.3.4 - OBJECT:0:CXXABI_1.3.5 - OBJECT:0:CXXABI_1.3.6 -+OBJECT:0:CXXABI_1.3.7 - OBJECT:0:CXXABI_LDBL_1.3 - OBJECT:0:CXXABI_TM_1 - OBJECT:0:GLIBCXX_3.4 -@@ -2736,6 +2749,8 @@ - OBJECT:0:GLIBCXX_3.4.15 - OBJECT:0:GLIBCXX_3.4.16 - OBJECT:0:GLIBCXX_3.4.17 -+OBJECT:0:GLIBCXX_3.4.18 -+OBJECT:0:GLIBCXX_3.4.19 - OBJECT:0:GLIBCXX_3.4.2 - OBJECT:0:GLIBCXX_3.4.3 - OBJECT:0:GLIBCXX_3.4.4 -@@ -3193,6 +3208,8 @@ - OBJECT:1:_ZNSt21__numeric_limits_base9is_moduloE@@GLIBCXX_3.4 - OBJECT:1:_ZNSt21__numeric_limits_base9is_signedE@@GLIBCXX_3.4 - OBJECT:1:_ZNSt6chrono12system_clock12is_monotonicE@@GLIBCXX_3.4.11 -+OBJECT:1:_ZNSt6chrono3_V212steady_clock9is_steadyE@@GLIBCXX_3.4.19 -+OBJECT:1:_ZNSt6chrono3_V212system_clock9is_steadyE@@GLIBCXX_3.4.19 - OBJECT:1:_ZSt10adopt_lock@@GLIBCXX_3.4.11 - OBJECT:1:_ZSt10defer_lock@@GLIBCXX_3.4.11 - OBJECT:1:_ZSt11try_to_lock@@GLIBCXX_3.4.11 -Index: configure.ac -=================================================================== ---- a/src/configure.ac (.../tags/gcc_4_8_1_release) -+++ b/src/configure.ac (.../branches/gcc-4_8-branch) -@@ -2848,6 +2848,13 @@ - target_configargs="--with-cross-host=${host_noncanonical} ${target_configargs}" - fi - -+# Pass --with-sysroot on darwin without SDK in / -+case "${target}" in -+ x86_64-*-darwin1[[3-9]]*) -+ host_configargs="--with-sysroot=\"`xcrun --show-sdk-path`\" ${host_configargs}" -+ ;; -+esac -+ - # Default to --enable-multilib. - if test x${enable_multilib} = x ; then - target_configargs="--enable-multilib ${target_configargs}" -Index: ChangeLog -=================================================================== ---- a/src/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,9 @@ -+2013-07-10 Jack Howarth -+ -+ PR target/57792 -+ * configure.ac: Use --with-sysroot=\"`xcrun --show-sdk-path`\" on darwin13 and later. -+ * configure: Regenerated. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -Index: libjava/classpath/m4/pkg.m4 -=================================================================== ---- a/src/libjava/classpath/m4/pkg.m4 (.../tags/gcc_4_8_1_release) -+++ b/src/libjava/classpath/m4/pkg.m4 (.../branches/gcc-4_8-branch) -@@ -6,7 +6,7 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- AC_PATH_PROG(PKG_CONFIG, pkg-config, no) -+ AC_PATH_TOOL(PKG_CONFIG, pkg-config, no) - fi - - if test "$PKG_CONFIG" = "no" ; then -Index: libjava/classpath/configure -=================================================================== ---- a/src/libjava/classpath/configure (.../tags/gcc_4_8_1_release) -+++ b/src/libjava/classpath/configure (.../branches/gcc-4_8-branch) -@@ -18779,8 +18779,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -18806,7 +18807,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -18820,8 +18820,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -18876,8 +18933,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -18903,7 +18961,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -18917,8 +18974,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -19751,8 +19865,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -19778,7 +19893,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -19792,8 +19906,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -19848,8 +20019,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -19875,7 +20047,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -19889,8 +20060,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -19945,8 +20173,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -19972,7 +20201,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -19986,8 +20214,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -20042,8 +20327,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -20069,7 +20355,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -20083,8 +20368,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -20245,8 +20587,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -20272,7 +20615,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -20286,8 +20628,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -20344,8 +20743,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -20371,7 +20771,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -20385,8 +20784,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -20453,8 +20909,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -20480,7 +20937,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -20494,8 +20950,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -20553,8 +21066,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -20580,7 +21094,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -20594,8 +21107,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -20653,8 +21223,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -20680,7 +21251,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -20694,8 +21264,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -20756,8 +21383,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -20783,7 +21411,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -20797,8 +21424,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -20863,8 +21547,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -20890,7 +21575,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -20904,8 +21588,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -21242,8 +21983,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -21269,7 +22011,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -21283,8 +22024,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -21340,8 +22138,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -21367,7 +22166,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -21381,8 +22179,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -21439,8 +22294,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -21466,7 +22322,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -21480,8 +22335,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -21538,8 +22450,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -21565,7 +22478,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -21579,8 +22491,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -21637,8 +22606,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -21664,7 +22634,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -21678,8 +22647,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -21736,8 +22762,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -21763,7 +22790,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -21777,8 +22803,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -21835,8 +22918,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -21862,7 +22946,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -21876,8 +22959,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -21937,8 +23077,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -21964,7 +23105,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -21978,8 +23118,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -22034,8 +23231,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -22061,7 +23259,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -22075,8 +23272,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -24046,7 +25300,7 @@ - JAVA_TEST=Object.java - CLASS_TEST=Object.class - cat << \EOF > $JAVA_TEST --/* #line 24049 "configure" */ -+/* #line 25303 "configure" */ - package java.lang; - - public class Object -@@ -24139,7 +25393,7 @@ - if uudecode$EXEEXT Test.uue; then - ac_cv_prog_uudecode_base64=yes - else -- echo "configure: 24142: uudecode had trouble decoding base 64 file 'Test.uue'" >&5 -+ echo "configure: 25396: uudecode had trouble decoding base 64 file 'Test.uue'" >&5 - echo "configure: failed file was:" >&5 - cat Test.uue >&5 - ac_cv_prog_uudecode_base64=no -@@ -24167,7 +25421,7 @@ - CLASS_TEST=Test.class - TEST=Test - cat << \EOF > $JAVA_TEST --/* [#]line 24170 "configure" */ -+/* [#]line 25424 "configure" */ - public class Test { - public static void main (String args[]) { - System.exit (0); -@@ -24375,7 +25629,7 @@ - JAVA_TEST=Test.java - CLASS_TEST=Test.class - cat << \EOF > $JAVA_TEST -- /* #line 24378 "configure" */ -+ /* #line 25632 "configure" */ - public class Test - { - public static void main(String args) -Index: libjava/ChangeLog -=================================================================== ---- a/src/libjava/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/libjava/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,10 @@ -+2013-06-19 Matthias Klose -+ -+ * pkg.m4 (PKG_CHECK_MODULES): Use AC_PATH_TOOL to check for pkg-config. -+ * classpath/m4/pkg.m4 (PKG_CHECK_MODULES): Likewise. -+ * configure: Regenerate. -+ * classpath/configure: Regenerate. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -Index: libjava/configure -=================================================================== ---- a/src/libjava/configure (.../tags/gcc_4_8_1_release) -+++ b/src/libjava/configure (.../branches/gcc-4_8-branch) -@@ -3206,7 +3206,7 @@ - -I\$(top_builddir)/../libstdc++-v3/include/\$(target_noncanonical) \ - -I\$(top_srcdir)/../libstdc++-v3/libsupc++" - LIBSTDCXX_RAW_CXX_LDFLAGS="\ -- -I\$(top_builddir)/../libstdc++-v3/src/libstdc++.la" -+ \$(top_builddir)/../libstdc++-v3/src/libstdc++.la" - - - -@@ -22806,8 +22806,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -22833,7 +22834,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -22847,8 +22847,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -22906,8 +22963,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -22933,7 +22991,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -22947,8 +23004,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -@@ -23006,8 +23120,9 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- # Extract the first word of "pkg-config", so it can be a program name with args. --set dummy pkg-config; ac_word=$2 -+ if test -n "$ac_tool_prefix"; then -+ # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. -+set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } - if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : -@@ -23033,7 +23148,6 @@ - done - IFS=$as_save_IFS - -- test -z "$ac_cv_path_PKG_CONFIG" && ac_cv_path_PKG_CONFIG="no" - ;; - esac - fi -@@ -23047,8 +23161,65 @@ - fi - - -+fi -+if test -z "$ac_cv_path_PKG_CONFIG"; then -+ ac_pt_PKG_CONFIG=$PKG_CONFIG -+ # Extract the first word of "pkg-config", so it can be a program name with args. -+set dummy pkg-config; ac_word=$2 -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -+$as_echo_n "checking for $ac_word... " >&6; } -+if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : -+ $as_echo_n "(cached) " >&6 -+else -+ case $ac_pt_PKG_CONFIG in -+ [\\/]* | ?:[\\/]*) -+ ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. -+ ;; -+ *) -+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -+for as_dir in $PATH -+do -+ IFS=$as_save_IFS -+ test -z "$as_dir" && as_dir=. -+ for ac_exec_ext in '' $ac_executable_extensions; do -+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" -+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 -+ break 2 - fi -+done -+ done -+IFS=$as_save_IFS - -+ ;; -+esac -+fi -+ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG -+if test -n "$ac_pt_PKG_CONFIG"; then -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 -+$as_echo "$ac_pt_PKG_CONFIG" >&6; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+fi -+ -+ if test "x$ac_pt_PKG_CONFIG" = x; then -+ PKG_CONFIG="no" -+ else -+ case $cross_compiling:$ac_tool_warned in -+yes:) -+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 -+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} -+ac_tool_warned=yes ;; -+esac -+ PKG_CONFIG=$ac_pt_PKG_CONFIG -+ fi -+else -+ PKG_CONFIG="$ac_cv_path_PKG_CONFIG" -+fi -+ -+ fi -+ - if test "$PKG_CONFIG" = "no" ; then - echo "*** The pkg-config script could not be found. Make sure it is" - echo "*** in your path, or set the PKG_CONFIG environment variable" -Index: libjava/pkg.m4 -=================================================================== ---- a/src/libjava/pkg.m4 (.../tags/gcc_4_8_1_release) -+++ b/src/libjava/pkg.m4 (.../branches/gcc-4_8-branch) -@@ -6,7 +6,7 @@ - succeeded=no - - if test -z "$PKG_CONFIG"; then -- AC_PATH_PROG(PKG_CONFIG, pkg-config, no) -+ AC_PATH_TOOL(PKG_CONFIG, pkg-config, no) - fi - - if test "$PKG_CONFIG" = "no" ; then -Index: configure -=================================================================== ---- a/src/configure (.../tags/gcc_4_8_1_release) -+++ b/src/configure (.../branches/gcc-4_8-branch) -@@ -7414,6 +7414,13 @@ - target_configargs="--with-cross-host=${host_noncanonical} ${target_configargs}" - fi - -+# Pass --with-sysroot on darwin without SDK in / -+case "${target}" in -+ x86_64-*-darwin1[3-9]*) -+ host_configargs="--with-sysroot=\"`xcrun --show-sdk-path`\" ${host_configargs}" -+ ;; -+esac -+ - # Default to --enable-multilib. - if test x${enable_multilib} = x ; then - target_configargs="--enable-multilib ${target_configargs}" -Index: libgcc/config.host -=================================================================== ---- a/src/libgcc/config.host (.../tags/gcc_4_8_1_release) -+++ b/src/libgcc/config.host (.../branches/gcc-4_8-branch) -@@ -316,7 +316,7 @@ - md_unwind_header=alpha/vms-unwind.h - ;; - arm-wrs-vxworks) -- tmake_file="$tmake_file arm/t-arm arm/t-vxworks t-fdpbit" -+ tmake_file="$tmake_file arm/t-arm arm/t-vxworks t-softfp-sfdf t-softfp-excl arm/t-softfp t-softfp" - extra_parts="$extra_parts crti.o crtn.o" - ;; - arm*-*-netbsdelf*) -@@ -834,7 +834,7 @@ - tmake_file="$tmake_file rs6000/t-netbsd rs6000/t-crtstuff" - ;; - powerpc-*-eabispe*) -- tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-savresfgpr rs6000/t-crtstuff t-crtstuff-pic" -+ tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-savresfgpr rs6000/t-crtstuff t-crtstuff-pic t-fdpbit" - extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o" - ;; - powerpc-*-eabisimaltivec*) -@@ -865,7 +865,7 @@ - tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-savresfgpr rs6000/t-crtstuff t-crtstuff-pic t-fdpbit" - extra_parts="$extra_parts crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o" - ;; --powerpc-*-linux* | powerpc64-*-linux*) -+powerpc*-*-linux*) - tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-savresfgpr rs6000/t-crtstuff rs6000/t-linux t-softfp-sfdf t-softfp-excl t-dfprules rs6000/t-ppc64-fp t-softfp t-slibgcc-libgcc" - extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o" - md_unwind_header=rs6000/linux-unwind.h -Index: libgcc/ChangeLog -=================================================================== ---- a/src/libgcc/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/libgcc/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,35 @@ -+2013-07-09 Janis Johnson -+ -+ * config.host (powerpc-*-eabispe*): Add t-fdpbit to tmake_file. -+ -+2013-06-19 Alan Modra -+ -+ Apply mainline patches -+ 2013-06-04 Alan Modra -+ * config/rs6000/ibm-ldouble.c: Enable for little-endian. -+ -+ 2013-04-25 Alan Modra -+ * config.host: Match little-endian powerpc-linux. -+ -+2013-06-08 Walter Lee -+ -+ Backport from mainline: -+ 2013-06-08 Walter Lee -+ -+ * config/tilepro/atomic.h: Don't include stdint.h or features.h. -+ Replace int64_t with long long. Add __extension__ where -+ appropriate. -+ -+2013-06-06 Douglas B Rupp -+ -+ * config.host (arm-wrs-vxworks): Configure with other soft float. -+ -+2013-05-31 Richard Henderson -+ -+ PR target/49146 -+ * unwind-dw2.c (UNWIND_COLUMN_IN_RANGE): New macro. -+ (execute_cfa_program): Use it when storing to fs->regs. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -@@ -30,7 +62,7 @@ - - Backport from mainline: - 2013-03-26 Walter Lee -- -+ - * config/tilegx/t-crtstuff: Add -fno-asynchronous-unwind-tables - -mcmodel=large to CRTSTUFF_T_CFLAGS_S variable. - -Index: libgcc/config/rs6000/ibm-ldouble.c -=================================================================== ---- a/src/libgcc/config/rs6000/ibm-ldouble.c (.../tags/gcc_4_8_1_release) -+++ b/src/libgcc/config/rs6000/ibm-ldouble.c (.../branches/gcc-4_8-branch) -@@ -42,10 +42,10 @@ - represented as (1.0, +0.0) or (1.0, -0.0), and the low part of a - NaN is don't-care. - -- This code currently assumes big-endian. */ -+ This code currently assumes the most significant double is in -+ the lower numbered register or lower addressed memory. */ - --#if (!defined (__LITTLE_ENDIAN__) \ -- && (defined (__MACH__) || defined (__powerpc__) || defined (_AIX))) -+#if defined (__MACH__) || defined (__powerpc__) || defined (_AIX) - - #define fabs(x) __builtin_fabs(x) - #define isless(x, y) __builtin_isless (x, y) -Index: libgcc/config/tilepro/atomic.h -=================================================================== ---- a/src/libgcc/config/tilepro/atomic.h (.../tags/gcc_4_8_1_release) -+++ b/src/libgcc/config/tilepro/atomic.h (.../branches/gcc-4_8-branch) -@@ -92,8 +92,6 @@ - compare-and-exchange routine, so may be potentially less efficient. */ - #endif - --#include --#include - #ifdef __tilegx__ - #include - #else -@@ -122,9 +120,9 @@ - - /* 64-bit integer compare-and-exchange. */ - static __inline __attribute__ ((always_inline)) -- int64_t arch_atomic_val_compare_and_exchange_8 (volatile int64_t * mem, -- int64_t oldval, -- int64_t newval) -+ long long arch_atomic_val_compare_and_exchange_8 (volatile long long -+ *mem, long long oldval, -+ long long newval) - { - #ifdef __tilegx__ - __insn_mtspr (SPR_CMPEXCH_VALUE, oldval); -@@ -139,7 +137,7 @@ - "R04" (newval_lo), "R05" (newval_hi), - "m" (*mem):"r20", "r21", "r22", "r23", "r24", "r25", - "r26", "r27", "r28", "r29", "memory"); -- return ((uint64_t) result_hi) << 32 | result_lo; -+ return ((long long) result_hi) << 32 | result_lo; - #endif - } - -@@ -150,11 +148,11 @@ - - - #define arch_atomic_val_compare_and_exchange(mem, o, n) \ -- ({ \ -+ __extension__ ({ \ - (__typeof(*(mem)))(__typeof(*(mem)-*(mem))) \ - ((sizeof(*(mem)) == 8) ? \ - arch_atomic_val_compare_and_exchange_8( \ -- (volatile int64_t*)(mem), (__typeof((o)-(o)))(o), \ -+ (volatile long long*)(mem), (__typeof((o)-(o)))(o), \ - (__typeof((n)-(n)))(n)) : \ - (sizeof(*(mem)) == 4) ? \ - arch_atomic_val_compare_and_exchange_4( \ -@@ -164,7 +162,7 @@ - }) - - #define arch_atomic_bool_compare_and_exchange(mem, o, n) \ -- ({ \ -+ __extension__ ({ \ - __typeof(o) __o = (o); \ - __builtin_expect( \ - __o == arch_atomic_val_compare_and_exchange((mem), __o, (n)), 1); \ -@@ -174,7 +172,7 @@ - /* Loop with compare_and_exchange until we guess the correct value. - Normally "expr" will be an expression using __old and __value. */ - #define __arch_atomic_update_cmpxchg(mem, value, expr) \ -- ({ \ -+ __extension__ ({ \ - __typeof(value) __value = (value); \ - __typeof(*(mem)) *__mem = (mem), __old = *__mem, __guess; \ - do { \ -@@ -189,12 +187,14 @@ - /* Generic atomic op with 8- or 4-byte variant. - The _mask, _addend, and _expr arguments are ignored on tilegx. */ - #define __arch_atomic_update(mem, value, op, _mask, _addend, _expr) \ -- ({ \ -+ __extension__ ({ \ - ((__typeof(*(mem))) \ - ((sizeof(*(mem)) == 8) ? (__typeof(*(mem)-*(mem)))__insn_##op( \ -- (void *)(mem), (int64_t)(__typeof((value)-(value)))(value)) : \ -+ (volatile void *)(mem), \ -+ (long long)(__typeof((value)-(value)))(value)) : \ - (sizeof(*(mem)) == 4) ? (int)__insn_##op##4( \ -- (void *)(mem), (int32_t)(__typeof((value)-(value)))(value)) : \ -+ (volatile void *)(mem), \ -+ (int)(__typeof((value)-(value)))(value)) : \ - __arch_atomic_error_bad_argument_size())); \ - }) - -@@ -224,7 +224,7 @@ - /* Generic atomic op with 8- or 4-byte variant. - The _op argument is ignored on tilepro. */ - #define __arch_atomic_update(mem, value, _op, mask, addend, expr) \ -- ({ \ -+ __extension__ ({ \ - (__typeof(*(mem)))(__typeof(*(mem)-*(mem))) \ - ((sizeof(*(mem)) == 8) ? \ - __arch_atomic_update_cmpxchg((mem), (value), (expr)) : \ -@@ -263,13 +263,13 @@ - __arch_atomic_update_cmpxchg(mem, mask, ~(__old & __value)) - - #define arch_atomic_bit_set(mem, bit) \ -- ({ \ -+ __extension__ ({ \ - __typeof(*(mem)) __mask = (__typeof(*(mem)))1 << (bit); \ - __mask & arch_atomic_or((mem), __mask); \ - }) - - #define arch_atomic_bit_clear(mem, bit) \ -- ({ \ -+ __extension__ ({ \ - __typeof(*(mem)) __mask = (__typeof(*(mem)))1 << (bit); \ - __mask & arch_atomic_and((mem), ~__mask); \ - }) -Index: libgcc/unwind-dw2.c -=================================================================== ---- a/src/libgcc/unwind-dw2.c (.../tags/gcc_4_8_1_release) -+++ b/src/libgcc/unwind-dw2.c (.../branches/gcc-4_8-branch) -@@ -59,6 +59,35 @@ - #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO) - #endif - -+/* ??? For the public function interfaces, we tend to gcc_assert that the -+ column numbers are in range. For the dwarf2 unwind info this does happen, -+ although so far in a case that doesn't actually matter. -+ -+ See PR49146, in which a call from x86_64 ms abi to x86_64 unix abi stores -+ the call-saved xmm registers and annotates them. We havn't bothered -+ providing support for the xmm registers for the x86_64 port primarily -+ because the 64-bit windows targets don't use dwarf2 unwind, using sjlj or -+ SEH instead. Adding the support for unix targets would generally be a -+ waste. However, some runtime libraries supplied with ICC do contain such -+ an unorthodox transition, as well as the unwind info to match. This loss -+ of register restoration doesn't matter in practice, because the exception -+ is caught in the native unix abi, where all of the xmm registers are -+ call clobbered. -+ -+ Ideally, we'd record some bit to notice when we're failing to restore some -+ register recorded in the unwind info, but to do that we need annotation on -+ the unix->ms abi edge, so that we know when the register data may be -+ discarded. And since this edge is also within the ICC library, we're -+ unlikely to be able to get the new annotation. -+ -+ Barring a magic solution to restore the ms abi defined 128-bit xmm registers -+ (as distictly opposed to the full runtime width) without causing extra -+ overhead for normal unix abis, the best solution seems to be to simply -+ ignore unwind data for unknown columns. */ -+ -+#define UNWIND_COLUMN_IN_RANGE(x) \ -+ __builtin_expect((x) <= DWARF_FRAME_REGISTERS, 1) -+ - #ifdef REG_VALUE_IN_UNWIND_CONTEXT - typedef _Unwind_Word _Unwind_Context_Reg_Val; - -@@ -939,14 +968,19 @@ - reg = insn & 0x3f; - insn_ptr = read_uleb128 (insn_ptr, &utmp); - offset = (_Unwind_Sword) utmp * fs->data_align; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how -- = REG_SAVED_OFFSET; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_OFFSET; -+ fs->regs.reg[reg].loc.offset = offset; -+ } - } - else if ((insn & 0xc0) == DW_CFA_restore) - { - reg = insn & 0x3f; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how = REG_UNSAVED; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ fs->regs.reg[reg].how = REG_UNSAVED; - } - else switch (insn) - { -@@ -977,26 +1011,35 @@ - insn_ptr = read_uleb128 (insn_ptr, ®); - insn_ptr = read_uleb128 (insn_ptr, &utmp); - offset = (_Unwind_Sword) utmp * fs->data_align; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how -- = REG_SAVED_OFFSET; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_OFFSET; -+ fs->regs.reg[reg].loc.offset = offset; -+ } - break; - - case DW_CFA_restore_extended: - insn_ptr = read_uleb128 (insn_ptr, ®); - /* FIXME, this is wrong; the CIE might have said that the - register was saved somewhere. */ -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN(reg)].how = REG_UNSAVED; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ fs->regs.reg[reg].how = REG_UNSAVED; - break; - - case DW_CFA_same_value: - insn_ptr = read_uleb128 (insn_ptr, ®); -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN(reg)].how = REG_UNSAVED; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ fs->regs.reg[reg].how = REG_UNSAVED; - break; - - case DW_CFA_undefined: - insn_ptr = read_uleb128 (insn_ptr, ®); -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN(reg)].how = REG_UNDEFINED; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ fs->regs.reg[reg].how = REG_UNDEFINED; - break; - - case DW_CFA_nop: -@@ -1007,9 +1050,12 @@ - _uleb128_t reg2; - insn_ptr = read_uleb128 (insn_ptr, ®); - insn_ptr = read_uleb128 (insn_ptr, ®2); -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how = REG_SAVED_REG; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.reg = -- (_Unwind_Word)reg2; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_REG; -+ fs->regs.reg[reg].loc.reg = (_Unwind_Word)reg2; -+ } - } - break; - -@@ -1067,8 +1113,12 @@ - - case DW_CFA_expression: - insn_ptr = read_uleb128 (insn_ptr, ®); -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how = REG_SAVED_EXP; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.exp = insn_ptr; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_EXP; -+ fs->regs.reg[reg].loc.exp = insn_ptr; -+ } - insn_ptr = read_uleb128 (insn_ptr, &utmp); - insn_ptr += utmp; - break; -@@ -1078,9 +1128,12 @@ - insn_ptr = read_uleb128 (insn_ptr, ®); - insn_ptr = read_sleb128 (insn_ptr, &stmp); - offset = stmp * fs->data_align; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how -- = REG_SAVED_OFFSET; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_OFFSET; -+ fs->regs.reg[reg].loc.offset = offset; -+ } - break; - - case DW_CFA_def_cfa_sf: -@@ -1103,25 +1156,34 @@ - insn_ptr = read_uleb128 (insn_ptr, ®); - insn_ptr = read_uleb128 (insn_ptr, &utmp); - offset = (_Unwind_Sword) utmp * fs->data_align; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how -- = REG_SAVED_VAL_OFFSET; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_VAL_OFFSET; -+ fs->regs.reg[reg].loc.offset = offset; -+ } - break; - - case DW_CFA_val_offset_sf: - insn_ptr = read_uleb128 (insn_ptr, ®); - insn_ptr = read_sleb128 (insn_ptr, &stmp); - offset = stmp * fs->data_align; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how -- = REG_SAVED_VAL_OFFSET; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_VAL_OFFSET; -+ fs->regs.reg[reg].loc.offset = offset; -+ } - break; - - case DW_CFA_val_expression: - insn_ptr = read_uleb128 (insn_ptr, ®); -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how -- = REG_SAVED_VAL_EXP; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.exp = insn_ptr; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_VAL_EXP; -+ fs->regs.reg[reg].loc.exp = insn_ptr; -+ } - insn_ptr = read_uleb128 (insn_ptr, &utmp); - insn_ptr += utmp; - break; -@@ -1147,9 +1209,12 @@ - insn_ptr = read_uleb128 (insn_ptr, ®); - insn_ptr = read_uleb128 (insn_ptr, &utmp); - offset = (_Unwind_Word) utmp * fs->data_align; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how -- = REG_SAVED_OFFSET; -- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = -offset; -+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg); -+ if (UNWIND_COLUMN_IN_RANGE (reg)) -+ { -+ fs->regs.reg[reg].how = REG_SAVED_OFFSET; -+ fs->regs.reg[reg].loc.offset = -offset; -+ } - break; - - default: -Index: gcc/file-find.h -=================================================================== ---- a/src/gcc/file-find.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/file-find.h (.../branches/gcc-4_8-branch) -@@ -38,7 +38,7 @@ - }; - - extern void find_file_set_debug (bool); --extern char *find_a_file (struct path_prefix *, const char *); -+extern char *find_a_file (struct path_prefix *, const char *, int); - extern void add_prefix (struct path_prefix *, const char *); - extern void prefix_from_env (const char *, struct path_prefix *); - extern void prefix_from_string (const char *, struct path_prefix *); -Index: gcc/DATESTAMP -=================================================================== ---- a/src/gcc/DATESTAMP (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/DATESTAMP (.../branches/gcc-4_8-branch) -@@ -1 +1 @@ --20130531 -+20130717 -Index: gcc/ipa-cp.c -=================================================================== ---- a/src/gcc/ipa-cp.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ipa-cp.c (.../branches/gcc-4_8-branch) -@@ -1507,7 +1507,8 @@ - tree otr_type; - tree t; - -- if (param_index == -1) -+ if (param_index == -1 -+ || known_vals.length () <= (unsigned int) param_index) - return NULL_TREE; - - if (!ie->indirect_info->polymorphic) -@@ -1528,8 +1529,7 @@ - t = NULL; - } - else -- t = (known_vals.length () > (unsigned int) param_index -- ? known_vals[param_index] : NULL); -+ t = known_vals[param_index]; - - if (t && - TREE_CODE (t) == ADDR_EXPR -Index: gcc/configure -=================================================================== ---- a/src/gcc/configure (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/configure (.../branches/gcc-4_8-branch) -@@ -23281,35 +23281,9 @@ - tls_first_major=0 - tls_first_minor=0 - ;; -- powerpc-*-*) -+ powerpc64*-*-*) - conftest_s=' - .section ".tdata","awT",@progbits -- .align 2 --ld0: .space 4 --ld1: .space 4 --x1: .space 4 --x2: .space 4 --x3: .space 4 -- .text -- addi 3,31,ld0@got@tlsgd -- bl __tls_get_addr -- addi 3,31,x1@got@tlsld -- bl __tls_get_addr -- addi 9,3,x1@dtprel -- addis 9,3,x2@dtprel@ha -- addi 9,9,x2@dtprel@l -- lwz 9,x3@got@tprel(31) -- add 9,9,x@tls -- addi 9,2,x1@tprel -- addis 9,2,x2@tprel@ha -- addi 9,9,x2@tprel@l' -- tls_first_major=2 -- tls_first_minor=14 -- tls_as_opt="-a32 --fatal-warnings" -- ;; -- powerpc64-*-*) -- conftest_s=' -- .section ".tdata","awT",@progbits - .align 3 - ld0: .space 8 - ld1: .space 8 -@@ -23341,6 +23315,32 @@ - tls_first_minor=14 - tls_as_opt="-a64 --fatal-warnings" - ;; -+ powerpc*-*-*) -+ conftest_s=' -+ .section ".tdata","awT",@progbits -+ .align 2 -+ld0: .space 4 -+ld1: .space 4 -+x1: .space 4 -+x2: .space 4 -+x3: .space 4 -+ .text -+ addi 3,31,ld0@got@tlsgd -+ bl __tls_get_addr -+ addi 3,31,x1@got@tlsld -+ bl __tls_get_addr -+ addi 9,3,x1@dtprel -+ addis 9,3,x2@dtprel@ha -+ addi 9,9,x2@dtprel@l -+ lwz 9,x3@got@tprel(31) -+ add 9,9,x@tls -+ addi 9,2,x1@tprel -+ addis 9,2,x2@tprel@ha -+ addi 9,9,x2@tprel@l' -+ tls_first_major=2 -+ tls_first_minor=14 -+ tls_as_opt="-a32 --fatal-warnings" -+ ;; - s390-*-*) - conftest_s=' - .section ".tdata","awT",@progbits -@@ -26472,6 +26472,9 @@ - case "$target:$tm_file" in - powerpc64-*-freebsd* | powerpc64*-*-linux* | powerpc*-*-linux*rs6000/biarch64.h*) - case "$target" in -+ *le-*-linux*) -+ emul_name="-melf64lppc" -+ ;; - *-*-linux*) - emul_name="-melf64ppc" - ;; -Index: gcc/ChangeLog -=================================================================== ---- a/src/gcc/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,348 @@ -+2013-07-11 Georg-Johann Lay -+ -+ Backport from 2013-07-11 trunk r200901. -+ -+ PR target/57631 -+ * config/avr/avr.c (avr_set_current_function): Sanity-check signal -+ name seen by assembler/linker if available. -+ -+2013-07-10 Georg-Johann Lay -+ -+ Backport from 2013-07-10 trunk r200872. -+ -+ PR target/57844 -+ * config/avr/avr.c (avr_prologue_setup_frame): Trunk -size to mode -+ of my_fp. -+ -+2013-07-10 Georg-Johann Lay -+ -+ Backport from 2013-07-10 trunk r200870. -+ -+ PR target/57506 -+ * config/avr/avr-mcus.def (atmega16hva, atmega16hva2, atmega16hvb) -+ (atmega16m1, atmega16u4, atmega32a, atmega32c1, atmega32hvb) -+ (atmega32m1, atmega32u4, atmega32u6, atmega64c1, atmega64m1): -+ Remove duplicate devices. -+ * config/avr/gen-avr-mmcu-texi.c (print_mcus): Fail on duplicate MCUs. -+ * config/avr/t-multilib: Regenerate. -+ * config/avr/avr-tables.opt: Regenerate. -+ * doc/avr-mmcu.texi: Regenerate. -+ -+2013-07-10 Georg-Johann Lay -+ -+ PR target/56987 -+ * config/avr/avr.opt (Waddr-space-convert): Fix typo. -+ -+2013-07-09 Joseph Myers -+ -+ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Only -+ adjust register size for TDmode and TFmode for VSX registers. -+ -+2013-07-08 Kai Tietz -+ -+ Backport from mainline -+ PR target/56892 -+ * config/i386/i386.c (TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P): Define as -+ hook_bool_const_tree_true. -+ -+2013-07-08 Uros Bizjak -+ -+ Backport from mainline -+ 2013-07-07 Uros Bizjak -+ -+ * config/i386/driver-i386.c (host_detect_local_cpu): Do not check -+ signature_TM2_ebx, it interferes with signature_INTEL_ebx. -+ -+ Backport from mainline -+ 2013-07-06 Uros Bizjak -+ -+ * config/i386/sse.md (sse_movlhps): Change alternative 3 -+ of operand 2 to "m". -+ -+2013-07-08 Eric Botcazou -+ -+ * Makefile.in (tree-ssa-reassoc.o): Add dependency on $(PARAMS_H). -+ -+2013-07-08 Jakub Jelinek -+ -+ PR rtl-optimization/57829 -+ * simplify-rtx.c (simplify_binary_operation_1) : Ensure that -+ mask bits outside of mode are just sign-extension from mode to HWI. -+ -+2013-07-03 Jakub Jelinek -+ -+ PR target/57777 -+ * config/i386/predicates.md (vsib_address_operand): Disallow -+ SYMBOL_REF or LABEL_REF in parts.disp if TARGET_64BIT && flag_pic. -+ -+2013-06-30 Terry Guo -+ -+ Backport from mainline -+ 2013-03-27 Bin Cheng -+ -+ PR target/56102 -+ * config/arm/arm.c (thumb1_rtx_costs, thumb1_size_rtx_costs): Fix -+ rtx costs for SET/ASHIFT/ASHIFTRT/LSHIFTRT/ROTATERT patterns with -+ mult-word mode. -+ -+2013-06-28 Jakub Jelinek -+ -+ PR target/57736 -+ * config/i386/i386.c (ix86_expand_builtin): If target == NULL -+ and mode is VOIDmode, don't create a VOIDmode pseudo to copy result -+ into. -+ -+2013-06-27 Jakub Jelinek -+ -+ PR target/57623 -+ * config/i386/i386.md (bmi_bextr_): Swap predicates and -+ constraints of operand 1 and 2. -+ -+ PR target/57623 -+ * config/i386/i386.md (bmi2_bzhi_3): Swap AND arguments -+ to match RTL canonicalization. Swap predicates and -+ constraints of operand 1 and 2. -+ -+ * tree-vect-stmts.c (vectorizable_store): Move ptr_incr var -+ decl before the loop, initialize to NULL. -+ (vectorizable_load): Initialize ptr_incr to NULL. -+ -+2013-06-24 Martin Jambor -+ -+ PR tree-optimization/57358 -+ * ipa-prop.c (parm_ref_data_preserved_p): Always return true when -+ not optimizing. -+ -+2013-06-24 Alan Modra -+ -+ * config/rs6000/rs6000.c (vspltis_constant): Correct for little-endian. -+ (gen_easy_altivec_constant): Likewise. -+ * config/rs6000/predicates.md (easy_vector_constant_add_self, -+ easy_vector_constant_msb): Likewise. -+ -+2013-06-21 Uros Bizjak -+ -+ Backport from mainline -+ 2013-06-20 Uros Bizjak -+ -+ PR target/57655 -+ * config/i386/i386.c (construct_container): Report error if -+ long double is used with disabled x87 float returns. -+ -+2013-06-20 Wei Mi -+ -+ Backport from mainline -+ 2013-06-19 Wei Mi -+ -+ PR rtl-optimization/57518 -+ * ira.c (set_paradoxical_subreg): Set pdx_subregs[regno] -+ if regno is used in paradoxical subreg. -+ (update_equiv_regs): Check pdx_subregs[regno] before -+ set a reg to be equivalent with a mem. -+ -+ -+2013-06-20 David Edelsohn -+ -+ Backport from mainline -+ 2013-06-19 David Edelsohn -+ -+ PR driver/57652 -+ * collect2.c (collect_atexit): New. -+ (collect_exit): Delete. -+ (main): Register collect_atexit with atexit. -+ (collect_wait): Change collect_exit to exit. -+ (do_wait): Same. -+ * collect2.h (collect_exit): Delete. -+ * tlink.c (do_tlink): Rename exit to ret. Change collect_exit to exit. -+ -+2013-06-19 Matthias Klose -+ -+ PR driver/57651 -+ * file-find.h (find_a_file): Add a mode parameter. -+ * file-find.c (find_a_file): Likewise. -+ * gcc-ar.c (main): Call find_a_file with R_OK for the plugin, -+ with X_OK for the executables. -+ * collect2.c (main): Call find_a_file with X_OK. -+ -+2013-06-19 Igor Zamyatin -+ -+ * doc/invoke.texi (core-avx2): Document. -+ (atom): Updated with MOVBE. -+ -+2013-06-19 Jakub Jelinek -+ -+ PR driver/57651 -+ * gcc-ar.c (main): If not CROSS_DIRECTORY_STRUCTURE, look for -+ PERSONALITY in $PATH derived prefixes. -+ -+2013-06-19 Paolo Carlini -+ -+ PR c++/56544 -+ * doc/cpp.texi [Standard Predefined Macros, __cplusplus]: Document -+ that now in C++ the value is correct per the C++ standards. -+ -+2013-06-19 Alan Modra -+ -+ Apply mainline patches -+ 2013-06-13 Alan Modra -+ * config/rs6000/rs6000.h (LONG_DOUBLE_LARGE_FIRST): Define. -+ * config/rs6000/rs6000.md (signbittf2): New insn. -+ (extenddftf2_internal): Use LONG_DOUBLE_LARGE_FIRST. -+ (abstf2_internal, cmptf_internal2): Likewise. -+ * config/rs6000/spe.md (spe_abstf2_cmp, spe_abstf2_tst): Likewise. -+ -+ 2013-06-11 Anton Blanchard -+ * config/rs6000/rs6000.c (rs6000_adjust_atomic_subword): Calculate -+ correct shift value in little-endian mode. -+ -+ 2013-06-07 Alan Modra -+ * config/rs6000/rs6000.c (setup_incoming_varargs): Round up -+ va_list_gpr_size. -+ -+ 2013-06-04 Alan Modra -+ * config/rs6000/rs6000.c (output_toc): Correct little-endian float -+ constant output. -+ -+ 2013-05-10 Alan Modra -+ * configure.ac (HAVE_AS_TLS): Swap powerpc64 and powerpc cases. -+ (HAVE_LD_LARGE_TOC): Don't mention AIX in help text. -+ * configure: Regenerate. -+ -+ 2013-05-09 Alan Modra -+ * configure.ac (HAVE_AS_TLS): Enable tests for powerpcle and -+ powerpc64le. -+ * configure: Regenerate. -+ -+ 2013-05-07 Anton Blanchard -+ * configure.ac (HAVE_LD_LARGE_TOC): Use right linker emulation -+ for powerpc64 little endian. -+ * configure: Regenerate. -+ -+ 2013-05-06 Alan Modra -+ * config/rs6000/linux.h (DEFAULT_ASM_ENDIAN): Define. -+ (LINK_OS_LINUX_EMUL): Use ENDIAN_SELECT. -+ * config/rs6000/linux64.h (DEFAULT_ASM_ENDIAN): Define. -+ * config/rs6000/sysv4le.h (DEFAULT_ASM_ENDIAN): Define. -+ (LINK_TARGET_SPEC): Use ENDIAN_SELECT. -+ * config/rs6000/sysv4.h (DEFAULT_ASM_ENDIAN): Define as -mbig. -+ -+ 2013-05-06 Alan Modra -+ * config/rs6000/sysv4.h (ENDIAN_SELECT): Define, extracted from -+ (ASM_SPEC): ..here. Emit DEFAULT_ASM_ENDIAN too. -+ (DEFAULT_ASM_ENDIAN): Define. -+ (CC1_SPEC, LINK_TARGET_SPEC): Use ENDIAN_SELECT. -+ * config/rs6000/linux64.h (ASM_SPEC32): Remove endian options. -+ Update -K PIC clause from sysv4.h. -+ (ASM_SPEC_COMMON): Use ENDIAN_SELECT. -+ (LINK_OS_LINUX_EMUL32, LINK_OS_LINUX_EMUL64): Likewise. -+ -+ 2013-05-06 Alan Modra -+ * config/rs6000/rs6000.md (bswapdi 2nd splitter): Don't swap words -+ twice for little-endian. -+ (ashrdi3_no_power, ashrdi3): Support little-endian. -+ -+ 2013-04-25 Alan Modra -+ * config.gcc: Support little-endian powerpc-linux targets. -+ * config/rs6000/linux.h (LINK_OS_LINUX_EMUL): Define. -+ (LINK_OS_LINUX_SPEC): Define. -+ * config/rs6000/linuxspe.h (TARGET_DEFAULT): -+ Preserve MASK_LITTLE_ENDIAN. -+ * config/rs6000/default64.h (TARGET_DEFAULT): Likewise. -+ * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Likewise. -+ * config/rs6000/linux64.h (OPTION_LITTLE_ENDIAN): Don't zero. -+ (LINK_OS_LINUX_EMUL32, LINK_OS_LINUX_EMUL64): Define. -+ (LINK_OS_LINUX_SPEC32, LINK_OS_LINUX_SPEC64): Use above. -+ * config/rs6000/rs6000.c (output_toc): Don't use .tc for TARGET_ELF. -+ Correct fp word order for little-endian. Don't shift toc entries -+ smaller than a word for little-endian. -+ * config/rs6000/rs6000.md (bswaphi2, bswapsi2 split): Comment. -+ (bswapdi2 splits): Correct low-part subreg for little-endian. -+ Remove wrong BYTES_BIG_ENDIAN tests, and rename vars to remove -+ low/high where such is correct only for be. -+ * config/rs6000/sysv4.h (SUBTARGET_OVERRIDE_OPTIONS): Allow -+ little-endian for -mcall-aixdesc. -+ -+2013-06-12 Martin Jambor -+ -+ * ipa-cp.c (ipa_get_indirect_edge_target_1): Check that param_index is -+ within bounds at the beginning of the function. -+ -+2013-06-12 Jakub Jelinek -+ -+ PR tree-optimization/57537 -+ * tree-vect-patterns.c (vect_recog_widen_mult_pattern): If -+ vect_handle_widen_op_by_const, convert oprnd1 to half_type1. -+ -+2013-06-10 Uros Bizjak -+ -+ Backport from mainline -+ 2013-06-10 Uros Bizjak -+ -+ * config/alpha/alpha.c (alpha_emit_xfloating_compare): Also use -+ cmp_code to construct REG_EQUAL note. -+ -+2013-06-10 Oleg Endo -+ -+ Backport from mainline -+ 2013-05-20 Oleg Endo -+ -+ PR target/56547 -+ * config/sh/sh.md (fmasf4): Remove empty constraints strings. -+ (*fmasf4, *fmasf4_media): New insns. -+ -+2013-06-09 Jakub Jelinek -+ -+ PR target/57568 -+ * config/i386/i386.md (TARGET_READ_MODIFY_WRITE peepholes): Ensure -+ that operands[2] doesn't overlap with operands[0]. -+ -+2013-06-07 Richard Sandiford -+ -+ * recog.c (offsettable_address_addr_space_p): Fix calculation of -+ address mode. Move pointer mode initialization to the same place. -+ -+2013-06-07 Sofiane Naci -+ -+ Backport from mainline -+ * config/aarch64/aarch64.md (*movdi_aarch64): Define "simd" attribute. -+ -+2013-06-07 Uros Bizjak -+ -+ Backport from mainline -+ 2013-06-05 Uros Bizjak -+ -+ * config/alpha/alpha.c (alpha_emit_conditional_move): Swap all -+ GE, GT, GEU and GTU compares, modulo DImode compares with zero. -+ -+ Backport from mainline -+ 2013-05-23 Uros Bizjak -+ -+ PR target/57379 -+ * config/alpha/alpha.md (unspec): Add UNSPEC_XFLT_COMPARE. -+ * config/alpha/alpha.c (alpha_emit_xfloating_compare): Construct -+ REG_EQUAL note as UNSPEC_XFLT_COMPARE unspec. -+ -+2013-06-04 Bill Schmidt -+ -+ Backport from mainline. -+ 2013-05-22 Bill Schmidt -+ -+ * config/rs6000/rs6000.h (MALLOC_ABI_ALIGNMENT): New #define. -+ -+2013-06-03 James Greenhalgh -+ -+ Backport from mainline. -+ 2013-04-25 James Greenhalgh -+ -+ * config/aarch64/aarch64.c (aarch64_print_operand): Fix asm_fprintf -+ format specifier in 'X' case. -+ -+2013-05-31 Richard Henderson -+ -+ PR target/56742 -+ * config/i386/i386.c (ix86_seh_fixup_eh_fallthru): New. -+ (ix86_reorg): Call it. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -@@ -7,7 +357,7 @@ - Backport from mainline - 2013-05-02 Greta Yorsh - -- PR target/56732 -+ PR target/56732 - * config/arm/arm.c (arm_expand_epilogue): Check really_return before - generating simple_return for naked functions. - -@@ -203,14 +553,14 @@ - - 2013-05-09 Martin Jambor - -- PR middle-end/56988 -- * ipa-prop.h (ipa_agg_replacement_value): New flag by_ref. -- * ipa-cp.c (find_aggregate_values_for_callers_subset): Fill in the -+ PR middle-end/56988 -+ * ipa-prop.h (ipa_agg_replacement_value): New flag by_ref. -+ * ipa-cp.c (find_aggregate_values_for_callers_subset): Fill in the - by_ref flag of ipa_agg_replacement_value structures. -- (known_aggs_to_agg_replacement_list): Likewise. -- * ipa-prop.c (write_agg_replacement_chain): Stream by_ref flag. -- (read_agg_replacement_chain): Likewise. -- (ipcp_transform_function): Also check that by_ref flags match. -+ (known_aggs_to_agg_replacement_list): Likewise. -+ * ipa-prop.c (write_agg_replacement_chain): Stream by_ref flag. -+ (read_agg_replacement_chain): Likewise. -+ (ipcp_transform_function): Also check that by_ref flags match. - - 2013-05-08 Diego Novillo - -@@ -315,7 +665,7 @@ - 2013-04-25 Marek Polacek - - PR tree-optimization/57066 -- * builtins.c (fold_builtin_logb): Return +Inf for -Inf. -+ * builtins.c (fold_builtin_logb): Return +Inf for -Inf. - - 2013-05-02 Vladimir Makarov - -@@ -351,40 +701,40 @@ - Backport from mainline - 2013-04-24 Vladimir Makarov - -- PR rtl-optimizations/57046 -- * lra-constraints (split_reg): Set up lra_risky_transformations_p -- for multi-reg splits. -+ PR rtl-optimizations/57046 -+ * lra-constraints (split_reg): Set up lra_risky_transformations_p -+ for multi-reg splits. - - 2013-05-02 Vladimir Makarov - - Backport from mainline - 2013-04-22 Vladimir Makarov - -- PR target/57018 -- * lra-eliminations.c (mark_not_eliminable): Prevent elimination of -- a set sp if no stack realignment. -+ PR target/57018 -+ * lra-eliminations.c (mark_not_eliminable): Prevent elimination of -+ a set sp if no stack realignment. - - 2013-05-02 Vladimir Makarov - - Backport from mainline - 2013-04-18 Vladimir Makarov - -- PR rtl-optimization/56999 -- * lra-coalesce.c (coalescable_pseudo_p): Remove 2nd parameter and -- related code. -- (lra_coalesce): Remove split_origin_bitmap and related code. -- * lra.c (lra): Coalesce after undoing inheritance. Recreate live -- ranges if necessary. -+ PR rtl-optimization/56999 -+ * lra-coalesce.c (coalescable_pseudo_p): Remove 2nd parameter and -+ related code. -+ (lra_coalesce): Remove split_origin_bitmap and related code. -+ * lra.c (lra): Coalesce after undoing inheritance. Recreate live -+ ranges if necessary. - - 2013-05-02 Vladimir Makarov - - Backport from mainline - 2013-04-19 Vladimir Makarov - -- PR rtl-optimization/56847 -- * lra-constraints.c (process_alt_operands): Discourage alternative -- with non-matche doffsettable memory constraint fro memory with -- known offset. -+ PR rtl-optimization/56847 -+ * lra-constraints.c (process_alt_operands): Discourage alternative -+ with non-matche doffsettable memory constraint fro memory with -+ known offset. - - 2013-05-02 Ian Bolton - -Index: gcc/testsuite/gcc.target/powerpc/altivec-consts.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/powerpc/altivec-consts.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/powerpc/altivec-consts.c (.../branches/gcc-4_8-branch) -@@ -11,31 +11,24 @@ - typedef __attribute__ ((vector_size (16))) unsigned short v8hi; - typedef __attribute__ ((vector_size (16))) unsigned int v4si; - --char w[16] __attribute__((aligned(16))); -- -- --/* Emulate the vspltis? instructions on a 16-byte array of chars. */ -+typedef __attribute__((aligned(16))) char c16[16]; -+typedef __attribute__((aligned(16))) short s8[8]; -+typedef __attribute__((aligned(16))) int i4[4]; - --void vspltisb (char *v, int val) --{ -- int i; -- for (i = 0; i < 16; i++) -- v[i] = val; --} -+#define V16QI(V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16) \ -+ v16qi v = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16}; \ -+ static c16 w = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16}; \ -+ check_v16qi (v, w); - --void vspltish (char *v, int val) --{ -- int i; -- for (i = 0; i < 16; i += 2) -- v[i] = val >> 7, v[i + 1] = val; --} -+#define V8HI(V1,V2,V3,V4,V5,V6,V7,V8) \ -+ v8hi v = {V1,V2,V3,V4,V5,V6,V7,V8}; \ -+ static s8 w = {V1,V2,V3,V4,V5,V6,V7,V8}; \ -+ check_v8hi (v, w); - --void vspltisw (char *v, int val) --{ -- int i; -- for (i = 0; i < 16; i += 4) -- v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val; --} -+#define V4SI(V1,V2,V3,V4) \ -+ v4si v = {V1,V2,V3,V4}; \ -+ static i4 w = {V1,V2,V3,V4}; \ -+ check_v4si (v, w); - - - /* Use three different check functions for each mode-instruction pair. -@@ -48,13 +41,13 @@ - abort (); - } - --void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2) -+void __attribute__ ((noinline)) check_v8hi (v8hi v1, short *v2) - { - if (memcmp (&v1, v2, 16)) - abort (); - } - --void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2) -+void __attribute__ ((noinline)) check_v4si (v4si v1, int *v2) - { - if (memcmp (&v1, v2, 16)) - abort (); -@@ -65,72 +58,52 @@ - - void v16qi_vspltisb () - { -- v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 }; -- vspltisb (w, 15); -- check_v16qi (v, w); -+ V16QI (15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15); - } - - void v16qi_vspltisb_neg () - { -- v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 }; -- vspltisb (w, -5); -- check_v16qi (v, w); -+ V16QI (-5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5); - } - - void v16qi_vspltisb_addself () - { -- v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 }; -- vspltisb (w, 30); -- check_v16qi (v, w); -+ V16QI (30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30); - } - - void v16qi_vspltisb_neg_addself () - { -- v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 }; -- vspltisb (w, -24); -- check_v16qi (v, w); -+ V16QI (-24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24); - } - - void v16qi_vspltish () - { -- v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 }; -- vspltish (w, 15); -- check_v16qi (v, w); -+ V16QI (0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15); - } - - void v16qi_vspltish_addself () - { -- v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 }; -- vspltish (w, 30); -- check_v16qi (v, w); -+ V16QI (0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30); - } - - void v16qi_vspltish_neg () - { -- v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 }; -- vspltish (w, -5); -- check_v16qi (v, w); -+ V16QI (-1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5); - } - - void v16qi_vspltisw () - { -- v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 }; -- vspltisw (w, 15); -- check_v16qi (v, w); -+ V16QI (0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15); - } - - void v16qi_vspltisw_addself () - { -- v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 }; -- vspltisw (w, 30); -- check_v16qi (v, w); -+ V16QI (0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30); - } - - void v16qi_vspltisw_neg () - { -- v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 }; -- vspltisw (w, -5); -- check_v16qi (v, w); -+ V16QI (-1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5); - } - - -@@ -138,144 +111,104 @@ - - void v8hi_vspltisb () - { -- v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F }; -- vspltisb (w, 15); -- check_v8hi (v, w); -+ V8HI (0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F); - } - - void v8hi_vspltisb_addself () - { -- v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E }; -- vspltisb (w, 30); -- check_v8hi (v, w); -+ V8HI (0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E); - } - - void v8hi_vspltisb_neg () - { -- v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB }; -- vspltisb (w, -5); -- check_v8hi (v, w); -+ V8HI (0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB); - } - - void v8hi_vspltish () - { -- v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 }; -- vspltish (w, 15); -- check_v8hi (v, w); -+ V8HI (15, 15, 15, 15, 15, 15, 15, 15); - } - - void v8hi_vspltish_neg () - { -- v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 }; -- vspltish (w, -5); -- check_v8hi (v, w); -+ V8HI (-5, -5, -5, -5, -5, -5, -5, -5); - } - - void v8hi_vspltish_addself () - { -- v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 }; -- vspltish (w, 30); -- check_v8hi (v, w); -+ V8HI (30, 30, 30, 30, 30, 30, 30, 30); - } - - void v8hi_vspltish_neg_addself () - { -- v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 }; -- vspltish (w, -24); -- check_v8hi (v, w); -+ V8HI (-24, -24, -24, -24, -24, -24, -24, -24); - } - - void v8hi_vspltisw () - { -- v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 }; -- vspltisw (w, 15); -- check_v8hi (v, w); -+ V8HI (0, 15, 0, 15, 0, 15, 0, 15); - } - - void v8hi_vspltisw_addself () - { -- v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 }; -- vspltisw (w, 30); -- check_v8hi (v, w); -+ V8HI (0, 30, 0, 30, 0, 30, 0, 30); - } - - void v8hi_vspltisw_neg () - { -- v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 }; -- vspltisw (w, -5); -- check_v8hi (v, w); -+ V8HI (-1, -5, -1, -5, -1, -5, -1, -5); - } - - /* V4SI tests. */ - - void v4si_vspltisb () - { -- v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F }; -- vspltisb (w, 15); -- check_v4si (v, w); -+ V4SI (0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F); - } - - void v4si_vspltisb_addself () - { -- v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E }; -- vspltisb (w, 30); -- check_v4si (v, w); -+ V4SI (0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E); - } - - void v4si_vspltisb_neg () - { -- v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB }; -- vspltisb (w, -5); -- check_v4si (v, w); -+ V4SI (0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB); - } - - void v4si_vspltish () - { -- v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F }; -- vspltish (w, 15); -- check_v4si (v, w); -+ V4SI (0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F); - } - - void v4si_vspltish_addself () - { -- v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E }; -- vspltish (w, 30); -- check_v4si (v, w); -+ V4SI (0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E); - } - - void v4si_vspltish_neg () - { -- v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB }; -- vspltish (w, -5); -- check_v4si (v, w); -+ V4SI (0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB); - } - - void v4si_vspltisw () - { -- v4si v = { 15, 15, 15, 15 }; -- vspltisw (w, 15); -- check_v4si (v, w); -+ V4SI (15, 15, 15, 15); - } - - void v4si_vspltisw_neg () - { -- v4si v = { -5, -5, -5, -5 }; -- vspltisw (w, -5); -- check_v4si (v, w); -+ V4SI (-5, -5, -5, -5); - } - - void v4si_vspltisw_addself () - { -- v4si v = { 30, 30, 30, 30 }; -- vspltisw (w, 30); -- check_v4si (v, w); -+ V4SI (30, 30, 30, 30); - } - - void v4si_vspltisw_neg_addself () - { -- v4si v = { -24, -24, -24, -24 }; -- vspltisw (w, -24); -- check_v4si (v, w); -+ V4SI (-24, -24, -24, -24); - } - - -@@ -316,3 +249,5 @@ - v4si_vspltisw_neg_addself (); - return 0; - } -+ -+/* { dg-final { scan-assembler-not "lvx" { target { ! powerpc*le-*-* } } } } */ -Index: gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,253 @@ -+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ -+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ -+/* { dg-require-effective-target powerpc_altivec_ok } */ -+/* { dg-options "-maltivec -mabi=altivec -O2" } */ -+ -+/* Check that "easy" AltiVec constants are correctly synthesized. */ -+ -+extern void abort (void); -+ -+typedef __attribute__ ((vector_size (16))) unsigned char v16qi; -+typedef __attribute__ ((vector_size (16))) unsigned short v8hi; -+typedef __attribute__ ((vector_size (16))) unsigned int v4si; -+ -+typedef __attribute__((aligned(16))) char c16[16]; -+typedef __attribute__((aligned(16))) short s8[8]; -+typedef __attribute__((aligned(16))) int i4[4]; -+ -+#define V16QI(V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16) \ -+ v16qi v = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16}; \ -+ static c16 w = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16}; \ -+ check_v16qi (v, w); -+ -+#define V8HI(V1,V2,V3,V4,V5,V6,V7,V8) \ -+ v8hi v = {V1,V2,V3,V4,V5,V6,V7,V8}; \ -+ static s8 w = {V1,V2,V3,V4,V5,V6,V7,V8}; \ -+ check_v8hi (v, w); -+ -+#define V4SI(V1,V2,V3,V4) \ -+ v4si v = {V1,V2,V3,V4}; \ -+ static i4 w = {V1,V2,V3,V4}; \ -+ check_v4si (v, w); -+ -+ -+/* Use three different check functions for each mode-instruction pair. -+ The callers have no typecasting and no addressable vectors, to make -+ the test more robust. */ -+ -+void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2) -+{ -+ if (memcmp (&v1, v2, 16)) -+ abort (); -+} -+ -+void __attribute__ ((noinline)) check_v8hi (v8hi v1, short *v2) -+{ -+ if (memcmp (&v1, v2, 16)) -+ abort (); -+} -+ -+void __attribute__ ((noinline)) check_v4si (v4si v1, int *v2) -+{ -+ if (memcmp (&v1, v2, 16)) -+ abort (); -+} -+ -+ -+/* V16QI tests. */ -+ -+void v16qi_vspltisb () -+{ -+ V16QI (15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15); -+} -+ -+void v16qi_vspltisb_neg () -+{ -+ V16QI (-5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5); -+} -+ -+void v16qi_vspltisb_addself () -+{ -+ V16QI (30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30); -+} -+ -+void v16qi_vspltisb_neg_addself () -+{ -+ V16QI (-24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24); -+} -+ -+void v16qi_vspltish () -+{ -+ V16QI (15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0); -+} -+ -+void v16qi_vspltish_addself () -+{ -+ V16QI (30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0); -+} -+ -+void v16qi_vspltish_neg () -+{ -+ V16QI (-5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1); -+} -+ -+void v16qi_vspltisw () -+{ -+ V16QI (15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0); -+} -+ -+void v16qi_vspltisw_addself () -+{ -+ V16QI (30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0); -+} -+ -+void v16qi_vspltisw_neg () -+{ -+ V16QI (-5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1); -+} -+ -+ -+/* V8HI tests. */ -+ -+void v8hi_vspltisb () -+{ -+ V8HI (0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F); -+} -+ -+void v8hi_vspltisb_addself () -+{ -+ V8HI (0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E); -+} -+ -+void v8hi_vspltisb_neg () -+{ -+ V8HI (0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB); -+} -+ -+void v8hi_vspltish () -+{ -+ V8HI (15, 15, 15, 15, 15, 15, 15, 15); -+} -+ -+void v8hi_vspltish_neg () -+{ -+ V8HI (-5, -5, -5, -5, -5, -5, -5, -5); -+} -+ -+void v8hi_vspltish_addself () -+{ -+ V8HI (30, 30, 30, 30, 30, 30, 30, 30); -+} -+ -+void v8hi_vspltish_neg_addself () -+{ -+ V8HI (-24, -24, -24, -24, -24, -24, -24, -24); -+} -+ -+void v8hi_vspltisw () -+{ -+ V8HI (15, 0, 15, 0, 15, 0, 15, 0); -+} -+ -+void v8hi_vspltisw_addself () -+{ -+ V8HI (30, 0, 30, 0, 30, 0, 30, 0); -+} -+ -+void v8hi_vspltisw_neg () -+{ -+ V8HI (-5, -1, -5, -1, -5, -1, -5, -1); -+} -+ -+/* V4SI tests. */ -+ -+void v4si_vspltisb () -+{ -+ V4SI (0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F); -+} -+ -+void v4si_vspltisb_addself () -+{ -+ V4SI (0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E); -+} -+ -+void v4si_vspltisb_neg () -+{ -+ V4SI (0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB); -+} -+ -+void v4si_vspltish () -+{ -+ V4SI (0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F); -+} -+ -+void v4si_vspltish_addself () -+{ -+ V4SI (0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E); -+} -+ -+void v4si_vspltish_neg () -+{ -+ V4SI (0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB); -+} -+ -+void v4si_vspltisw () -+{ -+ V4SI (15, 15, 15, 15); -+} -+ -+void v4si_vspltisw_neg () -+{ -+ V4SI (-5, -5, -5, -5); -+} -+ -+void v4si_vspltisw_addself () -+{ -+ V4SI (30, 30, 30, 30); -+} -+ -+void v4si_vspltisw_neg_addself () -+{ -+ V4SI (-24, -24, -24, -24); -+} -+ -+ -+ -+int main () -+{ -+ v16qi_vspltisb (); -+ v16qi_vspltisb_neg (); -+ v16qi_vspltisb_addself (); -+ v16qi_vspltisb_neg_addself (); -+ v16qi_vspltish (); -+ v16qi_vspltish_addself (); -+ v16qi_vspltish_neg (); -+ v16qi_vspltisw (); -+ v16qi_vspltisw_addself (); -+ v16qi_vspltisw_neg (); -+ -+ v8hi_vspltisb (); -+ v8hi_vspltisb_addself (); -+ v8hi_vspltisb_neg (); -+ v8hi_vspltish (); -+ v8hi_vspltish_neg (); -+ v8hi_vspltish_addself (); -+ v8hi_vspltish_neg_addself (); -+ v8hi_vspltisw (); -+ v8hi_vspltisw_addself (); -+ v8hi_vspltisw_neg (); -+ -+ v4si_vspltisb (); -+ v4si_vspltisb_addself (); -+ v4si_vspltisb_neg (); -+ v4si_vspltish (); -+ v4si_vspltish_addself (); -+ v4si_vspltish_neg (); -+ v4si_vspltisw (); -+ v4si_vspltisw_neg (); -+ v4si_vspltisw_addself (); -+ v4si_vspltisw_neg_addself (); -+ return 0; -+} -+ -+/* { dg-final { scan-assembler-not "lvx" { target { powerpc*le-*-* } } } } */ -Index: gcc/testsuite/gcc.target/powerpc/tfmode_off.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/powerpc/tfmode_off.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/powerpc/tfmode_off.c (.../branches/gcc-4_8-branch) -@@ -1,5 +1,6 @@ - /* { dg-do assemble } */ - /* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ -+/* { dg-skip-if "no TFmode" { powerpc-*-eabi* } { "*" } { "" } } */ - /* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */ - - typedef float TFmode __attribute__ ((mode (TF))); -Index: gcc/testsuite/gcc.target/powerpc/pr47197.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/powerpc/pr47197.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/powerpc/pr47197.c (.../branches/gcc-4_8-branch) -@@ -1,4 +1,5 @@ - /* { dg-do compile } */ -+/* { dg-require-effective-target powerpc_altivec_ok } */ - /* { dg-options "-maltivec" } */ - - /* Compile-only test to ensure that expressions can be passed to -Index: gcc/testsuite/gcc.target/powerpc/20020118-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/powerpc/20020118-1.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/powerpc/20020118-1.c (.../branches/gcc-4_8-branch) -@@ -1,6 +1,8 @@ - /* { dg-do run { target powerpc*-*-* } }*/ - /* VxWorks only guarantees 64 bits of alignment (STACK_BOUNDARY == 64). */ - /* { dg-skip-if "" { "powerpc*-*-vxworks*" } { "*" } { "" } } */ -+/* Force 128-bit stack alignment for eabi targets. */ -+/* { dg-options "-mno-eabi" { target powerpc*-*-eabi* } } */ - - /* Test local alignment. Test new target macro STARTING_FRAME_PHASE. */ - /* Origin: Aldy Hernandez . */ -Index: gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c (.../branches/gcc-4_8-branch) -@@ -4,4 +4,4 @@ - /* { dg-options "-m64" } */ - - /* { dg-error "-m64 not supported in this configuration" "SPE not 64-bit" { target *-*-* } 0 } */ --/* { dg-error "64-bit E500 not supported" "64-bit E500" { target *-*-* } 0 } */ -+/* { dg-error "64-bit SPE not supported" "64-bit SPE" { target *-*-* } 0 } */ -Index: gcc/testsuite/gcc.target/i386/pr57736.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/i386/pr57736.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/i386/pr57736.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,41 @@ -+/* PR target/57736 */ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+#include -+ -+unsigned long long -+f1 (void) -+{ -+ return __rdtsc (); -+} -+ -+unsigned long long -+f2 (unsigned int *x) -+{ -+ return __rdtscp (x); -+} -+ -+unsigned long long -+f3 (unsigned int x) -+{ -+ return __rdpmc (x); -+} -+ -+void -+f4 (void) -+{ -+ __rdtsc (); -+} -+ -+void -+f5 (unsigned int *x) -+{ -+ __rdtscp (x); -+} -+ -+void -+f6 (unsigned int x) -+{ -+ __rdpmc (x); -+} -Index: gcc/testsuite/gcc.target/i386/bmi2-bzhi-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/i386/bmi2-bzhi-1.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/i386/bmi2-bzhi-1.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,31 @@ -+/* PR target/57623 */ -+/* { dg-do assemble { target bmi2 } } */ -+/* { dg-options "-O2 -mbmi2" } */ -+ -+#include -+ -+unsigned int -+f1 (unsigned int x, unsigned int *y) -+{ -+ return _bzhi_u32 (x, *y); -+} -+ -+unsigned int -+f2 (unsigned int *x, unsigned int y) -+{ -+ return _bzhi_u32 (*x, y); -+} -+ -+#ifdef __x86_64__ -+unsigned long long -+f3 (unsigned long long x, unsigned long long *y) -+{ -+ return _bzhi_u64 (x, *y); -+} -+ -+unsigned long long -+f4 (unsigned long long *x, unsigned long long y) -+{ -+ return _bzhi_u64 (*x, y); -+} -+#endif -Index: gcc/testsuite/gcc.target/i386/pr57777.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/i386/pr57777.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/i386/pr57777.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,13 @@ -+/* PR target/57777 */ -+/* { dg-do assemble { target avx2 } } */ -+/* { dg-options "-O3 -mavx2" } */ -+/* { dg-additional-options "-fpic" { target fpic } } */ -+ -+void -+foo (unsigned long *x, int *y) -+{ -+ static unsigned long b[2] = { 0x0UL, 0x9908b0dfUL }; -+ int c; -+ for (c = 0; c < 512; c++) -+ x[c] = b[x[c] & 1UL]; -+} -Index: gcc/testsuite/gcc.target/i386/bmi-bextr-3.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/i386/bmi-bextr-3.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/i386/bmi-bextr-3.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,31 @@ -+/* PR target/57623 */ -+/* { dg-do assemble { target bmi } } */ -+/* { dg-options "-O2 -mbmi" } */ -+ -+#include -+ -+unsigned int -+f1 (unsigned int x, unsigned int *y) -+{ -+ return __bextr_u32 (x, *y); -+} -+ -+unsigned int -+f2 (unsigned int *x, unsigned int y) -+{ -+ return __bextr_u32 (*x, y); -+} -+ -+#ifdef __x86_64__ -+unsigned long long -+f3 (unsigned long long x, unsigned long long *y) -+{ -+ return __bextr_u64 (x, *y); -+} -+ -+unsigned long long -+f4 (unsigned long long *x, unsigned long long y) -+{ -+ return __bextr_u64 (*x, y); -+} -+#endif -Index: gcc/testsuite/gcc.target/i386/pr57655.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/i386/pr57655.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/i386/pr57655.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,10 @@ -+/* { dg-do compile } */ -+/* { dg-options "-mavx -mvzeroupper -mno-fp-ret-in-387" } -+ -+/* { dg-error "x87 register return with x87 disabled" "" { target { ! ia32 } } 8 } */ -+ -+long double -+foo (long double x) -+{ -+ return __builtin_ilogbl (x); -+} -Index: gcc/testsuite/gcc.target/sh/pr56547-2.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/sh/pr56547-2.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/sh/pr56547-2.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,18 @@ -+/* Verify that the fmac insn is used for the expression 'a * b + a' and -+ 'a * a + a' when -ffast-math is specified. */ -+/* { dg-do compile { target "sh*-*-*" } } */ -+/* { dg-options "-O1 -ffast-math" } */ -+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ -+/* { dg-final { scan-assembler-times "fmac" 2 } } */ -+ -+float -+test_00 (float a, float b) -+{ -+ return a * b + a; -+} -+ -+float -+test_01 (float a) -+{ -+ return a * a + a; -+} -Index: gcc/testsuite/gcc.target/sh/pr56547-1.c -=================================================================== ---- a/src/gcc/testsuite/gcc.target/sh/pr56547-1.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.target/sh/pr56547-1.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,19 @@ -+/* Verify that the fmac insn is used for the expression 'a * b + a' and -+ 'a * a + a'. -+ This assumes that the default compiler setting is -ffp-contract=fast. */ -+/* { dg-do compile { target "sh*-*-*" } } */ -+/* { dg-options "-O1" } */ -+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */ -+/* { dg-final { scan-assembler-times "fmac" 2 } } */ -+ -+float -+test_00 (float a, float b) -+{ -+ return a * b + a; -+} -+ -+float -+test_01 (float a) -+{ -+ return a * a + a; -+} -Index: gcc/testsuite/go.test/test/64bit.go -=================================================================== ---- a/src/gcc/testsuite/go.test/test/64bit.go (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/go.test/test/64bit.go (.../branches/gcc-4_8-branch) -@@ -594,6 +594,19 @@ - "}\n" + - "\n" - -+const binaryConstR0 = "func test%vBinaryR%v(a, add, sub, mul, div, mod, and, or, xor, andnot %v, dodiv bool) {\n" + -+ " const b %v = %v;\n" + -+ " const typ = `%s`;\n" + -+ " if n, op, want := a + b, `+`, add; n != want { ok=false; println(typ, `var`, a, op, `const`, b, `=`, n, `should be`, want); }\n" + -+ " if n, op, want := a - b, `-`, sub; n != want { ok=false; println(typ, `var`, a, op, `const`, b, `=`, n, `should be`, want); }\n" + -+ " if n, op, want := a * b, `*`, mul; n != want { ok=false; println(typ, `var`, a, op, `const`, b, `=`, n, `should be`, want); }\n" + -+ " if n, op, want := a & b, `&`, and; n != want { ok=false; println(typ, `var`, a, op, `const`, b, `=`, n, `should be`, want); }\n" + -+ " if n, op, want := a | b, `|`, or; n != want { ok=false; println(typ, `var`, a, op, `const`, b, `=`, n, `should be`, want); }\n" + -+ " if n, op, want := a ^ b, `^`, xor; n != want { ok=false; println(typ, `var`, a, op, `const`, b, `=`, n, `should be`, want); }\n" + -+ " if n, op, want := a &^ b, `&^`, andnot; n != want { ok=false; println(typ, `var`, a, op, `const`, b, `=`, n, `should be`, want); }\n" + -+ "}\n" + -+ "\n" -+ - const shiftConstL = "func test%vShiftL%v(b uint64, left, right %v) {\n" + - " const a %v = %v;\n" + - " const typ = `%s`;\n" + -@@ -621,12 +634,20 @@ - func constTests() { - for i, a := range int64Values { - fmt.Fprintf(bout, binaryConstL, "Int64", i, "int64", "int64", a, "int64") -- fmt.Fprintf(bout, binaryConstR, "Int64", i, "int64", "int64", a, "int64") -+ if a.hi == 0 && a.lo == 0 { -+ fmt.Fprintf(bout, binaryConstR0, "Int64", i, "int64", "int64", a, "int64") -+ } else { -+ fmt.Fprintf(bout, binaryConstR, "Int64", i, "int64", "int64", a, "int64") -+ } - fmt.Fprintf(bout, shiftConstL, "Int64", i, "int64", "int64", a, "int64") - } - for i, a := range uint64Values { - fmt.Fprintf(bout, binaryConstL, "Uint64", i, "uint64", "uint64", a, "uint64") -- fmt.Fprintf(bout, binaryConstR, "Uint64", i, "uint64", "uint64", a, "uint64") -+ if a.hi == 0 && a.lo == 0 { -+ fmt.Fprintf(bout, binaryConstR0, "Uint64", i, "uint64", "uint64", a, "uint64") -+ } else { -+ fmt.Fprintf(bout, binaryConstR, "Uint64", i, "uint64", "uint64", a, "uint64") -+ } - fmt.Fprintf(bout, shiftConstL, "Uint64", i, "uint64", "uint64", a, "uint64") - } - for i, a := range shiftValues { -Index: gcc/testsuite/go.test/test/shift1.go -=================================================================== ---- a/src/gcc/testsuite/go.test/test/shift1.go (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/go.test/test/shift1.go (.../branches/gcc-4_8-branch) -@@ -23,7 +23,7 @@ - - // non-constant shift expressions - var ( -- e1 = g(2.0 << s) // ERROR "invalid" "as type interface" -+ e1 = g(2.0 << s) // ERROR "invalid|shift of non-integer operand" "as type interface" - f1 = h(2 << s) // ERROR "invalid" "as type float64" - g1 int64 = 1.1 << s // ERROR "truncated" - ) -@@ -36,3 +36,206 @@ - b2 = 1.0 << c // ERROR "overflow" - d2 = f(1.0 << c) // ERROR "overflow" - ) -+ -+var ( -+ // issues 4882, 4936. -+ a3 = 1.0< assign -+ end type -+contains -+ subroutine assign (lhs, rhs) -+ class (ref_counter), intent(inout) :: lhs -+ class (ref_counter), intent(in) :: rhs -+ end subroutine -+end module -+module FEpetra_BlockMap -+ use ForTrilinos_ref_counter, only : ref_counter -+ type :: Epetra_BlockMap -+ type(ref_counter) :: counter -+ end type -+contains -+ function from_struct() result(new_Epetra_BlockMap) -+ type(Epetra_BlockMap) :: new_Epetra_BlockMap -+ end function -+ type(Epetra_BlockMap) function create_arbitrary() -+ create_arbitrary = from_struct() -+ end function -+end module -Index: gcc/testsuite/gfortran.dg/dot_product_2.f90 -=================================================================== ---- a/src/gcc/testsuite/gfortran.dg/dot_product_2.f90 (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gfortran.dg/dot_product_2.f90 (.../branches/gcc-4_8-branch) -@@ -0,0 +1,38 @@ -+! { dg-do compile } -+! { dg-options "-fdump-tree-original" } -+! -+! PR fortran/57785 -+! -+! Contributed by Kontantinos Anagnostopoulos -+! -+! The implicit complex conjugate was missing for DOT_PRODUCT -+ -+ -+! For the following, the compile-time simplification fails for SUM; -+! see PR fortran/56342. Hence, a manually expanded SUM is used. -+ -+!if (DOT_PRODUCT ((/ (1.0, 2.0), (2.0, 3.0) /), (/ (1.0, 1.0), (1.0, 4.0) /)) & -+! /= SUM (CONJG ((/ (1.0, 2.0), (2.0, 3.0) /))*(/ (1.0, 1.0), (1.0, 4.0) /))) & -+! call abort () -+! -+!if (ANY (MATMUL ((/ (1.0, 2.0), (2.0, 3.0) /), & -+! RESHAPE ((/ (1.0, 1.0), (1.0, 4.0) /),(/2, 1/))) /= & -+! SUM ((/ (1.0, 2.0), (2.0, 3.0) /)*(/ (1.0, 1.0), (1.0, 4.0) /)))) & -+! call abort () -+ -+ -+if (DOT_PRODUCT ((/ (1.0, 2.0), (2.0, 3.0) /), (/ (1.0, 1.0), (1.0, 4.0) /)) & -+ /= CONJG (cmplx(1.0, 2.0)) * cmplx(1.0, 1.0) & -+ + CONJG (cmplx(2.0, 3.0)) * cmplx(1.0, 4.0)) & -+ call abort () -+ -+if (ANY (MATMUL ((/ (1.0, 2.0), (2.0, 3.0) /), & -+ RESHAPE ((/ (1.0, 1.0), (1.0, 4.0) /),(/2, 1/))) & -+ /= cmplx(1.0, 2.0) * cmplx(1.0, 1.0) & -+ + cmplx(2.0, 3.0) * cmplx(1.0, 4.0))) & -+ call abort () -+end -+ -+ -+! { dg-final { scan-tree-dump-not "abort" "original" } } -+! { dg-final { cleanup-tree-dump "original" } } -Index: gcc/testsuite/gfortran.dg/defined_assignment_6.f90 -=================================================================== ---- a/src/gcc/testsuite/gfortran.dg/defined_assignment_6.f90 (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gfortran.dg/defined_assignment_6.f90 (.../branches/gcc-4_8-branch) -@@ -0,0 +1,36 @@ -+! { dg-do compile } -+! -+! PR fortran/57364 -+! -+! Contributed by Damian Rouson -+! -+module ref_counter_implementation -+ type ref_counter -+ contains -+ procedure :: assign -+ generic :: assignment(=) => assign -+ end type -+contains -+ subroutine assign (lhs, rhs) -+ class (ref_counter), intent(inout) :: lhs -+ class (ref_counter), intent(in) :: rhs -+ end subroutine -+end module -+module foo_parent_implementation -+ use ref_counter_implementation ,only: ref_counter -+ type :: foo_parent -+ type(ref_counter) :: counter -+ end type -+contains -+ type(foo_parent) function new_foo_parent() -+ end function -+end module -+module foo_implementation -+ use foo_parent_implementation ,only: foo_parent,new_foo_parent -+ type, extends(foo_parent) :: foo -+ end type -+contains -+ type(foo) function new_foo() -+ new_foo%foo_parent = new_foo_parent() -+ end function -+end module -Index: gcc/testsuite/gfortran.dg/typebound_override_4.f90 -=================================================================== ---- a/src/gcc/testsuite/gfortran.dg/typebound_override_4.f90 (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gfortran.dg/typebound_override_4.f90 (.../branches/gcc-4_8-branch) -@@ -0,0 +1,34 @@ -+! { dg-do compile } -+! -+! PR 57217: [4.7/4.8/4.9 Regression][OOP] Accepts invalid TBP overriding - lacking arguments check -+! -+! Contributed by Salvatore Filippone -+ -+module base_mod -+ implicit none -+ type base_type -+ contains -+ procedure, pass(map) :: clone => base_clone -+ end type -+contains -+ subroutine base_clone(map,mapout) -+ class(base_type) :: map -+ class(base_type) :: mapout -+ end subroutine -+end module -+ -+module r_mod -+ use base_mod -+ implicit none -+ type, extends(base_type) :: r_type -+ contains -+ procedure, pass(map) :: clone => r_clone ! { dg-error "Type/rank mismatch in argument" } -+ end type -+contains -+ subroutine r_clone(map,mapout) -+ class(r_type) :: map -+ class(r_type) :: mapout -+ end subroutine -+end module -+ -+! { dg-final { cleanup-modules "base_mod r_mod" } } -Index: gcc/testsuite/gcc.c-torture/execute/nest-align-1.x -=================================================================== ---- a/src/gcc/testsuite/gcc.c-torture/execute/nest-align-1.x (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.c-torture/execute/nest-align-1.x (.../branches/gcc-4_8-branch) -@@ -0,0 +1,5 @@ -+# Force bigger stack alignment for PowerPC EABI targets. -+if { [istarget "powerpc-*-eabi*"] } { -+ set additional_flags "-mno-eabi" -+} -+return 0 -Index: gcc/testsuite/gcc.c-torture/execute/pr57829.c -=================================================================== ---- a/src/gcc/testsuite/gcc.c-torture/execute/pr57829.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr57829.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,31 @@ -+/* PR rtl-optimization/57829 */ -+ -+__attribute__((noinline, noclone)) -+int -+f1 (int k) -+{ -+ return 2 | ((k - 1) >> ((int) sizeof (int) * __CHAR_BIT__ - 1)); -+} -+ -+__attribute__((noinline, noclone)) -+long int -+f2 (long int k) -+{ -+ return 2L | ((k - 1L) >> ((int) sizeof (long int) * __CHAR_BIT__ - 1)); -+} -+ -+__attribute__((noinline, noclone)) -+int -+f3 (int k) -+{ -+ k &= 63; -+ return 4 | ((k + 2) >> 5); -+} -+ -+int -+main () -+{ -+ if (f1 (1) != 2 || f2 (1L) != 2L || f3 (63) != 6 || f3 (1) != 4) -+ __builtin_abort (); -+ return 0; -+} -Index: gcc/testsuite/gcc.c-torture/execute/pr57568.c -=================================================================== ---- a/src/gcc/testsuite/gcc.c-torture/execute/pr57568.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.c-torture/execute/pr57568.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,12 @@ -+/* PR target/57568 */ -+ -+extern void abort (void); -+int a[6][9] = { }, b = 1, *c = &a[3][5]; -+ -+int -+main () -+{ -+ if (b && (*c = *c + *c)) -+ abort (); -+ return 0; -+} -Index: gcc/testsuite/gcc.dg/pr57518.c -=================================================================== ---- a/src/gcc/testsuite/gcc.dg/pr57518.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.dg/pr57518.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,15 @@ -+/* PR rtl-optimization/57130 */ -+ -+/* { dg-do compile } */ -+/* { dg-options "-O2 -fdump-rtl-ira" } */ -+/* { dg-final { scan-rtl-dump-not "REG_EQUIV.*mem.*\"ip\"" "ira" } } */ -+ -+char ip[10]; -+int total; -+ -+void foo() { -+ int t; -+ -+ t = ip[2]; -+ total = t & 0x3; -+} -Index: gcc/testsuite/gcc.dg/ipa/pr57358.c -=================================================================== ---- a/src/gcc/testsuite/gcc.dg/ipa/pr57358.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/gcc.dg/ipa/pr57358.c (.../branches/gcc-4_8-branch) -@@ -0,0 +1,9 @@ -+/* { dg-do compile } */ -+/* { dg-options "-O2" } */ -+ -+struct t { void (*func)(void*); }; -+void test_func(struct t* a) __attribute__((optimize("O0"))); -+void test_func(struct t* a) -+{ -+ a->func(0); -+} -Index: gcc/testsuite/ChangeLog -=================================================================== ---- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,151 @@ -+2013-07-16 Iain Sandoe -+ -+ PR target/55656 -+ PR target/55657 -+ * obj-c++.dg/cxx-ivars-3.mm: Use NSObject instead of Object. -+ * obj-c++.dg/strings/const-cfstring-5.mm: Likewise. -+ * obj-c++.dg/torture/strings/const-str-10.mm: Likewise. -+ * obj-c++.dg/torture/strings/const-str-9.mm: Likewise. -+ * objc.dg/image-info.m: Likewise. -+ * objc.dg/symtab-1.m: Likewise. -+ * objc.dg/torture/strings/const-str-10.m: Likewise. -+ * objc.dg/torture/strings/const-str-11.m: Likewise. -+ * objc.dg/torture/strings/const-str-9.m: Likewise. -+ * objc.dg/zero-link-1.m: Likewise. -+ * objc.dg/zero-link-2.m: Likewise. -+ * objc.dg/no-extra-load.m: Avoid Foundation.h. -+ * objc.dg/objc-foreach-4.m: Likewise. -+ * objc.dg/objc-foreach-5.m: Likewise. -+ * obj-c++.dg/proto-lossage-7.mm: Use NSObject instead of Object -+ (for Darwin). -+ * obj-c++.dg/strings/const-str-12.mm: Likewise. -+ * obj-c++.dg/syntax-error-1.mm: Likewise. -+ * objc.dg/method-6.m: Likewise. -+ * objc.dg/pr23214.m: Likewise. -+ * objc.dg/proto-lossage-7.m: Likewise. -+ * objc.dg/strings/const-str-12b.m: Likewise. -+ * objc.dg/zero-link-3.m: Likewise. -+ * obj-c++.dg/method-12.mm: Skip on Darwin versions without 'Object'. -+ * objc.dg/encode-7-next-64bit.m: Use NSObject instead of Object, -+ adjust headers, interfaces and encoded types to reflect current system -+ versions. Add FIXME and outputs from current system compiler for -+ reference. -+ -+2013-07-10 Janis Johnson -+ -+ * gcc.target/powerpc/20020118-1.c: Force 128-bit stack alignment -+ for EABI targets. -+ * gcc.c-torture/execute/nest-align-1.x: New. -+ -+2013-07-08 Janis Johnson -+ -+ * gcc.target/powerpc/tfmode_off.c: Skip for EABI targets. -+ -+ * gcc.target/powerpc/ppc-spe64-1.c: Update expected error message. -+ -+ * gcc.target/powerpc/pr47197.c: Require powerpc_altivec_ok. -+ -+2013-07-08 Tobias Burnus -+ -+ PR fortran/57785 -+ * gfortran.dg/dot_product_2.f90: New. -+ -+2013-07-08 Jakub Jelinek -+ -+ PR rtl-optimization/57829 -+ * gcc.c-torture/execute/pr57829.c: New test. -+ -+2013-07-05 Paolo Carlini -+ -+ PR c++/57645 -+ * g++.dg/cpp0x/noexcept21.C: New. -+ -+2013-07-03 Jakub Jelinek -+ -+ PR target/57777 -+ * gcc.target/i386/pr57777.c: New test. -+ -+ PR c++/57771 -+ * g++.dg/template/arg9.C: New test. -+ -+2013-06-28 Jakub Jelinek -+ -+ PR target/57736 -+ * gcc.target/i386/pr57736.c: New test. -+ -+2013-06-27 Jakub Jelinek -+ -+ PR target/57623 -+ * gcc.target/i386/bmi-bextr-3.c: New test. -+ -+ PR target/57623 -+ * gcc.target/i386/bmi2-bzhi-1.c: New test. -+ -+2013-06-24 Martin Jambor -+ -+ PR tree-optimization/57358 -+ * gcc.dg/ipa/pr57358.c: New test. -+ -+2013-06-24 Alan Modra -+ -+ * gcc.target/powerpc/altivec-consts.c: Correct for little-endian. -+ Add scan-assembler-not "lvx". -+ * gcc.target/powerpc/le-altivec-consts.c: New. -+ -+2013-06-21 Uros Bizjak -+ -+ Backport from mainline -+ 2013-06-20 Uros Bizjak -+ -+ PR target/57655 -+ * gcc.target/i386/pr57655.c: New test. -+ -+2013-06-21 Paolo Carlini -+ -+ PR c++/53211 -+ * g++.dg/cpp0x/decltype55.C: New. -+ -+2013-06-20 Wei Mi -+ -+ Backport from mainline -+ 2013-06-19 Wei Mi -+ -+ PR rtl-optimization/57518 -+ * testsuite/gcc.dg/pr57518.c: New test. -+ -+2013-06-11 Tobias Burnus -+ -+ PR fortran/57508 -+ * gfortran.dg/defined_assignment_7.f90: New. -+ -+2013-06-10 Oleg Endo -+ -+ Backport from mainline -+ 2013-05-20 Oleg Endo -+ -+ PR target/56547 -+ * gcc.target/sh/pr56547-1.c: New. -+ * gcc.target/sh/pr56547-2.c: New. -+ -+2013-06-09 Jakub Jelinek -+ -+ PR target/57568 -+ * gcc.c-torture/execute/pr57568.c: New test. -+ -+2013-06-04 Tobias Burnus -+ -+ Backport from mainline -+ 2013-05-22 Tobias Burnus -+ -+ PR fortran/57364 -+ * gfortran.dg/defined_assignment_6.f90: New. -+ -+2013-05-31 Janus Weil -+ Tobias Burnus -+ -+ PR fortran/57217 -+ * gfortran.dg/typebound_override_4.f90: New. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -Index: gcc/testsuite/g++.dg/debug/template2.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/debug/template2.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/debug/template2.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,14 @@ -+// PR c++/57545 -+ -+template -+struct array { -+ T data[N]; -+}; -+ -+template -+struct derived { -+ typedef long unsigned int size_type; -+ static const size_type n = 42; -+ -+ array a; -+}; -Index: gcc/testsuite/g++.dg/expr/const1.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/expr/const1.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/expr/const1.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,9 @@ -+// PR c++/57551 -+ -+extern unsigned long ADDR; -+ -+unsigned long f(){ -+ const unsigned long* const var=&ADDR; -+ const unsigned long retval=var[1]; -+ return retval; -+} -Index: gcc/testsuite/g++.dg/parse/ref-qual2.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/parse/ref-qual2.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/parse/ref-qual2.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,6 @@ -+// PR c++/57532 -+ -+int main() -+{ -+ return (int() & int()); -+} -Index: gcc/testsuite/g++.dg/cpp0x/lambda/lambda-auto3.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-auto3.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-auto3.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,24 @@ -+// PR c++/57526 -+// { dg-require-effective-target c++11 } -+ -+template -+struct A -+{ -+ void bar( ) { } -+ -+ void foo( ) -+ { -+ auto* this_ptr = this; -+ auto lc = [&]( ) -+ { -+ this_ptr->bar(); -+ }; -+ lc(); -+ } -+}; -+ -+int main() -+{ -+ A a; -+ a.foo(); -+} -Index: gcc/testsuite/g++.dg/cpp0x/lambda/lambda-return1.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-return1.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-return1.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,26 @@ -+// PR c++/57437 -+// { dg-require-effective-target c++11 } -+ -+struct A { -+ int i; -+ -+ A(): i(42) {} -+ A(const A&) = default; -+ A(A&& a): i(a.i) { a.i = 0; } -+}; -+ -+int main() -+{ -+ A x; -+ -+ auto y = [x] () mutable { -+ x.i++; -+ return x; -+ }; -+ -+ if (y().i != 43) -+ __builtin_abort (); -+ -+ if (y().i != 44) -+ __builtin_abort (); -+} -Index: gcc/testsuite/g++.dg/cpp0x/defaulted45.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/cpp0x/defaulted45.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/cpp0x/defaulted45.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,20 @@ -+// { dg-do run } -+// { dg-require-effective-target c++11 } -+ -+struct A -+{ -+ int i; -+ A() = default; -+ A(int i): i{i} { } -+ ~A() {} -+}; -+ -+int main(int argc, char **argv) -+{ -+ { int i[4] = { 42, 42, 42, 42 }; } -+ { -+ A a[4] = { argc }; -+ if (a[1].i != 0) -+ __builtin_abort (); -+ } -+} -Index: gcc/testsuite/g++.dg/cpp0x/initlist71.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/cpp0x/initlist71.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/cpp0x/initlist71.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,9 @@ -+// PR c++/56930 -+// { dg-require-effective-target c++11 } -+// { dg-options -Wconversion } -+ -+int main() -+{ -+ int x = sizeof(int); -+ int y { sizeof(int) }; -+} -Index: gcc/testsuite/g++.dg/cpp0x/decltype55.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/cpp0x/decltype55.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/cpp0x/decltype55.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,20 @@ -+// PR c++/53211 -+// { dg-do compile { target c++11 } } -+ -+template -+ struct is_same { static const bool value = false; }; -+ -+template -+ struct is_same { static const bool value = true; }; -+ -+template -+void func(Args... args) -+{ -+ int arr[] = { args... }; -+ static_assert (is_same::value, ""); -+} -+ -+int main() -+{ -+ func(1, 2, 3, 4); -+} -Index: gcc/testsuite/g++.dg/cpp0x/noexcept21.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/cpp0x/noexcept21.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/cpp0x/noexcept21.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,87 @@ -+// PR c++/57645 -+// { dg-do compile { target c++11 } } -+ -+struct Thrower -+{ -+ ~Thrower() noexcept(false) { throw 1; } -+}; -+ -+struct ExplicitA -+{ -+ ~ExplicitA() {} -+ -+ Thrower t; -+}; -+ -+struct ExplicitB -+{ -+ ~ExplicitB(); -+ -+ Thrower t; -+}; -+ -+ExplicitB::~ExplicitB() {} -+ -+struct ExplicitC -+{ -+ ~ExplicitC() = default; -+ -+ Thrower t; -+}; -+ -+struct ExplicitD -+{ -+ ~ExplicitD(); -+ -+ Thrower t; -+}; -+ -+ExplicitD::~ExplicitD() = default; -+ -+struct NoThrower -+{ -+ ~NoThrower() noexcept(true) {} -+}; -+ -+struct ExplicitE -+{ -+ ~ExplicitE() {} -+ -+ NoThrower t; -+}; -+ -+struct ExplicitF -+{ -+ ~ExplicitF(); -+ -+ NoThrower t; -+}; -+ -+ExplicitF::~ExplicitF() {} -+ -+struct ExplicitG -+{ -+ ~ExplicitG() = default; -+ -+ NoThrower t; -+}; -+ -+struct ExplicitH -+{ -+ ~ExplicitH(); -+ -+ NoThrower t; -+}; -+ -+ExplicitH::~ExplicitH() = default; -+ -+#define SA(X) static_assert(X, #X) -+ -+SA( !noexcept(ExplicitA()) ); -+SA( !noexcept(ExplicitB()) ); -+SA( !noexcept(ExplicitC()) ); -+SA( !noexcept(ExplicitD()) ); -+SA( noexcept(ExplicitE()) ); -+SA( noexcept(ExplicitF()) ); -+SA( noexcept(ExplicitG()) ); -+SA( noexcept(ExplicitH()) ); -Index: gcc/testsuite/g++.dg/cpp0x/defaulted44.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/cpp0x/defaulted44.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/cpp0x/defaulted44.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,24 @@ -+// PR c++/57319 -+// { dg-require-effective-target c++11 } -+ -+namespace N1 { -+ struct A { }; -+ struct B: virtual A { }; -+ struct C: virtual B { }; -+ -+ struct D: C -+ { -+ void operator= (D &); -+ }; -+} -+ -+namespace N2 { -+ struct A { A& operator=(A&&); }; -+ struct B: virtual A { }; // { dg-warning "move assignment" } -+ struct C: virtual B { }; // { dg-warning "move assignment" } -+ -+ struct D: C -+ { -+ void operator= (D &); -+ }; -+} -Index: gcc/testsuite/g++.dg/template/access27.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/template/access27.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/template/access27.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,17 @@ -+// PR c++/57550 -+ -+template bool Wrapper(double); -+template void MakeHandler(bool (T)); -+ -+class Handler -+{ -+public: -+ template static void SetPrimitiveHandlers() -+ { -+ MakeHandler(Wrapper >); -+ } -+private : -+ template static bool Append(T); -+}; -+ -+template void Handler::SetPrimitiveHandlers(); -Index: gcc/testsuite/g++.dg/template/arg9.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/template/arg9.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/template/arg9.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,8 @@ -+// PR c++/57771 -+// { dg-do compile } -+ -+template -+struct S {}; -+ -+S (4>>2)> s1; -+S (4>>2)> s2; -Index: gcc/testsuite/g++.dg/template/using23.C -=================================================================== ---- a/src/gcc/testsuite/g++.dg/template/using23.C (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/g++.dg/template/using23.C (.../branches/gcc-4_8-branch) -@@ -0,0 +1,15 @@ -+// PR c++/57831 -+ -+struct A { -+ void f(); -+}; -+template struct B : T { -+ typedef T base; -+ using base::f; // If I write "using B::f" it's ok -+ void g( ) { -+ B::f(); // This is OK as expected -+ (this->*&T::f)(); // This is also OK -+ (this->*&B::f)(); // This causes error -+ } -+}; -+template struct B< A >; -Index: gcc/testsuite/objc.dg/no-extra-load.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/no-extra-load.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/no-extra-load.m (.../branches/gcc-4_8-branch) -@@ -1,7 +1,7 @@ - /* { dg-do compile { target *-*-darwin* } } */ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - --#import -+#include - main() { [NSObject new]; } - - /* { dg-final { scan-assembler-not "L_objc_msgSend\\\$non_lazy_ptr" } } */ -Index: gcc/testsuite/objc.dg/method-6.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/method-6.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/method-6.m (.../branches/gcc-4_8-branch) -@@ -4,14 +4,21 @@ - /* { dg-do compile } */ - /* { dg-options "-Wstrict-selector-match" } */ - -+#ifdef __NEXT_RUNTIME__ -+#include -+#define OBJECT NSObject -+#else -+#include - #include -+#define OBJECT Object -+#endif - - @interface Base - - (unsigned)port; - @end - - @interface Derived: Base --- (Object *)port; -+- (OBJECT *)port; - + (Protocol *)port; - - (id)starboard; - @end -@@ -20,13 +27,13 @@ - Class receiver; - - [receiver port]; /* { dg-warning "multiple methods named .\\+port. found" } */ -- /* { dg-message "using .\\-\\(unsigned( int)?\\)port." "" { target *-*-* } 10 } */ -- /* { dg-message "also found .\\+\\(Protocol \\*\\)port." "" { target *-*-* } 15 } */ -+ /* { dg-message "using .\\-\\(unsigned( int)?\\)port." "" { target *-*-* } 17 } */ -+ /* { dg-message "also found .\\+\\(Protocol \\*\\)port." "" { target *-*-* } 22 } */ - - [receiver starboard]; /* { dg-warning "no .\\+starboard. method found" } */ -- /* { dg-warning "Messages without a matching method signature" "" { target *-*-* } 26 } */ -- /* { dg-warning "will be assumed to return .id. and accept" "" { target *-*-* } 26 } */ -- /* { dg-warning ".\.\.\.. as arguments" "" { target *-*-* } 26 } */ -+ /* { dg-warning "Messages without a matching method signature" "" { target *-*-* } 33 } */ -+ /* { dg-warning "will be assumed to return .id. and accept" "" { target *-*-* } 33 } */ -+ /* { dg-warning ".\.\.\.. as arguments" "" { target *-*-* } 33 } */ - - [Class port]; /* { dg-error ".Class. is not an Objective\\-C class name or alias" } */ - } -Index: gcc/testsuite/objc.dg/strings/const-cfstring-5.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/strings/const-cfstring-5.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/strings/const-cfstring-5.m (.../branches/gcc-4_8-branch) -@@ -6,16 +6,16 @@ - /* { dg-skip-if "NeXT only" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-mconstant-cfstrings" } */ - --#include -+#include - --@interface Foo: Object { -+@interface Foo: NSObject { - char *cString; - unsigned int len; - } - + (Foo *)description; - @end - --@interface Bar: Object -+@interface Bar: NSObject - + (Foo *) getString: (int) which; - @end - -Index: gcc/testsuite/objc.dg/strings/const-str-12b.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/strings/const-str-12b.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/strings/const-str-12b.m (.../branches/gcc-4_8-branch) -@@ -5,17 +5,23 @@ - /* { dg-options "-fconstant-string-class=Foo" } */ - /* { dg-options "-mno-constant-cfstrings -fconstant-string-class=Foo" { target *-*-darwin* } } */ - -+#ifdef __NEXT_RUNTIME__ -+#include -+#define OBJECT NSObject -+#else - #include -+#define OBJECT Object -+#endif - #include "../../objc-obj-c++-shared/objc-test-suite-types.h" - --@interface Foo: Object { -+@interface Foo: OBJECT { - char *cString; - unsigned int len; - } - + (id)description; - @end - --@interface Bar: Object -+@interface Bar: OBJECT - + (Foo *) getString: (int) which; - @end - -Index: gcc/testsuite/objc.dg/encode-7-next-64bit.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/encode-7-next-64bit.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/encode-7-next-64bit.m (.../branches/gcc-4_8-branch) -@@ -4,24 +4,25 @@ - /* { dg-require-effective-target lp64 } */ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-xfail-run-if "Needs OBJC2 ABI" { *-*-darwin* && { lp64 && { ! objc2 } } } { "-fnext-runtime" } { "" } } */ -+/* { dg-additional-options "-framework Foundation" } */ - - #include - #include - #include --#include -+#include - #include "../objc-obj-c++-shared/runtime.h" - --#define CHECK_IF(E) if (!(E)) abort () -+extern int printf(char *,...); -+void CHECK_IF(const char *s1, const char *s2) -+{ -+ if (strcmp(s1,s2) != 0) { -+ printf ("'%s'\n'%s'\n",s1,s2); -+ abort (); -+ } -+} - - @class NSDictionary, NSFont, NSError, _NSATSTypesetterGuts, NSString, NSMenu, NSArray; - --typedef unsigned char UInt8; --typedef const signed long OSStatus; --typedef unsigned long CFIndex; --typedef unsigned int UInt32; --typedef UInt32 FourCharCode; --typedef FourCharCode OSType; -- - struct FSRef { - UInt8 hidden[80]; - }; -@@ -99,10 +100,10 @@ - unsigned int parameterMask; - } NSErrorUserInfoFormatter; - --typedef Object MyObj; --typedef Object *MyPtr; -+typedef NSObject MyObj; -+typedef NSObject *MyPtr; - --@interface Foo: Object { -+@interface Foo: NSObject { - NSATSGlyphStorageRun r; - } - - (NSError *)_errorWithOSStatus:(OSStatus)inOSStatus ref1:(const FSRef *)inRef1 ref2:(const struct FSRef *)inRef2 -@@ -114,7 +115,7 @@ - - (id)str1:(const char *)str1 str2:(char *)str2 str3:(char *const)str3 str4:(const char *const)str4; - - (oneway void)foo1:(Foo *)foo1 foo2:(const Foo *)foo2 foo3:(Foo *const)foo3 foo4:(const Foo *const)foo4; - - (in const char *)sel1:(const SEL)sel1 id1:(const id)id1; --- (inout id)obj1:(const MyPtr)obj1 obj2:(Object *const)obj2 obj3:(MyObj *const)obj3; -+- (inout id)obj1:(const MyPtr)obj1 obj2:(NSObject *const)obj2 obj3:(MyObj *const)obj3; - + (ComponentInstance)_defaultScriptingComponent; - - (NSString *)_formatCocoaErrorString:(NSString *)formatString parameters:(const char *)parameters - applicableFormatters:(NSErrorUserInfoFormatter **)formatters count:(int)numFormatters; -@@ -156,7 +157,7 @@ - - (in const char *)sel1:(const SEL)sel1 id1:(const id)id1 { - return "Hello"; - } --- (inout id)obj1:(const MyPtr)obj1 obj2:(Object *const)obj2 obj3:(MyObj *const)obj3 { -+- (inout id)obj1:(const MyPtr)obj1 obj2:(NSObject *const)obj2 obj3:(MyObj *const)obj3 { - return self; - } - + (ComponentInstance)_defaultScriptingComponent { -@@ -191,6 +192,8 @@ - } - @end - -+/* FIXME: we produce different output c.f. the system compiler on OSX10.6+ */ -+ - int main(void) { - Class fooClass = objc_getClass ("Foo"); - Method meth; -@@ -199,72 +202,76 @@ - Ivar ivar; - - meth = class_getInstanceMethod (fooClass, @selector(_errorWithOSStatus:ref1:ref2:reading:)); -- CHECK_IF (!strcmp (method_getTypeEncoding(meth), "@44@0:8q16r^{FSRef=[80C]}24r^{FSRef=[80C]}32c40")); -+ CHECK_IF (method_getTypeEncoding(meth), "@40@0:8i16r^{FSRef=[80C]}20r^{FSRef=[80C]}28c36"); - - meth = class_getInstanceMethod (fooClass, @selector(_attributeRunForCharacterAtIndex:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "r^{?=@@QQ^Qffff{_NSRect={_NSPoint=ff}{_NSSize=ff}}q^qQ^Q@@@:::****{?=b1b1b1b1b1b27}}24@0:8Q16")); -+ CHECK_IF (method_getTypeEncoding (meth), "r^{?=@@qq^qffff{_NSRect={_NSPoint=ff}{_NSSize=ff}}q^qQ^Q@@@:::****{?=b1b1b1b1b1b27}}24@0:8q16"); -+/* clang produces: r^{?=@@qq^qffff{_NSRect={_NSPoint=ff}{_NSSize=ff}}q^qQ^Q@@@::^{objc_selector}****{?=b1b1b1b1b1b27}}24@0:8q16 */ - - meth = class_getInstanceMethod (fooClass, @selector(_getATSTypesetterGuts:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "r@24@0:8r:16")); -+ CHECK_IF (method_getTypeEncoding (meth), "r@24@0:8r:16"); -+/* "@24@0:8r^{objc_selector=}16" */ - - meth = class_getInstanceMethod (fooClass, @selector(resumeWithSuspensionID:and:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "v32@0:8^{__NSAppleEventManagerSuspension=}16r^Q24")); -+ CHECK_IF (method_getTypeEncoding (meth), "v32@0:8^{__NSAppleEventManagerSuspension=}16r^q24"); - - meth = class_getInstanceMethod (fooClass, @selector(anotherMeth:and:and:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "r@40@0:8r:16r@24r@32")); -+ CHECK_IF (method_getTypeEncoding (meth), "r@40@0:8r:16r@24r@32"); - - meth = class_getInstanceMethod (fooClass, @selector(str1:str2:str3:str4:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "@48@0:8r*16*24*32r*40")); -+ CHECK_IF (method_getTypeEncoding (meth), "@48@0:8r*16*24*32r*40"); - - meth = class_getInstanceMethod (fooClass, @selector(foo1:foo2:foo3:foo4:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "Vv48@0:8@16r@24@32r@40")); -+ CHECK_IF (method_getTypeEncoding (meth), "Vv48@0:8@16r@24@32r@40"); - - meth = class_getInstanceMethod (fooClass, @selector(sel1:id1:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "rn*32@0:8r:16r@24")); -+ CHECK_IF (method_getTypeEncoding (meth), "rn*32@0:8r:16r@24"); - - meth = class_getInstanceMethod (fooClass, @selector(obj1:obj2:obj3:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "N@40@0:8r@16@24^{Object=#}32")); -+ CHECK_IF (method_getTypeEncoding (meth), "N@40@0:8r@16@24^{NSObject=#}32"); - - meth = class_getClassMethod (fooClass, @selector(_defaultScriptingComponent)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "^{ComponentInstanceRecord=[1q]}16@0:8")); -+ CHECK_IF (method_getTypeEncoding (meth), "^{ComponentInstanceRecord=[1q]}16@0:8"); - - meth = class_getInstanceMethod (fooClass, @selector(_formatCocoaErrorString:parameters:applicableFormatters:count:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "@44@0:8@16r*24^^{?}32i40")); -+ CHECK_IF (method_getTypeEncoding (meth), "@44@0:8@16r*24^^{?}32i40"); - - meth = class_getInstanceMethod (fooClass, @selector(formatter_func:run:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "^{?=^?@I}32@0:8@16r^^{?}24")); -+ CHECK_IF (method_getTypeEncoding (meth), "^{?=^?@I}32@0:8@16r^^{?}24"); - - meth = class_getInstanceMethod (fooClass, @selector(_forgetWord:inDictionary:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "c32@0:8nO@16nO@24")); -+ CHECK_IF (method_getTypeEncoding (meth), "c32@0:8nO@16nO@24"); - - meth = class_getInstanceMethod (fooClass, @selector(_registerServicesMenu:withSendTypes:andReturnTypes:addToList:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "v44@0:8@16r^*24r^*32c40")); -+ CHECK_IF (method_getTypeEncoding (meth), "v44@0:8@16r^*24r^*32c40"); - - meth = class_getClassMethod (fooClass, @selector(_proxySharePointer)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "^^{__CFSet}16@0:8")); -+ CHECK_IF (method_getTypeEncoding (meth), "^^{__CFSet}16@0:8"); - - meth = class_getInstanceMethod (fooClass, @selector(_checkGrammarInString:language:details:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "{_NSRange=II}40@0:8n@16nO@24oO^@32")); -+ CHECK_IF (method_getTypeEncoding (meth), "{_NSRange=II}40@0:8n@16nO@24oO^@32"); - - meth = class_getInstanceMethod (fooClass, @selector(_resolvePositionalStakeGlyphsForLineFragment:lineFragmentRect:minPosition:maxPosition:maxLineFragmentWidth:breakHint:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "B60@0:8^{__CTLine=}16{_NSRect={_NSPoint=ff}{_NSSize=ff}}24f40f44f48^Q52")); -+ CHECK_IF (method_getTypeEncoding (meth), "B60@0:8^{__CTLine=}16{_NSRect={_NSPoint=ff}{_NSSize=ff}}24f40f44f48^q52"); - - meth = class_getClassMethod (fooClass, @selector(findVoiceByIdentifier:returningCreator:returningID:)); -- CHECK_IF (!strcmp (method_getTypeEncoding (meth), "c40@0:8@16^I24^I32")); -+ CHECK_IF (method_getTypeEncoding (meth), "c40@0:8@16^I24^I32"); - - ivars = class_copyIvarList (fooClass, &ivar_count); -- CHECK_IF (ivar_count == 1); -+ if (ivar_count != 1) { -+ abort (); -+ } - - ivar = ivars[0]; -- CHECK_IF (!strcmp (ivar_getName(ivar), "r")); -- CHECK_IF (!strcmp (ivar_getTypeEncoding(ivar), -+ CHECK_IF (ivar_getName(ivar), "r"); -+ CHECK_IF (ivar_getTypeEncoding(ivar), - "{?=\"_attributes\"@\"NSDictionary\"\"_font\"@\"NSFont\"\"_characterLength\"" -- "Q\"_nominalGlyphLocation\"Q\"p\"^Q\"_defaultLineHeight\"f\"_defaultBaselineOffset\"" -+ "q\"_nominalGlyphLocation\"q\"p\"^q\"_defaultLineHeight\"f\"_defaultBaselineOffset\"" - "f\"_horizExpansion\"f\"_baselineDelta\"f\"_attachmentBBox\"{_NSRect=\"origin\"" - "{_NSPoint=\"x\"f\"y\"f}\"size\"{_NSSize=\"width\"f\"height\"f}}\"ll\"q\"llp\"^q\"ull\"" - "Q\"ullp\"^Q\"a\"@\"a1\"@\"a2\"@\"b\":\"b1\":\"b2\":\"str1\"*\"str2\"*\"str3\"*\"str4\"" - "*\"_rFlags\"{?=\"_isAttachmentRun\"b1\"_hasPositionalStake\"b1\"_isDefaultFace\"" -- "b1\"_hasCombiningMarks\"b1\"_isScreenFont\"b1\"_reserved\"b27}}")); -- -+ "b1\"_hasCombiningMarks\"b1\"_isScreenFont\"b1\"_reserved\"b27}}"); -+/*"{?=\"_attributes\"@\"NSDictionary\"\"_font\"@\"NSFont\"\"_characterLength\"q\"_nominalGlyphLocation\"q\"p\"^q\"_defaultLineHeight\"f\"_defaultBaselineOffset\"f\"_horizExpansion\"f\"_baselineDelta\"f\"_attachmentBBox\"{_NSRect=\"origin\"{_NSPoint=\"x\"f\"y\"f}\"size\"{_NSSize=\"width\"f\"height\"f}}\"ll\"q\"llp\"^q\"ull\"Q\"ullp\"^Q\"a\"@\"a1\"@\"a2\"@\"b\":\"b1\":\"b2\"^{objc_selector}\"str1\"*\"str2\"*\"str3\"*\"str4\"*\"_rFlags\"{?=\"_isAttachmentRun\"b1\"_hasPositionalStake\"b1\"_isDefaultFace\"b1\"_hasCombiningMarks\"b1\"_isScreenFont\"b1\"_reserved\"b27}}"*/ - return 0; - } -Index: gcc/testsuite/objc.dg/proto-lossage-7.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/proto-lossage-7.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/proto-lossage-7.m (.../branches/gcc-4_8-branch) -@@ -1,12 +1,19 @@ - /* Check that typedefs of ObjC classes preserve - any @protocol qualifiers. */ - /* { dg-do compile } */ -+ -+#ifdef __NEXT_RUNTIME__ -+#include -+#define OBJECT NSObject -+#else - #include -+#define OBJECT Object -+#endif - - @protocol CanDoStuff; - --typedef Object CanDoStuffType; --typedef Object *CanDoStuffTypePtr; -+typedef OBJECT CanDoStuffType; -+typedef OBJECT *CanDoStuffTypePtr; - - @protocol CanDoStuff - - (int) dostuff; -Index: gcc/testsuite/objc.dg/symtab-1.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/symtab-1.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/symtab-1.m (.../branches/gcc-4_8-branch) -@@ -4,9 +4,9 @@ - /* { dg-do compile { target { *-*-darwin* } } } */ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - --#include -+#include - --@interface Base: Object -+@interface Base: NSObject - - (void)setValues; - @end - -Index: gcc/testsuite/objc.dg/objc-foreach-4.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/objc-foreach-4.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/objc-foreach-4.m (.../branches/gcc-4_8-branch) -@@ -1,18 +1,14 @@ - /* Test for valid objc objects used in a for-each statement. */ - /* FIXME: Run this test with the GNU runtime as well. */ --/* { dg-do compile { target *-*-darwin* } } */ -+/* { dg-do run { target *-*-darwin* } } */ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-skip-if "No NeXT fast enum. pre-Darwin9" { *-*-darwin[5-8]* } { "-fnext-runtime" } { "" } } */ -+/* { dg-additional-options "-framework Foundation" { target { *-*-darwin* } } } */ - --#include --#include -+#include -+#include -+#include - --#if defined (__NEXT_RUNTIME__) && defined (__LP64__) --/* Fudge the class reference until we implement the compiler-side -- const strings. */ --extern void *_NSConstantStringClassReference; --#endif -- - // gcc -o foo foo.m -framework Foundation - - int main (int argc, char const* argv[]) { -Index: gcc/testsuite/objc.dg/objc-foreach-5.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/objc-foreach-5.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/objc-foreach-5.m (.../branches/gcc-4_8-branch) -@@ -2,8 +2,10 @@ - /* { dg-do compile { target *-*-darwin* } } */ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-skip-if "No NeXT fast enum. pre-Darwin9" { *-*-darwin[5-8]* } { "-fnext-runtime" } { "" } } */ -+/* { dg-additional-options "-framework Foundation" { target { *-*-darwin* } } } */ - --#import -+#include -+#include - - NSArray * createTestVictim(unsigned capacity) { - NSMutableArray * arr = [[NSMutableArray alloc] initWithCapacity:capacity]; -Index: gcc/testsuite/objc.dg/zero-link-1.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/zero-link-1.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/zero-link-1.m (.../branches/gcc-4_8-branch) -@@ -5,13 +5,12 @@ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-fzero-link" } */ - --#include --#include -+#include - - extern void abort(void); - #define CHECK_IF(expr) if(!(expr)) abort(); - --@interface Base: Object -+@interface Base: NSObject - + (int) getValue; - @end - -Index: gcc/testsuite/objc.dg/zero-link-2.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/zero-link-2.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/zero-link-2.m (.../branches/gcc-4_8-branch) -@@ -5,12 +5,12 @@ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-fno-zero-link" } */ - --#include -+#include - - extern void abort(void); - #define CHECK_IF(expr) if(!(expr)) abort(); - --@interface Base: Object -+@interface Base: NSObject - + (int) getValue; - @end - -Index: gcc/testsuite/objc.dg/torture/strings/const-str-10.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/torture/strings/const-str-10.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/torture/strings/const-str-10.m (.../branches/gcc-4_8-branch) -@@ -6,10 +6,10 @@ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-mno-constant-cfstrings" { target *-*-darwin* } } */ - --#include -+#include - #include "../../../objc-obj-c++-shared/runtime.h" /* For NEXT_OBJC_USE_NEW_INTERFACE. */ - --@interface NSString: Object -+@interface NSString: NSObject - @end - - @interface NSSimpleCString : NSString { -Index: gcc/testsuite/objc.dg/torture/strings/const-str-11.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/torture/strings/const-str-11.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/torture/strings/const-str-11.m (.../branches/gcc-4_8-branch) -@@ -7,10 +7,10 @@ - /* { dg-options "-fconstant-string-class=XStr" } */ - /* { dg-options "-mno-constant-cfstrings -fconstant-string-class=XStr" { target *-*-darwin* } } */ - --#include -+#include - #include "../../../objc-obj-c++-shared/runtime.h" /* For NEXT_OBJC_USE_NEW_INTERFACE. */ - --@interface XString: Object { -+@interface XString: NSObject { - @protected - char *bytes; - } -Index: gcc/testsuite/objc.dg/torture/strings/const-str-9.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/torture/strings/const-str-9.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/torture/strings/const-str-9.m (.../branches/gcc-4_8-branch) -@@ -5,10 +5,10 @@ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-mno-constant-cfstrings" { target *-*-darwin* } } */ - --#include -+#include - #include "../../../objc-obj-c++-shared/runtime.h" /* For NEXT_OBJC_USE_NEW_INTERFACE. */ - --@interface NSConstantString: Object { -+@interface NSConstantString: NSObject { - char *cString; - unsigned int len; - } -Index: gcc/testsuite/objc.dg/zero-link-3.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/zero-link-3.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/zero-link-3.m (.../branches/gcc-4_8-branch) -@@ -2,15 +2,23 @@ - /* Contributed by Ziemowit Laski . */ - - /* { dg-do run { target *-*-darwin* } } */ --/* { dg-options "-fzero-link" } */ -+/* { dg-additional-options "-fzero-link" } */ -+/* { dg-additional-options "-framework Foundation" { target { *-*-darwin* } } } */ - /* { dg-xfail-run-if "Needs OBJC2 ABI" { *-*-darwin* && { lp64 && { ! objc2 } } } { "-fnext-runtime" } { "" } } */ - -+#ifdef __NEXT_RUNTIME__ -+#include -+#define OBJECT NSObject -+#else - #include -+#include -+#define OBJECT Object -+#endif - - extern void abort(void); - #define CHECK_IF(expr) if(!(expr)) abort(); - --@interface Base: Object -+@interface Base: OBJECT - + (int) getValue; - @end - -Index: gcc/testsuite/objc.dg/image-info.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/image-info.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/image-info.m (.../branches/gcc-4_8-branch) -@@ -7,20 +7,19 @@ - /* { dg-skip-if "NeXT-only" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-freplace-objc-classes" } */ - --#include --#include -+#include - - extern void abort(void); - #define CHECK_IF(expr) if(!(expr)) abort(); - --@interface Object (TEST_SUITE_C1) -+@interface NSObject (TEST_SUITE_C1) - - init; - @end --@implementation Object (TEST_SUITE_C1) -+@implementation NSObject (TEST_SUITE_C1) - - init {return self;} - @end - --@interface Base: Object { -+@interface Base: NSObject { - @public - int a; - float b; -Index: gcc/testsuite/objc.dg/pr23214.m -=================================================================== ---- a/src/gcc/testsuite/objc.dg/pr23214.m (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/objc.dg/pr23214.m (.../branches/gcc-4_8-branch) -@@ -3,14 +3,24 @@ - - /* { dg-do run } */ - /* { dg-xfail-run-if "Needs OBJC2 ABI" { *-*-darwin* && { lp64 && { ! objc2 } } } { "-fnext-runtime" } { "" } } */ -+/* { dg-additional-options "-framework Foundation" { target { { *-*-darwin* } && objc2 } } } */ - -+#if defined (__NEXT_RUNTIME__) && defined(__OBJC2__) \ -+ && defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) \ -+ && __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1070 - #include -- --@interface Object (TS_CAT) -+#define OBJECT NSObject -+#else -+#include -+#define OBJECT Object -+#include -+#endif -+ -+@interface OBJECT (TS_CAT) - - test; - @end - --@implementation Object (TS_CAT) -+@implementation OBJECT (TS_CAT) - - test { return self; } - @end - -@@ -20,7 +30,7 @@ - @protocol B - @end - --@interface Dummy : Object -+@interface Dummy : OBJECT - @end - - int main () -Index: gcc/testsuite/obj-c++.dg/cxx-ivars-3.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/cxx-ivars-3.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/cxx-ivars-3.mm (.../branches/gcc-4_8-branch) -@@ -2,12 +2,15 @@ - - // { dg-do run { target *-*-darwin* } } - // { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } --// { dg-options "-fobjc-call-cxx-cdtors -mmacosx-version-min=10.4" } -+// { dg-additional-options "-fobjc-call-cxx-cdtors -mmacosx-version-min=10.4 -framework Foundation" } - // This test has no equivalent or meaning for m64/ABI V2 - // { dg-xfail-run-if "No Test Avail" { *-*-darwin* && lp64 } { "-fnext-runtime" } { "" } } - - #include - #include -+#include -+ -+//extern "C" { int printf(const char *,...); } - #define CHECK_IF(expr) if(!(expr)) abort() - - #ifndef CLS_HAS_CXX_STRUCTORS -@@ -19,7 +22,7 @@ - cxx_struct (void) { a = b = 55; } - }; - --@interface Foo { -+@interface Foo: NSObject { - int c; - cxx_struct s; - } -@@ -42,9 +45,11 @@ - Class cls; - - cls = objc_getClass("Foo"); -- CHECK_IF(cls->info & CLS_HAS_CXX_STRUCTORS); -+// printf((const char *)"Foo info %lx\n",cls->info); -+ CHECK_IF((cls->info & CLS_HAS_CXX_STRUCTORS) != 0); - cls = objc_getClass("Bar"); -- CHECK_IF(!(cls->info & CLS_HAS_CXX_STRUCTORS)); -+// printf((const char *)"Bar info %lx\n",cls->info); -+ CHECK_IF((cls->info & CLS_HAS_CXX_STRUCTORS) == 0); - - #else - /* No test needed or available. */ -Index: gcc/testsuite/obj-c++.dg/method-12.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/method-12.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/method-12.mm (.../branches/gcc-4_8-branch) -@@ -2,6 +2,7 @@ - /* Author: Ziemowit Laski */ - /* { dg-options "-Wstrict-selector-match" } */ - /* { dg-do compile } */ -+/* { dg-skip-if "Object interface removed" { *-*-darwin[1-2]* && { lp64 } } { "-fnext-runtime" } { "" } } */ - - #include - -@@ -19,13 +20,13 @@ - Class receiver; - - [receiver port]; /* { dg-warning "multiple methods named .\\+port. found" } */ -- /* { dg-message "using .\\-\\(unsigned( int)?\\)port." "" { target *-*-* } 9 } */ -- /* { dg-message "also found .\\+\\(Protocol \\*\\)port." "" { target *-*-* } 14 } */ -+ /* { dg-message "using .\\-\\(unsigned( int)?\\)port." "" { target *-*-* } 10 } */ -+ /* { dg-message "also found .\\+\\(Protocol \\*\\)port." "" { target *-*-* } 15 } */ - - [receiver starboard]; /* { dg-warning "no .\\+starboard. method found" } */ -- /* { dg-warning "Messages without a matching method signature" "" { target *-*-* } 25 } */ -- /* { dg-warning "will be assumed to return .id. and accept" "" { target *-*-* } 25 } */ -- /* { dg-warning ".\.\.\.. as arguments" "" { target *-*-* } 25 } */ -+ /* { dg-warning "Messages without a matching method signature" "" { target *-*-* } 26 } */ -+ /* { dg-warning "will be assumed to return .id. and accept" "" { target *-*-* } 26 } */ -+ /* { dg-warning ".\.\.\.. as arguments" "" { target *-*-* } 26 } */ - - [Class port]; /* { dg-error ".Class. is not an Objective\\-C class name or alias" } */ - } -Index: gcc/testsuite/obj-c++.dg/torture/strings/const-str-10.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/torture/strings/const-str-10.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/torture/strings/const-str-10.mm (.../branches/gcc-4_8-branch) -@@ -6,10 +6,10 @@ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-mno-constant-cfstrings" { target *-*-darwin* } } */ - --#include -+#include - #include "../../../objc-obj-c++-shared/runtime.h" /* For NEXT_OBJC_USE_NEW_INTERFACE. */ - --@interface NSString: Object -+@interface NSString: NSObject - @end - - @interface NSSimpleCString : NSString { -Index: gcc/testsuite/obj-c++.dg/torture/strings/const-str-11.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/torture/strings/const-str-11.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/torture/strings/const-str-11.mm (.../branches/gcc-4_8-branch) -@@ -7,10 +7,10 @@ - /* { dg-options "-fconstant-string-class=XStr" } */ - /* { dg-options "-mno-constant-cfstrings -fconstant-string-class=XStr" { target *-*-darwin* } } */ - --#include -+#include - #include "../../../objc-obj-c++-shared/runtime.h" /* For NEXT_OBJC_USE_NEW_INTERFACE. */ - --@interface XString: Object { -+@interface XString: NSObject { - @protected - char *bytes; - } -Index: gcc/testsuite/obj-c++.dg/torture/strings/const-str-9.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/torture/strings/const-str-9.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/torture/strings/const-str-9.mm (.../branches/gcc-4_8-branch) -@@ -5,10 +5,10 @@ - /* { dg-skip-if "" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-mno-constant-cfstrings" { target *-*-darwin* } } */ - --#include -+#include - #include "../../../objc-obj-c++-shared/runtime.h" /* For NEXT_OBJC_USE_NEW_INTERFACE. */ - --@interface NSConstantString: Object { -+@interface NSConstantString: NSObject { - char *cString; - unsigned int len; - } -Index: gcc/testsuite/obj-c++.dg/strings/const-str-12.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/strings/const-str-12.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/strings/const-str-12.mm (.../branches/gcc-4_8-branch) -@@ -5,17 +5,23 @@ - /* { dg-options "-fconstant-string-class=Foo" } */ - /* { dg-options "-mno-constant-cfstrings -fconstant-string-class=Foo" { target *-*-darwin* } } */ - -+#ifdef __NEXT_RUNTIME__ -+#include -+#define OBJECT NSObject -+#else - #include -+#define OBJECT Object -+#endif - #include "../../objc-obj-c++-shared/objc-test-suite-types.h" - --@interface Foo: Object { -+@interface Foo: OBJECT { - char *cString; - unsigned int len; - } - + (id)description; - @end - --@interface Bar: Object -+@interface Bar: OBJECT - + (Foo *) getString: (int) which; - @end - -Index: gcc/testsuite/obj-c++.dg/strings/const-cfstring-5.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/strings/const-cfstring-5.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/strings/const-cfstring-5.mm (.../branches/gcc-4_8-branch) -@@ -6,16 +6,16 @@ - /* { dg-skip-if "NeXT only" { *-*-* } { "-fgnu-runtime" } { "" } } */ - /* { dg-options "-mconstant-cfstrings" } */ - --#include -+#include - --@interface Foo: Object { -+@interface Foo: NSObject { - char *cString; - unsigned int len; - } - + (Foo *)description; - @end - --@interface Bar: Object -+@interface Bar: NSObject - + (Foo *) getString: (int) which; - @end - -Index: gcc/testsuite/obj-c++.dg/proto-lossage-7.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/proto-lossage-7.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/proto-lossage-7.mm (.../branches/gcc-4_8-branch) -@@ -1,12 +1,19 @@ - /* Check that typedefs of ObjC classes preserve - any @protocol qualifiers. */ - /* { dg-do compile } */ -+ -+#ifdef __NEXT_RUNTIME__ -+#include -+#define OBJECT NSObject -+#else - #include -+#define OBJECT Object -+#endif - - @protocol CanDoStuff; - --typedef Object CanDoStuffType; --typedef Object *CanDoStuffTypePtr; -+typedef OBJECT CanDoStuffType; -+typedef OBJECT *CanDoStuffTypePtr; - - @protocol CanDoStuff - - (int) dostuff; -Index: gcc/testsuite/obj-c++.dg/syntax-error-1.mm -=================================================================== ---- a/src/gcc/testsuite/obj-c++.dg/syntax-error-1.mm (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/testsuite/obj-c++.dg/syntax-error-1.mm (.../branches/gcc-4_8-branch) -@@ -1,7 +1,13 @@ - /* Graceful handling of a syntax error. */ - /* { dg-do compile } */ - -+#ifdef __NEXT_RUNTIME__ -+#include -+#define OBJECT NSObject -+#else - #include -+#define OBJECT Object -+#endif - - class foo { - public: -@@ -12,7 +18,7 @@ - - extern void NXLog(const char *, ...); - --@interface Test2 : Object { -+@interface Test2 : OBJECT { - } - - (void) foo2; - @end -@@ -23,4 +29,4 @@ - } /* { dg-error "stray .\}. between Objective\\-C\\+\\+ methods" } */ - @end - --/* { dg-error "expected constructor, destructor, or type conversion before" "" { target *-*-* } 22 } */ -+/* { dg-error "expected constructor, destructor, or type conversion before" "" { target *-*-* } 28 } */ -Index: gcc/cp/typeck.c -=================================================================== ---- a/src/gcc/cp/typeck.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/typeck.c (.../branches/gcc-4_8-branch) -@@ -8307,7 +8307,8 @@ - && TREE_CODE (retval) == VAR_DECL - && DECL_CONTEXT (retval) == current_function_decl - && ! TREE_STATIC (retval) -- && ! DECL_ANON_UNION_VAR_P (retval) -+ /* And not a lambda or anonymous union proxy. */ -+ && !DECL_HAS_VALUE_EXPR_P (retval) - && (DECL_ALIGN (retval) >= DECL_ALIGN (result)) - /* The cv-unqualified type of the returned value must be the - same as the cv-unqualified return type of the -@@ -8352,7 +8353,8 @@ - Note that these conditions are similar to, but not as strict as, - the conditions for the named return value optimization. */ - if ((cxx_dialect != cxx98) -- && (TREE_CODE (retval) == VAR_DECL -+ && ((TREE_CODE (retval) == VAR_DECL -+ && !DECL_HAS_VALUE_EXPR_P (retval)) - || TREE_CODE (retval) == PARM_DECL) - && DECL_CONTEXT (retval) == current_function_decl - && !TREE_STATIC (retval) -Index: gcc/cp/init.c -=================================================================== ---- a/src/gcc/cp/init.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/init.c (.../branches/gcc-4_8-branch) -@@ -3524,6 +3524,8 @@ - - /* Clear out INIT so that we don't get confused below. */ - init = NULL_TREE; -+ /* Any elements without explicit initializers get {}. */ -+ explicit_value_init_p = true; - } - else if (from_array) - { -Index: gcc/cp/class.c -=================================================================== ---- a/src/gcc/cp/class.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/class.c (.../branches/gcc-4_8-branch) -@@ -4574,15 +4574,20 @@ - static void - deduce_noexcept_on_destructors (tree t) - { -- tree fns; -- - /* If for some reason we don't have a CLASSTYPE_METHOD_VEC, we bail - out now. */ - if (!CLASSTYPE_METHOD_VEC (t)) - return; - -- for (fns = CLASSTYPE_DESTRUCTORS (t); fns; fns = OVL_NEXT (fns)) -+ bool saved_nontrivial_dtor = TYPE_HAS_NONTRIVIAL_DESTRUCTOR (t); -+ -+ /* Avoid early exit from synthesized_method_walk (c++/57645). */ -+ TYPE_HAS_NONTRIVIAL_DESTRUCTOR (t) = true; -+ -+ for (tree fns = CLASSTYPE_DESTRUCTORS (t); fns; fns = OVL_NEXT (fns)) - deduce_noexcept_on_destructor (OVL_CURRENT (fns)); -+ -+ TYPE_HAS_NONTRIVIAL_DESTRUCTOR (t) = saved_nontrivial_dtor; - } - - /* Subroutine of set_one_vmethod_tm_attributes. Search base classes -@@ -4833,6 +4838,44 @@ - return false; - } - -+/* TYPE is being used as a virtual base, and has a non-trivial move -+ assignment. Return true if this is due to there being a user-provided -+ move assignment in TYPE or one of its subobjects; if there isn't, then -+ multiple move assignment can't cause any harm. */ -+ -+bool -+vbase_has_user_provided_move_assign (tree type) -+{ -+ /* Does the type itself have a user-provided move assignment operator? */ -+ for (tree fns -+ = lookup_fnfields_slot_nolazy (type, ansi_assopname (NOP_EXPR)); -+ fns; fns = OVL_NEXT (fns)) -+ { -+ tree fn = OVL_CURRENT (fns); -+ if (move_fn_p (fn) && user_provided_p (fn)) -+ return true; -+ } -+ -+ /* Do any of its bases? */ -+ tree binfo = TYPE_BINFO (type); -+ tree base_binfo; -+ for (int i = 0; BINFO_BASE_ITERATE (binfo, i, base_binfo); ++i) -+ if (vbase_has_user_provided_move_assign (BINFO_TYPE (base_binfo))) -+ return true; -+ -+ /* Or non-static data members? */ -+ for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) -+ { -+ if (TREE_CODE (field) == FIELD_DECL -+ && CLASS_TYPE_P (TREE_TYPE (field)) -+ && vbase_has_user_provided_move_assign (TREE_TYPE (field))) -+ return true; -+ } -+ -+ /* Seems not. */ -+ return false; -+} -+ - /* If default-initialization leaves part of TYPE uninitialized, returns - a DECL for the field or TYPE itself (DR 253). */ - -Index: gcc/cp/method.c -=================================================================== ---- a/src/gcc/cp/method.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/method.c (.../branches/gcc-4_8-branch) -@@ -1340,7 +1340,8 @@ - if (diag && assign_p && move_p - && BINFO_VIRTUAL_P (base_binfo) - && rval && TREE_CODE (rval) == FUNCTION_DECL -- && move_fn_p (rval) && !trivial_fn_p (rval)) -+ && move_fn_p (rval) && !trivial_fn_p (rval) -+ && vbase_has_user_provided_move_assign (basetype)) - warning (OPT_Wvirtual_move_assign, - "defaulted move assignment for %qT calls a non-trivial " - "move assignment operator for virtual base %qT", -Index: gcc/cp/ChangeLog -=================================================================== ---- a/src/gcc/cp/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,76 @@ -+2013-07-12 Jason Merrill -+ -+ * init.c (build_vec_init): Value-initialize the rest of the array. -+ -+2013-07-09 Jason Merrill -+ -+ PR c++/57526 -+ * semantics.c (lambda_capture_field_type): Build a DECLTYPE_TYPE -+ if the variable type uses 'auto'. -+ -+ PR c++/57437 -+ * typeck.c (check_return_expr): Lambda proxies aren't eligible -+ for nrv or return by move. -+ -+ PR c++/57532 -+ * parser.c (cp_parser_ref_qualifier_opt): Don't tentatively parse -+ a ref-qualifier in C++98 mode. -+ -+ PR c++/57545 -+ * pt.c (convert_nontype_argument) [INTEGER_CST]: Force the -+ argument to have the exact type of the parameter. -+ -+ PR c++/57551 -+ * semantics.c (cxx_eval_indirect_ref): Don't try to look through -+ a POINTER_PLUS_EXPR for type punning diagnostic. -+ -+ PR c++/57831 -+ * pt.c (tsubst_copy): Handle USING_DECL. -+ -+2013-07-08 Jason Merrill -+ -+ PR c++/57550 -+ * pt.c (fn_type_unification): Only defer during substitution. -+ (type_unification_real): Defer during defarg substitution, -+ add checks parm to pass back deferred checks. -+ (unify, do_auto_deduction): Adjust. -+ * semantics.c (reopen_deferring_access_checks): New. -+ * cp-tree.h: Declare it. -+ -+2013-07-05 Paolo Carlini -+ -+ PR c++/57645 -+ * class.c (deduce_noexcept_on_destructors): Save, set, and restore -+ TYPE_HAS_NONTRIVIAL_DESTRUCTOR (t) around the main loop over the -+ destructors. -+ -+2013-07-03 Jakub Jelinek -+ -+ PR c++/57771 -+ * parser.c (cp_parser_postfix_expression) -+ Temporarily set parser->greater_than_is_operator_p for -+ cp_parser_expression and restore from saved value afterwards. -+ -+2013-06-21 Paolo Carlini -+ -+ PR c++/53211 -+ * pt.c (type_dependent_expression_p): Handle an array of unknown -+ bound depending on a variadic parameter. -+ * parser.c (cp_parser_range_for): Revert PR56794 changes. -+ -+2013-05-31 Jason Merrill -+ -+ PR c++/57319 -+ * class.c (vbase_has_user_provided_move_assign): New. -+ * method.c (synthesized_method_walk): Check it. -+ * cp-tree.h: Declare it. -+ -+ PR c++/56930 -+ * call.c (convert_like_real): Use cp_convert_and_check. -+ * cvt.c (cp_convert_and_check): Use maybe_constant_value. -+ * semantics.c (cxx_eval_constant_expression): Handle LTGT_EXPR. -+ (potential_constant_expression_1): Handle OMP_ATOMIC*. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -Index: gcc/cp/pt.c -=================================================================== ---- a/src/gcc/cp/pt.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/pt.c (.../branches/gcc-4_8-branch) -@@ -138,6 +138,7 @@ - tree); - static int type_unification_real (tree, tree, tree, const tree *, - unsigned int, int, unification_kind_t, int, -+ vec **, - bool); - static void note_template_header (int); - static tree convert_nontype_argument_function (tree, tree); -@@ -5612,6 +5613,10 @@ - else - return NULL_TREE; - } -+ -+ /* Avoid typedef problems. */ -+ if (TREE_TYPE (expr) != type) -+ expr = fold_convert (type, expr); - } - /* [temp.arg.nontype]/5, bullet 2 - -@@ -12507,6 +12512,9 @@ - case TYPE_DECL: - return tsubst (t, args, complain, in_decl); - -+ case USING_DECL: -+ t = DECL_NAME (t); -+ /* Fall through. */ - case IDENTIFIER_NODE: - if (IDENTIFIER_TYPENAME_P (t)) - { -@@ -14974,7 +14982,6 @@ - return error_mark_node; - tinst = build_tree_list (fn, NULL_TREE); - ++deduction_depth; -- push_deferring_access_checks (dk_deferred); - - gcc_assert (TREE_CODE (fn) == TEMPLATE_DECL); - -@@ -15066,8 +15073,13 @@ - } - processing_template_decl += incomplete; - input_location = DECL_SOURCE_LOCATION (fn); -+ /* Ignore any access checks; we'll see them again in -+ instantiate_template and they might have the wrong -+ access path at this point. */ -+ push_deferring_access_checks (dk_deferred); - fntype = tsubst (TREE_TYPE (fn), explicit_targs, - complain | tf_partial, NULL_TREE); -+ pop_deferring_access_checks (); - input_location = loc; - processing_template_decl -= incomplete; - pop_tinst_level (); -@@ -15075,12 +15087,6 @@ - if (fntype == error_mark_node) - goto fail; - -- /* Throw away these access checks; we'll see them again in -- instantiate_template and they might have the wrong -- access path at this point. */ -- pop_deferring_access_checks (); -- push_deferring_access_checks (dk_deferred); -- - /* Place the explicitly specified arguments in TARGS. */ - for (i = NUM_TMPL_ARGS (explicit_targs); i--;) - TREE_VEC_ELT (targs, i) = TREE_VEC_ELT (explicit_targs, i); -@@ -15106,9 +15112,15 @@ - callers must be ready to deal with unification failures in any - event. */ - -+ /* type_unification_real will pass back any access checks from default -+ template argument substitution. */ -+ vec *checks; -+ checks = NULL; -+ - ok = !type_unification_real (DECL_INNERMOST_TEMPLATE_PARMS (fn), - targs, parms, args, nargs, /*subr=*/0, -- strict, flags, explain_p); -+ strict, flags, &checks, explain_p); -+ - if (!ok) - goto fail; - -@@ -15155,16 +15167,23 @@ - excessive_deduction_depth = true; - goto fail; - } -+ -+ /* Also collect access checks from the instantiation. */ -+ reopen_deferring_access_checks (checks); -+ - decl = instantiate_template (fn, targs, complain); -+ -+ checks = get_deferred_access_checks (); -+ pop_deferring_access_checks (); -+ - pop_tinst_level (); - - if (decl == error_mark_node) - goto fail; - -- /* Now perform any access checks encountered during deduction, such as -- for default template arguments. */ -+ /* Now perform any access checks encountered during substitution. */ - push_access_scope (decl); -- ok = perform_deferred_access_checks (complain); -+ ok = perform_access_checks (checks, complain); - pop_access_scope (decl); - if (!ok) - goto fail; -@@ -15193,7 +15212,6 @@ - r = decl; - - fail: -- pop_deferring_access_checks (); - --deduction_depth; - if (excessive_deduction_depth) - { -@@ -15454,8 +15472,11 @@ - - If SUBR is 1, we're being called recursively (to unify the - arguments of a function or method parameter of a function -- template). */ -+ template). - -+ CHECKS is a pointer to a vector of access checks encountered while -+ substituting default template arguments. */ -+ - static int - type_unification_real (tree tparms, - tree targs, -@@ -15465,6 +15486,7 @@ - int subr, - unification_kind_t strict, - int flags, -+ vec **checks, - bool explain_p) - { - tree parm, arg; -@@ -15604,6 +15626,7 @@ - { - tree parm = TREE_VALUE (TREE_VEC_ELT (tparms, i)); - tree arg = TREE_PURPOSE (TREE_VEC_ELT (tparms, i)); -+ reopen_deferring_access_checks (*checks); - location_t save_loc = input_location; - if (DECL_P (parm)) - input_location = DECL_SOURCE_LOCATION (parm); -@@ -15611,6 +15634,8 @@ - arg = convert_template_argument (parm, arg, targs, complain, - i, NULL_TREE); - input_location = save_loc; -+ *checks = get_deferred_access_checks (); -+ pop_deferring_access_checks (); - if (arg == error_mark_node) - return 1; - else -@@ -17078,7 +17103,7 @@ - - return type_unification_real (tparms, targs, TYPE_ARG_TYPES (parm), - args, nargs, 1, DEDUCE_EXACT, -- LOOKUP_NORMAL, explain_p); -+ LOOKUP_NORMAL, NULL, explain_p); - } - - case OFFSET_TYPE: -@@ -19888,6 +19913,29 @@ - && VAR_HAD_UNKNOWN_BOUND (expression)) - return true; - -+ /* An array of unknown bound depending on a variadic parameter, eg: -+ -+ template -+ void foo (Args... args) -+ { -+ int arr[] = { args... }; -+ } -+ -+ template -+ void bar () -+ { -+ int arr[] = { vals... }; -+ } -+ -+ If the array has no length and has an initializer, it must be that -+ we couldn't determine its length in cp_complete_array_type because -+ it is dependent. */ -+ if (TREE_CODE (expression) == VAR_DECL -+ && TREE_CODE (TREE_TYPE (expression)) == ARRAY_TYPE -+ && !TYPE_DOMAIN (TREE_TYPE (expression)) -+ && DECL_INITIAL (expression)) -+ return true; -+ - if (TREE_TYPE (expression) == unknown_type_node) - { - if (TREE_CODE (expression) == ADDR_EXPR) -@@ -20626,7 +20674,7 @@ - = build_tree_list (NULL_TREE, TYPE_NAME (auto_node)); - val = type_unification_real (tparms, targs, parms, args, 1, 0, - DEDUCE_CALL, LOOKUP_NORMAL, -- /*explain_p=*/false); -+ NULL, /*explain_p=*/false); - if (val > 0) - { - if (processing_template_decl) -Index: gcc/cp/semantics.c -=================================================================== ---- a/src/gcc/cp/semantics.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/semantics.c (.../branches/gcc-4_8-branch) -@@ -155,6 +155,17 @@ - } - } - -+/* Save the current deferred access states and start deferred access -+ checking, continuing the set of deferred checks in CHECKS. */ -+ -+void -+reopen_deferring_access_checks (vec * checks) -+{ -+ push_deferring_access_checks (dk_deferred); -+ if (!deferred_access_no_check) -+ deferred_access_stack->last().deferred_access_checks = checks; -+} -+ - /* Resume deferring access checks again after we stopped doing - this previously. */ - -@@ -7635,11 +7646,6 @@ - { - tree sub = op0; - STRIP_NOPS (sub); -- if (TREE_CODE (sub) == POINTER_PLUS_EXPR) -- { -- sub = TREE_OPERAND (sub, 0); -- STRIP_NOPS (sub); -- } - if (TREE_CODE (sub) == ADDR_EXPR) - { - /* We couldn't fold to a constant value. Make sure it's not -@@ -7990,6 +7996,7 @@ - case UNGT_EXPR: - case UNGE_EXPR: - case UNEQ_EXPR: -+ case LTGT_EXPR: - case RANGE_EXPR: - case COMPLEX_EXPR: - r = cxx_eval_binary_expression (call, t, allow_non_constant, addr, -@@ -8846,6 +8853,12 @@ - } - return false; - -+ case OMP_ATOMIC: -+ case OMP_ATOMIC_READ: -+ case OMP_ATOMIC_CAPTURE_OLD: -+ case OMP_ATOMIC_CAPTURE_NEW: -+ return false; -+ - default: - if (objc_is_property_ref (t)) - return false; -@@ -9065,7 +9078,8 @@ - { - tree type; - if (type_dependent_expression_p (expr) -- && !(TREE_TYPE (expr) && TREE_CODE (TREE_TYPE (expr)) == POINTER_TYPE)) -+ && !(TREE_TYPE (expr) && TREE_CODE (TREE_TYPE (expr)) == POINTER_TYPE -+ && !type_uses_auto (TREE_TYPE (expr)))) - { - type = cxx_make_type (DECLTYPE_TYPE); - DECLTYPE_TYPE_EXPR (type) = expr; -Index: gcc/cp/parser.c -=================================================================== ---- a/src/gcc/cp/parser.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/parser.c (.../branches/gcc-4_8-branch) -@@ -5438,11 +5438,18 @@ - /* Restore the old message. */ - parser->type_definition_forbidden_message = saved_message; - -+ bool saved_greater_than_is_operator_p -+ = parser->greater_than_is_operator_p; -+ parser->greater_than_is_operator_p = true; -+ - /* And the expression which is being cast. */ - cp_parser_require (parser, CPP_OPEN_PAREN, RT_OPEN_PAREN); - expression = cp_parser_expression (parser, /*cast_p=*/true, & idk); - cp_parser_require (parser, CPP_CLOSE_PAREN, RT_CLOSE_PAREN); - -+ parser->greater_than_is_operator_p -+ = saved_greater_than_is_operator_p; -+ - /* Only type conversions to integral or enumeration types - can be used in constant-expressions. */ - if (!cast_valid_in_integral_constant_expression_p (type) -@@ -9595,10 +9602,7 @@ - range_expr = error_mark_node; - stmt = begin_range_for_stmt (scope, init); - finish_range_for_decl (stmt, range_decl, range_expr); -- if (range_expr != error_mark_node -- && !type_dependent_expression_p (range_expr) -- /* The length of an array might be dependent. */ -- && COMPLETE_TYPE_P (complete_type (TREE_TYPE (range_expr))) -+ if (!type_dependent_expression_p (range_expr) - /* do_auto_deduction doesn't mess with template init-lists. */ - && !BRACE_ENCLOSED_INITIALIZER_P (range_expr)) - do_range_for_auto_deduction (range_decl, range_expr); -@@ -16982,6 +16986,11 @@ - { - cp_ref_qualifier ref_qual = REF_QUAL_NONE; - cp_token *token = cp_lexer_peek_token (parser->lexer); -+ -+ /* Don't try to parse bitwise '&' as a ref-qualifier (c++/57532). */ -+ if (cxx_dialect < cxx11 && cp_parser_parsing_tentatively (parser)) -+ return ref_qual; -+ - switch (token->type) - { - case CPP_AND: -Index: gcc/cp/call.c -=================================================================== ---- a/src/gcc/cp/call.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/call.c (.../branches/gcc-4_8-branch) -@@ -6195,8 +6195,8 @@ - if (convs->check_narrowing) - check_narrowing (totype, expr); - -- if (issue_conversion_warnings && (complain & tf_warning)) -- expr = convert_and_check (totype, expr); -+ if (issue_conversion_warnings) -+ expr = cp_convert_and_check (totype, expr, complain); - else - expr = convert (totype, expr); - -Index: gcc/cp/cvt.c -=================================================================== ---- a/src/gcc/cp/cvt.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/cvt.c (.../branches/gcc-4_8-branch) -@@ -620,6 +620,9 @@ - - if (TREE_TYPE (expr) == type) - return expr; -+ -+ if (TREE_CODE (expr) == SIZEOF_EXPR) -+ expr = maybe_constant_value (expr); - - result = cp_convert (type, expr, complain); - -Index: gcc/cp/cp-tree.h -=================================================================== ---- a/src/gcc/cp/cp-tree.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/cp/cp-tree.h (.../branches/gcc-4_8-branch) -@@ -5057,6 +5057,7 @@ - extern bool user_provided_p (tree); - extern bool type_has_user_provided_constructor (tree); - extern bool type_has_user_provided_default_constructor (tree); -+extern bool vbase_has_user_provided_move_assign (tree); - extern tree default_init_uninitialized_part (tree); - extern bool trivial_default_constructor_is_constexpr (tree); - extern bool type_has_constexpr_default_constructor (tree); -@@ -5585,6 +5586,7 @@ - extern void stop_deferring_access_checks (void); - extern void pop_deferring_access_checks (void); - extern vec *get_deferred_access_checks (void); -+extern void reopen_deferring_access_checks (vec *); - extern void pop_to_parent_deferring_access_checks (void); - extern bool perform_access_checks (vec *, - tsubst_flags_t); -Index: gcc/config.in -=================================================================== ---- a/src/gcc/config.in (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/config.in (.../branches/gcc-4_8-branch) -@@ -1228,7 +1228,7 @@ - #endif - - --/* Define if your AIX linker supports a large TOC. */ -+/* Define if your PowerPC64 linker supports a large TOC. */ - #ifndef USED_FOR_TARGET - #undef HAVE_LD_LARGE_TOC - #endif -Index: gcc/go/go-gcc.cc -=================================================================== ---- a/src/gcc/go/go-gcc.cc (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/go-gcc.cc (.../branches/gcc-4_8-branch) -@@ -287,10 +287,10 @@ - Location, Bstatement**); - - Bvariable* -- immutable_struct(const std::string&, bool, Btype*, Location); -+ immutable_struct(const std::string&, bool, bool, Btype*, Location); - - void -- immutable_struct_set_init(Bvariable*, const std::string&, bool, Btype*, -+ immutable_struct_set_init(Bvariable*, const std::string&, bool, bool, Btype*, - Location, Bexpression*); - - Bvariable* -@@ -1454,8 +1454,8 @@ - // Create a named immutable initialized data structure. - - Bvariable* --Gcc_backend::immutable_struct(const std::string& name, bool, Btype* btype, -- Location location) -+Gcc_backend::immutable_struct(const std::string& name, bool, bool, -+ Btype* btype, Location location) - { - tree type_tree = btype->get_tree(); - if (type_tree == error_mark_node) -@@ -1482,7 +1482,7 @@ - - void - Gcc_backend::immutable_struct_set_init(Bvariable* var, const std::string&, -- bool is_common, Btype*, -+ bool is_hidden, bool is_common, Btype*, - Location, - Bexpression* initializer) - { -@@ -1495,7 +1495,10 @@ - - // We can't call make_decl_one_only until we set DECL_INITIAL. - if (!is_common) -- TREE_PUBLIC(decl) = 1; -+ { -+ if (!is_hidden) -+ TREE_PUBLIC(decl) = 1; -+ } - else - { - make_decl_one_only(decl, DECL_ASSEMBLER_NAME(decl)); -Index: gcc/go/ChangeLog -=================================================================== ---- a/src/gcc/go/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,9 @@ -+2013-06-18 Ian Lance Taylor -+ -+ * go-gcc.cc (Gcc_backend::immutable_struct): Add is_hidden -+ parameter. -+ (Gcc_backend::immutable_struct_set_init): Likewise. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -Index: gcc/go/gofrontend/gogo.cc -=================================================================== ---- a/src/gcc/go/gofrontend/gogo.cc (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/gogo.cc (.../branches/gcc-4_8-branch) -@@ -364,7 +364,7 @@ - // Declare "main" as a function which takes no parameters and - // returns no value. - Location uloc = Linemap::unknown_location(); -- this->declare_function("main", -+ this->declare_function(Gogo::pack_hidden_name("main", false), - Type::make_function_type (NULL, NULL, NULL, uloc), - uloc); - } -@@ -819,7 +819,8 @@ - char buf[30]; - snprintf(buf, sizeof buf, ".$sink%d", sink_count); - ++sink_count; -- ret = Named_object::make_function(buf, NULL, function); -+ ret = this->package_->bindings()->add_function(buf, NULL, function); -+ ret->func_value()->set_is_sink(); - } - else if (!type->is_method()) - { -@@ -1277,6 +1278,14 @@ - n.c_str()); - inform(pf->second, "%qs imported here", n.c_str()); - } -+ -+ // No package scope identifier may be named "init". -+ if (!p->second->is_function() -+ && Gogo::unpack_hidden_name(p->second->name()) == "init") -+ { -+ error_at(p->second->location(), -+ "cannot declare init - must be func"); -+ } - } - } - -@@ -1599,8 +1608,9 @@ - return TRAVERSE_CONTINUE; - } - --// Lower function closure types. Record the function while lowering --// it, so that we can pass it down when lowering an expression. -+// Lower the body of a function, and set the closure type. Record the -+// function while lowering it, so that we can pass it down when -+// lowering an expression. - - int - Lower_parse_tree::function(Named_object* no) -@@ -1732,6 +1742,146 @@ - lower.constant(no, false); - } - -+// Traverse the tree to create function descriptors as needed. -+ -+class Create_function_descriptors : public Traverse -+{ -+ public: -+ Create_function_descriptors(Gogo* gogo) -+ : Traverse(traverse_functions | traverse_expressions), -+ gogo_(gogo) -+ { } -+ -+ int -+ function(Named_object*); -+ -+ int -+ expression(Expression**); -+ -+ private: -+ Gogo* gogo_; -+}; -+ -+// Create a descriptor for every top-level exported function. -+ -+int -+Create_function_descriptors::function(Named_object* no) -+{ -+ if (no->is_function() -+ && no->func_value()->enclosing() == NULL -+ && !no->func_value()->is_method() -+ && !no->func_value()->is_descriptor_wrapper() -+ && !Gogo::is_hidden_name(no->name())) -+ no->func_value()->descriptor(this->gogo_, no); -+ -+ return TRAVERSE_CONTINUE; -+} -+ -+// If we see a function referenced in any way other than calling it, -+// create a descriptor for it. -+ -+int -+Create_function_descriptors::expression(Expression** pexpr) -+{ -+ Expression* expr = *pexpr; -+ -+ Func_expression* fe = expr->func_expression(); -+ if (fe != NULL) -+ { -+ // We would not get here for a call to this function, so this is -+ // a reference to a function other than calling it. We need a -+ // descriptor. -+ if (fe->closure() != NULL) -+ return TRAVERSE_CONTINUE; -+ Named_object* no = fe->named_object(); -+ if (no->is_function() && !no->func_value()->is_method()) -+ no->func_value()->descriptor(this->gogo_, no); -+ else if (no->is_function_declaration() -+ && !no->func_declaration_value()->type()->is_method() -+ && !Linemap::is_predeclared_location(no->location())) -+ no->func_declaration_value()->descriptor(this->gogo_, no); -+ return TRAVERSE_CONTINUE; -+ } -+ -+ Bound_method_expression* bme = expr->bound_method_expression(); -+ if (bme != NULL) -+ { -+ // We would not get here for a call to this method, so this is a -+ // method value. We need to create a thunk. -+ Bound_method_expression::create_thunk(this->gogo_, bme->method(), -+ bme->function()); -+ return TRAVERSE_CONTINUE; -+ } -+ -+ Interface_field_reference_expression* ifre = -+ expr->interface_field_reference_expression(); -+ if (ifre != NULL) -+ { -+ // We would not get here for a call to this interface method, so -+ // this is a method value. We need to create a thunk. -+ Interface_type* type = ifre->expr()->type()->interface_type(); -+ if (type != NULL) -+ Interface_field_reference_expression::create_thunk(this->gogo_, type, -+ ifre->name()); -+ return TRAVERSE_CONTINUE; -+ } -+ -+ Call_expression* ce = expr->call_expression(); -+ if (ce != NULL) -+ { -+ Expression* fn = ce->fn(); -+ if (fn->func_expression() != NULL -+ || fn->bound_method_expression() != NULL -+ || fn->interface_field_reference_expression() != NULL) -+ { -+ // Traverse the arguments but not the function. -+ Expression_list* args = ce->args(); -+ if (args != NULL) -+ { -+ if (args->traverse(this) == TRAVERSE_EXIT) -+ return TRAVERSE_EXIT; -+ } -+ return TRAVERSE_SKIP_COMPONENTS; -+ } -+ } -+ -+ return TRAVERSE_CONTINUE; -+} -+ -+// Create function descriptors as needed. We need a function -+// descriptor for all exported functions and for all functions that -+// are referenced without being called. -+ -+void -+Gogo::create_function_descriptors() -+{ -+ // Create a function descriptor for any exported function that is -+ // declared in this package. This is so that we have a descriptor -+ // for functions written in assembly. Gather the descriptors first -+ // so that we don't add declarations while looping over them. -+ std::vector fndecls; -+ Bindings* b = this->package_->bindings(); -+ for (Bindings::const_declarations_iterator p = b->begin_declarations(); -+ p != b->end_declarations(); -+ ++p) -+ { -+ Named_object* no = p->second; -+ if (no->is_function_declaration() -+ && !no->func_declaration_value()->type()->is_method() -+ && !Linemap::is_predeclared_location(no->location()) -+ && !Gogo::is_hidden_name(no->name())) -+ fndecls.push_back(no); -+ } -+ for (std::vector::const_iterator p = fndecls.begin(); -+ p != fndecls.end(); -+ ++p) -+ (*p)->func_declaration_value()->descriptor(this, *p); -+ fndecls.clear(); -+ -+ Create_function_descriptors cfd(this); -+ this->traverse(&cfd); -+} -+ - // Look for interface types to finalize methods of inherited - // interfaces. - -@@ -2643,6 +2793,13 @@ - Expression* closure = NULL; - if (orig_func->needs_closure()) - { -+ // For the new function we are creating, declare a new parameter -+ // variable NEW_CLOSURE_NO and set it to be the closure variable -+ // of the function. This will be set to the closure value -+ // passed in by the caller. Then pass a reference to this -+ // variable as the closure value when calling the original -+ // function. In other words, simply pass the closure value -+ // through the thunk we are creating. - Named_object* orig_closure_no = orig_func->closure_var(); - Variable* orig_closure_var = orig_closure_no->var_value(); - Variable* new_var = new Variable(orig_closure_var->type(), NULL, false, -@@ -2682,22 +2839,7 @@ - // Any varargs call has already been lowered. - call->set_varargs_are_lowered(); - -- Statement* s; -- if (orig_fntype->results() == NULL || orig_fntype->results()->empty()) -- s = Statement::make_statement(call, true); -- else -- { -- Expression_list* vals = new Expression_list(); -- size_t rc = orig_fntype->results()->size(); -- if (rc == 1) -- vals->push_back(call); -- else -- { -- for (size_t i = 0; i < rc; ++i) -- vals->push_back(Expression::make_call_result(call, i)); -- } -- s = Statement::make_return_statement(vals, location); -- } -+ Statement* s = Statement::make_return_from_call(call, location); - s->determine_types(); - gogo->add_statement(s); - -@@ -3101,6 +3243,7 @@ - Map_type::make_map_descriptor_type(); - Channel_type::make_chan_type_descriptor_type(); - Interface_type::make_interface_type_descriptor_type(); -+ Expression::make_func_descriptor_type(); - Type::convert_builtin_named_types(this); - - Runtime::convert_types(this); -@@ -3128,10 +3271,10 @@ - Location location) - : type_(type), enclosing_(enclosing), results_(NULL), - closure_var_(NULL), block_(block), location_(location), labels_(), -- local_type_count_(0), fndecl_(NULL), defer_stack_(NULL), -- results_are_named_(false), nointerface_(false), calls_recover_(false), -- is_recover_thunk_(false), has_recover_thunk_(false), -- in_unique_section_(false) -+ local_type_count_(0), descriptor_(NULL), fndecl_(NULL), defer_stack_(NULL), -+ is_sink_(false), results_are_named_(false), nointerface_(false), -+ calls_recover_(false), is_recover_thunk_(false), has_recover_thunk_(false), -+ in_unique_section_(false), is_descriptor_wrapper_(false) - { - } - -@@ -3206,6 +3349,7 @@ - { - if (this->closure_var_ == NULL) - { -+ go_assert(this->descriptor_ == NULL); - // We don't know the type of the variable yet. We add fields as - // we find them. - Location loc = this->type_->location(); -@@ -3229,7 +3373,14 @@ - return; - Named_object* closure = this->closure_var_; - Struct_type* st = closure->var_value()->type()->deref()->struct_type(); -- unsigned int index = 0; -+ -+ // The first field of a closure is always a pointer to the function -+ // code. -+ Type* voidptr_type = Type::make_pointer_type(Type::make_void_type()); -+ st->push_field(Struct_field(Typed_identifier(".$f", voidptr_type, -+ this->location_))); -+ -+ unsigned int index = 1; - for (Closure_fields::const_iterator p = this->closure_fields_.begin(); - p != this->closure_fields_.end(); - ++p, ++index) -@@ -3410,6 +3561,96 @@ - this->block_->determine_types(); - } - -+// Build a wrapper function for a function descriptor. A function -+// descriptor refers to a function that takes a closure as its last -+// argument. In this case there will be no closure, but an indirect -+// call will pass nil as the last argument. We need to build a -+// wrapper function that accepts and discards that last argument, so -+// that cases like -mrtd will work correctly. In most cases the -+// wrapper function will simply be a jump. -+ -+Named_object* -+Function::make_descriptor_wrapper(Gogo* gogo, Named_object* no, -+ Function_type* orig_fntype) -+{ -+ Location loc = no->location(); -+ -+ Type* vt = Type::make_pointer_type(Type::make_void_type()); -+ Function_type* new_fntype = orig_fntype->copy_with_closure(vt); -+ -+ std::string name = no->name() + "$descriptorfn"; -+ Named_object* dno = gogo->start_function(name, new_fntype, false, loc); -+ dno->func_value()->is_descriptor_wrapper_ = true; -+ -+ gogo->start_block(loc); -+ -+ Expression* fn = Expression::make_func_reference(no, NULL, loc); -+ -+ // Call the function begin wrapped, passing all of the arguments -+ // except for the last one (the last argument is the ignored -+ // closure). -+ const Typed_identifier_list* orig_params = orig_fntype->parameters(); -+ Expression_list* args; -+ if (orig_params == NULL || orig_params->empty()) -+ args = NULL; -+ else -+ { -+ const Typed_identifier_list* new_params = new_fntype->parameters(); -+ args = new Expression_list(); -+ for (Typed_identifier_list::const_iterator p = new_params->begin(); -+ p + 1 != new_params->end(); -+ ++p) -+ { -+ Named_object* p_no = gogo->lookup(p->name(), NULL); -+ go_assert(p_no != NULL -+ && p_no->is_variable() -+ && p_no->var_value()->is_parameter()); -+ args->push_back(Expression::make_var_reference(p_no, loc)); -+ } -+ } -+ -+ Call_expression* call = Expression::make_call(fn, args, -+ orig_fntype->is_varargs(), -+ loc); -+ call->set_varargs_are_lowered(); -+ -+ Statement* s = Statement::make_return_from_call(call, loc); -+ gogo->add_statement(s); -+ Block* b = gogo->finish_block(loc); -+ gogo->add_block(b, loc); -+ gogo->lower_block(dno, b); -+ gogo->finish_function(loc); -+ -+ return dno; -+} -+ -+// Return the function descriptor, the value you get when you refer to -+// the function in Go code without calling it. -+ -+Expression* -+Function::descriptor(Gogo* gogo, Named_object* no) -+{ -+ go_assert(!this->is_method()); -+ go_assert(this->closure_var_ == NULL); -+ go_assert(!this->is_descriptor_wrapper_); -+ if (this->descriptor_ == NULL) -+ { -+ // Make and record the descriptor first, so that when we lower -+ // the descriptor wrapper we don't try to make it again. -+ Func_descriptor_expression* descriptor = -+ Expression::make_func_descriptor(no); -+ this->descriptor_ = descriptor; -+ if (no->package() == NULL -+ && !Linemap::is_predeclared_location(no->location())) -+ { -+ Named_object* dno = Function::make_descriptor_wrapper(gogo, no, -+ this->type_); -+ descriptor->set_descriptor_wrapper(dno); -+ } -+ } -+ return this->descriptor_; -+} -+ - // Get a pointer to the variable representing the defer stack for this - // function, making it if necessary. The value of the variable is set - // by the runtime routines to true if the function is returning, -@@ -3940,6 +4181,32 @@ - } - } - -+// Class Function_declaration. -+ -+// Return the function descriptor. -+ -+Expression* -+Function_declaration::descriptor(Gogo* gogo, Named_object* no) -+{ -+ go_assert(!this->fntype_->is_method()); -+ if (this->descriptor_ == NULL) -+ { -+ // Make and record the descriptor first, so that when we lower -+ // the descriptor wrapper we don't try to make it again. -+ Func_descriptor_expression* descriptor = -+ Expression::make_func_descriptor(no); -+ this->descriptor_ = descriptor; -+ if (no->package() == NULL -+ && !Linemap::is_predeclared_location(no->location())) -+ { -+ Named_object* dno = Function::make_descriptor_wrapper(gogo, no, -+ this->fntype_); -+ descriptor->set_descriptor_wrapper(dno); -+ } -+ } -+ return this->descriptor_; -+} -+ - // Class Variable. - - Variable::Variable(Type* type, Expression* init, bool is_global, -@@ -4755,6 +5022,12 @@ - Named_object::set_function_value(Function* function) - { - go_assert(this->classification_ == NAMED_OBJECT_FUNC_DECLARATION); -+ if (this->func_declaration_value()->has_descriptor()) -+ { -+ Expression* descriptor = -+ this->func_declaration_value()->descriptor(NULL, NULL); -+ function->set_descriptor(descriptor); -+ } - this->classification_ = NAMED_OBJECT_FUNC; - // FIXME: We should free the old value. - this->u_.func_value = function; -Index: gcc/go/gofrontend/runtime.def -=================================================================== ---- a/src/gcc/go/gofrontend/runtime.def (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/runtime.def (.../branches/gcc-4_8-branch) -@@ -224,11 +224,6 @@ - DEF_GO_RUNTIME(NEW_NOPOINTERS, "__go_new_nopointers", P1(UINTPTR), R1(POINTER)) - - --// Allocate a trampoline for a function literal. --DEF_GO_RUNTIME(ALLOCATE_GO_TRAMPOLINE, "__go_allocate_trampoline", -- P2(UINTPTR, POINTER), R1(POINTER)) -- -- - // Start a new goroutine. - DEF_GO_RUNTIME(GO, "__go_go", P2(FUNC_PTR, POINTER), R0()) - -Index: gcc/go/gofrontend/gogo.h -=================================================================== ---- a/src/gcc/go/gofrontend/gogo.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/gogo.h (.../branches/gcc-4_8-branch) -@@ -476,6 +476,10 @@ - void - lower_constant(Named_object*); - -+ // Create all necessary function descriptors. -+ void -+ create_function_descriptors(); -+ - // Finalize the method lists and build stub methods for named types. - void - finalize_methods(); -@@ -614,10 +618,6 @@ - receive_from_channel(tree type_tree, tree type_descriptor_tree, tree channel, - Location); - -- // Make a trampoline which calls FNADDR passing CLOSURE. -- tree -- make_trampoline(tree fnaddr, tree closure, Location); -- - private: - // During parsing, we keep a stack of functions. Each function on - // the stack is one that we are currently parsing. For each -@@ -669,10 +669,6 @@ - tree - ptr_go_string_constant_tree(const std::string&); - -- // Return the type of a trampoline. -- static tree -- trampoline_type_tree(); -- - // Type used to map import names to packages. - typedef std::map Imports; - -@@ -915,6 +911,14 @@ - result_variables() - { return this->results_; } - -+ bool -+ is_sink() const -+ { return this->is_sink_; } -+ -+ void -+ set_is_sink() -+ { this->is_sink_ = true; } -+ - // Whether the result variables have names. - bool - results_are_named() const -@@ -1046,6 +1050,12 @@ - set_in_unique_section() - { this->in_unique_section_ = true; } - -+ // Whether this function was created as a descriptor wrapper for -+ // another function. -+ bool -+ is_descriptor_wrapper() const -+ { return this->is_descriptor_wrapper_; } -+ - // Swap with another function. Used only for the thunk which calls - // recover. - void -@@ -1059,6 +1069,26 @@ - void - determine_types(); - -+ // Return an expression for the function descriptor, given the named -+ // object for this function. This may only be called for functions -+ // without a closure. This will be an immutable struct with one -+ // field that points to the function's code. -+ Expression* -+ descriptor(Gogo*, Named_object*); -+ -+ // Set the descriptor for this function. This is used when a -+ // function declaration is followed by a function definition. -+ void -+ set_descriptor(Expression* descriptor) -+ { -+ go_assert(this->descriptor_ == NULL); -+ this->descriptor_ = descriptor; -+ } -+ -+ // Build a descriptor wrapper function. -+ static Named_object* -+ make_descriptor_wrapper(Gogo*, Named_object*, Function_type*); -+ - // Return the function's decl given an identifier. - tree - get_or_make_decl(Gogo*, Named_object*, tree id); -@@ -1137,25 +1167,32 @@ - Labels labels_; - // The number of local types defined in this function. - unsigned int local_type_count_; -+ // The function descriptor, if any. -+ Expression* descriptor_; - // The function decl. - tree fndecl_; - // The defer stack variable. A pointer to this variable is used to - // distinguish the defer stack for one function from another. This - // is NULL unless we actually need a defer stack. - Temporary_statement* defer_stack_; -+ // True if this function is sink-named. No code is generated. -+ bool is_sink_ : 1; - // True if the result variables are named. -- bool results_are_named_; -+ bool results_are_named_ : 1; - // True if this method should not be included in the type descriptor. -- bool nointerface_; -+ bool nointerface_ : 1; - // True if this function calls the predeclared recover function. -- bool calls_recover_; -+ bool calls_recover_ : 1; - // True if this a thunk built for a function which calls recover. -- bool is_recover_thunk_; -+ bool is_recover_thunk_ : 1; - // True if this function already has a recover thunk. -- bool has_recover_thunk_; -+ bool has_recover_thunk_ : 1; - // True if this function should be put in a unique section. This is - // turned on for field tracking. - bool in_unique_section_ : 1; -+ // True if this is a function wrapper created to put in a function -+ // descriptor. -+ bool is_descriptor_wrapper_ : 1; - }; - - // A snapshot of the current binding state. -@@ -1198,7 +1235,8 @@ - { - public: - Function_declaration(Function_type* fntype, Location location) -- : fntype_(fntype), location_(location), asm_name_(), fndecl_(NULL) -+ : fntype_(fntype), location_(location), asm_name_(), descriptor_(NULL), -+ fndecl_(NULL) - { } - - Function_type* -@@ -1218,10 +1256,27 @@ - set_asm_name(const std::string& asm_name) - { this->asm_name_ = asm_name; } - -+ // Return an expression for the function descriptor, given the named -+ // object for this function. This may only be called for functions -+ // without a closure. This will be an immutable struct with one -+ // field that points to the function's code. -+ Expression* -+ descriptor(Gogo*, Named_object*); -+ -+ // Return true if we have created a descriptor for this declaration. -+ bool -+ has_descriptor() const -+ { return this->descriptor_ != NULL; } -+ - // Return a decl for the function given an identifier. - tree - get_or_make_decl(Gogo*, Named_object*, tree id); - -+ // If there is a descriptor, build it into the backend -+ // representation. -+ void -+ build_backend_descriptor(Gogo*); -+ - // Export a function declaration. - void - export_func(Export* exp, const std::string& name) const -@@ -1235,6 +1290,8 @@ - // The assembler name: this is the name to use in references to the - // function. This is normally empty. - std::string asm_name_; -+ // The function descriptor, if any. -+ Expression* descriptor_; - // The function decl if needed. - tree fndecl_; - }; -@@ -1630,7 +1687,7 @@ - Named_constant(Type* type, Expression* expr, int iota_value, - Location location) - : type_(type), expr_(expr), iota_value_(iota_value), location_(location), -- lowering_(false) -+ lowering_(false), is_sink_(false) - { } - - Type* -@@ -1664,6 +1721,14 @@ - clear_lowering() - { this->lowering_ = false; } - -+ bool -+ is_sink() const -+ { return this->is_sink_; } -+ -+ void -+ set_is_sink() -+ { this->is_sink_ = true; } -+ - // Traverse the expression. - int - traverse_expression(Traverse*); -@@ -1699,6 +1764,8 @@ - Location location_; - // Whether we are currently lowering this constant. - bool lowering_; -+ // Whether this constant is blank named and needs only type checking. -+ bool is_sink_; - }; - - // A type declaration. -Index: gcc/go/gofrontend/go.cc -=================================================================== ---- a/src/gcc/go/gofrontend/go.cc (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/go.cc (.../branches/gcc-4_8-branch) -@@ -44,7 +44,7 @@ - GO_EXTERN_C - void - go_parse_input_files(const char** filenames, unsigned int filename_count, -- bool only_check_syntax, bool require_return_statement) -+ bool only_check_syntax, bool) - { - go_assert(filename_count > 0); - -@@ -84,10 +84,16 @@ - // Finalize method lists and build stub methods for named types. - ::gogo->finalize_methods(); - -+ // Check that functions have a terminating statement. -+ ::gogo->check_return_statements(); -+ - // Now that we have seen all the names, lower the parse tree into a - // form which is easier to use. - ::gogo->lower_parse_tree(); - -+ // Create function descriptors as needed. -+ ::gogo->create_function_descriptors(); -+ - // Write out queued up functions for hash and comparison of types. - ::gogo->write_specific_type_functions(); - -@@ -104,10 +110,6 @@ - if (only_check_syntax) - return; - -- // Check that functions have return statements. -- if (require_return_statement) -- ::gogo->check_return_statements(); -- - // Export global identifiers as appropriate. - ::gogo->do_exports(); - -Index: gcc/go/gofrontend/types.h -=================================================================== ---- a/src/gcc/go/gofrontend/types.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/types.h (.../branches/gcc-4_8-branch) -@@ -523,6 +523,14 @@ - static Type* - make_forward_declaration(Named_object*); - -+ // Make a builtin struct type from a list of fields. -+ static Struct_type* -+ make_builtin_struct_type(int nfields, ...); -+ -+ // Make a builtin named type. -+ static Named_type* -+ make_builtin_named_type(const char* name, Type* type); -+ - // Traverse a type. - static int - traverse(Type*, Traverse*); -@@ -1035,14 +1043,6 @@ - type_descriptor_constructor(Gogo*, int runtime_type_kind, Named_type*, - const Methods*, bool only_value_methods); - -- // Make a builtin struct type from a list of fields. -- static Struct_type* -- make_builtin_struct_type(int nfields, ...); -- -- // Make a builtin named type. -- static Named_type* -- make_builtin_named_type(const char* name, Type* type); -- - // For the benefit of child class reflection string generation. - void - append_reflection(const Type* type, Gogo* gogo, std::string* ret) const -@@ -1789,6 +1789,12 @@ - Function_type* - copy_with_receiver(Type*) const; - -+ // Return a copy of this type ignoring any receiver and adding a -+ // final closure parameter of type CLOSURE_TYPE. This is used when -+ // creating descriptors. -+ Function_type* -+ copy_with_closure(Type* closure_type) const; -+ - static Type* - make_function_type_descriptor_type(); - -@@ -1796,7 +1802,7 @@ - int - do_traverse(Traverse*); - -- // A trampoline function has a pointer which matters for GC. -+ // A function descriptor may be allocated on the heap. - bool - do_has_pointer() const - { return true; } -Index: gcc/go/gofrontend/parse.cc -=================================================================== ---- a/src/gcc/go/gofrontend/parse.cc (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/parse.cc (.../branches/gcc-4_8-branch) -@@ -1457,6 +1457,16 @@ - - if (!Gogo::is_sink_name(pi->name())) - this->gogo_->add_constant(*pi, *pe, this->iota_value()); -+ else -+ { -+ static int count; -+ char buf[30]; -+ snprintf(buf, sizeof buf, ".$sinkconst%d", count); -+ ++count; -+ Typed_identifier ti(std::string(buf), type, pi->location()); -+ Named_object* no = this->gogo_->add_constant(ti, *pe, this->iota_value()); -+ no->const_value()->set_is_sink(); -+ } - } - if (pe != expr_list->end()) - error_at(this->location(), "too many initializers"); -@@ -2627,7 +2637,11 @@ - Named_object* this_function = this->gogo_->current_function(); - Named_object* closure = this_function->func_value()->closure_var(); - -- Enclosing_var ev(var, in_function, this->enclosing_vars_.size()); -+ // The last argument to the Enclosing_var constructor is the index -+ // of this variable in the closure. We add 1 to the current number -+ // of enclosed variables, because the first field in the closure -+ // points to the function code. -+ Enclosing_var ev(var, in_function, this->enclosing_vars_.size() + 1); - std::pair ins = - this->enclosing_vars_.insert(ev); - if (ins.second) -@@ -2882,8 +2896,9 @@ - // Create a closure for the nested function FUNCTION. This is based - // on ENCLOSING_VARS, which is a list of all variables defined in - // enclosing functions and referenced from FUNCTION. A closure is the --// address of a struct which contains the addresses of all the --// referenced variables. This returns NULL if no closure is required. -+// address of a struct which point to the real function code and -+// contains the addresses of all the referenced variables. This -+// returns NULL if no closure is required. - - Expression* - Parse::create_closure(Named_object* function, Enclosing_vars* enclosing_vars, -@@ -2899,16 +2914,25 @@ - for (Enclosing_vars::const_iterator p = enclosing_vars->begin(); - p != enclosing_vars->end(); - ++p) -- ev[p->index()] = *p; -+ { -+ // Subtract 1 because index 0 is the function code. -+ ev[p->index() - 1] = *p; -+ } - - // Build an initializer for a composite literal of the closure's - // type. - - Named_object* enclosing_function = this->gogo_->current_function(); - Expression_list* initializer = new Expression_list; -+ -+ initializer->push_back(Expression::make_func_code_reference(function, -+ location)); -+ - for (size_t i = 0; i < enclosing_var_count; ++i) - { -- go_assert(ev[i].index() == i); -+ // Add 1 to i because the first field in the closure is a -+ // pointer to the function code. -+ go_assert(ev[i].index() == i + 1); - Named_object* var = ev[i].var(); - Expression* ref; - if (ev[i].in_function() == enclosing_function) -@@ -3016,7 +3040,7 @@ - && t->array_type()->length()->is_nil_expression()) - { - error_at(ret->location(), -- "invalid use of %<...%> in type conversion"); -+ "use of %<[...]%> outside of array literal"); - ret = Expression::make_error(loc); - } - else -@@ -4499,9 +4523,12 @@ - bool is_fallthrough = false; - if (this->peek_token()->is_keyword(KEYWORD_FALLTHROUGH)) - { -+ Location fallthrough_loc = this->location(); - is_fallthrough = true; - if (this->advance_token()->is_op(OPERATOR_SEMICOLON)) - this->advance_token(); -+ if (this->peek_token()->is_op(OPERATOR_RCURLY)) -+ error_at(fallthrough_loc, _("cannot fallthrough final case in switch")); - } - - if (is_default) -Index: gcc/go/gofrontend/expressions.h -=================================================================== ---- a/src/gcc/go/gofrontend/expressions.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/expressions.h (.../branches/gcc-4_8-branch) -@@ -16,6 +16,7 @@ - class Traverse; - class Statement_inserter; - class Type; -+class Method; - struct Type_context; - class Integer_type; - class Float_type; -@@ -32,6 +33,7 @@ - class Binary_expression; - class Call_expression; - class Func_expression; -+class Func_descriptor_expression; - class Unknown_expression; - class Index_expression; - class Map_index_expression; -@@ -67,6 +69,8 @@ - EXPRESSION_SET_AND_USE_TEMPORARY, - EXPRESSION_SINK, - EXPRESSION_FUNC_REFERENCE, -+ EXPRESSION_FUNC_DESCRIPTOR, -+ EXPRESSION_FUNC_CODE_REFERENCE, - EXPRESSION_UNKNOWN_REFERENCE, - EXPRESSION_BOOLEAN, - EXPRESSION_STRING, -@@ -150,10 +154,24 @@ - static Expression* - make_sink(Location); - -- // Make a reference to a function in an expression. -+ // Make a reference to a function in an expression. This returns a -+ // pointer to the struct holding the address of the function -+ // followed by any closed-over variables. - static Expression* - make_func_reference(Named_object*, Expression* closure, Location); - -+ // Make a function descriptor, an immutable struct with a single -+ // field that points to the function code. This may only be used -+ // with functions that do not have closures. FN is the function for -+ // which we are making the descriptor. -+ static Func_descriptor_expression* -+ make_func_descriptor(Named_object* fn); -+ -+ // Make a reference to the code of a function. This is used to set -+ // descriptor and closure fields. -+ static Expression* -+ make_func_code_reference(Named_object*, Location); -+ - // Make a reference to an unknown name. In a correct program this - // will always be lowered to a real const/var/func reference. - static Unknown_expression* -@@ -207,9 +225,11 @@ - make_call_result(Call_expression*, unsigned int index); - - // Make an expression which is a method bound to its first -- // parameter. -+ // parameter. METHOD is the method being called, FUNCTION is the -+ // function to call. - static Bound_method_expression* -- make_bound_method(Expression* object, Named_object* method, Location); -+ make_bound_method(Expression* object, const Method* method, -+ Named_object* function, Location); - - // Make an index or slice expression. This is a parser expression - // which represents LEFT[START:END]. END may be NULL, meaning an -@@ -523,6 +543,11 @@ - bool - is_local_variable() const; - -+ // Make the builtin function descriptor type, so that it can be -+ // converted. -+ static void -+ make_func_descriptor_type(); -+ - // Traverse an expression. - static int - traverse(Expression**, Traverse*); -@@ -1057,8 +1082,7 @@ - do_type(); - - void -- do_determine_type(const Type_context*) -- { } -+ do_determine_type(const Type_context*); - - Expression* - do_copy() -@@ -1484,7 +1508,7 @@ - { } - - // Return the object associated with the function. -- const Named_object* -+ Named_object* - named_object() const - { return this->function_; } - -@@ -1494,9 +1518,9 @@ - closure() - { return this->closure_; } - -- // Return a tree for this function without evaluating the closure. -- tree -- get_tree_without_closure(Gogo*); -+ // Return a tree for the code for a function. -+ static tree -+ get_code_pointer(Gogo*, Named_object* function, Location loc); - - protected: - int -@@ -1532,11 +1556,68 @@ - // The function itself. - Named_object* function_; - // A closure. This is normally NULL. For a nested function, it may -- // be a heap-allocated struct holding pointers to all the variables -- // referenced by this function and defined in enclosing functions. -+ // be a struct holding pointers to all the variables referenced by -+ // this function and defined in enclosing functions. - Expression* closure_; - }; - -+// A function descriptor. A function descriptor is a struct with a -+// single field pointing to the function code. This is used for -+// functions without closures. -+ -+class Func_descriptor_expression : public Expression -+{ -+ public: -+ Func_descriptor_expression(Named_object* fn); -+ -+ // Set the descriptor wrapper. -+ void -+ set_descriptor_wrapper(Named_object* dfn) -+ { -+ go_assert(this->dfn_ == NULL); -+ this->dfn_ = dfn; -+ } -+ -+ // Make the function descriptor type, so that it can be converted. -+ static void -+ make_func_descriptor_type(); -+ -+ protected: -+ int -+ do_traverse(Traverse*); -+ -+ Type* -+ do_type(); -+ -+ void -+ do_determine_type(const Type_context*) -+ { } -+ -+ Expression* -+ do_copy(); -+ -+ bool -+ do_is_addressable() const -+ { return true; } -+ -+ tree -+ do_get_tree(Translate_context*); -+ -+ void -+ do_dump_expression(Ast_dump_context* context) const; -+ -+ private: -+ // The type of all function descriptors. -+ static Type* descriptor_type; -+ -+ // The function for which this is the descriptor. -+ Named_object* fn_; -+ // The descriptor function. -+ Named_object* dfn_; -+ // The descriptor variable. -+ Bvariable* dvar_; -+}; -+ - // A reference to an unknown name. - - class Unknown_expression : public Parser_expression -@@ -1773,10 +1854,10 @@ - class Bound_method_expression : public Expression - { - public: -- Bound_method_expression(Expression* expr, Named_object* method, -- Location location) -+ Bound_method_expression(Expression* expr, const Method *method, -+ Named_object* function, Location location) - : Expression(EXPRESSION_BOUND_METHOD, location), -- expr_(expr), expr_type_(NULL), method_(method) -+ expr_(expr), expr_type_(NULL), method_(method), function_(function) - { } - - // Return the object which is the first argument. -@@ -1791,20 +1872,33 @@ - first_argument_type() const - { return this->expr_type_; } - -- // Return the method function. -- Named_object* -- method() -+ // Return the method. -+ const Method* -+ method() const - { return this->method_; } - -+ // Return the function to call. -+ Named_object* -+ function() const -+ { return this->function_; } -+ - // Set the implicit type of the expression. - void - set_first_argument_type(Type* type) - { this->expr_type_ = type; } - -+ // Create a thunk to call FUNCTION, for METHOD, when it is used as -+ // part of a method value. -+ static Named_object* -+ create_thunk(Gogo*, const Method* method, Named_object* function); -+ - protected: - int - do_traverse(Traverse*); - -+ Expression* -+ do_lower(Gogo*, Named_object*, Statement_inserter*, int); -+ - Type* - do_type(); - -@@ -1818,7 +1912,7 @@ - do_copy() - { - return new Bound_method_expression(this->expr_->copy(), this->method_, -- this->location()); -+ this->function_, this->location()); - } - - tree -@@ -1828,6 +1922,11 @@ - do_dump_expression(Ast_dump_context*) const; - - private: -+ // A mapping from method functions to the thunks we have created for -+ // them. -+ typedef Unordered_map(Named_object*, Named_object*) Method_value_thunks; -+ static Method_value_thunks method_value_thunks; -+ - // The object used to find the method. This is passed to the method - // as the first argument. - Expression* expr_; -@@ -1835,8 +1934,12 @@ - // NULL in the normal case, non-NULL when using a method from an - // anonymous field which does not require a stub. - Type* expr_type_; -- // The method itself. -- Named_object* method_; -+ // The method. -+ const Method* method_; -+ // The function to call. This is not the same as -+ // method_->named_object() when the method has a stub. This will be -+ // the real function rather than the stub. -+ Named_object* function_; - }; - - // A reference to a field in a struct. -@@ -1847,7 +1950,7 @@ - Field_reference_expression(Expression* expr, unsigned int field_index, - Location location) - : Expression(EXPRESSION_FIELD_REFERENCE, location), -- expr_(expr), field_index_(field_index), called_fieldtrack_(false) -+ expr_(expr), field_index_(field_index), implicit_(false), called_fieldtrack_(false) - { } - - // Return the struct expression. -@@ -1860,6 +1963,15 @@ - field_index() const - { return this->field_index_; } - -+ // Return whether this node was implied by an anonymous field. -+ bool -+ implicit() const -+ { return this->implicit_; } -+ -+ void -+ set_implicit(bool implicit) -+ { this->implicit_ = implicit; } -+ - // Set the struct expression. This is used when parsing. - void - set_struct_expression(Expression* expr) -@@ -1914,6 +2026,9 @@ - Expression* expr_; - // The zero-based index of the field we are retrieving. - unsigned int field_index_; -+ // Whether this node was emitted implicitly for an embedded field, -+ // that is, expr_ is not the expr_ of the original user node. -+ bool implicit_; - // Whether we have already emitted a fieldtrack call. - bool called_fieldtrack_; - }; -@@ -1940,6 +2055,11 @@ - name() const - { return this->name_; } - -+ // Create a thunk to call the method NAME in TYPE when it is used as -+ // part of a method value. -+ static Named_object* -+ create_thunk(Gogo*, Interface_type* type, const std::string& name); -+ - // Return a tree for the pointer to the function to call, given a - // tree for the expression. - tree -@@ -1955,6 +2075,9 @@ - int - do_traverse(Traverse* traverse); - -+ Expression* -+ do_lower(Gogo*, Named_object*, Statement_inserter*, int); -+ - Type* - do_type(); - -@@ -1979,6 +2102,13 @@ - do_dump_expression(Ast_dump_context*) const; - - private: -+ // A mapping from interface types to a list of thunks we have -+ // created for methods. -+ typedef std::vector > Method_thunks; -+ typedef Unordered_map(Interface_type*, Method_thunks*) -+ Interface_method_thunks; -+ static Interface_method_thunks interface_method_thunks; -+ - // The expression for the interface object. This should have a type - // of interface or pointer to interface. - Expression* expr_; -Index: gcc/go/gofrontend/statements.cc -=================================================================== ---- a/src/gcc/go/gofrontend/statements.cc (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/statements.cc (.../branches/gcc-4_8-branch) -@@ -569,7 +569,10 @@ - Assignment_statement::do_determine_types() - { - this->lhs_->determine_type_no_context(); -- Type_context context(this->lhs_->type(), false); -+ Type* rhs_context_type = this->lhs_->type(); -+ if (rhs_context_type->is_sink_type()) -+ rhs_context_type = NULL; -+ Type_context context(rhs_context_type, false); - this->rhs_->determine_type(&context); - } - -@@ -1707,8 +1710,8 @@ - this->expr_->discarding_value(); - } - --// An expression statement may fall through unless it is a call to a --// function which does not return. -+// An expression statement is only a terminating statement if it is -+// a call to panic. - - bool - Expression_statement::do_may_fall_through() const -@@ -1717,22 +1720,28 @@ - if (call != NULL) - { - const Expression* fn = call->fn(); -- const Func_expression* fe = fn->func_expression(); -- if (fe != NULL) -+ // panic is still an unknown named object. -+ const Unknown_expression* ue = fn->unknown_expression(); -+ if (ue != NULL) - { -- const Named_object* no = fe->named_object(); -+ Named_object* no = ue->named_object(); - -- Function_type* fntype; -- if (no->is_function()) -- fntype = no->func_value()->type(); -- else if (no->is_function_declaration()) -- fntype = no->func_declaration_value()->type(); -- else -- fntype = NULL; -+ if (no->is_unknown()) -+ no = no->unknown_value()->real_named_object(); -+ if (no != NULL) -+ { -+ Function_type* fntype; -+ if (no->is_function()) -+ fntype = no->func_value()->type(); -+ else if (no->is_function_declaration()) -+ fntype = no->func_declaration_value()->type(); -+ else -+ fntype = NULL; - -- // The builtin function panic does not return. -- if (fntype != NULL && fntype->is_builtin() && no->name() == "panic") -- return false; -+ // The builtin function panic does not return. -+ if (fntype != NULL && fntype->is_builtin() && no->name() == "panic") -+ return false; -+ } - } - } - return true; -@@ -1953,12 +1962,17 @@ - && results->begin()->type()->points_to() == NULL))) - return false; - -- // If this calls something which is not a simple function, then we -+ // If this calls something that is not a simple function, then we - // need a thunk. - Expression* fn = this->call_->call_expression()->fn(); -- if (fn->interface_field_reference_expression() != NULL) -+ if (fn->func_expression() == NULL) - return false; - -+ // If the function uses a closure, then we need a thunk. FIXME: We -+ // could accept a zero argument function with a closure. -+ if (fn->func_expression()->closure() != NULL) -+ return false; -+ - return true; - } - -@@ -2496,7 +2510,11 @@ - - Call_expression* ce = this->call_->call_expression(); - -- *pfn = ce->fn(); -+ Expression* fn = ce->fn(); -+ Func_expression* fe = fn->func_expression(); -+ go_assert(fe != NULL); -+ *pfn = Expression::make_func_code_reference(fe->named_object(), -+ fe->location()); - - const Expression_list* args = ce->args(); - if (args == NULL || args->empty()) -@@ -2800,6 +2818,28 @@ - return new Return_statement(vals, location); - } - -+// Make a statement that returns the result of a call expression. -+ -+Statement* -+Statement::make_return_from_call(Call_expression* call, Location location) -+{ -+ size_t rc = call->result_count(); -+ if (rc == 0) -+ return Statement::make_statement(call, true); -+ else -+ { -+ Expression_list* vals = new Expression_list(); -+ if (rc == 1) -+ vals->push_back(call); -+ else -+ { -+ for (size_t i = 0; i < rc; ++i) -+ vals->push_back(Expression::make_call_result(call, i)); -+ } -+ return Statement::make_return_statement(vals, location); -+ } -+} -+ - // A break or continue statement. - - class Bc_statement : public Statement -@@ -3700,9 +3740,6 @@ - void - do_check_types(Gogo*); - -- bool -- do_may_fall_through() const; -- - Bstatement* - do_get_backend(Translate_context*); - -@@ -3746,22 +3783,6 @@ - this->set_is_error(); - } - --// Return whether this switch may fall through. -- --bool --Constant_switch_statement::do_may_fall_through() const --{ -- if (this->clauses_ == NULL) -- return true; -- -- // If we have a break label, then some case needed it. That implies -- // that the switch statement as a whole can fall through. -- if (this->break_label_ != NULL) -- return true; -- -- return this->clauses_->may_fall_through(); --} -- - // Convert to GENERIC. - - Bstatement* -@@ -3911,6 +3932,22 @@ - ast_dump_context->ostream() << std::endl; - } - -+// Return whether this switch may fall through. -+ -+bool -+Switch_statement::do_may_fall_through() const -+{ -+ if (this->clauses_ == NULL) -+ return true; -+ -+ // If we have a break label, then some case needed it. That implies -+ // that the switch statement as a whole can fall through. -+ if (this->break_label_ != NULL) -+ return true; -+ -+ return this->clauses_->may_fall_through(); -+} -+ - // Make a switch statement. - - Switch_statement* -@@ -4050,6 +4087,17 @@ - } - } - -+// Return true if this type clause may fall through to the statements -+// following the switch. -+ -+bool -+Type_case_clauses::Type_case_clause::may_fall_through() const -+{ -+ if (this->statements_ == NULL) -+ return true; -+ return this->statements_->may_fall_through(); -+} -+ - // Dump the AST representation for a type case clause - - void -@@ -4148,6 +4196,25 @@ - NULL); - } - -+// Return true if these clauses may fall through to the statements -+// following the switch statement. -+ -+bool -+Type_case_clauses::may_fall_through() const -+{ -+ bool found_default = false; -+ for (Type_clauses::const_iterator p = this->clauses_.begin(); -+ p != this->clauses_.end(); -+ ++p) -+ { -+ if (p->may_fall_through()) -+ return true; -+ if (p->is_default()) -+ found_default = true; -+ } -+ return !found_default; -+} -+ - // Dump the AST representation for case clauses (from a switch statement) - - void -@@ -4237,6 +4304,22 @@ - return Statement::make_block_statement(b, loc); - } - -+// Return whether this switch may fall through. -+ -+bool -+Type_switch_statement::do_may_fall_through() const -+{ -+ if (this->clauses_ == NULL) -+ return true; -+ -+ // If we have a break label, then some case needed it. That implies -+ // that the switch statement as a whole can fall through. -+ if (this->break_label_ != NULL) -+ return true; -+ -+ return this->clauses_->may_fall_through(); -+} -+ - // Return the break label for this type switch statement, creating it - // if necessary. - -@@ -4954,6 +5037,19 @@ - return Statement::make_block_statement(b, loc); - } - -+// Whether the select statement itself may fall through to the following -+// statement. -+ -+bool -+Select_statement::do_may_fall_through() const -+{ -+ // A select statement is terminating if no break statement -+ // refers to it and all of its clauses are terminating. -+ if (this->break_label_ != NULL) -+ return true; -+ return this->clauses_->may_fall_through(); -+} -+ - // Return the backend representation for a select statement. - - Bstatement* -@@ -5114,6 +5210,20 @@ - this->continue_label_ = continue_label; - } - -+// Whether the overall statement may fall through. -+ -+bool -+For_statement::do_may_fall_through() const -+{ -+ // A for loop is terminating if it has no condition and -+ // no break statement. -+ if(this->cond_ != NULL) -+ return true; -+ if(this->break_label_ != NULL) -+ return true; -+ return false; -+} -+ - // Dump the AST representation for a for statement. - - void -Index: gcc/go/gofrontend/gogo-tree.cc -=================================================================== ---- a/src/gcc/go/gofrontend/gogo-tree.cc (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/gogo-tree.cc (.../branches/gcc-4_8-branch) -@@ -755,6 +755,18 @@ - this->build_interface_method_tables(); - - Bindings* bindings = this->current_bindings(); -+ -+ for (Bindings::const_declarations_iterator p = bindings->begin_declarations(); -+ p != bindings->end_declarations(); -+ ++p) -+ { -+ // If any function declarations needed a descriptor, make sure -+ // we build it. -+ Named_object* no = p->second; -+ if (no->is_function_declaration()) -+ no->func_declaration_value()->build_backend_descriptor(this); -+ } -+ - size_t count_definitions = bindings->size_definitions(); - size_t count = count_definitions; - -@@ -782,6 +794,8 @@ - { - Named_object* no = *p; - -+ go_assert(i < count); -+ - go_assert(!no->is_type_declaration() && !no->is_function_declaration()); - // There is nothing to do for a package. - if (no->is_package()) -@@ -800,6 +814,15 @@ - continue; - } - -+ // Skip blank named functions and constants. -+ if ((no->is_function() && no->func_value()->is_sink()) -+ || (no->is_const() && no->const_value()->is_sink())) -+ { -+ --i; -+ --count; -+ continue; -+ } -+ - // There is nothing useful we can output for constants which - // have ideal or non-integral type. - if (no->is_const()) -@@ -1255,14 +1278,47 @@ - if (this->fndecl_ == NULL_TREE) - { - tree functype = type_to_tree(this->type_->get_backend(gogo)); -+ -+ if (functype != error_mark_node) -+ { -+ // The type of a function comes back as a pointer to a -+ // struct whose first field is the function, but we want the -+ // real function type for a function declaration. -+ go_assert(POINTER_TYPE_P(functype) -+ && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE); -+ functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype))); -+ go_assert(FUNCTION_POINTER_TYPE_P(functype)); -+ functype = TREE_TYPE(functype); -+ -+ // In the struct, the function type always has a trailing -+ // closure argument. For the function body, we only use -+ // that trailing arg if this is a function literal or if it -+ // is a wrapper created to store in a descriptor. Remove it -+ // in that case. -+ if (this->enclosing_ == NULL && !this->is_descriptor_wrapper_) -+ { -+ tree old_params = TYPE_ARG_TYPES(functype); -+ go_assert(old_params != NULL_TREE -+ && old_params != void_list_node); -+ tree new_params = NULL_TREE; -+ tree *pp = &new_params; -+ while (TREE_CHAIN (old_params) != void_list_node) -+ { -+ tree p = TREE_VALUE(old_params); -+ go_assert(TYPE_P(p)); -+ *pp = tree_cons(NULL_TREE, p, NULL_TREE); -+ pp = &TREE_CHAIN(*pp); -+ old_params = TREE_CHAIN (old_params); -+ } -+ *pp = void_list_node; -+ functype = build_function_type(TREE_TYPE(functype), new_params); -+ } -+ } -+ - if (functype == error_mark_node) - this->fndecl_ = error_mark_node; - else - { -- // The type of a function comes back as a pointer, but we -- // want the real function type for a function declaration. -- go_assert(POINTER_TYPE_P(functype)); -- functype = TREE_TYPE(functype); - tree decl = build_decl(this->location().gcc_location(), FUNCTION_DECL, - id, functype); - -@@ -1308,9 +1364,6 @@ - DECL_CONTEXT(resdecl) = decl; - DECL_RESULT(decl) = resdecl; - -- if (this->enclosing_ != NULL) -- DECL_STATIC_CHAIN(decl) = 1; -- - // If a function calls the predeclared recover function, we - // can't inline it, because recover behaves differently in a - // function passed directly to defer. If this is a recover -@@ -1333,29 +1386,6 @@ - resolve_unique_section (decl, 0, 1); - - go_preserve_from_gc(decl); -- -- if (this->closure_var_ != NULL) -- { -- push_struct_function(decl); -- -- Bvariable* bvar = this->closure_var_->get_backend_variable(gogo, -- no); -- tree closure_decl = var_to_tree(bvar); -- if (closure_decl == error_mark_node) -- this->fndecl_ = error_mark_node; -- else -- { -- DECL_ARTIFICIAL(closure_decl) = 1; -- DECL_IGNORED_P(closure_decl) = 1; -- TREE_USED(closure_decl) = 1; -- DECL_ARG_TYPE(closure_decl) = TREE_TYPE(closure_decl); -- TREE_READONLY(closure_decl) = 1; -- -- DECL_STRUCT_FUNCTION(decl)->static_chain_decl = closure_decl; -- } -- -- pop_cfun(); -- } - } - } - return this->fndecl_; -@@ -1382,15 +1412,44 @@ - } - - tree functype = type_to_tree(this->fntype_->get_backend(gogo)); -+ -+ if (functype != error_mark_node) -+ { -+ // The type of a function comes back as a pointer to a -+ // struct whose first field is the function, but we want the -+ // real function type for a function declaration. -+ go_assert(POINTER_TYPE_P(functype) -+ && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE); -+ functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype))); -+ go_assert(FUNCTION_POINTER_TYPE_P(functype)); -+ functype = TREE_TYPE(functype); -+ -+ // In the struct, the function type always has a trailing -+ // closure argument. Here we are referring to the function -+ // code directly, and we know it is not a function literal, -+ // and we know it is not a wrapper created to store in a -+ // descriptor. Remove that trailing argument. -+ tree old_params = TYPE_ARG_TYPES(functype); -+ go_assert(old_params != NULL_TREE && old_params != void_list_node); -+ tree new_params = NULL_TREE; -+ tree *pp = &new_params; -+ while (TREE_CHAIN (old_params) != void_list_node) -+ { -+ tree p = TREE_VALUE(old_params); -+ go_assert(TYPE_P(p)); -+ *pp = tree_cons(NULL_TREE, p, NULL_TREE); -+ pp = &TREE_CHAIN(*pp); -+ old_params = TREE_CHAIN (old_params); -+ } -+ *pp = void_list_node; -+ functype = build_function_type(TREE_TYPE(functype), new_params); -+ } -+ - tree decl; - if (functype == error_mark_node) - decl = error_mark_node; - else - { -- // The type of a function comes back as a pointer, but we -- // want the real function type for a function declaration. -- go_assert(POINTER_TYPE_P(functype)); -- functype = TREE_TYPE(functype); - decl = build_decl(this->location().gcc_location(), FUNCTION_DECL, id, - functype); - TREE_PUBLIC(decl) = 1; -@@ -1599,6 +1658,32 @@ - } - } - } -+ -+ // The closure variable is passed last, if this is a function -+ // literal or a descriptor wrapper. -+ if (this->closure_var_ != NULL) -+ { -+ Bvariable* bvar = -+ this->closure_var_->get_backend_variable(gogo, named_function); -+ tree var_decl = var_to_tree(bvar); -+ if (var_decl != error_mark_node) -+ { -+ go_assert(TREE_CODE(var_decl) == PARM_DECL); -+ *pp = var_decl; -+ pp = &DECL_CHAIN(*pp); -+ } -+ } -+ else if (this->enclosing_ != NULL || this->is_descriptor_wrapper_) -+ { -+ tree parm_decl = build_decl(this->location_.gcc_location(), PARM_DECL, -+ get_identifier("$closure"), -+ const_ptr_type_node); -+ DECL_CONTEXT(parm_decl) = current_function_decl; -+ DECL_ARG_TYPE(parm_decl) = const_ptr_type_node; -+ *pp = parm_decl; -+ pp = &DECL_CHAIN(*pp); -+ } -+ - *pp = NULL_TREE; - - DECL_ARGUMENTS(fndecl) = params; -@@ -1681,6 +1766,13 @@ - - DECL_SAVED_TREE(fndecl) = code; - } -+ -+ // If we created a descriptor for the function, make sure we emit it. -+ if (this->descriptor_ != NULL) -+ { -+ Translate_context context(gogo, NULL, NULL, NULL); -+ this->descriptor_->get_tree(&context); -+ } - } - - // Build the wrappers around function code needed if the function has -@@ -1844,6 +1936,20 @@ - } - } - -+// Build the descriptor for a function declaration. This won't -+// necessarily happen if the package has just a declaration for the -+// function and no other reference to it, but we may still need the -+// descriptor for references from other packages. -+void -+Function_declaration::build_backend_descriptor(Gogo* gogo) -+{ -+ if (this->descriptor_ != NULL) -+ { -+ Translate_context context(gogo, NULL, NULL, NULL); -+ this->descriptor_->get_tree(&context); -+ } -+} -+ - // Return the integer type to use for a size. - - GO_EXTERN_C -@@ -2437,70 +2543,3 @@ - build2(COMPOUND_EXPR, type_tree, call, tmp)); - } - } -- --// Return the type of a function trampoline. This is like --// get_trampoline_type in tree-nested.c. -- --tree --Gogo::trampoline_type_tree() --{ -- static tree type_tree; -- if (type_tree == NULL_TREE) -- { -- unsigned int size; -- unsigned int align; -- go_trampoline_info(&size, &align); -- tree t = build_index_type(build_int_cst(integer_type_node, size - 1)); -- t = build_array_type(char_type_node, t); -- -- type_tree = Gogo::builtin_struct(NULL, "__go_trampoline", NULL_TREE, 1, -- "__data", t); -- t = TYPE_FIELDS(type_tree); -- DECL_ALIGN(t) = align; -- DECL_USER_ALIGN(t) = 1; -- -- go_preserve_from_gc(type_tree); -- } -- return type_tree; --} -- --// Make a trampoline which calls FNADDR passing CLOSURE. -- --tree --Gogo::make_trampoline(tree fnaddr, tree closure, Location location) --{ -- tree trampoline_type = Gogo::trampoline_type_tree(); -- tree trampoline_size = TYPE_SIZE_UNIT(trampoline_type); -- -- closure = save_expr(closure); -- -- // We allocate the trampoline using a special function which will -- // mark it as executable. -- static tree trampoline_fndecl; -- tree x = Gogo::call_builtin(&trampoline_fndecl, -- location, -- "__go_allocate_trampoline", -- 2, -- ptr_type_node, -- size_type_node, -- trampoline_size, -- ptr_type_node, -- fold_convert_loc(location.gcc_location(), -- ptr_type_node, closure)); -- if (x == error_mark_node) -- return error_mark_node; -- -- x = save_expr(x); -- -- // Initialize the trampoline. -- tree calldecl = builtin_decl_implicit(BUILT_IN_INIT_HEAP_TRAMPOLINE); -- tree ini = build_call_expr(calldecl, 3, x, fnaddr, closure); -- -- // On some targets the trampoline address needs to be adjusted. For -- // example, when compiling in Thumb mode on the ARM, the address -- // needs to have the low bit set. -- x = build_call_expr(builtin_decl_explicit(BUILT_IN_ADJUST_TRAMPOLINE), 1, x); -- x = fold_convert(TREE_TYPE(fnaddr), x); -- -- return build2(COMPOUND_EXPR, TREE_TYPE(x), ini, x); --} -Index: gcc/go/gofrontend/statements.h -=================================================================== ---- a/src/gcc/go/gofrontend/statements.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/statements.h (.../branches/gcc-4_8-branch) -@@ -207,6 +207,13 @@ - static Return_statement* - make_return_statement(Expression_list*, Location); - -+ // Make a statement that returns the result of a call expression. -+ // If the call does not return any results, this just returns the -+ // call expression as a statement, assuming that the function will -+ // end immediately afterward. -+ static Statement* -+ make_return_from_call(Call_expression*, Location); -+ - // Make a break statement. - static Statement* - make_break_statement(Unnamed_label* label, Location); -@@ -894,8 +901,7 @@ - { this->clauses_->check_types(); } - - bool -- do_may_fall_through() const -- { return this->clauses_->may_fall_through(); } -+ do_may_fall_through() const; - - Bstatement* - do_get_backend(Translate_context*); -@@ -1086,6 +1092,9 @@ - Statement* - do_lower(Gogo*, Named_object*, Block*, Statement_inserter*); - -+ bool -+ do_may_fall_through() const; -+ - Bstatement* - do_get_backend(Translate_context*) - { go_unreachable(); } -@@ -1399,6 +1408,9 @@ - void - do_dump_statement(Ast_dump_context*) const; - -+ bool -+ do_may_fall_through() const; -+ - private: - // The value to switch on. This may be NULL. - Expression* val_; -@@ -1449,6 +1461,11 @@ - lower(Type*, Block*, Temporary_statement* descriptor_temp, - Unnamed_label* break_label) const; - -+ // Return true if these clauses may fall through to the statements -+ // following the switch statement. -+ bool -+ may_fall_through() const; -+ - // Dump the AST representation to a dump context. - void - dump_clauses(Ast_dump_context*) const; -@@ -1493,6 +1510,12 @@ - lower(Type*, Block*, Temporary_statement* descriptor_temp, - Unnamed_label* break_label, Unnamed_label** stmts_label) const; - -+ // Return true if this clause may fall through to execute the -+ // statements following the switch statement. This is not the -+ // same as whether this clause falls through to the next clause. -+ bool -+ may_fall_through() const; -+ - // Dump the AST representation to a dump context. - void - dump_clause(Ast_dump_context*) const; -@@ -1556,6 +1579,9 @@ - void - do_dump_statement(Ast_dump_context*) const; - -+ bool -+ do_may_fall_through() const; -+ - private: - // The variable holding the value we are switching on. - Named_object* var_; -Index: gcc/go/gofrontend/backend.h -=================================================================== ---- a/src/gcc/go/gofrontend/backend.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/backend.h (.../branches/gcc-4_8-branch) -@@ -95,7 +95,10 @@ - - // Get a function type. The receiver, parameter, and results are - // generated from the types in the Function_type. The Function_type -- // is provided so that the names are available. -+ // is provided so that the names are available. This should return -+ // not the type of a Go function (which is a pointer to a struct) -+ // but the type of a C function pointer (which will be used as the -+ // type of the first field of the struct). - virtual Btype* - function_type(const Btyped_identifier& receiver, - const std::vector& parameters, -@@ -388,18 +391,22 @@ - Bstatement** pstatement) = 0; - - // Create a named immutable initialized data structure. This is -- // used for type descriptors and map descriptors. This returns a -- // Bvariable because it corresponds to an initialized const global -- // variable in C. -+ // used for type descriptors, map descriptors, and function -+ // descriptors. This returns a Bvariable because it corresponds to -+ // an initialized const variable in C. - // - // NAME is the name to use for the initialized global variable which - // this call will create. - // -+ // IS_HIDDEN will be true if the descriptor should only be visible -+ // within the current object. -+ // - // IS_COMMON is true if NAME may be defined by several packages, and - // the linker should merge all such definitions. If IS_COMMON is - // false, NAME should be defined in only one file. In general - // IS_COMMON will be true for the type descriptor of an unnamed type -- // or a builtin type. -+ // or a builtin type. IS_HIDDEN and IS_COMMON will never both be -+ // true. - // - // TYPE will be a struct type; the type of the returned expression - // must be a pointer to this struct type. -@@ -409,20 +416,20 @@ - // address. After calling this the frontend will call - // immutable_struct_set_init. - virtual Bvariable* -- immutable_struct(const std::string& name, bool is_common, Btype* type, -- Location) = 0; -+ immutable_struct(const std::string& name, bool is_hidden, bool is_common, -+ Btype* type, Location) = 0; - - // Set the initial value of a variable created by immutable_struct. -- // The NAME, IS_COMMON, TYPE, and location parameters are the same -- // ones passed to immutable_struct. INITIALIZER will be a composite -- // literal of type TYPE. It will not contain any function calls or -- // anything else which can not be put into a read-only data section. -- // It may contain the address of variables created by -+ // The NAME, IS_HIDDEN, IS_COMMON, TYPE, and location parameters are -+ // the same ones passed to immutable_struct. INITIALIZER will be a -+ // composite literal of type TYPE. It will not contain any function -+ // calls or anything else that can not be put into a read-only data -+ // section. It may contain the address of variables created by - // immutable_struct. - virtual void - immutable_struct_set_init(Bvariable*, const std::string& name, -- bool is_common, Btype* type, Location, -- Bexpression* initializer) = 0; -+ bool is_hidden, bool is_common, Btype* type, -+ Location, Bexpression* initializer) = 0; - - // Create a reference to a named immutable initialized data - // structure defined in some other package. This will be a -Index: gcc/go/gofrontend/types.cc -=================================================================== ---- a/src/gcc/go/gofrontend/types.cc (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/types.cc (.../branches/gcc-4_8-branch) -@@ -1298,8 +1298,8 @@ - // converting INITIALIZER. - - this->type_descriptor_var_ = -- gogo->backend()->immutable_struct(var_name, is_common, initializer_btype, -- loc); -+ gogo->backend()->immutable_struct(var_name, false, is_common, -+ initializer_btype, loc); - if (phash != NULL) - *phash = this->type_descriptor_var_; - -@@ -1308,7 +1308,7 @@ - Bexpression* binitializer = tree_to_expr(initializer->get_tree(&context)); - - gogo->backend()->immutable_struct_set_init(this->type_descriptor_var_, -- var_name, is_common, -+ var_name, false, is_common, - initializer_btype, loc, - binitializer); - } -@@ -1528,26 +1528,6 @@ - - // The type descriptor type. - -- Typed_identifier_list* params = new Typed_identifier_list(); -- params->push_back(Typed_identifier("key", unsafe_pointer_type, bloc)); -- params->push_back(Typed_identifier("key_size", uintptr_type, bloc)); -- -- Typed_identifier_list* results = new Typed_identifier_list(); -- results->push_back(Typed_identifier("", uintptr_type, bloc)); -- -- Type* hashfn_type = Type::make_function_type(NULL, params, results, bloc); -- -- params = new Typed_identifier_list(); -- params->push_back(Typed_identifier("key1", unsafe_pointer_type, bloc)); -- params->push_back(Typed_identifier("key2", unsafe_pointer_type, bloc)); -- params->push_back(Typed_identifier("key_size", uintptr_type, bloc)); -- -- results = new Typed_identifier_list(); -- results->push_back(Typed_identifier("", Type::lookup_bool_type(), bloc)); -- -- Type* equalfn_type = Type::make_function_type(NULL, params, results, -- bloc); -- - Struct_type* type_descriptor_type = - Type::make_builtin_struct_type(10, - "Kind", uint8_type, -@@ -1555,8 +1535,8 @@ - "fieldAlign", uint8_type, - "size", uintptr_type, - "hash", uint32_type, -- "hashfn", hashfn_type, -- "equalfn", equalfn_type, -+ "hashfn", uintptr_type, -+ "equalfn", uintptr_type, - "string", pointer_string_type, - "", pointer_uncommon_type, - "ptrToThis", -@@ -1946,8 +1926,8 @@ - Named_object* equal_fn; - this->type_functions(gogo, name, hash_fntype, equal_fntype, &hash_fn, - &equal_fn); -- vals->push_back(Expression::make_func_reference(hash_fn, NULL, bloc)); -- vals->push_back(Expression::make_func_reference(equal_fn, NULL, bloc)); -+ vals->push_back(Expression::make_func_code_reference(hash_fn, bloc)); -+ vals->push_back(Expression::make_func_code_reference(equal_fn, bloc)); - - ++p; - go_assert(p->is_field_name("string")); -@@ -2207,7 +2187,7 @@ - - ++p; - go_assert(p->is_field_name("tfn")); -- vals->push_back(Expression::make_func_reference(no, NULL, bloc)); -+ vals->push_back(Expression::make_func_code_reference(no, bloc)); - - ++p; - go_assert(p == fields->end()); -@@ -3407,6 +3387,19 @@ - Btype* - Function_type::do_get_backend(Gogo* gogo) - { -+ // When we do anything with a function value other than call it, it -+ // is represented as a pointer to a struct whose first field is the -+ // actual function. So that is what we return as the type of a Go -+ // function. The function stored in the first field always that -+ // takes one additional trailing argument: the closure pointer. For -+ // a top-level function, this additional argument will only be -+ // passed when invoking the function indirectly, via the struct. -+ -+ Location loc = this->location(); -+ Btype* struct_type = -+ gogo->backend()->placeholder_struct_type("__go_descriptor", loc); -+ Btype* ptr_struct_type = gogo->backend()->pointer_type(struct_type); -+ - Backend::Btyped_identifier breceiver; - if (this->receiver_ != NULL) - { -@@ -3422,9 +3415,15 @@ - } - - std::vector bparameters; -- if (this->parameters_ != NULL) -+ size_t last; -+ if (this->parameters_ == NULL) - { -- bparameters.resize(this->parameters_->size()); -+ bparameters.resize(1); -+ last = 0; -+ } -+ else -+ { -+ bparameters.resize(this->parameters_->size() + 1); - size_t i = 0; - for (Typed_identifier_list::const_iterator p = this->parameters_->begin(); - p != this->parameters_->end(); -@@ -3434,8 +3433,12 @@ - bparameters[i].btype = p->type()->get_backend(gogo); - bparameters[i].location = p->location(); - } -- go_assert(i == bparameters.size()); -+ last = i; - } -+ go_assert(last + 1 == bparameters.size()); -+ bparameters[last].name = "$closure"; -+ bparameters[last].btype = ptr_struct_type; -+ bparameters[last].location = loc; - - std::vector bresults; - if (this->results_ != NULL) -@@ -3453,8 +3456,15 @@ - go_assert(i == bresults.size()); - } - -- return gogo->backend()->function_type(breceiver, bparameters, bresults, -- this->location()); -+ Btype* fntype = gogo->backend()->function_type(breceiver, bparameters, -+ bresults, loc); -+ std::vector fields(1); -+ fields[0].name = "code"; -+ fields[0].btype = fntype; -+ fields[0].location = loc; -+ if (!gogo->backend()->set_placeholder_struct_type(struct_type, fields)) -+ return gogo->backend()->error_type(); -+ return ptr_struct_type; - } - - // The type of a function type descriptor. -@@ -3826,6 +3836,49 @@ - return ret; - } - -+// Make a copy of a function type ignoring any receiver and adding a -+// closure parameter. -+ -+Function_type* -+Function_type::copy_with_closure(Type* closure_type) const -+{ -+ Typed_identifier_list* new_params = new Typed_identifier_list(); -+ const Typed_identifier_list* orig_params = this->parameters_; -+ if (orig_params != NULL && !orig_params->empty()) -+ { -+ static int count; -+ char buf[50]; -+ for (Typed_identifier_list::const_iterator p = orig_params->begin(); -+ p != orig_params->end(); -+ ++p) -+ { -+ snprintf(buf, sizeof buf, "pt.%u", count); -+ ++count; -+ new_params->push_back(Typed_identifier(buf, p->type(), -+ p->location())); -+ } -+ } -+ new_params->push_back(Typed_identifier("closure.0", closure_type, -+ this->location_)); -+ -+ const Typed_identifier_list* orig_results = this->results_; -+ Typed_identifier_list* new_results; -+ if (orig_results == NULL || orig_results->empty()) -+ new_results = NULL; -+ else -+ { -+ new_results = new Typed_identifier_list(); -+ for (Typed_identifier_list::const_iterator p = orig_results->begin(); -+ p != orig_results->end(); -+ ++p) -+ new_results->push_back(Typed_identifier("", p->type(), -+ p->location())); -+ } -+ -+ return Type::make_function_type(NULL, new_params, new_results, -+ this->location()); -+} -+ - // Make a function type. - - Function_type* -@@ -4532,6 +4585,7 @@ - go_assert(sub != NULL); - } - sub->set_struct_expression(here); -+ sub->set_implicit(true); - } - else if (subdepth > found_depth) - delete sub; -@@ -6227,7 +6281,8 @@ - - std::string mangled_name = "__go_map_" + this->mangled_name(gogo); - Btype* map_descriptor_btype = map_descriptor_type->get_backend(gogo); -- Bvariable* bvar = gogo->backend()->immutable_struct(mangled_name, true, -+ Bvariable* bvar = gogo->backend()->immutable_struct(mangled_name, false, -+ true, - map_descriptor_btype, - bloc); - -@@ -6235,7 +6290,7 @@ - context.set_is_const(); - Bexpression* binitializer = tree_to_expr(initializer->get_tree(&context)); - -- gogo->backend()->immutable_struct_set_init(bvar, mangled_name, true, -+ gogo->backend()->immutable_struct_set_init(bvar, mangled_name, false, true, - map_descriptor_btype, bloc, - binitializer); - -@@ -7569,7 +7624,7 @@ - // the child class. - return this->do_bind_method(expr, location); - } -- return Expression::make_bound_method(expr, this->stub_, location); -+ return Expression::make_bound_method(expr, this, this->stub_, location); - } - - // Return the named object associated with a method. This may only be -@@ -7612,8 +7667,8 @@ - Named_method::do_bind_method(Expression* expr, Location location) const - { - Named_object* no = this->named_object_; -- Bound_method_expression* bme = Expression::make_bound_method(expr, no, -- location); -+ Bound_method_expression* bme = Expression::make_bound_method(expr, this, -+ no, location); - // If this is not a local method, and it does not use a stub, then - // the real method expects a different type. We need to cast the - // first argument. -@@ -8991,28 +9046,16 @@ - Call_expression* call = Expression::make_call(func, arguments, is_varargs, - location); - call->set_hidden_fields_are_ok(); -- size_t count = call->result_count(); -- if (count == 0) -- gogo->add_statement(Statement::make_statement(call, true)); -- else -+ -+ Statement* s = Statement::make_return_from_call(call, location); -+ Return_statement* retstat = s->return_statement(); -+ if (retstat != NULL) - { -- Expression_list* retvals = new Expression_list(); -- if (count <= 1) -- retvals->push_back(call); -- else -- { -- for (size_t i = 0; i < count; ++i) -- retvals->push_back(Expression::make_call_result(call, i)); -- } -- Return_statement* retstat = Statement::make_return_statement(retvals, -- location); -- - // We can return values with hidden fields from a stub. This is - // necessary if the method is itself hidden. - retstat->set_hidden_fields_are_ok(); -- -- gogo->add_statement(retstat); - } -+ gogo->add_statement(s); - } - - // Apply FIELD_INDEXES to EXPR. The field indexes have to be applied -@@ -9353,13 +9396,18 @@ - fnt = pf->type()->deref()->named_type(); - go_assert(fnt != NULL); - -+ // Methods with pointer receivers on embedded field are -+ // inherited by the pointer to struct, and also by the struct -+ // type if the field itself is a pointer. -+ bool can_be_pointer = (receiver_can_be_pointer -+ || pf->type()->points_to() != NULL); - int sublevel = level == NULL ? 1 : *level + 1; - bool sub_is_method; - std::string subambig1; - std::string subambig2; - bool subfound = Type::find_field_or_method(fnt, - name, -- receiver_can_be_pointer, -+ can_be_pointer, - seen, - &sublevel, - &sub_is_method, -Index: gcc/go/gofrontend/expressions.cc -=================================================================== ---- a/src/gcc/go/gofrontend/expressions.cc (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/go/gofrontend/expressions.cc (.../branches/gcc-4_8-branch) -@@ -1090,6 +1090,15 @@ - return this->statement_->type(); - } - -+// Determine the type of the expression. -+ -+void -+Set_and_use_temporary_expression::do_determine_type( -+ const Type_context* context) -+{ -+ this->expr_->determine_type(context); -+} -+ - // Take the address. - - void -@@ -1255,17 +1264,16 @@ - go_unreachable(); - } - --// Get the tree for a function expression without evaluating the --// closure. -+// Get the tree for the code of a function expression. - - tree --Func_expression::get_tree_without_closure(Gogo* gogo) -+Func_expression::get_code_pointer(Gogo* gogo, Named_object* no, Location loc) - { - Function_type* fntype; -- if (this->function_->is_function()) -- fntype = this->function_->func_value()->type(); -- else if (this->function_->is_function_declaration()) -- fntype = this->function_->func_declaration_value()->type(); -+ if (no->is_function()) -+ fntype = no->func_value()->type(); -+ else if (no->is_function_declaration()) -+ fntype = no->func_declaration_value()->type(); - else - go_unreachable(); - -@@ -1273,14 +1281,12 @@ - // can't take their address. - if (fntype->is_builtin()) - { -- error_at(this->location(), -+ error_at(loc, - "invalid use of special builtin function %qs; must be called", -- this->function_->name().c_str()); -+ no->message_name().c_str()); - return error_mark_node; - } - -- Named_object* no = this->function_; -- - tree id = no->get_id(gogo); - if (id == error_mark_node) - return error_mark_node; -@@ -1296,46 +1302,55 @@ - if (fndecl == error_mark_node) - return error_mark_node; - -- return build_fold_addr_expr_loc(this->location().gcc_location(), fndecl); -+ return build_fold_addr_expr_loc(loc.gcc_location(), fndecl); - } - - // Get the tree for a function expression. This is used when we take --// the address of a function rather than simply calling it. If the --// function has a closure, we must use a trampoline. -+// the address of a function rather than simply calling it. A func -+// value is represented as a pointer to a block of memory. The first -+// word of that memory is a pointer to the function code. The -+// remaining parts of that memory are the addresses of variables that -+// the function closes over. - - tree - Func_expression::do_get_tree(Translate_context* context) - { -- Gogo* gogo = context->gogo(); -+ // If there is no closure, just use the function descriptor. -+ if (this->closure_ == NULL) -+ { -+ Gogo* gogo = context->gogo(); -+ Named_object* no = this->function_; -+ Expression* descriptor; -+ if (no->is_function()) -+ descriptor = no->func_value()->descriptor(gogo, no); -+ else if (no->is_function_declaration()) -+ { -+ if (no->func_declaration_value()->type()->is_builtin()) -+ { -+ error_at(this->location(), -+ ("invalid use of special builtin function %qs; " -+ "must be called"), -+ no->message_name().c_str()); -+ return error_mark_node; -+ } -+ descriptor = no->func_declaration_value()->descriptor(gogo, no); -+ } -+ else -+ go_unreachable(); - -- tree fnaddr = this->get_tree_without_closure(gogo); -- if (fnaddr == error_mark_node) -- return error_mark_node; -+ tree dtree = descriptor->get_tree(context); -+ if (dtree == error_mark_node) -+ return error_mark_node; -+ return build_fold_addr_expr_loc(this->location().gcc_location(), dtree); -+ } - -- go_assert(TREE_CODE(fnaddr) == ADDR_EXPR -- && TREE_CODE(TREE_OPERAND(fnaddr, 0)) == FUNCTION_DECL); -- TREE_ADDRESSABLE(TREE_OPERAND(fnaddr, 0)) = 1; -- -- // If there is no closure, that is all have to do. -- if (this->closure_ == NULL) -- return fnaddr; -- - go_assert(this->function_->func_value()->enclosing() != NULL); - -- // Get the value of the closure. This will be a pointer to space -- // allocated on the heap. -- tree closure_tree = this->closure_->get_tree(context); -- if (closure_tree == error_mark_node) -- return error_mark_node; -- go_assert(POINTER_TYPE_P(TREE_TYPE(closure_tree))); -- -- // Now we need to build some code on the heap. This code will load -- // the static chain pointer with the closure and then jump to the -- // body of the function. The normal gcc approach is to build the -- // code on the stack. Unfortunately we can not do that, as Go -- // permits us to return the function pointer. -- -- return gogo->make_trampoline(fnaddr, closure_tree, this->location()); -+ // If there is a closure, then the closure is itself the function -+ // expression. It is a pointer to a struct whose first field points -+ // to the function code and whose remaining fields are the addresses -+ // of the closed-over variables. -+ return this->closure_->get_tree(context); - } - - // Ast dump for function. -@@ -1361,6 +1376,197 @@ - return new Func_expression(function, closure, location); - } - -+// Class Func_descriptor_expression. -+ -+// Constructor. -+ -+Func_descriptor_expression::Func_descriptor_expression(Named_object* fn) -+ : Expression(EXPRESSION_FUNC_DESCRIPTOR, fn->location()), -+ fn_(fn), dfn_(NULL), dvar_(NULL) -+{ -+ go_assert(!fn->is_function() || !fn->func_value()->needs_closure()); -+} -+ -+// Traversal. -+ -+int -+Func_descriptor_expression::do_traverse(Traverse*) -+{ -+ return TRAVERSE_CONTINUE; -+} -+ -+// All function descriptors have the same type. -+ -+Type* Func_descriptor_expression::descriptor_type; -+ -+void -+Func_descriptor_expression::make_func_descriptor_type() -+{ -+ if (Func_descriptor_expression::descriptor_type != NULL) -+ return; -+ Type* uintptr_type = Type::lookup_integer_type("uintptr"); -+ Type* struct_type = Type::make_builtin_struct_type(1, "code", uintptr_type); -+ Func_descriptor_expression::descriptor_type = -+ Type::make_builtin_named_type("functionDescriptor", struct_type); -+} -+ -+Type* -+Func_descriptor_expression::do_type() -+{ -+ Func_descriptor_expression::make_func_descriptor_type(); -+ return Func_descriptor_expression::descriptor_type; -+} -+ -+// Copy a Func_descriptor_expression; -+ -+Expression* -+Func_descriptor_expression::do_copy() -+{ -+ Func_descriptor_expression* fde = -+ Expression::make_func_descriptor(this->fn_); -+ if (this->dfn_ != NULL) -+ fde->set_descriptor_wrapper(this->dfn_); -+ return fde; -+} -+ -+// The tree for a function descriptor. -+ -+tree -+Func_descriptor_expression::do_get_tree(Translate_context* context) -+{ -+ if (this->dvar_ != NULL) -+ return var_to_tree(this->dvar_); -+ -+ Gogo* gogo = context->gogo(); -+ Named_object* no = this->fn_; -+ Location loc = no->location(); -+ -+ std::string var_name; -+ if (no->package() == NULL) -+ var_name = gogo->pkgpath_symbol(); -+ else -+ var_name = no->package()->pkgpath_symbol(); -+ var_name.push_back('.'); -+ var_name.append(Gogo::unpack_hidden_name(no->name())); -+ var_name.append("$descriptor"); -+ -+ Btype* btype = this->type()->get_backend(gogo); -+ -+ Bvariable* bvar; -+ if (no->package() != NULL -+ || Linemap::is_predeclared_location(no->location())) -+ { -+ bvar = context->backend()->immutable_struct_reference(var_name, btype, -+ loc); -+ go_assert(this->dfn_ == NULL); -+ } -+ else -+ { -+ Location bloc = Linemap::predeclared_location(); -+ bool is_hidden = ((no->is_function() -+ && no->func_value()->enclosing() != NULL) -+ || Gogo::is_thunk(no)); -+ bvar = context->backend()->immutable_struct(var_name, is_hidden, false, -+ btype, bloc); -+ Expression_list* vals = new Expression_list(); -+ go_assert(this->dfn_ != NULL); -+ vals->push_back(Expression::make_func_code_reference(this->dfn_, bloc)); -+ Expression* init = -+ Expression::make_struct_composite_literal(this->type(), vals, bloc); -+ Translate_context bcontext(gogo, NULL, NULL, NULL); -+ bcontext.set_is_const(); -+ Bexpression* binit = tree_to_expr(init->get_tree(&bcontext)); -+ context->backend()->immutable_struct_set_init(bvar, var_name, is_hidden, -+ false, btype, bloc, binit); -+ } -+ -+ this->dvar_ = bvar; -+ return var_to_tree(bvar); -+} -+ -+// Print a function descriptor expression. -+ -+void -+Func_descriptor_expression::do_dump_expression(Ast_dump_context* context) const -+{ -+ context->ostream() << "[descriptor " << this->fn_->name() << "]"; -+} -+ -+// Make a function descriptor expression. -+ -+Func_descriptor_expression* -+Expression::make_func_descriptor(Named_object* fn) -+{ -+ return new Func_descriptor_expression(fn); -+} -+ -+// Make the function descriptor type, so that it can be converted. -+ -+void -+Expression::make_func_descriptor_type() -+{ -+ Func_descriptor_expression::make_func_descriptor_type(); -+} -+ -+// A reference to just the code of a function. -+ -+class Func_code_reference_expression : public Expression -+{ -+ public: -+ Func_code_reference_expression(Named_object* function, Location location) -+ : Expression(EXPRESSION_FUNC_CODE_REFERENCE, location), -+ function_(function) -+ { } -+ -+ protected: -+ int -+ do_traverse(Traverse*) -+ { return TRAVERSE_CONTINUE; } -+ -+ Type* -+ do_type() -+ { return Type::make_pointer_type(Type::make_void_type()); } -+ -+ void -+ do_determine_type(const Type_context*) -+ { } -+ -+ Expression* -+ do_copy() -+ { -+ return Expression::make_func_code_reference(this->function_, -+ this->location()); -+ } -+ -+ tree -+ do_get_tree(Translate_context*); -+ -+ void -+ do_dump_expression(Ast_dump_context* context) const -+ { context->ostream() << "[raw " << this->function_->name() << "]" ; } -+ -+ private: -+ // The function. -+ Named_object* function_; -+}; -+ -+// Get the tree for a reference to function code. -+ -+tree -+Func_code_reference_expression::do_get_tree(Translate_context* context) -+{ -+ return Func_expression::get_code_pointer(context->gogo(), this->function_, -+ this->location()); -+} -+ -+// Make a reference to the code of a function. -+ -+Expression* -+Expression::make_func_code_reference(Named_object* function, Location location) -+{ -+ return new Func_code_reference_expression(function, location); -+} -+ - // Class Unknown_expression. - - // Return the name of an unknown expression. -@@ -5462,6 +5668,7 @@ - if (tleft->is_abstract() - && subcontext.type != NULL - && !subcontext.may_be_abstract -+ && subcontext.type->interface_type() == NULL - && subcontext.type->integer_type() == NULL) - this->report_error(("invalid context-determined non-integer type " - "for left operand of shift")); -@@ -5641,6 +5848,20 @@ - this->set_is_error(); - return; - } -+ if (this->op_ == OPERATOR_DIV || this->op_ == OPERATOR_MOD) -+ { -+ // Division by a zero integer constant is an error. -+ Numeric_constant rconst; -+ unsigned long rval; -+ if (left_type->integer_type() != NULL -+ && this->right_->numeric_constant_value(&rconst) -+ && rconst.to_unsigned_long(&rval) == Numeric_constant::NC_UL_VALID -+ && rval == 0) -+ { -+ this->report_error(_("integer division by zero")); -+ return; -+ } -+ } - } - else - { -@@ -6429,20 +6650,49 @@ - return Expression::traverse(&this->expr_, traverse); - } - -+// Lower the expression. If this is a method value rather than being -+// called, and the method is accessed via a pointer, we may need to -+// add nil checks. Introduce a temporary variable so that those nil -+// checks do not cause multiple evaluation. -+ -+Expression* -+Bound_method_expression::do_lower(Gogo*, Named_object*, -+ Statement_inserter* inserter, int) -+{ -+ // For simplicity we use a temporary for every call to an embedded -+ // method, even though some of them might be pure value methods and -+ // not require a temporary. -+ if (this->expr_->var_expression() == NULL -+ && this->expr_->temporary_reference_expression() == NULL -+ && this->expr_->set_and_use_temporary_expression() == NULL -+ && (this->method_->field_indexes() != NULL -+ || (this->method_->is_value_method() -+ && this->expr_->type()->points_to() != NULL))) -+ { -+ Temporary_statement* temp = -+ Statement::make_temporary(this->expr_->type(), NULL, this->location()); -+ inserter->insert(temp); -+ this->expr_ = Expression::make_set_and_use_temporary(temp, this->expr_, -+ this->location()); -+ } -+ return this; -+} -+ - // Return the type of a bound method expression. The type of this --// object is really the type of the method with no receiver. We --// should be able to get away with just returning the type of the --// method. -+// object is simply the type of the method with no receiver. - - Type* - Bound_method_expression::do_type() - { -- if (this->method_->is_function()) -- return this->method_->func_value()->type(); -- else if (this->method_->is_function_declaration()) -- return this->method_->func_declaration_value()->type(); -+ Named_object* fn = this->method_->named_object(); -+ Function_type* fntype; -+ if (fn->is_function()) -+ fntype = fn->func_value()->type(); -+ else if (fn->is_function_declaration()) -+ fntype = fn->func_declaration_value()->type(); - else - return Type::make_error_type(); -+ return fntype->copy_without_receiver(); - } - - // Determine the types of a method expression. -@@ -6450,7 +6700,14 @@ - void - Bound_method_expression::do_determine_type(const Type_context*) - { -- Function_type* fntype = this->type()->function_type(); -+ Named_object* fn = this->method_->named_object(); -+ Function_type* fntype; -+ if (fn->is_function()) -+ fntype = fn->func_value()->type(); -+ else if (fn->is_function_declaration()) -+ fntype = fn->func_declaration_value()->type(); -+ else -+ fntype = NULL; - if (fntype == NULL || !fntype->is_method()) - this->expr_->determine_type_no_context(); - else -@@ -6465,31 +6722,278 @@ - void - Bound_method_expression::do_check_types(Gogo*) - { -- if (!this->method_->is_function() -- && !this->method_->is_function_declaration()) -- this->report_error(_("object is not a method")); -+ Named_object* fn = this->method_->named_object(); -+ if (!fn->is_function() && !fn->is_function_declaration()) -+ { -+ this->report_error(_("object is not a method")); -+ return; -+ } -+ -+ Function_type* fntype; -+ if (fn->is_function()) -+ fntype = fn->func_value()->type(); -+ else if (fn->is_function_declaration()) -+ fntype = fn->func_declaration_value()->type(); - else -+ go_unreachable(); -+ Type* rtype = fntype->receiver()->type()->deref(); -+ Type* etype = (this->expr_type_ != NULL -+ ? this->expr_type_ -+ : this->expr_->type()); -+ etype = etype->deref(); -+ if (!Type::are_identical(rtype, etype, true, NULL)) -+ this->report_error(_("method type does not match object type")); -+} -+ -+// If a bound method expression is not simply called, then it is -+// represented as a closure. The closure will hold a single variable, -+// the receiver to pass to the method. The function will be a simple -+// thunk that pulls that value from the closure and calls the method -+// with the remaining arguments. -+// -+// Because method values are not common, we don't build all thunks for -+// every methods, but instead only build them as we need them. In -+// particular, we even build them on demand for methods defined in -+// other packages. -+ -+Bound_method_expression::Method_value_thunks -+ Bound_method_expression::method_value_thunks; -+ -+// Find or create the thunk for METHOD. -+ -+Named_object* -+Bound_method_expression::create_thunk(Gogo* gogo, const Method* method, -+ Named_object* fn) -+{ -+ std::pair val(fn, NULL); -+ std::pair ins = -+ Bound_method_expression::method_value_thunks.insert(val); -+ if (!ins.second) - { -- Type* rtype = this->type()->function_type()->receiver()->type()->deref(); -- Type* etype = (this->expr_type_ != NULL -- ? this->expr_type_ -- : this->expr_->type()); -- etype = etype->deref(); -- if (!Type::are_identical(rtype, etype, true, NULL)) -- this->report_error(_("method type does not match object type")); -+ // We have seen this method before. -+ go_assert(ins.first->second != NULL); -+ return ins.first->second; - } -+ -+ Location loc = fn->location(); -+ -+ Function_type* orig_fntype; -+ if (fn->is_function()) -+ orig_fntype = fn->func_value()->type(); -+ else if (fn->is_function_declaration()) -+ orig_fntype = fn->func_declaration_value()->type(); -+ else -+ orig_fntype = NULL; -+ -+ if (orig_fntype == NULL || !orig_fntype->is_method()) -+ { -+ ins.first->second = Named_object::make_erroneous_name(Gogo::thunk_name()); -+ return ins.first->second; -+ } -+ -+ Struct_field_list* sfl = new Struct_field_list(); -+ // The type here is wrong--it should be new_fntype. But we don't -+ // have new_fntype yet, and it doesn't really matter. -+ Type* vt = Type::make_pointer_type(Type::make_void_type()); -+ sfl->push_back(Struct_field(Typed_identifier("fn.0", vt, loc))); -+ sfl->push_back(Struct_field(Typed_identifier("val.1", -+ orig_fntype->receiver()->type(), -+ loc))); -+ Type* closure_type = Type::make_struct_type(sfl, loc); -+ closure_type = Type::make_pointer_type(closure_type); -+ -+ Function_type* new_fntype = orig_fntype->copy_with_closure(closure_type); -+ -+ Named_object* new_no = gogo->start_function(Gogo::thunk_name(), new_fntype, -+ false, loc); -+ -+ gogo->start_block(loc); -+ -+ Named_object* cp = gogo->lookup("closure.0", NULL); -+ go_assert(cp != NULL -+ && cp->is_variable() -+ && cp->var_value()->is_parameter()); -+ -+ // Field 0 of the closure is the function code pointer, field 1 is -+ // the value on which to invoke the method. -+ Expression* arg = Expression::make_var_reference(cp, loc); -+ arg = Expression::make_unary(OPERATOR_MULT, arg, loc); -+ arg = Expression::make_field_reference(arg, 1, loc); -+ -+ Expression* bme = Expression::make_bound_method(arg, method, fn, loc); -+ -+ const Typed_identifier_list* orig_params = orig_fntype->parameters(); -+ Expression_list* args; -+ if (orig_params == NULL || orig_params->empty()) -+ args = NULL; -+ else -+ { -+ const Typed_identifier_list* new_params = new_fntype->parameters(); -+ args = new Expression_list(); -+ for (Typed_identifier_list::const_iterator p = new_params->begin(); -+ p + 1 != new_params->end(); -+ ++p) -+ { -+ Named_object* p_no = gogo->lookup(p->name(), NULL); -+ go_assert(p_no != NULL -+ && p_no->is_variable() -+ && p_no->var_value()->is_parameter()); -+ args->push_back(Expression::make_var_reference(p_no, loc)); -+ } -+ } -+ -+ Call_expression* call = Expression::make_call(bme, args, -+ orig_fntype->is_varargs(), -+ loc); -+ call->set_varargs_are_lowered(); -+ -+ Statement* s = Statement::make_return_from_call(call, loc); -+ gogo->add_statement(s); -+ Block* b = gogo->finish_block(loc); -+ gogo->add_block(b, loc); -+ gogo->lower_block(new_no, b); -+ gogo->finish_function(loc); -+ -+ ins.first->second = new_no; -+ return new_no; - } - --// Get the tree for a method expression. There is no standard tree --// representation for this. The only places it may currently be used --// are in a Call_expression or a Go_statement, which will take it --// apart directly. So this has nothing to do at present. -+// Return an expression to check *REF for nil while dereferencing -+// according to FIELD_INDEXES. Update *REF to build up the field -+// reference. This is a static function so that we don't have to -+// worry about declaring Field_indexes in expressions.h. - -+static Expression* -+bme_check_nil(const Method::Field_indexes* field_indexes, Location loc, -+ Expression** ref) -+{ -+ if (field_indexes == NULL) -+ return Expression::make_boolean(false, loc); -+ Expression* cond = bme_check_nil(field_indexes->next, loc, ref); -+ Struct_type* stype = (*ref)->type()->deref()->struct_type(); -+ go_assert(stype != NULL -+ && field_indexes->field_index < stype->field_count()); -+ if ((*ref)->type()->struct_type() == NULL) -+ { -+ go_assert((*ref)->type()->points_to() != NULL); -+ Expression* n = Expression::make_binary(OPERATOR_EQEQ, *ref, -+ Expression::make_nil(loc), -+ loc); -+ cond = Expression::make_binary(OPERATOR_OROR, cond, n, loc); -+ *ref = Expression::make_unary(OPERATOR_MULT, *ref, loc); -+ go_assert((*ref)->type()->struct_type() == stype); -+ } -+ *ref = Expression::make_field_reference(*ref, field_indexes->field_index, -+ loc); -+ return cond; -+} -+ -+// Get the tree for a method value. -+ - tree --Bound_method_expression::do_get_tree(Translate_context*) -+Bound_method_expression::do_get_tree(Translate_context* context) - { -- error_at(this->location(), "reference to method other than calling it"); -- return error_mark_node; -+ Named_object* thunk = Bound_method_expression::create_thunk(context->gogo(), -+ this->method_, -+ this->function_); -+ if (thunk->is_erroneous()) -+ { -+ go_assert(saw_errors()); -+ return error_mark_node; -+ } -+ -+ // FIXME: We should lower this earlier, but we can't lower it in the -+ // lowering pass because at that point we don't know whether we need -+ // to create the thunk or not. If the expression is called, we -+ // don't need the thunk. -+ -+ Location loc = this->location(); -+ -+ // If the method expects a value, and we have a pointer, we need to -+ // dereference the pointer. -+ -+ Named_object* fn = this->method_->named_object(); -+ Function_type* fntype; -+ if (fn->is_function()) -+ fntype = fn->func_value()->type(); -+ else if (fn->is_function_declaration()) -+ fntype = fn->func_declaration_value()->type(); -+ else -+ go_unreachable(); -+ -+ Expression* val = this->expr_; -+ if (fntype->receiver()->type()->points_to() == NULL -+ && val->type()->points_to() != NULL) -+ val = Expression::make_unary(OPERATOR_MULT, val, loc); -+ -+ // Note that we are ignoring this->expr_type_ here. The thunk will -+ // expect a closure whose second field has type this->expr_type_ (if -+ // that is not NULL). We are going to pass it a closure whose -+ // second field has type this->expr_->type(). Since -+ // this->expr_type_ is only not-NULL for pointer types, we can get -+ // away with this. -+ -+ Struct_field_list* fields = new Struct_field_list(); -+ fields->push_back(Struct_field(Typed_identifier("fn.0", -+ thunk->func_value()->type(), -+ loc))); -+ fields->push_back(Struct_field(Typed_identifier("val.1", val->type(), loc))); -+ Struct_type* st = Type::make_struct_type(fields, loc); -+ -+ Expression_list* vals = new Expression_list(); -+ vals->push_back(Expression::make_func_code_reference(thunk, loc)); -+ vals->push_back(val); -+ -+ Expression* ret = Expression::make_struct_composite_literal(st, vals, loc); -+ ret = Expression::make_heap_composite(ret, loc); -+ -+ tree ret_tree = ret->get_tree(context); -+ -+ Expression* nil_check = NULL; -+ -+ // See whether the expression or any embedded pointers are nil. -+ -+ Expression* expr = this->expr_; -+ if (this->method_->field_indexes() != NULL) -+ { -+ // Note that we are evaluating this->expr_ twice, but that is OK -+ // because in the lowering pass we forced it into a temporary -+ // variable. -+ Expression* ref = expr; -+ nil_check = bme_check_nil(this->method_->field_indexes(), loc, &ref); -+ expr = ref; -+ } -+ -+ if (this->method_->is_value_method() && expr->type()->points_to() != NULL) -+ { -+ Expression* n = Expression::make_binary(OPERATOR_EQEQ, expr, -+ Expression::make_nil(loc), -+ loc); -+ if (nil_check == NULL) -+ nil_check = n; -+ else -+ nil_check = Expression::make_binary(OPERATOR_OROR, nil_check, n, loc); -+ } -+ -+ if (nil_check != NULL) -+ { -+ tree nil_check_tree = nil_check->get_tree(context); -+ tree crash = -+ context->gogo()->runtime_error(RUNTIME_ERROR_NIL_DEREFERENCE, loc); -+ if (ret_tree == error_mark_node -+ || nil_check_tree == error_mark_node -+ || crash == error_mark_node) -+ return error_mark_node; -+ -+ ret_tree = fold_build2_loc(loc.gcc_location(), COMPOUND_EXPR, -+ TREE_TYPE(ret_tree), -+ build3_loc(loc.gcc_location(), COND_EXPR, -+ void_type_node, nil_check_tree, -+ crash, NULL_TREE), -+ ret_tree); -+ } -+ -+ return ret_tree; - } - - // Dump ast representation of a bound method expression. -@@ -6508,16 +7012,16 @@ - ast_dump_context->ostream() << ")"; - } - -- ast_dump_context->ostream() << "." << this->method_->name(); -+ ast_dump_context->ostream() << "." << this->function_->name(); - } - - // Make a method expression. - - Bound_method_expression* --Expression::make_bound_method(Expression* expr, Named_object* method, -- Location location) -+Expression::make_bound_method(Expression* expr, const Method* method, -+ Named_object* function, Location location) - { -- return new Bound_method_expression(expr, method, location); -+ return new Bound_method_expression(expr, method, function, location); - } - - // Class Builtin_call_expression. This is used for a call to a -@@ -6722,6 +7226,26 @@ - return Expression::make_error(loc); - } - -+ if (this->code_ == BUILTIN_OFFSETOF) -+ { -+ Expression* arg = this->one_arg(); -+ Field_reference_expression* farg = arg->field_reference_expression(); -+ while (farg != NULL) -+ { -+ if (!farg->implicit()) -+ break; -+ // When the selector refers to an embedded field, -+ // it must not be reached through pointer indirections. -+ if (farg->expr()->deref() != farg->expr()) -+ { -+ this->report_error(_("argument of Offsetof implies indirection of an embedded field")); -+ return this; -+ } -+ // Go up until we reach the original base. -+ farg = farg->expr()->field_reference_expression(); -+ } -+ } -+ - if (this->is_constant()) - { - Numeric_constant nc; -@@ -6874,6 +7398,8 @@ - Type* uintptr_type = Type::lookup_integer_type("uintptr"); - int uintptr_bits = uintptr_type->integer_type()->bits(); - -+ Type_context int_context(Type::lookup_integer_type("int"), false); -+ - ++parg; - Expression* len_arg; - if (parg == args->end()) -@@ -6892,6 +7418,7 @@ - else - { - len_arg = *parg; -+ len_arg->determine_type(&int_context); - if (!this->check_int_value(len_arg, true)) - return Expression::make_error(this->location()); - if (len_arg->type()->integer_type() != NULL -@@ -6904,6 +7431,7 @@ - if (is_slice && parg != args->end()) - { - cap_arg = *parg; -+ cap_arg->determine_type(&int_context); - if (!this->check_int_value(cap_arg, false)) - return Expression::make_error(this->location()); - -@@ -7279,19 +7807,31 @@ - Field_reference_expression* farg = arg->field_reference_expression(); - if (farg == NULL) - return false; -- Expression* struct_expr = farg->expr(); -- Type* st = struct_expr->type(); -- if (st->struct_type() == NULL) -- return false; -- if (st->named_type() != NULL) -- st->named_type()->convert(this->gogo_); -- unsigned int offset; -- if (!st->struct_type()->backend_field_offset(this->gogo_, -- farg->field_index(), -- &offset)) -- return false; -+ unsigned int total_offset = 0; -+ while (true) -+ { -+ Expression* struct_expr = farg->expr(); -+ Type* st = struct_expr->type(); -+ if (st->struct_type() == NULL) -+ return false; -+ if (st->named_type() != NULL) -+ st->named_type()->convert(this->gogo_); -+ unsigned int offset; -+ if (!st->struct_type()->backend_field_offset(this->gogo_, -+ farg->field_index(), -+ &offset)) -+ return false; -+ total_offset += offset; -+ if (farg->implicit() && struct_expr->field_reference_expression() != NULL) -+ { -+ // Go up until we reach the original base. -+ farg = struct_expr->field_reference_expression(); -+ continue; -+ } -+ break; -+ } - nc->set_unsigned_long(Type::lookup_integer_type("uintptr"), -- static_cast(offset)); -+ static_cast(total_offset)); - return true; - } - else if (this->code_ == BUILTIN_REAL || this->code_ == BUILTIN_IMAG) -@@ -7509,6 +8049,8 @@ - case BUILTIN_REAL: - case BUILTIN_IMAG: - arg_type = Builtin_call_expression::complex_type(context->type); -+ if (arg_type == NULL) -+ arg_type = Type::lookup_complex_type("complex128"); - is_print = false; - break; - -@@ -7517,6 +8059,8 @@ - // For the complex function the type of one operand can - // determine the type of the other, as in a binary expression. - arg_type = Builtin_call_expression::real_imag_type(context->type); -+ if (arg_type == NULL) -+ arg_type = Type::lookup_float_type("float64"); - if (args != NULL && args->size() == 2) - { - Type* t1 = args->front()->type(); -@@ -8509,6 +9053,74 @@ - - // Class Call_expression. - -+// A Go function can be viewed in a couple of different ways. The -+// code of a Go function becomes a backend function with parameters -+// whose types are simply the backend representation of the Go types. -+// If there are multiple results, they are returned as a backend -+// struct. -+ -+// However, when Go code refers to a function other than simply -+// calling it, the backend type of that function is actually a struct. -+// The first field of the struct points to the Go function code -+// (sometimes a wrapper as described below). The remaining fields -+// hold addresses of closed-over variables. This struct is called a -+// closure. -+ -+// There are a few cases to consider. -+ -+// A direct function call of a known function in package scope. In -+// this case there are no closed-over variables, and we know the name -+// of the function code. We can simply produce a backend call to the -+// function directly, and not worry about the closure. -+ -+// A direct function call of a known function literal. In this case -+// we know the function code and we know the closure. We generate the -+// function code such that it expects an additional final argument of -+// the closure type. We pass the closure as the last argument, after -+// the other arguments. -+ -+// An indirect function call. In this case we have a closure. We -+// load the pointer to the function code from the first field of the -+// closure. We pass the address of the closure as the last argument. -+ -+// A call to a method of an interface. Type methods are always at -+// package scope, so we call the function directly, and don't worry -+// about the closure. -+ -+// This means that for a function at package scope we have two cases. -+// One is the direct call, which has no closure. The other is the -+// indirect call, which does have a closure. We can't simply ignore -+// the closure, even though it is the last argument, because that will -+// fail on targets where the function pops its arguments. So when -+// generating a closure for a package-scope function we set the -+// function code pointer in the closure to point to a wrapper -+// function. This wrapper function accepts a final argument that -+// points to the closure, ignores it, and calls the real function as a -+// direct function call. This wrapper will normally be efficient, and -+// can often simply be a tail call to the real function. -+ -+// We don't use GCC's static chain pointer because 1) we don't need -+// it; 2) GCC only permits using a static chain to call a known -+// function, so we can't use it for an indirect call anyhow. Since we -+// can't use it for an indirect call, we may as well not worry about -+// using it for a direct call either. -+ -+// We pass the closure last rather than first because it means that -+// the function wrapper we put into a closure for a package-scope -+// function can normally just be a tail call to the real function. -+ -+// For method expressions we generate a wrapper that loads the -+// receiver from the closure and then calls the method. This -+// unfortunately forces reshuffling the arguments, since there is a -+// new first argument, but we can't avoid reshuffling either for -+// method expressions or for indirect calls of package-scope -+// functions, and since the latter are more common we reshuffle for -+// method expressions. -+ -+// Note that the Go code retains the Go types. The extra final -+// argument only appears when we convert to the backend -+// representation. -+ - // Traversal. - - int -@@ -8624,7 +9236,7 @@ - Bound_method_expression* bme = this->fn_->bound_method_expression(); - if (bme != NULL) - { -- Named_object* method = bme->method(); -+ Named_object* methodfn = bme->function(); - Expression* first_arg = bme->first_argument(); - - // We always pass a pointer when calling a method. -@@ -8665,7 +9277,7 @@ - // old arguments, because we may be traversing them up in some - // caller. FIXME. - this->args_ = new_args; -- this->fn_ = Expression::make_func_reference(method, NULL, -+ this->fn_ = Expression::make_func_reference(methodfn, NULL, - bme->location()); - } - -@@ -9117,11 +9729,21 @@ - const bool has_closure = func != NULL && func->closure() != NULL; - const bool is_interface_method = interface_method != NULL; - -+ int closure_arg; -+ if (has_closure) -+ closure_arg = 1; -+ else if (func != NULL) -+ closure_arg = 0; -+ else if (is_interface_method) -+ closure_arg = 0; -+ else -+ closure_arg = 1; -+ - int nargs; - tree* args; - if (this->args_ == NULL || this->args_->empty()) - { -- nargs = is_interface_method ? 1 : 0; -+ nargs = (is_interface_method ? 1 : 0) + closure_arg; - args = nargs == 0 ? NULL : new tree[nargs]; - } - else if (fntype->parameters() == NULL || fntype->parameters()->empty()) -@@ -9130,7 +9752,7 @@ - go_assert(!is_interface_method - && fntype->is_method() - && this->args_->size() == 1); -- nargs = 1; -+ nargs = 1 + closure_arg; - args = new tree[nargs]; - args[0] = this->args_->front()->get_tree(context); - } -@@ -9141,6 +9763,7 @@ - nargs = this->args_->size(); - int i = is_interface_method ? 1 : 0; - nargs += i; -+ nargs += closure_arg; - args = new tree[nargs]; - - Typed_identifier_list::const_iterator pp = params->begin(); -@@ -9161,36 +9784,71 @@ - arg_val, - location); - if (args[i] == error_mark_node) -- { -- delete[] args; -- return error_mark_node; -- } -+ return error_mark_node; - } - go_assert(pp == params->end()); -- go_assert(i == nargs); -+ go_assert(i + closure_arg == nargs); - } - -- tree rettype = TREE_TYPE(TREE_TYPE(type_to_tree(fntype->get_backend(gogo)))); -+ tree fntype_tree = type_to_tree(fntype->get_backend(gogo)); -+ if (fntype_tree == error_mark_node) -+ return error_mark_node; -+ go_assert(POINTER_TYPE_P(fntype_tree)); -+ if (TREE_TYPE(fntype_tree) == error_mark_node) -+ return error_mark_node; -+ go_assert(TREE_CODE(TREE_TYPE(fntype_tree)) == RECORD_TYPE); -+ tree fnfield_type = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(fntype_tree))); -+ if (fnfield_type == error_mark_node) -+ return error_mark_node; -+ go_assert(FUNCTION_POINTER_TYPE_P(fnfield_type)); -+ tree rettype = TREE_TYPE(TREE_TYPE(fnfield_type)); - if (rettype == error_mark_node) -+ return error_mark_node; -+ -+ tree fn; -+ if (func != NULL) - { -- delete[] args; -- return error_mark_node; -+ Named_object* no = func->named_object(); -+ go_assert(!no->is_function() -+ || !no->func_value()->is_descriptor_wrapper()); -+ fn = Func_expression::get_code_pointer(gogo, no, location); -+ if (has_closure) -+ { -+ go_assert(closure_arg == 1 && nargs > 0); -+ args[nargs - 1] = func->closure()->get_tree(context); -+ } - } -- -- tree fn; -- if (has_closure) -- fn = func->get_tree_without_closure(gogo); - else if (!is_interface_method) -- fn = this->fn_->get_tree(context); -+ { -+ tree closure_tree = this->fn_->get_tree(context); -+ if (closure_tree == error_mark_node) -+ return error_mark_node; -+ tree fnc = fold_convert_loc(location.gcc_location(), fntype_tree, -+ closure_tree); -+ go_assert(POINTER_TYPE_P(TREE_TYPE(fnc)) -+ && (TREE_CODE(TREE_TYPE(TREE_TYPE(fnc))) -+ == RECORD_TYPE)); -+ tree field = TYPE_FIELDS(TREE_TYPE(TREE_TYPE(fnc))); -+ fn = fold_build3_loc(location.gcc_location(), COMPONENT_REF, -+ TREE_TYPE(field), -+ build_fold_indirect_ref_loc(location.gcc_location(), -+ fnc), -+ field, NULL_TREE); -+ go_assert(closure_arg == 1 && nargs > 0); -+ args[nargs - 1] = closure_tree; -+ } - else -- fn = this->interface_method_function(context, interface_method, &args[0]); -- -- if (fn == error_mark_node || TREE_TYPE(fn) == error_mark_node) - { -- delete[] args; -- return error_mark_node; -+ fn = this->interface_method_function(context, interface_method, -+ &args[0]); -+ if (fn == error_mark_node) -+ return error_mark_node; -+ go_assert(closure_arg == 0); - } - -+ if (fn == error_mark_node || TREE_TYPE(fn) == error_mark_node) -+ return error_mark_node; -+ - tree fndecl = fn; - if (TREE_CODE(fndecl) == ADDR_EXPR) - fndecl = TREE_OPERAND(fndecl, 0); -@@ -9198,12 +9856,7 @@ - // Add a type cast in case the type of the function is a recursive - // type which refers to itself. - if (!DECL_P(fndecl) || !DECL_IS_BUILTIN(fndecl)) -- { -- tree fnt = type_to_tree(fntype->get_backend(gogo)); -- if (fnt == error_mark_node) -- return error_mark_node; -- fn = fold_convert_loc(location.gcc_location(), fnt, fn); -- } -+ fn = fold_convert_loc(location.gcc_location(), fnfield_type, fn); - - // This is to support builtin math functions when using 80387 math. - tree excess_type = NULL_TREE; -@@ -9247,13 +9900,6 @@ - - SET_EXPR_LOCATION(ret, location.gcc_location()); - -- if (has_closure) -- { -- tree closure_tree = func->closure()->get_tree(context); -- if (closure_tree != error_mark_node) -- CALL_EXPR_STATIC_CHAIN(ret) = closure_tree; -- } -- - // If this is a recursive function type which returns itself, as in - // type F func() F - // we have used ptr_type_node for the return type. Add a cast here -@@ -9274,24 +9920,6 @@ - if (this->results_ != NULL) - ret = this->set_results(context, ret); - -- // We can't unwind the stack past a call to nil, so we need to -- // insert an explicit check so that the panic can be recovered. -- if (func == NULL) -- { -- tree compare = fold_build2_loc(location.gcc_location(), EQ_EXPR, -- boolean_type_node, fn, -- fold_convert_loc(location.gcc_location(), -- TREE_TYPE(fn), -- null_pointer_node)); -- tree crash = build3_loc(location.gcc_location(), COND_EXPR, -- void_type_node, compare, -- gogo->runtime_error(RUNTIME_ERROR_NIL_DEREFERENCE, -- location), -- NULL_TREE); -- ret = fold_build2_loc(location.gcc_location(), COMPOUND_EXPR, -- TREE_TYPE(ret), crash, ret); -- } -- - this->tree_ = ret; - - return ret; -@@ -9774,13 +10402,20 @@ - void - Array_index_expression::do_check_types(Gogo*) - { -- if (this->start_->type()->integer_type() == NULL) -+ Numeric_constant nc; -+ unsigned long v; -+ if (this->start_->type()->integer_type() == NULL -+ && !this->start_->type()->is_error() -+ && (!this->start_->numeric_constant_value(&nc) -+ || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT)) - this->report_error(_("index must be integer")); - if (this->end_ != NULL - && this->end_->type()->integer_type() == NULL - && !this->end_->type()->is_error() - && !this->end_->is_nil_expression() -- && !this->end_->is_error_expression()) -+ && !this->end_->is_error_expression() -+ && (!this->end_->numeric_constant_value(&nc) -+ || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT)) - this->report_error(_("slice end must be integer")); - - Array_type* array_type = this->array_->type()->array_type(); -@@ -10845,6 +11480,28 @@ - return Expression::traverse(&this->expr_, traverse); - } - -+// Lower the expression. If this expression is not called, we need to -+// evaluate the expression twice when converting to the backend -+// interface. So introduce a temporary variable if necessary. -+ -+Expression* -+Interface_field_reference_expression::do_lower(Gogo*, Named_object*, -+ Statement_inserter* inserter, -+ int) -+{ -+ if (this->expr_->var_expression() == NULL -+ && this->expr_->temporary_reference_expression() == NULL -+ && this->expr_->set_and_use_temporary_expression() == NULL) -+ { -+ Temporary_statement* temp = -+ Statement::make_temporary(this->expr_->type(), NULL, this->location()); -+ inserter->insert(temp); -+ this->expr_ = Expression::make_set_and_use_temporary(temp, this->expr_, -+ this->location()); -+ } -+ return this; -+} -+ - // Return the type of an interface field reference. - - Type* -@@ -10905,18 +11562,188 @@ - } - } - --// Get a tree for a reference to a field in an interface. There is no --// standard tree type representation for this: it's a function --// attached to its first argument, like a Bound_method_expression. --// The only places it may currently be used are in a Call_expression --// or a Go_statement, which will take it apart directly. So this has --// nothing to do at present. -+// If an interface field reference is not simply called, then it is -+// represented as a closure. The closure will hold a single variable, -+// the value of the interface on which the method should be called. -+// The function will be a simple thunk that pulls the value from the -+// closure and calls the method with the remaining arguments. - -+// Because method values are not common, we don't build all thunks for -+// all possible interface methods, but instead only build them as we -+// need them. In particular, we even build them on demand for -+// interface methods defined in other packages. -+ -+Interface_field_reference_expression::Interface_method_thunks -+ Interface_field_reference_expression::interface_method_thunks; -+ -+// Find or create the thunk to call method NAME on TYPE. -+ -+Named_object* -+Interface_field_reference_expression::create_thunk(Gogo* gogo, -+ Interface_type* type, -+ const std::string& name) -+{ -+ std::pair val(type, NULL); -+ std::pair ins = -+ Interface_field_reference_expression::interface_method_thunks.insert(val); -+ if (ins.second) -+ { -+ // This is the first time we have seen this interface. -+ ins.first->second = new Method_thunks(); -+ } -+ -+ for (Method_thunks::const_iterator p = ins.first->second->begin(); -+ p != ins.first->second->end(); -+ p++) -+ if (p->first == name) -+ return p->second; -+ -+ Location loc = type->location(); -+ -+ const Typed_identifier* method_id = type->find_method(name); -+ if (method_id == NULL) -+ return Named_object::make_erroneous_name(Gogo::thunk_name()); -+ -+ Function_type* orig_fntype = method_id->type()->function_type(); -+ if (orig_fntype == NULL) -+ return Named_object::make_erroneous_name(Gogo::thunk_name()); -+ -+ Struct_field_list* sfl = new Struct_field_list(); -+ // The type here is wrong--it should be new_fntype. But we don't -+ // have new_fntype yet, and it doesn't really matter. -+ Type* vt = Type::make_pointer_type(Type::make_void_type()); -+ sfl->push_back(Struct_field(Typed_identifier("fn.0", vt, loc))); -+ sfl->push_back(Struct_field(Typed_identifier("val.1", type, loc))); -+ Type* closure_type = Type::make_struct_type(sfl, loc); -+ closure_type = Type::make_pointer_type(closure_type); -+ -+ Function_type* new_fntype = orig_fntype->copy_with_closure(closure_type); -+ -+ Named_object* new_no = gogo->start_function(Gogo::thunk_name(), new_fntype, -+ false, loc); -+ -+ gogo->start_block(loc); -+ -+ Named_object* cp = gogo->lookup("closure.0", NULL); -+ go_assert(cp != NULL -+ && cp->is_variable() -+ && cp->var_value()->is_parameter()); -+ -+ // Field 0 of the closure is the function code pointer, field 1 is -+ // the value on which to invoke the method. -+ Expression* arg = Expression::make_var_reference(cp, loc); -+ arg = Expression::make_unary(OPERATOR_MULT, arg, loc); -+ arg = Expression::make_field_reference(arg, 1, loc); -+ -+ Expression *ifre = Expression::make_interface_field_reference(arg, name, -+ loc); -+ -+ const Typed_identifier_list* orig_params = orig_fntype->parameters(); -+ Expression_list* args; -+ if (orig_params == NULL || orig_params->empty()) -+ args = NULL; -+ else -+ { -+ const Typed_identifier_list* new_params = new_fntype->parameters(); -+ args = new Expression_list(); -+ for (Typed_identifier_list::const_iterator p = new_params->begin(); -+ p + 1 != new_params->end(); -+ ++p) -+ { -+ Named_object* p_no = gogo->lookup(p->name(), NULL); -+ go_assert(p_no != NULL -+ && p_no->is_variable() -+ && p_no->var_value()->is_parameter()); -+ args->push_back(Expression::make_var_reference(p_no, loc)); -+ } -+ } -+ -+ Call_expression* call = Expression::make_call(ifre, args, -+ orig_fntype->is_varargs(), -+ loc); -+ call->set_varargs_are_lowered(); -+ -+ Statement* s = Statement::make_return_from_call(call, loc); -+ gogo->add_statement(s); -+ Block* b = gogo->finish_block(loc); -+ gogo->add_block(b, loc); -+ gogo->lower_block(new_no, b); -+ gogo->finish_function(loc); -+ -+ ins.first->second->push_back(std::make_pair(name, new_no)); -+ return new_no; -+} -+ -+// Get a tree for a method value. -+ - tree --Interface_field_reference_expression::do_get_tree(Translate_context*) -+Interface_field_reference_expression::do_get_tree(Translate_context* context) - { -- error_at(this->location(), "reference to method other than calling it"); -- return error_mark_node; -+ Interface_type* type = this->expr_->type()->interface_type(); -+ if (type == NULL) -+ { -+ go_assert(saw_errors()); -+ return error_mark_node; -+ } -+ -+ Named_object* thunk = -+ Interface_field_reference_expression::create_thunk(context->gogo(), -+ type, this->name_); -+ if (thunk->is_erroneous()) -+ { -+ go_assert(saw_errors()); -+ return error_mark_node; -+ } -+ -+ // FIXME: We should lower this earlier, but we can't it lower it in -+ // the lowering pass because at that point we don't know whether we -+ // need to create the thunk or not. If the expression is called, we -+ // don't need the thunk. -+ -+ Location loc = this->location(); -+ -+ Struct_field_list* fields = new Struct_field_list(); -+ fields->push_back(Struct_field(Typed_identifier("fn.0", -+ thunk->func_value()->type(), -+ loc))); -+ fields->push_back(Struct_field(Typed_identifier("val.1", -+ this->expr_->type(), -+ loc))); -+ Struct_type* st = Type::make_struct_type(fields, loc); -+ -+ Expression_list* vals = new Expression_list(); -+ vals->push_back(Expression::make_func_code_reference(thunk, loc)); -+ vals->push_back(this->expr_); -+ -+ Expression* expr = Expression::make_struct_composite_literal(st, vals, loc); -+ expr = Expression::make_heap_composite(expr, loc); -+ -+ tree closure_tree = expr->get_tree(context); -+ -+ // Note that we are evaluating this->expr_ twice, but that is OK -+ // because in the lowering pass we forced it into a temporary -+ // variable. -+ tree expr_tree = this->expr_->get_tree(context); -+ tree nil_check_tree = Expression::comparison_tree(context, -+ Type::lookup_bool_type(), -+ OPERATOR_EQEQ, -+ this->expr_->type(), -+ expr_tree, -+ Type::make_nil_type(), -+ null_pointer_node, -+ loc); -+ tree crash = context->gogo()->runtime_error(RUNTIME_ERROR_NIL_DEREFERENCE, -+ loc); -+ if (closure_tree == error_mark_node -+ || nil_check_tree == error_mark_node -+ || crash == error_mark_node) -+ return error_mark_node; -+ return fold_build2_loc(loc.gcc_location(), COMPOUND_EXPR, -+ TREE_TYPE(closure_tree), -+ build3_loc(loc.gcc_location(), COND_EXPR, -+ void_type_node, nil_check_tree, crash, -+ NULL_TREE), -+ closure_tree); - } - - // Dump ast representation for an interface field reference. -@@ -11114,8 +11941,10 @@ - // as their first argument. If this is for a pointer type, we can - // simply reuse the existing function. We use an internal hack to - // get the right type. -- -- if (method != NULL && is_pointer) -+ // FIXME: This optimization is disabled because it doesn't yet work -+ // with function descriptors when the method expression is not -+ // directly called. -+ if (method != NULL && is_pointer && false) - { - Named_object* mno = (method->needs_stub_method() - ? method->stub_object() -@@ -11170,22 +11999,7 @@ - method_type->is_varargs(), - location); - -- size_t count = call->result_count(); -- Statement* s; -- if (count == 0) -- s = Statement::make_statement(call, true); -- else -- { -- Expression_list* retvals = new Expression_list(); -- if (count <= 1) -- retvals->push_back(call); -- else -- { -- for (size_t i = 0; i < count; ++i) -- retvals->push_back(Expression::make_call_result(call, i)); -- } -- s = Statement::make_return_statement(retvals, location); -- } -+ Statement* s = Statement::make_return_from_call(call, location); - gogo->add_statement(s); - - Block* b = gogo->finish_block(location); -Index: gcc/recog.c -=================================================================== ---- a/src/gcc/recog.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/recog.c (.../branches/gcc-4_8-branch) -@@ -1949,9 +1949,6 @@ - (strictp ? strict_memory_address_addr_space_p - : memory_address_addr_space_p); - unsigned int mode_sz = GET_MODE_SIZE (mode); --#ifdef POINTERS_EXTEND_UNSIGNED -- enum machine_mode pointer_mode = targetm.addr_space.pointer_mode (as); --#endif - - if (CONSTANT_ADDRESS_P (y)) - return 1; -@@ -1962,6 +1959,13 @@ - if (mode_dependent_address_p (y, as)) - return 0; - -+ enum machine_mode address_mode = GET_MODE (y); -+ if (address_mode == VOIDmode) -+ address_mode = targetm.addr_space.address_mode (as); -+#ifdef POINTERS_EXTEND_UNSIGNED -+ enum machine_mode pointer_mode = targetm.addr_space.pointer_mode (as); -+#endif -+ - /* ??? How much offset does an offsettable BLKmode reference need? - Clearly that depends on the situation in which it's being used. - However, the current situation in which we test 0xffffffff is -@@ -1977,7 +1981,7 @@ - int good; - - y1 = *y2; -- *y2 = plus_constant (GET_MODE (y), *y2, mode_sz - 1); -+ *y2 = plus_constant (address_mode, *y2, mode_sz - 1); - /* Use QImode because an odd displacement may be automatically invalid - for any wider mode. But it should be valid for a single byte. */ - good = (*addressp) (QImode, y, as); -@@ -1998,20 +2002,20 @@ - if (GET_CODE (y) == LO_SUM - && mode != BLKmode - && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT) -- z = gen_rtx_LO_SUM (GET_MODE (y), XEXP (y, 0), -- plus_constant (GET_MODE (y), XEXP (y, 1), -+ z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0), -+ plus_constant (address_mode, XEXP (y, 1), - mode_sz - 1)); - #ifdef POINTERS_EXTEND_UNSIGNED - /* Likewise for a ZERO_EXTEND from pointer_mode. */ - else if (POINTERS_EXTEND_UNSIGNED > 0 - && GET_CODE (y) == ZERO_EXTEND - && GET_MODE (XEXP (y, 0)) == pointer_mode) -- z = gen_rtx_ZERO_EXTEND (GET_MODE (y), -+ z = gen_rtx_ZERO_EXTEND (address_mode, - plus_constant (pointer_mode, XEXP (y, 0), - mode_sz - 1)); - #endif - else -- z = plus_constant (GET_MODE (y), y, mode_sz - 1); -+ z = plus_constant (address_mode, y, mode_sz - 1); - - /* Use QImode because an odd displacement may be automatically invalid - for any wider mode. But it should be valid for a single byte. */ -Index: gcc/ada/targparm.ads -=================================================================== ---- a/src/gcc/ada/targparm.ads (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ada/targparm.ads (.../branches/gcc-4_8-branch) -@@ -436,7 +436,7 @@ - -- the source program may not contain explicit 64-bit shifts. In addition, - -- the code generated for packed arrays will avoid the use of long shifts. - -- Support_Nondefault_SSO_On_Target : Boolean := False; -+ Support_Nondefault_SSO_On_Target : Boolean := True; - -- If True, the back end supports the non-default Scalar_Storage_Order - -- (i.e. allows non-confirming Scalar_Storage_Order attribute definition - -- clauses). -Index: gcc/ada/ChangeLog -=================================================================== ---- a/src/gcc/ada/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ada/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,20 @@ -+2013-06-13 Eric Botcazou -+ -+ * gcc-interface/ada-tree.h (DECL_BY_DOUBLE_REF_P): Delete. -+ * gcc-interface/gigi.h (annotate_object): Adjust prototype. -+ (convert_vms_descriptor): Likewise. -+ * gcc-interface/decl.c (gnat_to_gnu_param): Do not pass fat pointer -+ types by double dereference. -+ (annotate_object): Remove BY_DOUBLE_REF parameter and adjust. -+ (gnat_to_gnu_entity): Adjust calls to annotate_object. -+ * gcc-interface/trans.c (Identifier_to_gnu): Do not deal with double -+ dereference. -+ (Call_to_gnu): Likewise. -+ (build_function_stub): Adjust call to convert_vms_descriptor. -+ (Subprogram_Body_to_gnu): Adjust call to annotate_object. -+ * gcc-interface/utils.c (convert_vms_descriptor): Remove BY_REF -+ parameter and adjust. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -Index: gcc/ada/gcc-interface/utils.c -=================================================================== ---- a/src/gcc/ada/gcc-interface/utils.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ada/gcc-interface/utils.c (.../branches/gcc-4_8-branch) -@@ -4073,33 +4073,25 @@ - - /* Convert GNU_EXPR, a pointer to a VMS descriptor, to GNU_TYPE, a regular - pointer or fat pointer type. GNU_EXPR_ALT_TYPE is the alternate (32-bit) -- pointer type of GNU_EXPR. BY_REF is true if the result is to be used by -- reference. GNAT_SUBPROG is the subprogram to which the VMS descriptor is -- passed. */ -+ pointer type of GNU_EXPR. GNAT_SUBPROG is the subprogram to which the -+ descriptor is passed. */ - - tree - convert_vms_descriptor (tree gnu_type, tree gnu_expr, tree gnu_expr_alt_type, -- bool by_ref, Entity_Id gnat_subprog) -+ Entity_Id gnat_subprog) - { - tree desc_type = TREE_TYPE (TREE_TYPE (gnu_expr)); - tree desc = build1 (INDIRECT_REF, desc_type, gnu_expr); - tree mbo = TYPE_FIELDS (desc_type); - const char *mbostr = IDENTIFIER_POINTER (DECL_NAME (mbo)); - tree mbmo = DECL_CHAIN (DECL_CHAIN (DECL_CHAIN (mbo))); -- tree real_type, is64bit, gnu_expr32, gnu_expr64; -+ tree is64bit, gnu_expr32, gnu_expr64; - -- if (by_ref) -- real_type = TREE_TYPE (gnu_type); -- else -- real_type = gnu_type; -- - /* If the field name is not MBO, it must be 32-bit and no alternate. - Otherwise primary must be 64-bit and alternate 32-bit. */ - if (strcmp (mbostr, "MBO") != 0) - { -- tree ret = convert_vms_descriptor32 (real_type, gnu_expr, gnat_subprog); -- if (by_ref) -- ret = build_unary_op (ADDR_EXPR, gnu_type, ret); -+ tree ret = convert_vms_descriptor32 (gnu_type, gnu_expr, gnat_subprog); - return ret; - } - -@@ -4116,14 +4108,9 @@ - integer_minus_one_node)); - - /* Build the 2 possible end results. */ -- gnu_expr64 = convert_vms_descriptor64 (real_type, gnu_expr, gnat_subprog); -- if (by_ref) -- gnu_expr64 = build_unary_op (ADDR_EXPR, gnu_type, gnu_expr64); -+ gnu_expr64 = convert_vms_descriptor64 (gnu_type, gnu_expr, gnat_subprog); - gnu_expr = fold_convert (gnu_expr_alt_type, gnu_expr); -- gnu_expr32 = convert_vms_descriptor32 (real_type, gnu_expr, gnat_subprog); -- if (by_ref) -- gnu_expr32 = build_unary_op (ADDR_EXPR, gnu_type, gnu_expr32); -- -+ gnu_expr32 = convert_vms_descriptor32 (gnu_type, gnu_expr, gnat_subprog); - return build3 (COND_EXPR, gnu_type, is64bit, gnu_expr64, gnu_expr32); - } - -Index: gcc/ada/gcc-interface/decl.c -=================================================================== ---- a/src/gcc/ada/gcc-interface/decl.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ada/gcc-interface/decl.c (.../branches/gcc-4_8-branch) -@@ -1019,7 +1019,7 @@ - save_gnu_tree (gnat_entity, gnu_decl, true); - saved = true; - annotate_object (gnat_entity, gnu_type, NULL_TREE, -- false, false); -+ false); - /* This assertion will fail if the renamed object - isn't aligned enough as to make it possible to - honor the alignment set on the renaming. */ -@@ -1605,7 +1605,7 @@ - type of the object and not on the object directly, and makes it - possible to support all confirming representation clauses. */ - annotate_object (gnat_entity, TREE_TYPE (gnu_decl), gnu_object_size, -- used_by_ref, false); -+ used_by_ref); - } - break; - -@@ -5595,7 +5595,7 @@ - /* The parameter can be indirectly modified if its address is taken. */ - bool ro_param = in_param && !Address_Taken (gnat_param); - bool by_return = false, by_component_ptr = false; -- bool by_ref = false, by_double_ref = false; -+ bool by_ref = false; - tree gnu_param; - - /* Copy-return is used only for the first parameter of a valued procedure. -@@ -5720,19 +5720,6 @@ - gnu_param_type - = build_qualified_type (gnu_param_type, TYPE_QUAL_RESTRICT); - by_ref = true; -- -- /* In some ABIs, e.g. SPARC 32-bit, fat pointer types are themselves -- passed by reference. Pass them by explicit reference, this will -- generate more debuggable code at -O0. */ -- if (TYPE_IS_FAT_POINTER_P (gnu_param_type) -- && targetm.calls.pass_by_reference (pack_cumulative_args (NULL), -- TYPE_MODE (gnu_param_type), -- gnu_param_type, -- true)) -- { -- gnu_param_type = build_reference_type (gnu_param_type); -- by_double_ref = true; -- } - } - - /* Pass In Out or Out parameters using copy-in copy-out mechanism. */ -@@ -5775,7 +5762,6 @@ - gnu_param = create_param_decl (gnu_param_name, gnu_param_type, - ro_param || by_ref || by_component_ptr); - DECL_BY_REF_P (gnu_param) = by_ref; -- DECL_BY_DOUBLE_REF_P (gnu_param) = by_double_ref; - DECL_BY_COMPONENT_PTR_P (gnu_param) = by_component_ptr; - DECL_BY_DESCRIPTOR_P (gnu_param) = (mech == By_Descriptor || - mech == By_Short_Descriptor); -@@ -7427,18 +7413,13 @@ - /* Given GNAT_ENTITY, an object (constant, variable, parameter, exception) - and GNU_TYPE, its corresponding GCC type, set Esize and Alignment to the - size and alignment used by Gigi. Prefer SIZE over TYPE_SIZE if non-null. -- BY_REF is true if the object is used by reference and BY_DOUBLE_REF is -- true if the object is used by double reference. */ -+ BY_REF is true if the object is used by reference. */ - - void --annotate_object (Entity_Id gnat_entity, tree gnu_type, tree size, bool by_ref, -- bool by_double_ref) -+annotate_object (Entity_Id gnat_entity, tree gnu_type, tree size, bool by_ref) - { - if (by_ref) - { -- if (by_double_ref) -- gnu_type = TREE_TYPE (gnu_type); -- - if (TYPE_IS_FAT_POINTER_P (gnu_type)) - gnu_type = TYPE_UNCONSTRAINED_ARRAY (gnu_type); - else -Index: gcc/ada/gcc-interface/gigi.h -=================================================================== ---- a/src/gcc/ada/gcc-interface/gigi.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ada/gcc-interface/gigi.h (.../branches/gcc-4_8-branch) -@@ -177,10 +177,9 @@ - /* Given GNAT_ENTITY, an object (constant, variable, parameter, exception) - and GNU_TYPE, its corresponding GCC type, set Esize and Alignment to the - size and alignment used by Gigi. Prefer SIZE over TYPE_SIZE if non-null. -- BY_REF is true if the object is used by reference and BY_DOUBLE_REF is -- true if the object is used by double reference. */ -+ BY_REF is true if the object is used by reference. */ - extern void annotate_object (Entity_Id gnat_entity, tree gnu_type, tree size, -- bool by_ref, bool by_double_ref); -+ bool by_ref); - - /* Return the variant part of RECORD_TYPE, if any. Otherwise return NULL. */ - extern tree get_variant_part (tree record_type); -@@ -930,11 +929,10 @@ - - /* Convert GNU_EXPR, a pointer to a VMS descriptor, to GNU_TYPE, a regular - pointer or fat pointer type. GNU_EXPR_ALT_TYPE is the alternate (32-bit) -- pointer type of GNU_EXPR. BY_REF is true if the result is to be used by -- reference. GNAT_SUBPROG is the subprogram to which the VMS descriptor is -- passed. */ -+ pointer type of GNU_EXPR. GNAT_SUBPROG is the subprogram to which the -+ descriptor is passed. */ - extern tree convert_vms_descriptor (tree gnu_type, tree gnu_expr, -- tree gnu_expr_alt_type, bool by_ref, -+ tree gnu_expr_alt_type, - Entity_Id gnat_subprog); - - /* Indicate that we need to take the address of T and that it therefore -Index: gcc/ada/gcc-interface/ada-tree.h -=================================================================== ---- a/src/gcc/ada/gcc-interface/ada-tree.h (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ada/gcc-interface/ada-tree.h (.../branches/gcc-4_8-branch) -@@ -360,10 +360,6 @@ - constant CONSTRUCTOR. */ - #define DECL_CONST_ADDRESS_P(NODE) DECL_LANG_FLAG_0 (CONST_DECL_CHECK (NODE)) - --/* Nonzero in a PARM_DECL if it is always used by double reference, i.e. a -- pair of INDIRECT_REFs is needed to access the object. */ --#define DECL_BY_DOUBLE_REF_P(NODE) DECL_LANG_FLAG_0 (PARM_DECL_CHECK (NODE)) -- - /* Nonzero in a FIELD_DECL if it is declared as aliased. */ - #define DECL_ALIASED_P(NODE) DECL_LANG_FLAG_0 (FIELD_DECL_CHECK (NODE)) - -Index: gcc/ada/gcc-interface/trans.c -=================================================================== ---- a/src/gcc/ada/gcc-interface/trans.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ada/gcc-interface/trans.c (.../branches/gcc-4_8-branch) -@@ -1075,19 +1075,6 @@ - { - const bool read_only = DECL_POINTS_TO_READONLY_P (gnu_result); - -- /* First do the first dereference if needed. */ -- if (TREE_CODE (gnu_result) == PARM_DECL -- && DECL_BY_DOUBLE_REF_P (gnu_result)) -- { -- gnu_result = build_unary_op (INDIRECT_REF, NULL_TREE, gnu_result); -- if (TREE_CODE (gnu_result) == INDIRECT_REF) -- TREE_THIS_NOTRAP (gnu_result) = 1; -- -- /* The first reference, in case of a double reference, always points -- to read-only, see gnat_to_gnu_param for the rationale. */ -- TREE_READONLY (gnu_result) = 1; -- } -- - /* If it's a PARM_DECL to foreign convention subprogram, convert it. */ - if (TREE_CODE (gnu_result) == PARM_DECL - && DECL_BY_COMPONENT_PTR_P (gnu_result)) -@@ -3251,7 +3238,6 @@ - = convert_vms_descriptor (TREE_TYPE (gnu_subprog_param), - gnu_stub_param, - DECL_PARM_ALT_TYPE (gnu_stub_param), -- DECL_BY_DOUBLE_REF_P (gnu_subprog_param), - gnat_subprog); - } - else -@@ -3546,8 +3532,7 @@ - bool is_var_decl = (TREE_CODE (gnu_param) == VAR_DECL); - - annotate_object (gnat_param, TREE_TYPE (gnu_param), NULL_TREE, -- DECL_BY_REF_P (gnu_param), -- !is_var_decl && DECL_BY_DOUBLE_REF_P (gnu_param)); -+ DECL_BY_REF_P (gnu_param)); - - if (is_var_decl) - save_gnu_tree (gnat_param, NULL_TREE, false); -@@ -4009,12 +3994,6 @@ - /* The symmetry of the paths to the type of an entity is broken here - since arguments don't know that they will be passed by ref. */ - gnu_formal_type = TREE_TYPE (gnu_formal); -- -- if (DECL_BY_DOUBLE_REF_P (gnu_formal)) -- gnu_actual -- = build_unary_op (ADDR_EXPR, TREE_TYPE (gnu_formal_type), -- gnu_actual); -- - gnu_actual = build_unary_op (ADDR_EXPR, gnu_formal_type, gnu_actual); - } - else if (is_true_formal_parm && DECL_BY_COMPONENT_PTR_P (gnu_formal)) -Index: gcc/fortran/interface.c -=================================================================== ---- a/src/gcc/fortran/interface.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/fortran/interface.c (.../branches/gcc-4_8-branch) -@@ -1024,7 +1024,8 @@ - bool type_must_agree, char *errmsg, int err_len) - { - /* Check type and rank. */ -- if (type_must_agree && !compare_type_rank (s2, s1)) -+ if (type_must_agree && -+ (!compare_type_rank (s1, s2) || !compare_type_rank (s2, s1))) - { - snprintf (errmsg, err_len, "Type/rank mismatch in argument '%s'", - s1->name); -Index: gcc/fortran/ChangeLog -=================================================================== ---- a/src/gcc/fortran/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/fortran/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,30 @@ -+2013-07-08 Tobias Burnus -+ -+ PR fortran/57785 -+ * simplify.c (compute_dot_product): Complex conjugate for -+ dot_product. -+ (gfc_simplify_dot_product, gfc_simplify_matmul): Update call. -+ -+2013-06-11 Tobias Burnus -+ -+ PR fortran/57508 -+ * resolve.c (get_temp_from_expr): Don't copy function -+ result attributes to temporary. -+ -+2013-06-04 Tobias Burnus -+ -+ Backport from mainline -+ 2013-05-22 Tobias Burnus -+ -+ PR fortran/57364 -+ * resolve.c (get_temp_from_expr): Commit created sym. -+ -+2013-05-31 Janus Weil -+ Tobias Burnus -+ -+ PR fortran/57217 -+ * interface.c (check_dummy_characteristics): Symmetrize type check. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -Index: gcc/fortran/resolve.c -=================================================================== ---- a/src/gcc/fortran/resolve.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/fortran/resolve.c (.../branches/gcc-4_8-branch) -@@ -9746,6 +9746,10 @@ - - /* Add the attributes and the arrayspec to the temporary. */ - tmp->n.sym->attr = gfc_expr_attr (e); -+ tmp->n.sym->attr.function = 0; -+ tmp->n.sym->attr.result = 0; -+ tmp->n.sym->attr.flavor = FL_VARIABLE; -+ - if (as) - { - tmp->n.sym->as = gfc_copy_array_spec (as); -@@ -9759,6 +9763,7 @@ - - gfc_set_sym_referenced (tmp->n.sym); - gfc_add_flavor (&tmp->n.sym->attr, FL_VARIABLE, name, NULL); -+ gfc_commit_symbol (tmp->n.sym); - e = gfc_lval_expr_from_sym (tmp->n.sym); - - /* Should the lhs be a section, use its array ref for the -Index: gcc/fortran/simplify.c -=================================================================== ---- a/src/gcc/fortran/simplify.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/fortran/simplify.c (.../branches/gcc-4_8-branch) -@@ -332,13 +332,15 @@ - } - - --/* Helper function for gfc_simplify_dot_product() and gfc_simplify_matmul. */ -+/* Helper function for gfc_simplify_dot_product() and gfc_simplify_matmul; -+ if conj_a is true, the matrix_a is complex conjugated. */ - - static gfc_expr * - compute_dot_product (gfc_expr *matrix_a, int stride_a, int offset_a, -- gfc_expr *matrix_b, int stride_b, int offset_b) -+ gfc_expr *matrix_b, int stride_b, int offset_b, -+ bool conj_a) - { -- gfc_expr *result, *a, *b; -+ gfc_expr *result, *a, *b, *c; - - result = gfc_get_constant_expr (matrix_a->ts.type, matrix_a->ts.kind, - &matrix_a->where); -@@ -361,9 +363,11 @@ - case BT_INTEGER: - case BT_REAL: - case BT_COMPLEX: -- result = gfc_add (result, -- gfc_multiply (gfc_copy_expr (a), -- gfc_copy_expr (b))); -+ if (conj_a && a->ts.type == BT_COMPLEX) -+ c = gfc_simplify_conjg (a); -+ else -+ c = gfc_copy_expr (a); -+ result = gfc_add (result, gfc_multiply (c, gfc_copy_expr (b))); - break; - - default: -@@ -1881,7 +1885,7 @@ - gcc_assert (vector_b->rank == 1); - gcc_assert (gfc_compare_types (&vector_a->ts, &vector_b->ts)); - -- return compute_dot_product (vector_a, 1, 0, vector_b, 1, 0); -+ return compute_dot_product (vector_a, 1, 0, vector_b, 1, 0, true); - } - - -@@ -3894,7 +3898,7 @@ - for (row = 0; row < result_rows; ++row) - { - gfc_expr *e = compute_dot_product (matrix_a, stride_a, offset_a, -- matrix_b, 1, offset_b); -+ matrix_b, 1, offset_b, false); - gfc_constructor_append_expr (&result->value.constructor, - e, NULL); - -Index: gcc/configure.ac -=================================================================== ---- a/src/gcc/configure.ac (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/configure.ac (.../branches/gcc-4_8-branch) -@@ -3044,35 +3044,9 @@ - tls_first_major=0 - tls_first_minor=0 - ;; -- powerpc-*-*) -+ powerpc64*-*-*) - conftest_s=' - .section ".tdata","awT",@progbits -- .align 2 --ld0: .space 4 --ld1: .space 4 --x1: .space 4 --x2: .space 4 --x3: .space 4 -- .text -- addi 3,31,ld0@got@tlsgd -- bl __tls_get_addr -- addi 3,31,x1@got@tlsld -- bl __tls_get_addr -- addi 9,3,x1@dtprel -- addis 9,3,x2@dtprel@ha -- addi 9,9,x2@dtprel@l -- lwz 9,x3@got@tprel(31) -- add 9,9,x@tls -- addi 9,2,x1@tprel -- addis 9,2,x2@tprel@ha -- addi 9,9,x2@tprel@l' -- tls_first_major=2 -- tls_first_minor=14 -- tls_as_opt="-a32 --fatal-warnings" -- ;; -- powerpc64-*-*) -- conftest_s=' -- .section ".tdata","awT",@progbits - .align 3 - ld0: .space 8 - ld1: .space 8 -@@ -3104,6 +3078,32 @@ - tls_first_minor=14 - tls_as_opt="-a64 --fatal-warnings" - ;; -+ powerpc*-*-*) -+ conftest_s=' -+ .section ".tdata","awT",@progbits -+ .align 2 -+ld0: .space 4 -+ld1: .space 4 -+x1: .space 4 -+x2: .space 4 -+x3: .space 4 -+ .text -+ addi 3,31,ld0@got@tlsgd -+ bl __tls_get_addr -+ addi 3,31,x1@got@tlsld -+ bl __tls_get_addr -+ addi 9,3,x1@dtprel -+ addis 9,3,x2@dtprel@ha -+ addi 9,9,x2@dtprel@l -+ lwz 9,x3@got@tprel(31) -+ add 9,9,x@tls -+ addi 9,2,x1@tprel -+ addis 9,2,x2@tprel@ha -+ addi 9,9,x2@tprel@l' -+ tls_first_major=2 -+ tls_first_minor=14 -+ tls_as_opt="-a32 --fatal-warnings" -+ ;; - s390-*-*) - conftest_s=' - .section ".tdata","awT",@progbits -@@ -4507,6 +4507,9 @@ - case "$target:$tm_file" in - powerpc64-*-freebsd* | powerpc64*-*-linux* | powerpc*-*-linux*rs6000/biarch64.h*) - case "$target" in -+ *le-*-linux*) -+ emul_name="-melf64lppc" -+ ;; - *-*-linux*) - emul_name="-melf64ppc" - ;; -@@ -4611,7 +4614,7 @@ - ]) - if test x"$gcc_cv_ld_large_toc" = xyes; then - AC_DEFINE(HAVE_LD_LARGE_TOC, 1, -- [Define if your AIX linker supports a large TOC.]) -+ [Define if your PowerPC64 linker supports a large TOC.]) - fi - ;; - esac -Index: gcc/gcc-ar.c -=================================================================== ---- a/src/gcc/gcc-ar.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/gcc-ar.c (.../branches/gcc-4_8-branch) -@@ -136,7 +136,7 @@ - setup_prefixes (av[0]); - - /* Find the GCC LTO plugin */ -- plugin = find_a_file (&target_path, LTOPLUGINSONAME); -+ plugin = find_a_file (&target_path, LTOPLUGINSONAME, R_OK); - if (!plugin) - { - fprintf (stderr, "%s: Cannot find plugin '%s'\n", av[0], LTOPLUGINSONAME); -@@ -144,24 +144,20 @@ - } - - /* Find the wrapped binutils program. */ -- exe_name = find_a_file (&target_path, PERSONALITY); -+ exe_name = find_a_file (&target_path, PERSONALITY, X_OK); - if (!exe_name) - { -+ const char *real_exe_name = PERSONALITY; - #ifdef CROSS_DIRECTORY_STRUCTURE -- const char *cross_exe_name; -- -- cross_exe_name = concat (target_machine, "-", PERSONALITY, NULL); -- exe_name = find_a_file (&path, cross_exe_name); -+ real_exe_name = concat (target_machine, "-", PERSONALITY, NULL); -+#endif -+ exe_name = find_a_file (&path, real_exe_name, X_OK); - if (!exe_name) - { - fprintf (stderr, "%s: Cannot find binary '%s'\n", av[0], -- cross_exe_name); -+ real_exe_name); - exit (1); - } --#else -- fprintf (stderr, "%s: Cannot find binary '%s'\n", av[0], PERSONALITY); -- exit (1); --#endif - } - - /* Create new command line with plugin */ -Index: gcc/simplify-rtx.c -=================================================================== ---- a/src/gcc/simplify-rtx.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/simplify-rtx.c (.../branches/gcc-4_8-branch) -@@ -2784,6 +2784,7 @@ - HOST_WIDE_INT mask = INTVAL (trueop1) << count; - - if (mask >> count == INTVAL (trueop1) -+ && trunc_int_for_mode (mask, mode) == mask - && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) - return simplify_gen_binary (ASHIFTRT, mode, - plus_constant (mode, XEXP (op0, 0), -Index: gcc/ipa-prop.c -=================================================================== ---- a/src/gcc/ipa-prop.c (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/ipa-prop.c (.../branches/gcc-4_8-branch) -@@ -678,13 +678,19 @@ - bool modified = false; - ao_ref refd; - -- gcc_checking_assert (gimple_vuse (stmt)); - if (parm_ainfo && parm_ainfo->ref_modified) - return false; - -- ao_ref_init (&refd, ref); -- walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified, -- NULL); -+ if (optimize) -+ { -+ gcc_checking_assert (gimple_vuse (stmt)); -+ ao_ref_init (&refd, ref); -+ walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified, -+ NULL); -+ } -+ else -+ modified = true; -+ - if (parm_ainfo && modified) - parm_ainfo->ref_modified = true; - return !modified; -Index: gcc/po/ChangeLog -=================================================================== ---- a/src/gcc/po/ChangeLog (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/po/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,15 @@ -+2013-07-11 Joseph Myers -+ -+ * fi.po: Update. -+ -+2013-07-02 Joseph Myers -+ -+ * ru.po: Update. -+ -+2013-06-25 Joseph Myers -+ -+ * zh_TW.po: Update. -+ - 2013-05-31 Release Manager - - * GCC 4.8.1 released. -Index: gcc/po/ru.po -=================================================================== ---- a/src/gcc/po/ru.po (.../tags/gcc_4_8_1_release) -+++ b/src/gcc/po/ru.po (.../branches/gcc-4_8-branch) -@@ -6,13 +6,13 @@ - # Nickolay V. Shmyrev , 2008. - # Pavel Maryanov , 2006, 2008. - # Yuri Kozlov , 2011. --# Pavel Maryanov , 2012. -+# Pavel Maryanov , 2012, 2013. - msgid "" - msgstr "" --"Project-Id-Version: gcc 4.7.1\n" -+"Project-Id-Version: gcc 4.8.0\n" - "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n" --"POT-Creation-Date: 2013-02-24 01:09+0000\n" --"PO-Revision-Date: 2012-07-01 16:16+0200\n" -+"POT-Creation-Date: 2013-03-15 17:42+0000\n" -+"PO-Revision-Date: 2013-07-02 16:00+0200\n" - "Last-Translator: Pavel Maryanov \n" - "Language-Team: Russian \n" - "Language: ru\n" -@@ -20,20 +20,21 @@ - "Content-Type: text/plain; charset=UTF-8\n" - "Content-Transfer-Encoding: 8bit\n" - "Plural-Forms: nplurals=3; plural=(n%10==1 && n%100!=11 ? 0 : n%10>=2 && n%10<=4 && (n%100<10 || n%100>=20) ? 1 : 2);\n" -+"X-Generator: Poedit 1.5.5\n" - --#: cfgrtl.c:2320 -+#: cfgrtl.c:2318 - msgid "flow control insn inside a basic block" - msgstr "инструкция (insn) управления потоком выполнения внутри базового блока" - --#: cfgrtl.c:2448 -+#: cfgrtl.c:2446 - msgid "wrong insn in the fallthru edge" - msgstr "некорректная insn в сквозной дуге" - --#: cfgrtl.c:2502 -+#: cfgrtl.c:2500 - msgid "insn outside basic block" - msgstr "insn вне базового блока" - --#: cfgrtl.c:2509 -+#: cfgrtl.c:2507 - msgid "return not followed by barrier" - msgstr "отсутствует барьер после return" - -@@ -121,10 +122,6 @@ - - #: diagnostic.c:442 - #, fuzzy, c-format --#| msgid "" --#| "Please submit a full bug report,\n" --#| "with preprocessed source if appropriate.\n" --#| "See %s for instructions.\n" - msgid "" - "Please submit a full bug report,\n" - "with preprocessed source if appropriate.\n" -@@ -135,7 +132,6 @@ - - #: diagnostic.c:448 - #, fuzzy, c-format --#| msgid "Use fp double instructions" - msgid "See %s for instructions.\n" - msgstr "Использовать инструкции двойной точности плавающих вычислений" - -@@ -149,7 +145,7 @@ - msgid "%s:%d: confused by earlier errors, bailing out\n" - msgstr "%s:%d: невозможно восстановление после предыдущих ошибок\n" - --#: diagnostic.c:1126 -+#: diagnostic.c:1129 - #, c-format - msgid "Internal compiler error: Error reporting routines re-entered.\n" - msgstr "Внутренняя ошибка компилятора: повторный вход в программу диагностики\n" -@@ -212,12 +208,12 @@ - msgid "invalid expression as operand" - msgstr "в списке операндов задано некорректное выражение" - --#: gcc.c:1402 -+#: gcc.c:1403 - #, c-format - msgid "Using built-in specs.\n" - msgstr "Используются внутренние спецификации.\n" - --#: gcc.c:1599 -+#: gcc.c:1600 - #, c-format - msgid "" - "Setting spec %s to '%s'\n" -@@ -226,22 +222,22 @@ - "Спецификация %s установлена в '%s'\n" - "\n" - --#: gcc.c:1708 -+#: gcc.c:1709 - #, c-format - msgid "Reading specs from %s\n" - msgstr "Спецификации прочитаны из %s\n" - --#: gcc.c:1833 -+#: gcc.c:1834 - #, c-format - msgid "could not find specs file %s\n" - msgstr "не найден файл спецификаций %s\n" - --#: gcc.c:1902 -+#: gcc.c:1903 - #, c-format - msgid "rename spec %s to %s\n" - msgstr "переименование спецификации %s в %s\n" - --#: gcc.c:1904 -+#: gcc.c:1905 - #, c-format - msgid "" - "spec is '%s'\n" -@@ -250,12 +246,12 @@ - "спецификация '%s'\n" - "\n" - --#: gcc.c:2337 -+#: gcc.c:2338 - #, c-format - msgid "%s\n" - msgstr "%s\n" - --#: gcc.c:2704 -+#: gcc.c:2705 - #, c-format - msgid "" - "\n" -@@ -265,82 +261,79 @@ - "\n" - "Продолжать? (y - да, n - нет) " - --#: gcc.c:2844 -+#: gcc.c:2845 - #, c-format - msgid "# %s %.2f %.2f\n" - msgstr "# %s %.2f %.2f\n" - --#: gcc.c:3047 -+#: gcc.c:3048 - #, c-format - msgid "Usage: %s [options] file...\n" - msgstr "Синтаксис: %s [ключи] файл...\n" - --#: gcc.c:3048 -+#: gcc.c:3049 - msgid "Options:\n" - msgstr "Ключи:\n" - --#: gcc.c:3050 -+#: gcc.c:3051 - msgid " -pass-exit-codes Exit with highest error code from a phase\n" - msgstr " -pass-exit-codes Выход с максимальным кодом возврата от прохода\n" - --#: gcc.c:3051 -+#: gcc.c:3052 - msgid " --help Display this information\n" - msgstr " --help Вывести этот текст\n" - --#: gcc.c:3052 -+#: gcc.c:3053 - msgid " --target-help Display target specific command line options\n" - msgstr " --target-help Показать специфические ключи целевой платформы\n" - --#: gcc.c:3053 -+#: gcc.c:3054 - #, fuzzy - msgid " --help={common|optimizers|params|target|warnings|[^]{joined|separate|undocumented}}[,...]\n" - msgstr " --help={target|optimizers|warnings|params|[^]{joined|separate|undocumented}}[,...]\n" - --#: gcc.c:3054 -+#: gcc.c:3055 - msgid " Display specific types of command line options\n" - msgstr " Показать специфические ключи командной строки\n" - --#: gcc.c:3056 -+#: gcc.c:3057 - msgid " (Use '-v --help' to display command line options of sub-processes)\n" - msgstr " (Задайте '-v --help' для вывода ключей всех проходов компиляции)\n" - --#: gcc.c:3057 -+#: gcc.c:3058 - msgid " --version Display compiler version information\n" - msgstr " --version Показать информацию о версии компилятора\n" - --#: gcc.c:3058 -+#: gcc.c:3059 - msgid " -dumpspecs Display all of the built in spec strings\n" - msgstr " -dumpspecs Показать встроенные спецификации\n" - --#: gcc.c:3059 -+#: gcc.c:3060 - msgid " -dumpversion Display the version of the compiler\n" - msgstr " -dumpversion Показать версию компилятора\n" - --#: gcc.c:3060 -+#: gcc.c:3061 - msgid " -dumpmachine Display the compiler's target processor\n" - msgstr " -dumpmachine Показать имя целевой платформы\n" - --#: gcc.c:3061 -+#: gcc.c:3062 - msgid " -print-search-dirs Display the directories in the compiler's search path\n" - msgstr " -print-search-dirs Показать каталоги поиска\n" - --#: gcc.c:3062 -+#: gcc.c:3063 - msgid " -print-libgcc-file-name Display the name of the compiler's companion library\n" - msgstr " -print-libgcc-file-name Показать имя run-time библиотеки компилятора\n" - --#: gcc.c:3063 -+#: gcc.c:3064 - msgid " -print-file-name= Display the full path to library \n" - msgstr " -print-file-name=<биб> Показать полное маршрутное имя библиотеки <биб>\n" - --#: gcc.c:3064 -+#: gcc.c:3065 - msgid " -print-prog-name= Display the full path to compiler component \n" - msgstr " -print-prog-name=<прог> Показать полное имя компоненты компилятора <прог>\n" - --#: gcc.c:3065 -+#: gcc.c:3066 - #, fuzzy --#| msgid "" --#| " -print-multi-lib Display the mapping between command line options and\n" --#| " multiple library search directories\n" - msgid "" - " -print-multiarch Display the target's normalized GNU triplet, used as\n" - " a component in the library path\n" -@@ -348,11 +341,11 @@ - " -print-multi-lib Показать соответствие между ключами и каталогами\n" - " поиска библиотек\n" - --#: gcc.c:3068 -+#: gcc.c:3069 - msgid " -print-multi-directory Display the root directory for versions of libgcc\n" - msgstr " -print-multi-directory Показать корневой каталог с версиями libgcc\n" - --#: gcc.c:3069 -+#: gcc.c:3070 - msgid "" - " -print-multi-lib Display the mapping between command line options and\n" - " multiple library search directories\n" -@@ -360,51 +353,51 @@ - " -print-multi-lib Показать соответствие между ключами и каталогами\n" - " поиска библиотек\n" - --#: gcc.c:3072 -+#: gcc.c:3073 - msgid " -print-multi-os-directory Display the relative path to OS libraries\n" - msgstr " -print-multi-os-directory Показать относительный маршрут к библиотекам операционной системы\n" - --#: gcc.c:3073 -+#: gcc.c:3074 - msgid " -print-sysroot Display the target libraries directory\n" - msgstr " -print-sysroot Показать каталог библиотек цели\n" - --#: gcc.c:3074 -+#: gcc.c:3075 - msgid " -print-sysroot-headers-suffix Display the sysroot suffix used to find headers\n" - msgstr " -print-sysroot-headers-suffix Вывести суффикс sysroot, используемый для поиска заголовочных файлов\n" - --#: gcc.c:3075 -+#: gcc.c:3076 - msgid " -Wa, Pass comma-separated on to the assembler\n" - msgstr " -Wa,<ключи> Передать <ключи>, разделённые запятыми, ассемблеру\n" - --#: gcc.c:3076 -+#: gcc.c:3077 - msgid " -Wp, Pass comma-separated on to the preprocessor\n" - msgstr " -Wp,<ключи> Передать <ключи>, разделённые запятыми, препроцессору\n" - --#: gcc.c:3077 -+#: gcc.c:3078 - msgid " -Wl, Pass comma-separated on to the linker\n" - msgstr " -Wl,<ключи> Передать <ключи>, разделённые запятыми, компоновщику\n" - --#: gcc.c:3078 -+#: gcc.c:3079 - msgid " -Xassembler Pass on to the assembler\n" - msgstr " -Xassembler <арг> Передать <арг> ассемблеру\n" - --#: gcc.c:3079 -+#: gcc.c:3080 - msgid " -Xpreprocessor Pass on to the preprocessor\n" - msgstr " -Xpreprocessor <арг> Передать <арг> препроцессору\n" - --#: gcc.c:3080 -+#: gcc.c:3081 - msgid " -Xlinker Pass on to the linker\n" - msgstr " -Xlinker <арг> Передать <арг> компоновщику\n" - --#: gcc.c:3081 -+#: gcc.c:3082 - msgid " -save-temps Do not delete intermediate files\n" - msgstr " -save-temps Не удалять промежуточные файлы\n" - --#: gcc.c:3082 -+#: gcc.c:3083 - msgid " -save-temps= Do not delete intermediate files\n" - msgstr " -save-temps= Не удалять промежуточные файлы\n" - --#: gcc.c:3083 -+#: gcc.c:3084 - msgid "" - " -no-canonical-prefixes Do not canonicalize paths when building relative\n" - " prefixes to other gcc components\n" -@@ -412,25 +405,25 @@ - " -no-canonical-prefixes Не канонизировать пути при сборке относительных\n" - " префиксов к другим компонентам gcc\n" - --#: gcc.c:3086 -+#: gcc.c:3087 - msgid " -pipe Use pipes rather than intermediate files\n" - msgstr " -pipe Передавать промежуточные данные по конвейеру\n" - --#: gcc.c:3087 -+#: gcc.c:3088 - msgid " -time Time the execution of each subprocess\n" - msgstr " -time Включить хронометраж проходов\n" - --#: gcc.c:3088 -+#: gcc.c:3089 - msgid " -specs= Override built-in specs with the contents of \n" - msgstr "" - " -specs=<файл> Использовать <файл> спецификаций вместо \n" - " внутренних спецификаций компилятора\n" - --#: gcc.c:3089 -+#: gcc.c:3090 - msgid " -std= Assume that the input sources are for \n" - msgstr " -std=<стандарт> Считать, что исходный код следует <стандарту>\n" - --#: gcc.c:3090 -+#: gcc.c:3091 - msgid "" - " --sysroot= Use as the root directory for headers\n" - " and libraries\n" -@@ -438,47 +431,47 @@ - " --sysroot=<каталог> Использовать <каталог> как головной каталог для заголовков\n" - " и библиотек\n" - --#: gcc.c:3093 -+#: gcc.c:3094 - msgid " -B Add to the compiler's search paths\n" - msgstr "" - " -B <каталог> добавить <каталог> к списку поиска программ \n" - " компилятора\n" - --#: gcc.c:3094 -+#: gcc.c:3095 - msgid " -v Display the programs invoked by the compiler\n" - msgstr " -v Отображать команды, запускаемые компилятором\n" - --#: gcc.c:3095 -+#: gcc.c:3096 - msgid " -### Like -v but options quoted and commands not executed\n" - msgstr " -### Как -v, но параметры берутся в кавычки и команды не запускаются\n" - --#: gcc.c:3096 -+#: gcc.c:3097 - msgid " -E Preprocess only; do not compile, assemble or link\n" - msgstr " -E Только препроцессирование - без компиляции, ассемблирования, компоновки\n" - --#: gcc.c:3097 -+#: gcc.c:3098 - msgid " -S Compile only; do not assemble or link\n" - msgstr " -S Только компиляция - без ассемблирования и компоновки\n" - --#: gcc.c:3098 -+#: gcc.c:3099 - msgid " -c Compile and assemble, but do not link\n" - msgstr " -c Компиляция и ассемблирование, без компоновки\n" - --#: gcc.c:3099 -+#: gcc.c:3100 - msgid " -o Place the output into \n" - msgstr " -o <файл> Записать результат в <файл>\n" - --#: gcc.c:3100 -+#: gcc.c:3101 - #, fuzzy - msgid " -pie Create a position independent executable\n" - msgstr "Генерировать позиционно-независимый код для выполняемых модулей, если возможно (режим large)" - --#: gcc.c:3101 -+#: gcc.c:3102 - #, fuzzy - msgid " -shared Create a shared library\n" - msgstr " --javap\t\t Вывести результат в формате 'javap'\n" - --#: gcc.c:3102 -+#: gcc.c:3103 - msgid "" - " -x Specify the language of the following input files\n" - " Permissible languages include: c c++ assembler none\n" -@@ -490,7 +483,7 @@ - " 'none' означает, что далее язык нужно\n" - " определять по расширению имени файла\n" - --#: gcc.c:3109 -+#: gcc.c:3110 - #, c-format - msgid "" - "\n" -@@ -502,27 +495,27 @@ - "Ключи, начинающиеся с -g, -f, -m, -O, -W, или --param автоматически\n" - "передаются процессам, запускаемым %s. Для передачи ключей этим процессам, используйте ключи -W<буква>.\n" - --#: gcc.c:5364 -+#: gcc.c:5365 - #, fuzzy, c-format - msgid "Processing spec (%s), which is '%s'\n" - msgstr "Обработка спецификации %c%s%c, т.е. '%s'\n" - --#: gcc.c:6649 -+#: gcc.c:6651 - #, c-format - msgid "install: %s%s\n" - msgstr "установка: %s%s\n" - --#: gcc.c:6652 -+#: gcc.c:6654 - #, c-format - msgid "programs: %s\n" - msgstr "программы: %s\n" - --#: gcc.c:6654 -+#: gcc.c:6656 - #, c-format - msgid "libraries: %s\n" - msgstr "библиотеки: %s\n" - --#: gcc.c:6738 -+#: gcc.c:6740 - #, c-format - msgid "" - "\n" -@@ -531,16 +524,16 @@ - "\n" - "Инструкции по составлению и отправке отчётов об ошибках см. на:\n" - --#: gcc.c:6754 -+#: gcc.c:6756 - #, c-format - msgid "%s %s%s\n" - msgstr "%s %s%s\n" - --#: gcc.c:6757 gcov.c:491 fortran/gfortranspec.c:303 java/jcf-dump.c:1230 -+#: gcc.c:6759 gcov.c:491 fortran/gfortranspec.c:303 java/jcf-dump.c:1230 - msgid "(C)" - msgstr "(C)" - --#: gcc.c:6758 java/jcf-dump.c:1231 -+#: gcc.c:6760 java/jcf-dump.c:1231 - #, c-format - msgid "" - "This is free software; see the source for copying conditions. There is NO\n" -@@ -552,32 +545,32 @@ - "коммерческую ценность и применимость для каких-либо целей.\n" - "\n" - --#: gcc.c:6775 -+#: gcc.c:6777 - #, c-format - msgid "Target: %s\n" - msgstr "Целевая архитектура: %s\n" - --#: gcc.c:6776 -+#: gcc.c:6778 - #, c-format - msgid "Configured with: %s\n" - msgstr "Параметры конфигурации: %s\n" - --#: gcc.c:6790 -+#: gcc.c:6792 - #, c-format - msgid "Thread model: %s\n" - msgstr "Модель многопоточности: %s\n" - --#: gcc.c:6801 -+#: gcc.c:6803 - #, c-format - msgid "gcc version %s %s\n" - msgstr "gcc версия %s %s\n" - --#: gcc.c:6804 -+#: gcc.c:6806 - #, c-format - msgid "gcc driver version %s %sexecuting gcc version %s\n" - msgstr "драйвер gcc версия %s; %sисполняет gcc версия %s\n" - --#: gcc.c:7058 -+#: gcc.c:7061 - #, c-format - msgid "" - "\n" -@@ -590,7 +583,7 @@ - "==================\n" - "\n" - --#: gcc.c:7059 -+#: gcc.c:7062 - #, c-format - msgid "" - "Use \"-Wl,OPTION\" to pass \"OPTION\" to the linker.\n" -@@ -599,7 +592,7 @@ - "Используйте \"-Wl,КЛЮЧ\", чтобы передать \"КЛЮЧ\" компоновщику.\n" - "\n" - --#: gcc.c:8276 -+#: gcc.c:8279 - #, c-format - msgid "" - "Assembler options\n" -@@ -610,7 +603,7 @@ - "=================\n" - "\n" - --#: gcc.c:8277 -+#: gcc.c:8280 - #, c-format - msgid "" - "Use \"-Wa,OPTION\" to pass \"OPTION\" to the assembler.\n" -@@ -773,7 +766,6 @@ - - #: gcov.c:979 - #, fuzzy, c-format --#| msgid "%s:source file is newer than graph file '%s'\n" - msgid "%s:source file is newer than notes file '%s'\n" - msgstr "%s:исходный файл новее чем файл графа '%s'\n" - -@@ -784,13 +776,11 @@ - - #: gcov.c:1009 - #, fuzzy, c-format --#| msgid "%s:cannot open graph file\n" - msgid "%s:cannot open notes file\n" - msgstr "%s:ошибка открытия графического файла\n" - - #: gcov.c:1015 - #, fuzzy, c-format --#| msgid "%s:not a gcov data file\n" - msgid "%s:not a gcov notes file\n" - msgstr "%s:не файл данных gcov\n" - -@@ -831,7 +821,6 @@ - - #: gcov.c:1251 - #, fuzzy, c-format --#| msgid "%s:stamp mismatch with graph file\n" - msgid "%s:stamp mismatch with notes file\n" - msgstr "%s:штамп не соответствует графическому файлу\n" - -@@ -1046,17 +1035,17 @@ - msgid "ignoring nonexistent directory \"%s\"\n" - msgstr "несуществующий каталог \"%s\" проигнорирован\n" - --#: incpath.c:363 -+#: incpath.c:374 - #, c-format - msgid "#include \"...\" search starts here:\n" - msgstr "порядок поиска для #include \"...\":\n" - --#: incpath.c:367 -+#: incpath.c:378 - #, c-format - msgid "#include <...> search starts here:\n" - msgstr "порядок поиска для #include <...>:\n" - --#: incpath.c:372 -+#: incpath.c:383 - #, c-format - msgid "End of search list.\n" - msgstr "Конец списка поиска.\n" -@@ -1089,44 +1078,44 @@ - msgid "At top level:" - msgstr "На верхнем уровне:" - --#: langhooks.c:400 cp/error.c:3038 -+#: langhooks.c:400 cp/error.c:3042 - #, c-format - msgid "In member function %qs" - msgstr "В функции-члене %qs" - --#: langhooks.c:404 cp/error.c:3041 -+#: langhooks.c:404 cp/error.c:3045 - #, c-format - msgid "In function %qs" - msgstr "В функции %qs" - --#: langhooks.c:455 cp/error.c:2991 -+#: langhooks.c:455 cp/error.c:2995 - #, c-format - msgid " inlined from %qs at %s:%d:%d" - msgstr " включённом из %qs в %s:%d:%d" - --#: langhooks.c:460 cp/error.c:2996 -+#: langhooks.c:460 cp/error.c:3000 - #, c-format - msgid " inlined from %qs at %s:%d" - msgstr " включённом из %qs в %s:%d" - --#: langhooks.c:466 cp/error.c:3002 -+#: langhooks.c:466 cp/error.c:3006 - #, c-format - msgid " inlined from %qs" - msgstr " включённом из %qs" - --#: loop-iv.c:3029 tree-ssa-loop-niter.c:1924 -+#: loop-iv.c:3029 tree-ssa-loop-niter.c:1925 - msgid "assuming that the loop is not infinite" - msgstr "предполагается, что цикл не бесконечный" - --#: loop-iv.c:3030 tree-ssa-loop-niter.c:1925 -+#: loop-iv.c:3030 tree-ssa-loop-niter.c:1926 - msgid "cannot optimize possibly infinite loops" - msgstr "невозможно оптимизировать бесконечные циклы" - --#: loop-iv.c:3038 tree-ssa-loop-niter.c:1929 -+#: loop-iv.c:3038 tree-ssa-loop-niter.c:1930 - msgid "assuming that the loop counter does not overflow" - msgstr "предполагается, что счётчик цикла не выходит за границы" - --#: loop-iv.c:3039 tree-ssa-loop-niter.c:1930 -+#: loop-iv.c:3039 tree-ssa-loop-niter.c:1931 - msgid "cannot optimize loop, the loop counter may overflow" - msgstr "невозможно оптимизировать циклы, в которых счётчик выходит за границы" - -@@ -1204,80 +1193,80 @@ - msgid "This switch lacks documentation" - msgstr "Этот ключ не документирован" - --#: opts.c:1015 -+#: opts.c:1018 - msgid "[default]" - msgstr "[по умолчанию]" - --#: opts.c:1026 -+#: opts.c:1029 - msgid "[enabled]" - msgstr "[включено]" - --#: opts.c:1026 -+#: opts.c:1029 - msgid "[disabled]" - msgstr "[выключено]" - --#: opts.c:1045 -+#: opts.c:1048 - #, c-format - msgid " No options with the desired characteristics were found\n" - msgstr " Не найдено ключей с требуемыми характеристиками\n" - --#: opts.c:1054 -+#: opts.c:1057 - #, c-format - msgid " None found. Use --help=%s to show *all* the options supported by the %s front-end\n" - msgstr "" - --#: opts.c:1060 -+#: opts.c:1063 - #, c-format - msgid " All options with the desired characteristics have already been displayed\n" - msgstr " Все ключи с требуемыми характеристиками уже выведены\n" - --#: opts.c:1155 -+#: opts.c:1158 - msgid "The following options are target specific" --msgstr "Следующие ключи не зависят от целевой архитектуры" -+msgstr "Следующие ключи зависят от целевой архитектуры" - --#: opts.c:1158 -+#: opts.c:1161 - msgid "The following options control compiler warning messages" - msgstr "Следующие ключи контролируют предупреждения компилятора" - --#: opts.c:1161 -+#: opts.c:1164 - msgid "The following options control optimizations" - msgstr "Следующие ключи контролируют оптимизацию" - --#: opts.c:1164 opts.c:1203 -+#: opts.c:1167 opts.c:1206 - msgid "The following options are language-independent" - msgstr "Следующие ключи не зависят от входного языка" - --#: opts.c:1167 -+#: opts.c:1170 - msgid "The --param option recognizes the following as parameters" - msgstr "Ключ --param позволяет задать следующие параметры" - --#: opts.c:1173 -+#: opts.c:1176 - msgid "The following options are specific to just the language " - msgstr "Следующие ключи зависят только от языка " - --#: opts.c:1175 -+#: opts.c:1178 - msgid "The following options are supported by the language " - msgstr "Следующие ключи поддерживаются языком " - --#: opts.c:1186 -+#: opts.c:1189 - msgid "The following options are not documented" - msgstr "Следующие ключи не документированы" - --#: opts.c:1188 -+#: opts.c:1191 - #, fuzzy - msgid "The following options take separate arguments" - msgstr "Следующие ключи не документированы" - --#: opts.c:1190 -+#: opts.c:1193 - #, fuzzy - msgid "The following options take joined arguments" - msgstr "Следующие ключи не документированы" - --#: opts.c:1201 -+#: opts.c:1204 - msgid "The following options are language-related" - msgstr "Следующие ключи относятся к исходному языку" - --#: opts.c:2078 -+#: opts.c:2081 - msgid "enabled by default" - msgstr "по умолчанию включена" - -@@ -2499,7 +2488,7 @@ - msgid "" - msgstr "" - --#: c-family/c-pretty-print.c:2147 cp/error.c:1818 cp/error.c:2764 -+#: c-family/c-pretty-print.c:2147 cp/error.c:1818 cp/error.c:2768 - #, fuzzy - msgid "" - msgstr "Неизвестный источник" -@@ -2510,7 +2499,6 @@ - #: config/aarch64/aarch64.c:3298 config/aarch64/aarch64.c:3313 - #: config/aarch64/aarch64.c:3332 - #, fuzzy, c-format --#| msgid "invalid operand for code '%c'" - msgid "invalid operand for '%%%c'" - msgstr "недопустимый операнд для кода '%c'" - -@@ -2519,26 +2507,23 @@ - msgid "incompatible floating point / vector register operand for '%%%c'" - msgstr "" - --#: config/aarch64/aarch64.c:3399 config/arm/arm.c:18223 -+#: config/aarch64/aarch64.c:3399 config/arm/arm.c:18233 - #, c-format - msgid "missing operand" - msgstr "отсутствует операнд" - - #: config/aarch64/aarch64.c:3462 - #, fuzzy, c-format --#| msgid "invalid insn:" - msgid "invalid constant" - msgstr "недопустимая инструкция:" - - #: config/aarch64/aarch64.c:3465 - #, fuzzy, c-format --#| msgid "invalid %%d operand" - msgid "invalid operand" - msgstr "некорректный операнд для %%d" - - #: config/aarch64/aarch64.c:3545 - #, fuzzy, c-format --#| msgid "invalid operand code '%c'" - msgid "invalid operand prefix '%%%c'" - msgstr "некорректный код операнда '%c'" - -@@ -2626,33 +2611,34 @@ - msgid "invalid %%xn code" - msgstr "некорректный код %%xn" - --#: config/arm/arm.c:17560 config/arm/arm.c:17578 -+#: config/arm/arm.c:15438 config/arm/arm.c:15463 config/arm/arm.c:15473 -+#: config/arm/arm.c:15482 config/arm/arm.c:15490 - #, c-format -+msgid "invalid shift operand" -+msgstr "некорректный оператор сдвига" -+ -+#: config/arm/arm.c:17576 config/arm/arm.c:17594 -+#, c-format - msgid "predicated Thumb instruction" - msgstr "предикативная инструкция для архитектуры Thumb" - --#: config/arm/arm.c:17566 -+#: config/arm/arm.c:17582 - #, c-format - msgid "predicated instruction in conditional sequence" - msgstr "предикативная инструкция в условной последовательности" - --#: config/arm/arm.c:17697 config/arm/arm.c:17710 -+#: config/arm/arm.c:17713 config/arm/arm.c:17726 - #, fuzzy, c-format - msgid "Unsupported operand for code '%c'" - msgstr "недопустимый операнд для кода '%c'" - --#: config/arm/arm.c:17748 --#, c-format --msgid "invalid shift operand" --msgstr "некорректный оператор сдвига" -- --#: config/arm/arm.c:17805 config/arm/arm.c:17827 config/arm/arm.c:17837 --#: config/arm/arm.c:17847 config/arm/arm.c:17857 config/arm/arm.c:17896 --#: config/arm/arm.c:17914 config/arm/arm.c:17939 config/arm/arm.c:17954 --#: config/arm/arm.c:17981 config/arm/arm.c:17988 config/arm/arm.c:18006 --#: config/arm/arm.c:18013 config/arm/arm.c:18021 config/arm/arm.c:18042 --#: config/arm/arm.c:18049 config/arm/arm.c:18174 config/arm/arm.c:18181 --#: config/arm/arm.c:18204 config/arm/arm.c:18211 config/bfin/bfin.c:1439 -+#: config/arm/arm.c:17815 config/arm/arm.c:17837 config/arm/arm.c:17847 -+#: config/arm/arm.c:17857 config/arm/arm.c:17867 config/arm/arm.c:17906 -+#: config/arm/arm.c:17924 config/arm/arm.c:17949 config/arm/arm.c:17964 -+#: config/arm/arm.c:17991 config/arm/arm.c:17998 config/arm/arm.c:18016 -+#: config/arm/arm.c:18023 config/arm/arm.c:18031 config/arm/arm.c:18052 -+#: config/arm/arm.c:18059 config/arm/arm.c:18184 config/arm/arm.c:18191 -+#: config/arm/arm.c:18214 config/arm/arm.c:18221 config/bfin/bfin.c:1439 - #: config/bfin/bfin.c:1446 config/bfin/bfin.c:1453 config/bfin/bfin.c:1460 - #: config/bfin/bfin.c:1469 config/bfin/bfin.c:1476 config/bfin/bfin.c:1483 - #: config/bfin/bfin.c:1490 -@@ -2660,23 +2646,23 @@ - msgid "invalid operand for code '%c'" - msgstr "недопустимый операнд для кода '%c'" - --#: config/arm/arm.c:17909 -+#: config/arm/arm.c:17919 - #, c-format - msgid "instruction never executed" - msgstr "инструкция никогда не выполняется" - - #. Former Maverick support, removed after GCC-4.7. --#: config/arm/arm.c:17930 -+#: config/arm/arm.c:17940 - #, fuzzy, c-format - msgid "obsolete Maverick format code '%c'" - msgstr "недопустимый операнд для кода '%c'" - --#: config/arm/arm.c:20988 -+#: config/arm/arm.c:20998 - #, fuzzy - msgid "function parameters cannot have __fp16 type" - msgstr "функция возвращает агрегатное значение" - --#: config/arm/arm.c:20998 -+#: config/arm/arm.c:21008 - #, fuzzy - msgid "functions cannot return __fp16 type" - msgstr "функция возвращает значение не строкового типа" -@@ -2714,9 +2700,9 @@ - msgstr "внутренняя ошибка компилятора: некорректный адрес:" - - #: config/avr/avr.c:2234 --#, fuzzy, c-format --msgid "Unsupported code '%c'for fixed-point:" --msgstr "недопустимый операнд для кода '%c'" -+#, c-format -+msgid "Unsupported code '%c' for fixed-point:" -+msgstr "" - - #: config/avr/avr.c:2243 - msgid "internal compiler error. Unknown mode:" -@@ -2763,8 +2749,8 @@ - msgstr "некорректный операнд const_double" - - #: config/cris/cris.c:580 config/moxie/moxie.c:111 final.c:3311 final.c:3313 --#: fold-const.c:270 gcc.c:4712 gcc.c:4726 loop-iv.c:3031 loop-iv.c:3040 --#: rtl-error.c:102 toplev.c:332 tree-ssa-loop-niter.c:1933 tree-vrp.c:6783 -+#: fold-const.c:270 gcc.c:4713 gcc.c:4727 loop-iv.c:3031 loop-iv.c:3040 -+#: rtl-error.c:102 toplev.c:332 tree-ssa-loop-niter.c:1934 tree-vrp.c:6783 - #: cp/typeck.c:5618 java/expr.c:389 lto/lto-object.c:189 lto/lto-object.c:287 - #: lto/lto-object.c:344 lto/lto-object.c:368 - #, gcc-internal-format, gfc-internal-format -@@ -3107,8 +3093,8 @@ - msgid "invalid operation on %<__fpreg%>" - msgstr "некорректный операнд для %<__fpreg%>" - --#: config/iq2000/iq2000.c:3132 config/tilegx/tilegx.c:5205 --#: config/tilepro/tilepro.c:4695 -+#: config/iq2000/iq2000.c:3132 config/tilegx/tilegx.c:5203 -+#: config/tilepro/tilepro.c:4693 - #, c-format - msgid "invalid %%P operand" - msgstr "неверный операнд для кода %%P" -@@ -3123,21 +3109,21 @@ - msgid "invalid use of %%d, %%x, or %%X" - msgstr "некорректное использование %%d, %%x или %%X" - --#: config/lm32/lm32.c:521 -+#: config/lm32/lm32.c:518 - #, c-format - msgid "only 0.0 can be loaded as an immediate" - msgstr "" - --#: config/lm32/lm32.c:591 -+#: config/lm32/lm32.c:588 - #, fuzzy - msgid "bad operand" - msgstr "некорректный операнд" - --#: config/lm32/lm32.c:603 -+#: config/lm32/lm32.c:600 - msgid "can't use non gp relative absolute address" - msgstr "" - --#: config/lm32/lm32.c:607 -+#: config/lm32/lm32.c:604 - #, fuzzy - msgid "invalid addressing mode" - msgstr "некорректный адрес" -@@ -3207,37 +3193,37 @@ - msgid "invalid %%L code" - msgstr "недопустимое значение для кода %%j" - --#: config/microblaze/microblaze.c:1760 -+#: config/microblaze/microblaze.c:2156 - #, fuzzy, c-format - msgid "unknown punctuation '%c'" - msgstr "неизвестная функция '%s' в спецификации" - --#: config/microblaze/microblaze.c:1769 -+#: config/microblaze/microblaze.c:2165 - #, fuzzy, c-format - msgid "null pointer" - msgstr "нулевой указатель в вызове PRINT_OPERAND" - --#: config/microblaze/microblaze.c:1804 -+#: config/microblaze/microblaze.c:2200 - #, fuzzy, c-format - msgid "PRINT_OPERAND, invalid insn for %%C" - msgstr "PRINT_OPERAND_ADDRESS: некорректная инструкция #1" - --#: config/microblaze/microblaze.c:1833 -+#: config/microblaze/microblaze.c:2229 - #, fuzzy, c-format - msgid "PRINT_OPERAND, invalid insn for %%N" - msgstr "PRINT_OPERAND_ADDRESS: некорректная инструкция #1" - --#: config/microblaze/microblaze.c:1853 config/microblaze/microblaze.c:2014 -+#: config/microblaze/microblaze.c:2249 config/microblaze/microblaze.c:2420 - #, fuzzy - msgid "insn contains an invalid address !" - msgstr "некорректный адрес" - --#: config/microblaze/microblaze.c:1867 config/microblaze/microblaze.c:2054 -+#: config/microblaze/microblaze.c:2264 config/microblaze/microblaze.c:2479 - #: config/xtensa/xtensa.c:2443 - msgid "invalid address" - msgstr "некорректный адрес" - --#: config/microblaze/microblaze.c:1966 -+#: config/microblaze/microblaze.c:2363 - #, c-format - msgid "letter %c was found & insn was not CONST_INT" - msgstr "" -@@ -3526,25 +3512,25 @@ - msgid "invalid operand for code: '%c'" - msgstr "некорректный операнд для кода '%c'" - --#: config/sh/sh.c:1204 -+#: config/sh/sh.c:1201 - #, c-format - msgid "invalid operand to %%R" - msgstr "некорректный операнд для %%R" - --#: config/sh/sh.c:1231 -+#: config/sh/sh.c:1228 - #, c-format - msgid "invalid operand to %%S" - msgstr "некорректный операнд для %%S" - --#: config/sh/sh.c:9775 -+#: config/sh/sh.c:9772 - msgid "created and used with different architectures / ABIs" - msgstr "создан с одной архитектурой / ABI, а используется с другим" - --#: config/sh/sh.c:9777 -+#: config/sh/sh.c:9774 - msgid "created and used with different ABIs" - msgstr "создан с одним ABI, а используется с другим" - --#: config/sh/sh.c:9779 -+#: config/sh/sh.c:9776 - msgid "created and used with different endianness" - msgstr "создан с одним значением endianness, а используется с другим" - -@@ -3563,13 +3549,13 @@ - msgid "invalid %%B operand" - msgstr "некорректный операнд для %%B" - --#: config/sparc/sparc.c:8508 config/tilegx/tilegx.c:4988 --#: config/tilepro/tilepro.c:4498 -+#: config/sparc/sparc.c:8508 config/tilegx/tilegx.c:4986 -+#: config/tilepro/tilepro.c:4496 - #, fuzzy, c-format - msgid "invalid %%C operand" - msgstr "неверный операнд для кода %%P" - --#: config/sparc/sparc.c:8525 config/tilegx/tilegx.c:5021 -+#: config/sparc/sparc.c:8525 config/tilegx/tilegx.c:5019 - #, fuzzy, c-format - msgid "invalid %%D operand" - msgstr "неверный операнд для кода %%P" -@@ -3614,87 +3600,87 @@ - msgid "xstormy16_print_operand: unknown code" - msgstr "xstormy16_print_operand: некорректный код" - --#: config/tilegx/tilegx.c:4973 config/tilepro/tilepro.c:4483 -+#: config/tilegx/tilegx.c:4971 config/tilepro/tilepro.c:4481 - #, c-format - msgid "invalid %%c operand" - msgstr "некорректный операнд для %%c" - --#: config/tilegx/tilegx.c:5004 -+#: config/tilegx/tilegx.c:5002 - #, c-format - msgid "invalid %%d operand" - msgstr "некорректный операнд для %%d" - --#: config/tilegx/tilegx.c:5101 -+#: config/tilegx/tilegx.c:5099 - #, fuzzy, c-format - msgid "invalid %%H specifier" - msgstr "недопустимое значение для кода %%j" - --#: config/tilegx/tilegx.c:5143 config/tilepro/tilepro.c:4512 -+#: config/tilegx/tilegx.c:5141 config/tilepro/tilepro.c:4510 - #, fuzzy, c-format - msgid "invalid %%h operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilegx/tilegx.c:5155 config/tilepro/tilepro.c:4576 -+#: config/tilegx/tilegx.c:5153 config/tilepro/tilepro.c:4574 - #, fuzzy, c-format - msgid "invalid %%I operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilegx/tilegx.c:5169 config/tilepro/tilepro.c:4590 -+#: config/tilegx/tilegx.c:5167 config/tilepro/tilepro.c:4588 - #, fuzzy, c-format - msgid "invalid %%i operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilegx/tilegx.c:5192 config/tilepro/tilepro.c:4613 -+#: config/tilegx/tilegx.c:5190 config/tilepro/tilepro.c:4611 - #, fuzzy, c-format - msgid "invalid %%j operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilegx/tilegx.c:5223 -+#: config/tilegx/tilegx.c:5221 - #, fuzzy, c-format - msgid "invalid %%%c operand" - msgstr "некорректный операнд для %%c" - --#: config/tilegx/tilegx.c:5238 config/tilepro/tilepro.c:4727 -+#: config/tilegx/tilegx.c:5236 config/tilepro/tilepro.c:4725 - #, fuzzy, c-format - msgid "invalid %%N operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilegx/tilegx.c:5282 -+#: config/tilegx/tilegx.c:5280 - #, fuzzy, c-format - msgid "invalid operand for 'r' specifier" - msgstr "некорректный операнд для модификатора 'b'" - --#: config/tilegx/tilegx.c:5307 config/tilepro/tilepro.c:4809 -+#: config/tilegx/tilegx.c:5305 config/tilepro/tilepro.c:4807 - #, c-format - msgid "unable to print out operand yet; code == %d (%c)" - msgstr "" - --#: config/tilepro/tilepro.c:4548 -+#: config/tilepro/tilepro.c:4546 - #, fuzzy, c-format - msgid "invalid %%H operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilepro/tilepro.c:4652 -+#: config/tilepro/tilepro.c:4650 - #, fuzzy, c-format - msgid "invalid %%L operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilepro/tilepro.c:4712 -+#: config/tilepro/tilepro.c:4710 - #, fuzzy, c-format - msgid "invalid %%M operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilepro/tilepro.c:4755 -+#: config/tilepro/tilepro.c:4753 - #, fuzzy, c-format - msgid "invalid %%t operand" - msgstr "неверный операнд для кода %%P" - --#: config/tilepro/tilepro.c:4762 -+#: config/tilepro/tilepro.c:4760 - #, fuzzy, c-format - msgid "invalid %%t operand '" - msgstr "неверный операнд для кода %%P" - --#: config/tilepro/tilepro.c:4783 -+#: config/tilepro/tilepro.c:4781 - #, fuzzy, c-format - msgid "invalid %%r operand" - msgstr "неверный операнд для кода %%P" -@@ -3763,7 +3749,7 @@ - msgid "({anonymous})" - msgstr "({anonymous})" - --#: c/c-parser.c:943 cp/parser.c:23010 -+#: c/c-parser.c:943 cp/parser.c:23014 - #, gcc-internal-format - msgid "expected end of line" - msgstr "ожидался конец строки" -@@ -3773,8 +3759,8 @@ - #: c/c-parser.c:7357 c/c-parser.c:7392 c/c-parser.c:7423 c/c-parser.c:7470 - #: c/c-parser.c:7651 c/c-parser.c:8419 c/c-parser.c:8489 c/c-parser.c:8532 - #: c/c-parser.c:9810 c/c-parser.c:9825 c/c-parser.c:9834 c/c-parser.c:9979 --#: c/c-parser.c:10018 c/c-parser.c:2500 c/c-parser.c:7644 cp/parser.c:22423 --#: cp/parser.c:22956 -+#: c/c-parser.c:10018 c/c-parser.c:2500 c/c-parser.c:7644 cp/parser.c:22427 -+#: cp/parser.c:22960 - #, gcc-internal-format - msgid "expected %<;%>" - msgstr "ожидалось %<;%>" -@@ -3786,13 +3772,13 @@ - #: c/c-parser.c:6703 c/c-parser.c:6727 c/c-parser.c:7942 c/c-parser.c:8014 - #: c/c-parser.c:8841 c/c-parser.c:8862 c/c-parser.c:8912 c/c-parser.c:9065 - #: c/c-parser.c:9144 c/c-parser.c:9228 c/c-parser.c:9942 c/c-parser.c:10766 --#: c/c-parser.c:8985 c/c-parser.c:9010 cp/parser.c:20794 cp/parser.c:22959 -+#: c/c-parser.c:8985 c/c-parser.c:9010 cp/parser.c:20798 cp/parser.c:22963 - #, gcc-internal-format - msgid "expected %<(%>" - msgstr "ожидалось %<(%>" - - #: c/c-parser.c:1843 c/c-parser.c:6389 c/c-parser.c:6427 c/c-parser.c:6555 --#: cp/parser.c:22421 cp/parser.c:22974 -+#: cp/parser.c:22425 cp/parser.c:22978 - #, gcc-internal-format - msgid "expected %<,%>" - msgstr "ожидалось %<,%>" -@@ -3808,15 +3794,15 @@ - #: c/c-parser.c:7736 c/c-parser.c:7757 c/c-parser.c:7965 c/c-parser.c:8018 - #: c/c-parser.c:8391 c/c-parser.c:8844 c/c-parser.c:8865 c/c-parser.c:8943 - #: c/c-parser.c:9072 c/c-parser.c:9209 c/c-parser.c:9292 c/c-parser.c:9870 --#: c/c-parser.c:9987 c/c-parser.c:10029 c/c-parser.c:10775 cp/parser.c:20816 --#: cp/parser.c:23004 -+#: c/c-parser.c:9987 c/c-parser.c:10029 c/c-parser.c:10775 cp/parser.c:20820 -+#: cp/parser.c:23008 - #, gcc-internal-format - msgid "expected %<)%>" - msgstr "ожидалось %<)%>" - - #: c/c-parser.c:3095 c/c-parser.c:3911 c/c-parser.c:3945 c/c-parser.c:5228 - #: c/c-parser.c:6491 c/c-parser.c:6760 c/c-parser.c:6878 c/c-parser.c:10678 --#: c/c-parser.c:10680 cp/parser.c:22968 -+#: c/c-parser.c:10680 cp/parser.c:22972 - #, gcc-internal-format - msgid "expected %<]%>" - msgstr "ожидалось %<]%>" -@@ -3825,25 +3811,25 @@ - msgid "expected %<;%>, %<,%> or %<)%>" - msgstr "ожидалось %<;%>, %<,%> или %<)%>" - --#: c/c-parser.c:3774 c/c-parser.c:9826 cp/parser.c:22962 cp/parser.c:24780 -+#: c/c-parser.c:3774 c/c-parser.c:9826 cp/parser.c:22966 cp/parser.c:24784 - #, gcc-internal-format - msgid "expected %<}%>" - msgstr "ожидалось %<}%>" - - #: c/c-parser.c:4064 c/c-parser.c:7985 c/c-parser.c:10272 c/c-parser.c:2318 --#: c/c-parser.c:2521 c/c-parser.c:7539 cp/parser.c:14644 cp/parser.c:22965 -+#: c/c-parser.c:2521 c/c-parser.c:7539 cp/parser.c:14646 cp/parser.c:22969 - #, gcc-internal-format - msgid "expected %<{%>" - msgstr "ожидалось %<{%>" - - #: c/c-parser.c:4283 c/c-parser.c:4292 c/c-parser.c:5135 c/c-parser.c:5469 - #: c/c-parser.c:7750 c/c-parser.c:8125 c/c-parser.c:8182 c/c-parser.c:9198 --#: cp/parser.c:22998 cp/parser.c:24001 -+#: cp/parser.c:23002 cp/parser.c:24005 - #, gcc-internal-format - msgid "expected %<:%>" - msgstr "ожидалось %<:%>" - --#: c/c-parser.c:4831 cp/parser.c:22892 -+#: c/c-parser.c:4831 cp/parser.c:22896 - #, gcc-internal-format - msgid "expected %" - msgstr "ожидалось %" -@@ -3852,34 +3838,34 @@ - msgid "expected %<.%>" - msgstr "ожидалось %<.%>" - --#: c/c-parser.c:7210 c/c-parser.c:7242 c/c-parser.c:7482 cp/parser.c:24564 --#: cp/parser.c:24638 -+#: c/c-parser.c:7210 c/c-parser.c:7242 c/c-parser.c:7482 cp/parser.c:24568 -+#: cp/parser.c:24642 - #, gcc-internal-format - msgid "expected %<@end%>" - msgstr "ожидалось %<@end%>" - --#: c/c-parser.c:7899 cp/parser.c:22983 -+#: c/c-parser.c:7899 cp/parser.c:22987 - #, gcc-internal-format - msgid "expected %<>%>" - msgstr "ожидалось %<>%>" - --#: c/c-parser.c:9296 cp/parser.c:23007 -+#: c/c-parser.c:9296 cp/parser.c:23011 - #, gcc-internal-format - msgid "expected %<,%> or %<)%>" - msgstr "ожидалось %<,%> или %<)%>" - - #: c/c-parser.c:9549 c/c-parser.c:9580 c/c-parser.c:9816 c/c-parser.c:9968 --#: c/c-parser.c:3968 cp/parser.c:22986 -+#: c/c-parser.c:3968 cp/parser.c:22990 - #, gcc-internal-format - msgid "expected %<=%>" - msgstr "ожидалось %<=%>" - --#: c/c-parser.c:10329 c/c-parser.c:10319 cp/parser.c:27421 -+#: c/c-parser.c:10329 c/c-parser.c:10319 cp/parser.c:27425 - #, gcc-internal-format - msgid "expected %<#pragma omp section%> or %<}%>" - msgstr "ожидалось %<#pragma omp section%> или %<}%>" - --#: c/c-parser.c:10666 cp/parser.c:22971 -+#: c/c-parser.c:10666 cp/parser.c:22975 - #, fuzzy, gcc-internal-format - msgid "expected %<[%>" - msgstr "ожидалось %<{%>" -@@ -3888,11 +3874,11 @@ - msgid "(anonymous)" - msgstr "(anonymous)" - --#: cp/call.c:8680 -+#: cp/call.c:8698 - msgid "candidate 1:" - msgstr "кандидат 1:" - --#: cp/call.c:8681 -+#: cp/call.c:8699 - msgid "candidate 2:" - msgstr "кандидат 2:" - -@@ -3900,7 +3886,7 @@ - msgid "" - msgstr "" - --#: cp/cxx-pretty-print.c:2149 -+#: cp/cxx-pretty-print.c:2153 - #, fuzzy - msgid "template-parameter-" - msgstr "параметр шаблона `%#D'" -@@ -3972,7 +3958,6 @@ - - #: cp/error.c:1035 - #, fuzzy --#| msgid "(anonymous)" - msgid "(anonymous namespace)" - msgstr "(anonymous)" - -@@ -3990,7 +3975,7 @@ - msgid "" - msgstr "декларация %q#D" - --#: cp/error.c:1445 cp/error.c:2855 -+#: cp/error.c:1445 cp/error.c:2859 - msgid "with" - msgstr "" - -@@ -4015,114 +4000,118 @@ - msgid "" - msgstr "" - --#: cp/error.c:2504 -+#: cp/error.c:2498 -+msgid "" -+msgstr "" -+ -+#: cp/error.c:2508 - msgid "" - msgstr "" - --#: cp/error.c:2518 -+#: cp/error.c:2522 - #, fuzzy - msgid "" - msgstr "Неизвестный оператор '%s' в %%L" - --#: cp/error.c:2807 -+#: cp/error.c:2811 - #, fuzzy - msgid "{unknown}" - msgstr "Неизвестный источник" - --#: cp/error.c:2922 -+#: cp/error.c:2926 - msgid "At global scope:" - msgstr "" - --#: cp/error.c:3028 -+#: cp/error.c:3032 - #, fuzzy, c-format - msgid "In static member function %qs" - msgstr "В функции-члене %qs" - --#: cp/error.c:3030 -+#: cp/error.c:3034 - #, c-format - msgid "In copy constructor %qs" - msgstr "" - --#: cp/error.c:3032 -+#: cp/error.c:3036 - #, fuzzy, c-format - msgid "In constructor %qs" - msgstr "В функции %qs" - --#: cp/error.c:3034 -+#: cp/error.c:3038 - #, fuzzy, c-format - msgid "In destructor %qs" - msgstr "В функции %qs" - --#: cp/error.c:3036 -+#: cp/error.c:3040 - #, fuzzy - msgid "In lambda function" - msgstr "В функции-члене %qs" - --#: cp/error.c:3056 -+#: cp/error.c:3060 - #, fuzzy, c-format - msgid "%s: In substitution of %qS:\n" - msgstr " в конкретизации шаблона %qT" - --#: cp/error.c:3057 -+#: cp/error.c:3061 - #, fuzzy - msgid "%s: In instantiation of %q#D:\n" - msgstr " в конкретизации шаблона %qT" - --#: cp/error.c:3080 -+#: cp/error.c:3084 - #, c-format - msgid "%s:%d:%d: " - msgstr "" - --#: cp/error.c:3083 -+#: cp/error.c:3087 - #, fuzzy, c-format - msgid "%s:%d: " - msgstr "%s: %s" - --#: cp/error.c:3091 -+#: cp/error.c:3095 - #, c-format - msgid "recursively required by substitution of %qS\n" - msgstr "" - --#: cp/error.c:3092 -+#: cp/error.c:3096 - #, c-format - msgid "required by substitution of %qS\n" - msgstr "" - --#: cp/error.c:3097 -+#: cp/error.c:3101 - msgid "recursively required from %q#D\n" - msgstr "" - --#: cp/error.c:3098 -+#: cp/error.c:3102 - #, fuzzy - msgid "required from %q#D\n" - msgstr "задано для %q+D" - --#: cp/error.c:3105 -+#: cp/error.c:3109 - #, fuzzy - msgid "recursively required from here" - msgstr "которая вызвана здесь" - --#: cp/error.c:3106 -+#: cp/error.c:3110 - #, fuzzy - msgid "required from here" - msgstr "которая вызвана здесь" - --#: cp/error.c:3158 -+#: cp/error.c:3162 - #, c-format - msgid "%s:%d:%d: [ skipping %d instantiation contexts, use -ftemplate-backtrace-limit=0 to disable ]\n" - msgstr "" - --#: cp/error.c:3163 -+#: cp/error.c:3167 - #, c-format - msgid "%s:%d: [ skipping %d instantiation contexts, use -ftemplate-backtrace-limit=0 to disable ]\n" - msgstr "" - --#: cp/error.c:3227 -+#: cp/error.c:3231 - #, c-format - msgid "%s:%d:%d: in constexpr expansion of %qs" - msgstr "" - --#: cp/error.c:3231 -+#: cp/error.c:3235 - #, c-format - msgid "%s:%d: in constexpr expansion of %qs" - msgstr "" -@@ -4131,12 +4120,12 @@ - msgid "candidates are:" - msgstr "претенденты:" - --#: cp/pt.c:17926 cp/call.c:3290 --#, fuzzy, gcc-internal-format -+#: cp/pt.c:17922 cp/call.c:3290 -+#, gcc-internal-format - msgid "candidate is:" - msgid_plural "candidates are:" --msgstr[0] "кандидат 1:" --msgstr[1] "кандидат 1:" -+msgstr[0] "" -+msgstr[1] "" - msgstr[2] "" - - #: cp/rtti.c:537 -@@ -4699,12 +4688,12 @@ - msgid "Integer overflow when calculating the amount of memory to allocate" - msgstr "" - --#: fortran/trans-decl.c:4842 -+#: fortran/trans-decl.c:4844 - #, fuzzy, c-format - msgid "Actual string length does not match the declared one for dummy argument '%s' (%ld/%ld)" - msgstr "передано %qT для %s %P в %qD" - --#: fortran/trans-decl.c:4850 -+#: fortran/trans-decl.c:4852 - #, fuzzy, c-format - msgid "Actual string length is shorter than the declared one for dummy argument '%s' (%ld/%ld)" - msgstr "передано %qT для %s %P в %qD" -@@ -4719,12 +4708,12 @@ - msgid "Unequal character lengths (%ld/%ld) in %s" - msgstr "" - --#: fortran/trans-intrinsic.c:6157 -+#: fortran/trans-intrinsic.c:6156 - #, fuzzy, c-format - msgid "Argument NCOPIES of REPEAT intrinsic is negative (its value is %ld)" - msgstr "аргумент `asm' - не константная строка" - --#: fortran/trans-intrinsic.c:6189 -+#: fortran/trans-intrinsic.c:6188 - msgid "Argument NCOPIES of REPEAT intrinsic is too large" - msgstr "" - -@@ -4959,7 +4948,7 @@ - msgid "objc-cpp-output is deprecated; please use objective-c-cpp-output instead" - msgstr "" - --#: java/jvspec.c:79 ada/gcc-interface/lang-specs.h:33 gcc.c:844 -+#: java/jvspec.c:79 ada/gcc-interface/lang-specs.h:33 gcc.c:845 - msgid "-pg and -fomit-frame-pointer are incompatible" - msgstr "-pg и -fomit-frame-pointer несовместимы" - -@@ -5023,7 +5012,7 @@ - msgid "consider using '-pg' instead of '-p' with gprof(1)" - msgstr "" - --#: config/sh/sh.h:360 config/sh/sh.h:363 -+#: config/sh/sh.h:363 config/sh/sh.h:366 - msgid "SH2a does not support little-endian" - msgstr "SH2a не поддерживает little-endian" - -@@ -5088,7 +5077,7 @@ - msgstr "Ключ -shared не поддерживается для VAX ELF" - - #: config/i386/mingw-w64.h:82 config/i386/mingw32.h:115 --#: config/i386/cygwin.h:113 -+#: config/i386/cygwin.h:109 - msgid "shared and mdll are not compatible" - msgstr "shared и mdll несовместимы" - -@@ -5132,25 +5121,25 @@ - msgid "profiling not supported with -mg" - msgstr "профилирование с -mg не поддерживается\n" - --#: gcc.c:704 -+#: gcc.c:705 - #, fuzzy - msgid "-fuse-linker-plugin is not supported in this configuration" - msgstr "-m%s в данной конфигурации не поддерживается" - --#: gcc.c:718 -+#: gcc.c:719 - msgid "cannot specify -static with -fsanitize=address" - msgstr "" - --#: gcc.c:720 -+#: gcc.c:721 - msgid "-fsanitize=thread linking must be done with -pie or -shared" - msgstr "" - --#: gcc.c:1012 -+#: gcc.c:1013 - #, fuzzy - msgid "GNU C no longer supports -traditional without -E" - msgstr "ключ -C или -CC допустим только с -E" - --#: gcc.c:1021 -+#: gcc.c:1022 - msgid "-E or -x required when input is from standard input" - msgstr "ввод со стандартного ввода возможен только с ключом -E или -x" - -@@ -5210,7 +5199,7 @@ - msgid "Warn about most implicit conversions" - msgstr "Предупреждать о неявных декларациях функций" - --#: fortran/lang.opt:234 common.opt:542 -+#: fortran/lang.opt:234 common.opt:546 - msgid "Print extra (possibly unwanted) warnings" - msgstr "Печатать дополнительные (возможно, нежелательные) предупреждения" - -@@ -5244,13 +5233,11 @@ - - #: fortran/lang.opt:262 - #, fuzzy --#| msgid "Warn when a register variable is declared volatile" - msgid "Warn when a left-hand-side array variable is reallocated" - msgstr "Предупреждать о регистровых переменных, объявленных volatile" - - #: fortran/lang.opt:266 - #, fuzzy --#| msgid "Warn when a register variable is declared volatile" - msgid "Warn when a left-hand-side variable is reallocated" - msgstr "Предупреждать о регистровых переменных, объявленных volatile" - -@@ -5368,9 +5355,9 @@ - msgid "Allow dollar signs in entity names" - msgstr "" - --#: fortran/lang.opt:394 config/alpha/alpha.opt:31 common.opt:656 --#: common.opt:830 common.opt:834 common.opt:838 common.opt:842 common.opt:1227 --#: common.opt:1360 common.opt:1364 -+#: fortran/lang.opt:394 config/alpha/alpha.opt:31 common.opt:660 -+#: common.opt:834 common.opt:838 common.opt:842 common.opt:846 common.opt:1231 -+#: common.opt:1364 common.opt:1368 - msgid "Does nothing. Preserved for backward compatibility." - msgstr "" - -@@ -5618,7 +5605,7 @@ - #: c-family/c.opt:70 c-family/c.opt:73 c-family/c.opt:76 c-family/c.opt:79 - #: c-family/c.opt:175 c-family/c.opt:178 c-family/c.opt:216 c-family/c.opt:220 - #: c-family/c.opt:232 c-family/c.opt:1253 c-family/c.opt:1261 --#: config/darwin.opt:53 common.opt:300 common.opt:303 common.opt:2399 -+#: config/darwin.opt:53 common.opt:300 common.opt:303 common.opt:2403 - #, c-format - msgid "missing filename after %qs" - msgstr "не задано имя файла после %qs" -@@ -6077,7 +6064,6 @@ - - #: c-family/c.opt:654 - #, fuzzy --#| msgid "returning reference to temporary" - msgid "Warn about returning a pointer/reference to a local or temporary variable." - msgstr "возврат ссылки на временную переменную" - -@@ -6171,7 +6157,6 @@ - - #: c-family/c.opt:770 - #, fuzzy --#| msgid "Do not warn about using variadic macros when -pedantic" - msgid "Warn about using variadic macros" - msgstr "Не предупреждать об использовании макросов с переменным числом аргументов с -pedantic" - -@@ -6203,7 +6188,6 @@ - - #: c-family/c.opt:798 - #, fuzzy --#| msgid "Warn about misuses of pragmas" - msgid "Warn about useless casts" - msgstr "Предупреждать о неправильном использовании прагм" - -@@ -6260,9 +6244,9 @@ - msgstr "Разрешить разные типы для операндов операции '?'" - - #: c-family/c.opt:856 c-family/c.opt:876 c-family/c.opt:1074 --#: config/sh/sh.opt:209 common.opt:949 common.opt:1135 common.opt:1439 --#: common.opt:1713 common.opt:1749 common.opt:1834 common.opt:1838 --#: common.opt:1914 common.opt:1996 common.opt:2020 common.opt:2108 -+#: config/sh/sh.opt:213 common.opt:953 common.opt:1139 common.opt:1443 -+#: common.opt:1717 common.opt:1753 common.opt:1838 common.opt:1842 -+#: common.opt:1918 common.opt:2000 common.opt:2024 common.opt:2112 - msgid "Does nothing. Preserved for backward compatibility." - msgstr "" - -@@ -6461,9 +6445,8 @@ - msgstr "Ошибки соответствия трактовать как предупреждения" - - #: c-family/c.opt:1089 --#, fuzzy - msgid "Enable Plan 9 language extensions" --msgstr "Включить ключ -relax при компоновке" -+msgstr "Включить расширения языка Plan 9" - - #: c-family/c.opt:1093 - msgid "Treat the input file as already preprocessed" -@@ -6524,7 +6507,6 @@ - - #: c-family/c.opt:1159 - #, fuzzy --#| msgid "Set the maximum number of iterations for RPTS to N" - msgid "Set the maximum number of template instantiation notes for a single warning or error" - msgstr "Задать максимальное число итераций для RPTS" - -@@ -7489,7 +7471,7 @@ - msgstr "Включить раннее размещение stop-битов для улучшения планирования" - - #: config/ia64/ia64.opt:114 config/spu/spu.opt:72 config/pa/pa.opt:58 --#: config/sh/sh.opt:261 -+#: config/sh/sh.opt:265 - msgid "Specify range of registers to make fixed" - msgstr "Диапазон регистров с фиксированным назначением" - -@@ -7972,7 +7954,6 @@ - - #: config/i386/i386.opt:90 - #, fuzzy --#| msgid "Use 128-bit long double" - msgid "Use 80-bit long double" - msgstr "Использовать 128-битное представление long double" - -@@ -7981,7 +7962,7 @@ - msgid "Use 64-bit long double" - msgstr "Использовать 64-битное представление long double" - --#: config/i386/i386.opt:98 config/sh/sh.opt:205 -+#: config/i386/i386.opt:98 config/sh/sh.opt:209 - msgid "Reserve space for outgoing arguments in the function prologue" - msgstr "Выделять место для возвращаемых аргументов в прологе функции" - -@@ -8032,7 +8013,6 @@ - - #: config/i386/i386.opt:171 - #, fuzzy --#| msgid "Use given x86-64 code model" - msgid "Use given address mode" - msgstr "Использовать указанную модель кода x86-64" - -@@ -8338,7 +8318,6 @@ - - #: config/i386/i386.opt:552 - #, fuzzy --#| msgid "Support multiply accumulate instructions" - msgid "Support flag-preserving add-carry instructions" - msgstr "Использовать команды умножения со сложением" - -@@ -8348,13 +8327,11 @@ - - #: config/i386/i386.opt:560 - #, fuzzy --#| msgid "Support calls between Thumb and ARM instruction sets" - msgid "Support XSAVE and XRSTOR instructions" - msgstr "Включить поддержку вызовов между системами команд Thumb и ARM" - - #: config/i386/i386.opt:564 - #, fuzzy --#| msgid "Support MMX built-in functions" - msgid "Support XSAVEOPT instruction" - msgstr "Включить поддержку внутренних функций MMX" - -@@ -8533,7 +8510,6 @@ - - #: config/v850/v850.opt:41 - #, fuzzy --#| msgid "Do not use the callt instruction" - msgid "Do not use the callt instruction (default)" - msgstr "Не использовать команды callt" - -@@ -8603,7 +8579,6 @@ - - #: config/v850/v850.opt:117 - #, fuzzy --#| msgid "Compile for the v850e processor" - msgid "Compile for the v850e3v5 processor" - msgstr "Компилировать для процессора v850e" - -@@ -8623,13 +8598,11 @@ - - #: config/v850/v850.opt:139 - #, fuzzy --#| msgid "Prohibit PC relative function calls" - msgid "Prohibit PC relative jumps" - msgstr "Запретить вызовы функций относительно PC" - - #: config/v850/v850.opt:143 - #, fuzzy --#| msgid "Prevent the use of all hardware floating-point instructions" - msgid "Inhibit the use of hardware floating point instructions" - msgstr "Не использовать аппаратную реализацию плавающих операций" - -@@ -8645,7 +8618,6 @@ - - #: config/v850/v850.opt:155 - #, fuzzy --#| msgid "Enable support for huge objects" - msgid "Enable support for the old GCC ABI" - msgstr "Включить поддержку больших объектов" - -@@ -8763,6 +8735,10 @@ - msgid "The device has no SPH special function register. This option will be overridden by the compiler driver with the correct setting if presence/absence of SPH can be deduced from -mmcu=MCU." - msgstr "" - -+#: config/avr/avr.opt:80 -+msgid "Warn if the address space of an address is change." -+msgstr "" -+ - #: config/m32r/m32r.opt:34 - msgid "Compile for the m32rx" - msgstr "Компилировать для m32rx" -@@ -9883,68 +9859,72 @@ - msgstr "" - - #: config/microblaze/microblaze.opt:72 -+msgid "Use reorder instructions (swap and byte reversed load/store) (default)" -+msgstr "" -+ -+#: config/microblaze/microblaze.opt:76 - msgid "Use the software emulation for divides (default)" - msgstr "" - --#: config/microblaze/microblaze.opt:76 -+#: config/microblaze/microblaze.opt:80 - msgid "Use the hardware barrel shifter instead of emulation" - msgstr "" - --#: config/microblaze/microblaze.opt:80 -+#: config/microblaze/microblaze.opt:84 - #, fuzzy - msgid "Use pattern compare instructions" - msgstr "Использовать инструкции двойной точности плавающих вычислений" - --#: config/microblaze/microblaze.opt:83 -+#: config/microblaze/microblaze.opt:87 - #, fuzzy, c-format - msgid "%qs is deprecated; use -fstack-check" - msgstr "имя %qs будет исключено в будущих версиях" - --#: config/microblaze/microblaze.opt:84 -+#: config/microblaze/microblaze.opt:88 - #, fuzzy - msgid "Check for stack overflow at runtime" - msgstr "Проверить код на наличие синтаксических ошибок и завершить работу" - --#: config/microblaze/microblaze.opt:88 config/iq2000/iq2000.opt:65 -+#: config/microblaze/microblaze.opt:92 config/iq2000/iq2000.opt:65 - msgid "Use GP relative sdata/sbss sections" - msgstr "Использовать секции sdata/sbss, адресуемые относительно регистра GP" - --#: config/microblaze/microblaze.opt:91 -+#: config/microblaze/microblaze.opt:95 - #, c-format - msgid "%qs is deprecated; use -fno-zero-initialized-in-bss" - msgstr "" - --#: config/microblaze/microblaze.opt:92 -+#: config/microblaze/microblaze.opt:96 - msgid "Clear the BSS to zero and place zero initialized in BSS" - msgstr "" - --#: config/microblaze/microblaze.opt:96 -+#: config/microblaze/microblaze.opt:100 - msgid "Use multiply high instructions for high part of 32x32 multiply" - msgstr "" - --#: config/microblaze/microblaze.opt:100 -+#: config/microblaze/microblaze.opt:104 - #, fuzzy - msgid "Use hardware floating point conversion instructions" - msgstr "Использовать команды плавающей арифметики формата paired-single (над парами значений одинарной точности)" - --#: config/microblaze/microblaze.opt:104 -+#: config/microblaze/microblaze.opt:108 - #, fuzzy - msgid "Use hardware floating point square root instruction" - msgstr "Использовать команды плавающей арифметики формата paired-single (над парами значений одинарной точности)" - --#: config/microblaze/microblaze.opt:108 -+#: config/microblaze/microblaze.opt:112 - msgid "Description for mxl-mode-executable" - msgstr "" - --#: config/microblaze/microblaze.opt:112 -+#: config/microblaze/microblaze.opt:116 - msgid "Description for mxl-mode-xmdstub" - msgstr "" - --#: config/microblaze/microblaze.opt:116 -+#: config/microblaze/microblaze.opt:120 - msgid "Description for mxl-mode-bootstrap" - msgstr "" - --#: config/microblaze/microblaze.opt:120 -+#: config/microblaze/microblaze.opt:124 - msgid "Description for mxl-mode-novectors" - msgstr "" - -@@ -10293,330 +10273,327 @@ - msgid "Runtime name." - msgstr "" - --#: config/sh/sh.opt:44 -+#: config/sh/sh.opt:48 - msgid "Generate SH1 code" - msgstr "Генерировать код SH1" - --#: config/sh/sh.opt:48 -+#: config/sh/sh.opt:52 - msgid "Generate SH2 code" - msgstr "Генерировать код SH2" - --#: config/sh/sh.opt:52 -+#: config/sh/sh.opt:56 - #, fuzzy - msgid "Generate default double-precision SH2a-FPU code" - msgstr "Генерировать код SH2a с одинарной точностью по умолчанию" - --#: config/sh/sh.opt:56 -+#: config/sh/sh.opt:60 - msgid "Generate SH2a FPU-less code" - msgstr "Генерировать код для SH2a без FPU" - --#: config/sh/sh.opt:60 -+#: config/sh/sh.opt:64 - #, fuzzy - msgid "Generate default single-precision SH2a-FPU code" - msgstr "Генерировать код SH2a с одинарной точностью по умолчанию" - --#: config/sh/sh.opt:64 -+#: config/sh/sh.opt:68 - #, fuzzy - msgid "Generate only single-precision SH2a-FPU code" - msgstr "Генерировать только код SH2a с одинарной точностью" - --#: config/sh/sh.opt:68 -+#: config/sh/sh.opt:72 - msgid "Generate SH2e code" - msgstr "Генерировать код SH2e" - --#: config/sh/sh.opt:72 -+#: config/sh/sh.opt:76 - msgid "Generate SH3 code" - msgstr "Генерировать код SH3" - --#: config/sh/sh.opt:76 -+#: config/sh/sh.opt:80 - msgid "Generate SH3e code" - msgstr "Генерировать код SH3e" - --#: config/sh/sh.opt:80 -+#: config/sh/sh.opt:84 - msgid "Generate SH4 code" - msgstr "Генерировать код SH4" - --#: config/sh/sh.opt:84 -+#: config/sh/sh.opt:88 - #, fuzzy - msgid "Generate SH4-100 code" - msgstr "Генерировать код SH1" - --#: config/sh/sh.opt:88 -+#: config/sh/sh.opt:92 - #, fuzzy - msgid "Generate SH4-200 code" - msgstr "Генерировать код SH2" - --#: config/sh/sh.opt:94 -+#: config/sh/sh.opt:98 - #, fuzzy - msgid "Generate SH4-300 code" - msgstr "Генерировать код SH3" - --#: config/sh/sh.opt:98 -+#: config/sh/sh.opt:102 - msgid "Generate SH4 FPU-less code" - msgstr "Генерировать код для SH4 без FPU" - --#: config/sh/sh.opt:102 -+#: config/sh/sh.opt:106 - #, fuzzy - msgid "Generate SH4-100 FPU-less code" - msgstr "Генерировать код для SH4 без FPU" - --#: config/sh/sh.opt:106 -+#: config/sh/sh.opt:110 - #, fuzzy - msgid "Generate SH4-200 FPU-less code" - msgstr "Генерировать код для SH4 без FPU" - --#: config/sh/sh.opt:110 -+#: config/sh/sh.opt:114 - #, fuzzy - msgid "Generate SH4-300 FPU-less code" - msgstr "Генерировать код для SH4 без FPU" - --#: config/sh/sh.opt:114 -+#: config/sh/sh.opt:118 - #, fuzzy - msgid "Generate code for SH4 340 series (MMU/FPU-less)" - msgstr "Генерировать код для процессора C30" - --#: config/sh/sh.opt:119 -+#: config/sh/sh.opt:123 - #, fuzzy - msgid "Generate code for SH4 400 series (MMU/FPU-less)" - msgstr "Генерировать код для процессора C40" - --#: config/sh/sh.opt:124 -+#: config/sh/sh.opt:128 - #, fuzzy - msgid "Generate code for SH4 500 series (FPU-less)." - msgstr "Генерировать код для процессора C40" - --#: config/sh/sh.opt:129 -+#: config/sh/sh.opt:133 - msgid "Generate default single-precision SH4 code" - msgstr "Генерировать код SH4 с одинарной точностью по умолчанию" - --#: config/sh/sh.opt:133 -+#: config/sh/sh.opt:137 - #, fuzzy - msgid "Generate default single-precision SH4-100 code" - msgstr "Генерировать код SH4 с одинарной точностью по умолчанию" - --#: config/sh/sh.opt:137 -+#: config/sh/sh.opt:141 - #, fuzzy - msgid "Generate default single-precision SH4-200 code" - msgstr "Генерировать код SH4 с одинарной точностью по умолчанию" - --#: config/sh/sh.opt:141 -+#: config/sh/sh.opt:145 - #, fuzzy - msgid "Generate default single-precision SH4-300 code" - msgstr "Генерировать код SH4 с одинарной точностью по умолчанию" - --#: config/sh/sh.opt:145 -+#: config/sh/sh.opt:149 - msgid "Generate only single-precision SH4 code" - msgstr "Генерировать только код SH4 с одинарной точностью" - --#: config/sh/sh.opt:149 -+#: config/sh/sh.opt:153 - #, fuzzy - msgid "Generate only single-precision SH4-100 code" - msgstr "Генерировать только код SH4 с одинарной точностью" - --#: config/sh/sh.opt:153 -+#: config/sh/sh.opt:157 - #, fuzzy - msgid "Generate only single-precision SH4-200 code" - msgstr "Генерировать только код SH4 с одинарной точностью" - --#: config/sh/sh.opt:157 -+#: config/sh/sh.opt:161 - #, fuzzy - msgid "Generate only single-precision SH4-300 code" - msgstr "Генерировать только код SH4 с одинарной точностью" - --#: config/sh/sh.opt:161 -+#: config/sh/sh.opt:165 - msgid "Generate SH4a code" - msgstr "Генерировать код SH4a" - --#: config/sh/sh.opt:165 -+#: config/sh/sh.opt:169 - msgid "Generate SH4a FPU-less code" - msgstr "Генерировать код для SH4a без FPU" - --#: config/sh/sh.opt:169 -+#: config/sh/sh.opt:173 - msgid "Generate default single-precision SH4a code" - msgstr "Генерировать по умолчанию код SH4a одинарной точности" - --#: config/sh/sh.opt:173 -+#: config/sh/sh.opt:177 - msgid "Generate only single-precision SH4a code" - msgstr "Генерировать только код SH4a одинарной точности" - --#: config/sh/sh.opt:177 -+#: config/sh/sh.opt:181 - msgid "Generate SH4al-dsp code" - msgstr "Генерировать SH4al-dsp код" - --#: config/sh/sh.opt:181 -+#: config/sh/sh.opt:185 - msgid "Generate 32-bit SHmedia code" - msgstr "Генерировать 32-битный код для SHmedia" - --#: config/sh/sh.opt:185 -+#: config/sh/sh.opt:189 - msgid "Generate 32-bit FPU-less SHmedia code" - msgstr "Генерировать код 32-битный код без плавающий инструкций для SHmedia" - --#: config/sh/sh.opt:189 -+#: config/sh/sh.opt:193 - msgid "Generate 64-bit SHmedia code" - msgstr "Генерировать 64-битный код для SHmedia" - --#: config/sh/sh.opt:193 -+#: config/sh/sh.opt:197 - #, fuzzy - msgid "Generate 64-bit FPU-less SHmedia code" - msgstr "Генерировать код для обратного порядка байт (big endian)" - --#: config/sh/sh.opt:197 -+#: config/sh/sh.opt:201 - #, fuzzy - msgid "Generate SHcompact code" - msgstr "Генерировать код SA" - --#: config/sh/sh.opt:201 -+#: config/sh/sh.opt:205 - #, fuzzy - msgid "Generate FPU-less SHcompact code" - msgstr "Генерировать код относительно pc" - --#: config/sh/sh.opt:213 -+#: config/sh/sh.opt:217 - #, fuzzy - msgid "Generate code in big endian mode" - msgstr "Генерировать код для прямого (big endian) порядка байт" - --#: config/sh/sh.opt:217 -+#: config/sh/sh.opt:221 - #, fuzzy - msgid "Generate 32-bit offsets in switch tables" - msgstr "Генерировать 4-байтные элементы в таблицах переключателей" - --#: config/sh/sh.opt:221 -+#: config/sh/sh.opt:225 - #, fuzzy - msgid "Generate bit instructions" - msgstr "Генерировать команды isel" - --#: config/sh/sh.opt:225 -+#: config/sh/sh.opt:229 - #, fuzzy - msgid "Cost to assume for a branch insn" - msgstr "Цена для инструкции gettr" - --#: config/sh/sh.opt:229 -+#: config/sh/sh.opt:233 - msgid "Assume that zero displacement conditional branches are fast" - msgstr "" - --#: config/sh/sh.opt:233 -+#: config/sh/sh.opt:237 - msgid "Enable cbranchdi4 pattern" - msgstr "" - --#: config/sh/sh.opt:237 -+#: config/sh/sh.opt:241 - msgid "Emit cmpeqdi_t pattern even when -mcbranchdi is in effect." - msgstr "" - --#: config/sh/sh.opt:241 -+#: config/sh/sh.opt:245 - msgid "Enable SH5 cut2 workaround" - msgstr "" - --#: config/sh/sh.opt:245 -+#: config/sh/sh.opt:249 - #, fuzzy - msgid "Align doubles at 64-bit boundaries" - msgstr "Выравнивать переменные по границе 16 бит" - --#: config/sh/sh.opt:249 -+#: config/sh/sh.opt:253 - msgid "Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table" - msgstr "" - --#: config/sh/sh.opt:253 -+#: config/sh/sh.opt:257 - msgid "Specify name for 32 bit signed division function" - msgstr "Задать имя для функции деления 32-битных чисел со знаком" - --#: config/sh/sh.opt:257 -+#: config/sh/sh.opt:261 - msgid "Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required." - msgstr "" - --#: config/sh/sh.opt:265 -+#: config/sh/sh.opt:269 - msgid "Cost to assume for gettr insn" - msgstr "Цена для инструкции gettr" - --#: config/sh/sh.opt:269 config/sh/sh.opt:319 -+#: config/sh/sh.opt:273 config/sh/sh.opt:323 - msgid "Follow Renesas (formerly Hitachi) / SuperH calling conventions" - msgstr "Следовать соглашениям о вызовах Renesas (бывшая Hitachi) для SuperH" - --#: config/sh/sh.opt:273 -+#: config/sh/sh.opt:277 - #, fuzzy --#| msgid "Increase the IEEE compliance for floating-point code" - msgid "Increase the IEEE compliance for floating-point comparisons" - msgstr "Увеличить соответствие кода для плавающей арифметики стандарту IEEE" - --#: config/sh/sh.opt:277 -+#: config/sh/sh.opt:281 - msgid "Enable the use of the indexed addressing mode for SHmedia32/SHcompact" - msgstr "" - --#: config/sh/sh.opt:281 -+#: config/sh/sh.opt:285 - #, fuzzy - msgid "inline code to invalidate instruction cache entries after setting up nested function trampolines" - msgstr "Генерировать вызов библиотечной функции для сброса кэша инструкций после исправления трамплина" - --#: config/sh/sh.opt:285 -+#: config/sh/sh.opt:289 - msgid "Assume symbols might be invalid" - msgstr "Предполагать, что символы могут быть неправильными" - --#: config/sh/sh.opt:289 -+#: config/sh/sh.opt:293 - msgid "Annotate assembler instructions with estimated addresses" - msgstr "" - --#: config/sh/sh.opt:293 -+#: config/sh/sh.opt:297 - msgid "Generate code in little endian mode" - msgstr "Генерировать код для обратного (little endian) порядка байт" - --#: config/sh/sh.opt:297 -+#: config/sh/sh.opt:301 - msgid "Mark MAC register as call-clobbered" - msgstr "Регистр MAC портится при вызовах" - --#: config/sh/sh.opt:303 -+#: config/sh/sh.opt:307 - msgid "Make structs a multiple of 4 bytes (warning: ABI altered)" - msgstr "Размер структуры кратен 4 байтам (предупреждение: при этом изменяется ABI)" - --#: config/sh/sh.opt:307 -+#: config/sh/sh.opt:311 - msgid "Emit function-calls using global offset table when generating PIC" - msgstr "Вызывать функции с использованием глобальной таблицы смещений при генерации PIC кода" - --#: config/sh/sh.opt:311 -+#: config/sh/sh.opt:315 - msgid "Assume pt* instructions won't trap" - msgstr "Предполагать, что команды pt* не вызывают прерываний" - --#: config/sh/sh.opt:315 -+#: config/sh/sh.opt:319 - msgid "Shorten address references during linking" - msgstr "Укорачивать ссылки по адресу во время компоновки" - --#: config/sh/sh.opt:323 -+#: config/sh/sh.opt:327 - msgid "Deprecated. Use -matomic= instead to select the atomic model" - msgstr "" - --#: config/sh/sh.opt:327 -+#: config/sh/sh.opt:331 - #, fuzzy - msgid "Specify the model for atomic operations" - msgstr "Генерировать код для прямого (big endian) порядка байт" - --#: config/sh/sh.opt:331 -+#: config/sh/sh.opt:335 - msgid "Use tas.b instruction for __atomic_test_and_set" - msgstr "" - --#: config/sh/sh.opt:335 -+#: config/sh/sh.opt:339 - #, fuzzy - msgid "Deprecated. Use -Os instead" - msgstr "Ключ устарел. используйте -Os в качестве замены" - --#: config/sh/sh.opt:339 -+#: config/sh/sh.opt:343 - msgid "Cost to assume for a multiply insn" - msgstr "Цена за команду умножения" - --#: config/sh/sh.opt:343 -+#: config/sh/sh.opt:347 - msgid "Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode." - msgstr "" - --#: config/sh/sh.opt:349 -+#: config/sh/sh.opt:353 - msgid "Pretend a branch-around-a-move is a conditional move." - msgstr "" - --#: config/sh/sh.opt:353 -+#: config/sh/sh.opt:357 - #, fuzzy --#| msgid "Enable the use of the short load instructions" - msgid "Enable the use of the fsca instruction" - msgstr "Включить использование коротких команд загрузки" - --#: config/sh/sh.opt:357 -+#: config/sh/sh.opt:361 - #, fuzzy --#| msgid "Enable the use of the short load instructions" - msgid "Enable the use of the fsrra instruction" - msgstr "Включить использование коротких команд загрузки" - -@@ -10972,7 +10949,6 @@ - - #: config/mips/mips.opt:274 - #, fuzzy --#| msgid "Use MIPS-3D instructions" - msgid "Use MCU instructions" - msgstr "Использовать команды MIPS-3D" - -@@ -11076,7 +11052,6 @@ - - #: config/tilegx/tilegx.opt:45 - #, fuzzy --#| msgid "Use given x86-64 code model" - msgid "Use given TILE-Gx code model" - msgstr "Использовать указанную модель кода x86-64" - -@@ -11243,7 +11218,6 @@ - - #: common.opt:453 - #, fuzzy --#| msgid "Optimize for space rather than speed" - msgid "Optimize for debugging experience rather than speed or size" - msgstr "Оптимизировать размер, а не быстродействие" - -@@ -11256,1647 +11230,1646 @@ - msgstr "Предупреждать о возвращении функциями структур, объединений, массивов" - - #: common.opt:510 -+msgid "Warn if a loop with constant number of iterations triggers undefined behavior" -+msgstr "" -+ -+#: common.opt:514 - msgid "Warn if an array is accessed out of bounds" - msgstr "" - --#: common.opt:514 -+#: common.opt:518 - msgid "Warn about inappropriate attribute usage" - msgstr "Предупреждать о неадекватном использовании атрибутов" - --#: common.opt:518 -+#: common.opt:522 - msgid "Warn about pointer casts which increase alignment" - msgstr "Предупреждать о приведении указательных типов с увеличением выравнивания" - --#: common.opt:522 -+#: common.opt:526 - #, fuzzy - msgid "Warn when a #warning directive is encountered" - msgstr "Предупреждать о неиспользуемых параметрах функций" - --#: common.opt:526 -+#: common.opt:530 - msgid "Warn about uses of __attribute__((deprecated)) declarations" - msgstr "Предупреждать об использовании имён, декларированных с атрибутом deprecated" - --#: common.opt:530 -+#: common.opt:534 - msgid "Warn when an optimization pass is disabled" - msgstr "Предупреждать о невыполнении заказанных оптимизаций" - --#: common.opt:534 -+#: common.opt:538 - msgid "Treat all warnings as errors" - msgstr "Все предупреждения считать ошибками" - --#: common.opt:538 -+#: common.opt:542 - #, fuzzy - msgid "Treat specified warning as error" - msgstr "Все предупреждения считать ошибками" - --#: common.opt:546 -+#: common.opt:550 - msgid "Exit on the first error occurred" - msgstr "Закончить работу при первой обнаруженной ошибке" - --#: common.opt:550 -+#: common.opt:554 - msgid "-Wframe-larger-than=\tWarn if a function's stack frame requires more than bytes" - msgstr "" - --#: common.opt:554 -+#: common.opt:558 - msgid "Warn when attempting to free a non-heap object" - msgstr "" - --#: common.opt:558 -+#: common.opt:562 - msgid "Warn when an inlined function cannot be inlined" - msgstr "Предупреждать об inline-функциях, подстановка которых невозможна" - --#: common.opt:562 -+#: common.opt:566 - msgid "Warn when an atomic memory model parameter is known to be outside the valid range." - msgstr "" - --#: common.opt:569 -+#: common.opt:573 - #, fuzzy - msgid "-Wlarger-than=\tWarn if an object is larger than bytes" - msgstr "Предупреждать об объектах, размер которых превышает <число> байт" - --#: common.opt:573 -+#: common.opt:577 - msgid "Warn if the loop cannot be optimized due to nontrivial assumptions." - msgstr "Предупреждать, если оптимизация цикла невозможна из-за нетривиальных предположений" - --#: common.opt:580 -+#: common.opt:584 - #, fuzzy - msgid "Warn about overflow in arithmetic expressions" - msgstr "переполнение при вычислении константного выражения" - --#: common.opt:584 -+#: common.opt:588 - msgid "Warn when the packed attribute has no effect on struct layout" - msgstr "Предупреждать о случаях, когда атрибут packed не влияет на " - --#: common.opt:588 -+#: common.opt:592 - msgid "Warn when padding is required to align structure members" - msgstr "Предупреждать о дырах в результате выравнивания элементов структур" - --#: common.opt:592 -+#: common.opt:596 - msgid "Issue warnings needed for strict compliance to the standard" - msgstr "Выдавать предупреждения, требуемые для соответствия стандарту" - --#: common.opt:596 -+#: common.opt:600 - msgid "Warn when one local variable shadows another" - msgstr "Предупреждать когда одна локальная переменная перекрывает другую" - --#: common.opt:600 -+#: common.opt:604 - msgid "Warn when not issuing stack smashing protection for some reason" - msgstr "Предупреждать, если защита от разрушения стека по каким-то причинам не сгенерирована" - --#: common.opt:604 -+#: common.opt:608 - msgid "Warn if stack usage might be larger than specified amount" - msgstr "" - --#: common.opt:608 common.opt:612 -+#: common.opt:612 common.opt:616 - msgid "Warn about code which might break strict aliasing rules" - msgstr "Предупреждать о возможных нарушениях правил перекрытия данных в памяти" - --#: common.opt:616 common.opt:620 -+#: common.opt:620 common.opt:624 - #, fuzzy - msgid "Warn about optimizations that assume that signed overflow is undefined" - msgstr "Отменить оптимизации, предполагающие стандартное округление вещественных значений" - --#: common.opt:624 -+#: common.opt:628 - #, fuzzy - msgid "Warn about functions which might be candidates for __attribute__((const))" - msgstr "Предупреждать о функциях, которым можно назначить атрибут noreturn" - --#: common.opt:628 -+#: common.opt:632 - #, fuzzy - msgid "Warn about functions which might be candidates for __attribute__((pure))" - msgstr "Предупреждать о функциях, которым можно назначить атрибут noreturn" - --#: common.opt:632 -+#: common.opt:636 - msgid "Warn about functions which might be candidates for __attribute__((noreturn))" - msgstr "Предупреждать о функциях, которым можно назначить атрибут noreturn" - --#: common.opt:636 -+#: common.opt:640 - msgid "Do not suppress warnings from system headers" - msgstr "Не подавлять предупреждения от системных заголовков" - --#: common.opt:640 -+#: common.opt:644 - #, fuzzy - msgid "Warn whenever a trampoline is generated" - msgstr "Предупреждать о неиспользуемых переменных" - --#: common.opt:644 -+#: common.opt:648 - #, fuzzy - msgid "Warn if a comparison is always true or always false due to the limited range of the data type" - msgstr "из-за ограниченности диапазона типа данных, результат сравнения всегда ложь" - --#: common.opt:648 -+#: common.opt:652 - msgid "Warn about uninitialized automatic variables" - msgstr "Предупреждать о неинициализированных автоматических переменных" - --#: common.opt:652 -+#: common.opt:656 - #, fuzzy - msgid "Warn about maybe uninitialized automatic variables" - msgstr "Предупреждать о неинициализированных автоматических переменных" - --#: common.opt:660 -+#: common.opt:664 - msgid "Enable all -Wunused- warnings" - msgstr "Включить все предупреждения -Wunused-" - --#: common.opt:664 -+#: common.opt:668 - #, fuzzy - msgid "Warn when a function parameter is only set, otherwise unused" - msgstr "Предупреждать о неиспользуемых параметрах функций" - --#: common.opt:668 -+#: common.opt:672 - #, fuzzy - msgid "Warn when a variable is only set, otherwise unused" - msgstr "Предупреждать о неиспользуемых переменных" - --#: common.opt:672 -+#: common.opt:676 - msgid "Warn when a function is unused" - msgstr "Предупреждать о неиспользуемых функциях" - --#: common.opt:676 -+#: common.opt:680 - msgid "Warn when a label is unused" - msgstr "Предупреждать о неиспользуемых метках" - --#: common.opt:680 -+#: common.opt:684 - msgid "Warn when a function parameter is unused" - msgstr "Предупреждать о неиспользуемых параметрах функций" - --#: common.opt:684 -+#: common.opt:688 - msgid "Warn when an expression value is unused" - msgstr "Предупреждать о неиспользованных результатах выражений" - --#: common.opt:688 -+#: common.opt:692 - msgid "Warn when a variable is unused" - msgstr "Предупреждать о неиспользуемых переменных" - --#: common.opt:692 -+#: common.opt:696 - msgid "Warn in case profiles in -fprofile-use do not match" - msgstr "" - --#: common.opt:696 -+#: common.opt:700 - msgid "Warn when a vector operation is compiled outside the SIMD" - msgstr "" - --#: common.opt:712 -+#: common.opt:716 - #, fuzzy - msgid "-aux-info \tEmit declaration information into " - msgstr "Выдать информацию о декларациях в <файл>" - --#: common.opt:731 -+#: common.opt:735 - #, fuzzy - msgid "-d\tEnable dumps from specific passes of the compiler" - msgstr "Выдать дампы от различных проходов компиляции" - --#: common.opt:735 -+#: common.opt:739 - #, fuzzy - msgid "-dumpbase \tSet the file basename to be used for dumps" - msgstr "Базовое имя файла для дампов" - --#: common.opt:739 -+#: common.opt:743 - #, fuzzy - msgid "-dumpdir \tSet the directory name to be used for dumps" - msgstr "Базовое имя файла для дампов" - --#: common.opt:798 -+#: common.opt:802 - msgid "Aggressively optimize loops using language constraints" - msgstr "" - --#: common.opt:802 -+#: common.opt:806 - msgid "Align the start of functions" - msgstr "Выравнивать начало функций" - --#: common.opt:809 -+#: common.opt:813 - msgid "Align labels which are only reached by jumping" - msgstr "Выравнивать метки, доступные только по командам переходов" - --#: common.opt:816 -+#: common.opt:820 - msgid "Align all labels" - msgstr "Выравнивать все метки" - --#: common.opt:823 -+#: common.opt:827 - msgid "Align the start of loops" - msgstr "Выравнивать начало циклов" - --#: common.opt:846 -+#: common.opt:850 - msgid "Enable AddressSanitizer, a memory error detector" - msgstr "" - --#: common.opt:850 -+#: common.opt:854 - msgid "Enable ThreadSanitizer, a data race detector" - msgstr "" - --#: common.opt:854 -+#: common.opt:858 - msgid "Generate unwind tables that are exact at each instruction boundary" - msgstr "Генерировать unwind-таблицы, корректные на начало каждой команды" - --#: common.opt:858 -+#: common.opt:862 - #, fuzzy - msgid "Generate auto-inc/dec instructions" - msgstr "Генерировать команды isel" - --#: common.opt:866 -+#: common.opt:870 - msgid "Generate code to check bounds before indexing arrays" - msgstr "Генерировать код для проверки выхода за границы массивов" - --#: common.opt:870 -+#: common.opt:874 - msgid "Replace add, compare, branch with branch on count register" - msgstr "Генерировать для циклов переход по счётчику вместо команд продвижения счётчика, сравнения и перехода" - --#: common.opt:874 -+#: common.opt:878 - msgid "Use profiling information for branch probabilities" - msgstr "Оценивать вероятность переходов на основе данных профилирования" - --#: common.opt:878 -+#: common.opt:882 - msgid "Perform branch target load optimization before prologue / epilogue threading" - msgstr "Оптимизировать чтение из памяти в точках, куда передается управление, до генерации прологов и эпилогов" - --#: common.opt:882 -+#: common.opt:886 - msgid "Perform branch target load optimization after prologue / epilogue threading" - msgstr "Оптимизировать чтение из памяти в точках, куда передается управление, после генерации прологов и эпилогов" - --#: common.opt:886 -+#: common.opt:890 - msgid "Restrict target load migration not to re-use registers in any basic block" - msgstr "Ограничить миграцию регистров, в которые помещаются целевые адреса переходов, чтобы не переиспользовать эти регистры ни в каких блоках" - --#: common.opt:890 -+#: common.opt:894 - #, fuzzy - msgid "-fcall-saved-\tMark as being preserved across functions" - msgstr "Считать, что <регистр> сохраняется при вызовах функций" - --#: common.opt:894 -+#: common.opt:898 - #, fuzzy - msgid "-fcall-used-\tMark as being corrupted by function calls" - msgstr "Считать, что <регистр> портится при вызовах функций" - --#: common.opt:901 -+#: common.opt:905 - msgid "Save registers around function calls" - msgstr "Сохранять/восстанавливать регистры до/после вызовов функций" - --#: common.opt:905 -+#: common.opt:909 - msgid "Compare the results of several data dependence analyzers." - msgstr "" - --#: common.opt:909 -+#: common.opt:913 - msgid "Looks for opportunities to reduce stack adjustments and stack references." - msgstr "" - --#: common.opt:913 -+#: common.opt:917 - msgid "Do not put uninitialized globals in the common section" - msgstr "Не размещать неинициализированные глобальные данные в общих блоках" - --#: common.opt:921 -+#: common.opt:925 - msgid "-fcompare-debug[=]\tCompile with and without e.g. -gtoggle, and compare the final-insns dump" - msgstr "" - --#: common.opt:925 -+#: common.opt:929 - msgid "Run only the second compilation of -fcompare-debug" - msgstr "" - --#: common.opt:929 -+#: common.opt:933 - #, fuzzy - msgid "Perform comparison elimination after register allocation has finished" - msgstr "Выполнить глобальную экономию общих подвыражений после распределения регистров" - --#: common.opt:933 -+#: common.opt:937 - msgid "Do not perform optimizations increasing noticeably stack usage" - msgstr "" - --#: common.opt:937 -+#: common.opt:941 - msgid "Perform a register copy-propagation optimization pass" - msgstr "Выполнить оптимизацию распространения копий регистров" - --#: common.opt:941 -+#: common.opt:945 - msgid "Perform cross-jumping optimization" - msgstr "Выполнить оптимизацию кода вокруг команд передачи управления" - --#: common.opt:945 -+#: common.opt:949 - msgid "When running CSE, follow jumps to their targets" - msgstr "При экономии общих подвыражений прослеживать код, доступный по переходам" - --#: common.opt:953 -+#: common.opt:957 - msgid "Omit range reduction step when performing complex division" - msgstr "Отбрасывать шаг редукции отрезка при выполнении комплексного деления" - --#: common.opt:957 -+#: common.opt:961 - msgid "Complex multiplication and division follow Fortran rules" - msgstr "" - --#: common.opt:961 -+#: common.opt:965 - msgid "Place data items into their own section" - msgstr "Размещать элементы данных в отдельных секциях" - --#: common.opt:965 -+#: common.opt:969 - msgid "List all available debugging counters with their limits and counts." - msgstr "" - --#: common.opt:969 -+#: common.opt:973 - msgid "-fdbg-cnt=:[,:,...]\tSet the debug counter limit. " - msgstr "" - --#: common.opt:973 -+#: common.opt:977 - msgid "Map one directory name to another in debug information" - msgstr "" - --#: common.opt:977 -+#: common.opt:981 - msgid "Output .debug_types section when using DWARF v4 debuginfo." - msgstr "" - --#: common.opt:983 -+#: common.opt:987 - msgid "Defer popping functions args from stack until later" - msgstr "Откладывать \"на потом\" выталкивание аргументов из стека после вызовов функций" - --#: common.opt:987 -+#: common.opt:991 - msgid "Attempt to fill delay slots of branch instructions" - msgstr "Заполнять гнезда задержки команд перехода" - --#: common.opt:991 -+#: common.opt:995 - msgid "Delete dead instructions that may throw exceptions" - msgstr "" - --#: common.opt:995 -+#: common.opt:999 - msgid "Delete useless null pointer checks" - msgstr "Удалять ненужные сравнения указателей с нулем" - --#: common.opt:999 -+#: common.opt:1003 - msgid "Try to convert virtual calls to direct ones." - msgstr "" - --#: common.opt:1003 -+#: common.opt:1007 - #, fuzzy - msgid "-fdiagnostics-show-location=[once|every-line]\tHow often to emit source location at the beginning of line-wrapped diagnostics" - msgstr "Выдавать местоположение источника сообщения один раз или для каждой строки (для многострочных сообщений)" - --#: common.opt:1020 -+#: common.opt:1024 - msgid "Show the source line with a caret indicating the column" - msgstr "" - --#: common.opt:1024 -+#: common.opt:1028 - msgid "Amend appropriate diagnostic messages with the command line option that controls them" - msgstr "Дополнять диагностические сообщения ключом, который контролирует это сообщение" - --#: common.opt:1028 -+#: common.opt:1032 - msgid "-fdisable-[tree|rtl|ipa]-=range1+range2 disables an optimization pass" - msgstr "" - --#: common.opt:1032 -+#: common.opt:1036 - msgid "-fenable-[tree|rtl|ipa]-=range1+range2 enables an optimization pass" - msgstr "" - --#: common.opt:1036 -+#: common.opt:1040 - #, fuzzy - msgid "-fdump-\tDump various compiler internals to a file" - msgstr "Выдать внутреннюю информацию компилятора в файл" - --#: common.opt:1043 -+#: common.opt:1047 - msgid "-fdump-final-insns=filename\tDump to filename the insns at the end of translation" - msgstr "" - --#: common.opt:1047 -+#: common.opt:1051 - msgid "-fdump-go-spec=filename\tWrite all declarations to file as Go code" - msgstr "" - --#: common.opt:1051 -+#: common.opt:1055 - #, fuzzy - msgid "Suppress output of addresses in debugging dumps" - msgstr "Подавлять вывод номеров инструкций и номеров строк в отладочных дампах" - --#: common.opt:1055 -+#: common.opt:1059 - #, fuzzy - msgid "Dump optimization passes" - msgstr "Выполнить полную оптимизацию перемещения регистров" - --#: common.opt:1059 -+#: common.opt:1063 - #, fuzzy - msgid "Suppress output of instruction numbers, line number notes and addresses in debugging dumps" - msgstr "Подавлять вывод номеров инструкций и номеров строк в отладочных дампах" - --#: common.opt:1063 -+#: common.opt:1067 - #, fuzzy - msgid "Suppress output of previous and next insn numbers in debugging dumps" - msgstr "Подавлять вывод номеров инструкций и номеров строк в отладочных дампах" - --#: common.opt:1067 -+#: common.opt:1071 - msgid "Enable CFI tables via GAS assembler directives." - msgstr "" - --#: common.opt:1071 -+#: common.opt:1075 - msgid "Perform early inlining" - msgstr "Выполнить inline-подстановки на ранних проходах оптимизации" - --#: common.opt:1075 -+#: common.opt:1079 - msgid "Perform DWARF2 duplicate elimination" - msgstr "Исключить дублирование информации DWARF2" - --#: common.opt:1079 -+#: common.opt:1083 - #, fuzzy - msgid "Perform interprocedural reduction of aggregates" - msgstr "Выполнить межпроцедурное распространение констант" - --#: common.opt:1083 common.opt:1087 -+#: common.opt:1087 common.opt:1091 - msgid "Perform unused type elimination in debug info" - msgstr "Исключить отладочную информацию о неиспользуемых типах" - --#: common.opt:1091 -+#: common.opt:1095 - msgid "Do not suppress C++ class debug information." - msgstr "" - --#: common.opt:1095 -+#: common.opt:1099 - msgid "Enable exception handling" - msgstr "Активировать обработку исключительных ситуаций" - --#: common.opt:1099 -+#: common.opt:1103 - msgid "Perform a number of minor, expensive optimizations" - msgstr "Выполнить некоторые дополнительные дорогостоящие оптимизации" - --#: common.opt:1103 -+#: common.opt:1107 - msgid "-fexcess-precision=[fast|standard]\tSpecify handling of excess floating-point precision" - msgstr "" - --#: common.opt:1106 -+#: common.opt:1110 - #, fuzzy, c-format - msgid "unknown excess precision style %qs" - msgstr "неизвестный стиль декодирования имён '%s'" - --#: common.opt:1119 -+#: common.opt:1123 - msgid "Output lto objects containing both the intermediate language and binary output." - msgstr "" - --#: common.opt:1123 -+#: common.opt:1127 - msgid "Assume no NaNs or infinities are generated" - msgstr "Предполагать что результаты вычислений конечны и не NaN" - --#: common.opt:1127 -+#: common.opt:1131 - #, fuzzy - msgid "-ffixed-\tMark as being unavailable to the compiler" - msgstr "Не использовать <регистр> при генерации кода" - --#: common.opt:1131 -+#: common.opt:1135 - msgid "Don't allocate floats and doubles in extended-precision registers" - msgstr "Не выделять для значений типа float и double регистры повышенной точности" - --#: common.opt:1139 -+#: common.opt:1143 - #, fuzzy - msgid "Perform a forward propagation pass on RTL" - msgstr "Выполнить оптимизацию распространения диапазонов значений на древовидном представлении" - --#: common.opt:1143 -+#: common.opt:1147 - msgid "-ffp-contract=[off|on|fast] Perform floating-point expression contraction." - msgstr "" - --#: common.opt:1146 -+#: common.opt:1150 - #, fuzzy, c-format - msgid "unknown floating point contraction style %qs" - msgstr "не плавающий аргумент в вызове функции %qs" - --#: common.opt:1163 -+#: common.opt:1167 - msgid "Allow function addresses to be held in registers" - msgstr "Разрешить хранение адресов функций на регистрах" - --#: common.opt:1167 -+#: common.opt:1171 - msgid "Place each function into its own section" - msgstr "Помещать каждую функцию в отдельную секцию" - --#: common.opt:1171 -+#: common.opt:1175 - msgid "Perform global common subexpression elimination" - msgstr "Выполнить глобальную экономию общих подвыражений" - --#: common.opt:1175 -+#: common.opt:1179 - msgid "Perform enhanced load motion during global common subexpression elimination" - msgstr "В рамках глобальной экономии общих подвыражений выполнить расширенный перенос чтений из памяти между блоками" - --#: common.opt:1179 -+#: common.opt:1183 - msgid "Perform store motion after global common subexpression elimination" - msgstr "В рамках глобальной экономии общих подвыражений выполнить перенос записей в память между блоками" - --#: common.opt:1183 -+#: common.opt:1187 - msgid "Perform redundant load after store elimination in global common subexpression" - msgstr "В рамках глобальной экономии общих подвыражений исключать лишние чтения из памяти после записей по тем же адресам" - --#: common.opt:1188 -+#: common.opt:1192 - msgid "Perform global common subexpression elimination after register allocation" - msgstr "Выполнить глобальную экономию общих подвыражений после распределения регистров" - --#: common.opt:1194 -+#: common.opt:1198 - #, fuzzy - msgid "Enable in and out of Graphite representation" - msgstr "Выполнить оптимизацию удаления мертвых команд записи в память" - --#: common.opt:1198 -+#: common.opt:1202 - #, fuzzy - msgid "Enable Graphite Identity transformation" - msgstr "Выдавать граф вызовов" - --#: common.opt:1202 -+#: common.opt:1206 - #, fuzzy - msgid "Enable hoisting adjacent loads to encourage generating conditional move" - msgstr "Использовать условные команды move" - --#: common.opt:1207 -+#: common.opt:1211 - msgid "Mark all loops as parallel" - msgstr "" - --#: common.opt:1211 -+#: common.opt:1215 - msgid "Enable Loop Strip Mining transformation" - msgstr "" - --#: common.opt:1215 -+#: common.opt:1219 - msgid "Enable Loop Interchange transformation" - msgstr "" - --#: common.opt:1219 -+#: common.opt:1223 - #, fuzzy - msgid "Enable Loop Blocking transformation" - msgstr "Включить линейные трансформации циклов на древовидном представлении" - --#: common.opt:1223 -+#: common.opt:1227 - msgid "Enable support for GNU transactional memory" - msgstr "" - --#: common.opt:1231 -+#: common.opt:1235 - msgid "Enable the ISL based loop nest optimizer" - msgstr "" - --#: common.opt:1235 -+#: common.opt:1239 - msgid "Force bitfield accesses to match their type width" - msgstr "" - --#: common.opt:1239 -+#: common.opt:1243 - msgid "Enable guessing of branch probabilities" - msgstr "Оценивать вероятности переходов" - --#: common.opt:1247 -+#: common.opt:1251 - msgid "Process #ident directives" - msgstr "Обрабатывать директивы #ident" - --#: common.opt:1251 -+#: common.opt:1255 - msgid "Perform conversion of conditional jumps to branchless equivalents" - msgstr "Преобразовывать условные переходы в эквивалентный код без переходов" - --#: common.opt:1255 -+#: common.opt:1259 - msgid "Perform conversion of conditional jumps to conditional execution" - msgstr "Преобразовывать условные переходы в условно выполняемый код" - --#: common.opt:1259 -+#: common.opt:1263 - msgid "-fstack-reuse=[all|named_vars|none] Set stack reuse level for local variables." - msgstr "" - --#: common.opt:1262 -+#: common.opt:1266 - #, fuzzy, c-format - msgid "unknown Stack Reuse Level %qs" - msgstr "неизвестная машинный режим %qs" - --#: common.opt:1275 -+#: common.opt:1279 - #, fuzzy - msgid "Convert conditional jumps in innermost loops to branchless equivalents" - msgstr "Преобразовывать условные переходы в эквивалентный код без переходов" - --#: common.opt:1279 -+#: common.opt:1283 - msgid "Also if-convert conditional jumps containing memory writes" - msgstr "" - --#: common.opt:1287 -+#: common.opt:1291 - msgid "Do not generate .size directives" - msgstr "Не генерировать директивы .size" - --#: common.opt:1291 -+#: common.opt:1295 - #, fuzzy - msgid "Perform indirect inlining" - msgstr "Выполнить inline-подстановки на ранних проходах оптимизации" - --#: common.opt:1297 -+#: common.opt:1301 - msgid "Enable inlining of function declared \"inline\", disabling disables all inlining" - msgstr "" - --#: common.opt:1301 -+#: common.opt:1305 - #, fuzzy - msgid "Integrate functions into their callers when code size is known not to grow" - msgstr "Подставлять тела простых функций в места вызовов" - --#: common.opt:1305 -+#: common.opt:1309 - #, fuzzy - msgid "Integrate functions not declared \"inline\" into their callers when profitable" - msgstr "Подставлять тела функций, вызываемых один раз, в места вызовов" - --#: common.opt:1309 -+#: common.opt:1313 - #, fuzzy - msgid "Integrate functions only required by their single caller" - msgstr "Подставлять тела функций, вызываемых один раз, в места вызовов" - --#: common.opt:1316 -+#: common.opt:1320 - #, fuzzy - msgid "-finline-limit=\tLimit the size of inlined functions to " - msgstr "Максимальный <размер> функций для inline-подстановки" - --#: common.opt:1320 -+#: common.opt:1324 - msgid "Inline __atomic operations when a lock free instruction sequence is available." - msgstr "" - --#: common.opt:1324 -+#: common.opt:1328 - msgid "Instrument function entry and exit with profiling calls" - msgstr "При входе и выходе из функции генерировать вызовы профилирования" - --#: common.opt:1328 -+#: common.opt:1332 - msgid "-finstrument-functions-exclude-function-list=name,... Do not instrument listed functions" - msgstr "" - --#: common.opt:1332 -+#: common.opt:1336 - msgid "-finstrument-functions-exclude-file-list=filename,... Do not instrument functions listed in files" - msgstr "" - --#: common.opt:1336 -+#: common.opt:1340 - msgid "Perform Interprocedural constant propagation" - msgstr "Выполнить межпроцедурное распространение констант" - --#: common.opt:1340 -+#: common.opt:1344 - #, fuzzy - msgid "Perform cloning to make Interprocedural constant propagation stronger" - msgstr "Выполнить межпроцедурное распространение констант" - --#: common.opt:1344 -+#: common.opt:1348 - #, fuzzy - msgid "Perform interprocedural profile propagation" - msgstr "Выполнить межпроцедурное распространение констант" - --#: common.opt:1348 -+#: common.opt:1352 - #, fuzzy - msgid "Perform interprocedural points-to analysis" - msgstr "Выполнить межпроцедурное распространение констант" - --#: common.opt:1352 -+#: common.opt:1356 - msgid "Discover pure and const functions" - msgstr "Выявлять pure и const функции" - --#: common.opt:1356 -+#: common.opt:1360 - msgid "Discover readonly and non addressable static variables" - msgstr "Выявлять неадресуемые статические переменные, доступные только для чтения" - --#: common.opt:1368 -+#: common.opt:1372 - msgid "-fira-algorithm=[CB|priority] Set the used IRA algorithm" - msgstr "" - --#: common.opt:1371 -+#: common.opt:1375 - #, fuzzy, c-format - msgid "unknown IRA algorithm %qs" - msgstr "неизвестная машинный режим %qs" - --#: common.opt:1381 -+#: common.opt:1385 - msgid "-fira-region=[one|all|mixed] Set regions for IRA" - msgstr "" - --#: common.opt:1384 -+#: common.opt:1388 - #, fuzzy, c-format - msgid "unknown IRA region %qs" - msgstr "неизвестное имя регистра: %s" - --#: common.opt:1397 common.opt:1402 -+#: common.opt:1401 common.opt:1406 - msgid "Use IRA based register pressure calculation" - msgstr "" - --#: common.opt:1407 -+#: common.opt:1411 - msgid "Share slots for saving different hard registers." - msgstr "" - --#: common.opt:1411 -+#: common.opt:1415 - msgid "Share stack slots for spilled pseudo-registers." - msgstr "" - --#: common.opt:1415 -+#: common.opt:1419 - msgid "-fira-verbose=\tControl IRA's level of diagnostic messages." - msgstr "" - --#: common.opt:1419 -+#: common.opt:1423 - msgid "Optimize induction variables on trees" - msgstr "Оптимизировать индуктивные переменные в древовидном представлении" - --#: common.opt:1423 -+#: common.opt:1427 - msgid "Use jump tables for sufficiently large switch statements" - msgstr "Использовать таблицы переходов для достаточно больших операторов switch" - --#: common.opt:1427 -+#: common.opt:1431 - msgid "Generate code for functions even if they are fully inlined" - msgstr "Генерировать код для функций даже при 100%% inline-подстановке" - --#: common.opt:1431 -+#: common.opt:1435 - msgid "Emit static const variables even if they are not used" - msgstr "Не удалять даже неиспользуемые статические константные переменные" - --#: common.opt:1435 -+#: common.opt:1439 - msgid "Give external symbols a leading underscore" - msgstr "Добавлять в начало внешних символов подчеркивание" - --#: common.opt:1443 -+#: common.opt:1447 - #, fuzzy - msgid "Enable link-time optimization." - msgstr "Включить оптимизации компоновки" - --#: common.opt:1447 -+#: common.opt:1451 - msgid "Link-time optimization with number of parallel jobs or jobserver." - msgstr "" - --#: common.opt:1451 -+#: common.opt:1455 - msgid "Partition symbols and vars at linktime based on object files they originate from" - msgstr "" - --#: common.opt:1455 -+#: common.opt:1459 - msgid "Partition functions and vars at linktime into approximately same sized buckets" - msgstr "" - --#: common.opt:1459 -+#: common.opt:1463 - msgid "Put every symbol into separate partition" - msgstr "" - --#: common.opt:1463 -+#: common.opt:1467 - #, fuzzy - msgid "Disable partioning and streaming" - msgstr "Не использовать индексную адресацию" - --#: common.opt:1468 -+#: common.opt:1472 - msgid "-flto-compression-level=\tUse zlib compression level for IL" - msgstr "" - --#: common.opt:1472 -+#: common.opt:1476 - #, fuzzy - msgid "Report various link-time optimization statistics" - msgstr "Выполнить оптимизацию переименования регистров" - --#: common.opt:1476 -+#: common.opt:1480 - msgid "Set errno after built-in math functions" - msgstr "Устанавливать errno после вызовов встроенных мат. функций" - --#: common.opt:1480 -+#: common.opt:1484 - #, fuzzy - msgid "-fmax-errors=\tMaximum number of errors to report" - msgstr "Максимальный коэффициент развертки цикла" - --#: common.opt:1484 -+#: common.opt:1488 - msgid "Report on permanent memory allocation" - msgstr "Вывести информацию о распределении памяти" - --#: common.opt:1488 -+#: common.opt:1492 - #, fuzzy --#| msgid "Report on permanent memory allocation" - msgid "Report on permanent memory allocation in WPA only" - msgstr "Вывести информацию о распределении памяти" - --#: common.opt:1495 -+#: common.opt:1499 - msgid "Attempt to merge identical constants and constant variables" - msgstr "Слить идентичные константы и константные переменные" - --#: common.opt:1499 -+#: common.opt:1503 - msgid "Attempt to merge identical constants across compilation units" - msgstr "Слить идентичные константы по всем единицам компиляции" - --#: common.opt:1503 -+#: common.opt:1507 - #, fuzzy - msgid "Attempt to merge identical debug strings across compilation units" - msgstr "Слить идентичные константы по всем единицам компиляции" - --#: common.opt:1507 -+#: common.opt:1511 - #, fuzzy - msgid "-fmessage-length=\tLimit diagnostics to characters per line. 0 suppresses line-wrapping" - msgstr "Установить <длину> строк диагностических сообщений в символах. 0 - подавить разбиение на строки" - --#: common.opt:1511 -+#: common.opt:1515 - msgid "Perform SMS based modulo scheduling before the first scheduling pass" - msgstr "Выполнять планирование циклов по модулю методом SMS перед первым проходом планирования команд" - --#: common.opt:1515 -+#: common.opt:1519 - #, fuzzy - msgid "Perform SMS based modulo scheduling with register moves allowed" - msgstr "Выполнять планирование циклов по модулю методом SMS перед первым проходом планирования команд" - --#: common.opt:1519 -+#: common.opt:1523 - msgid "Move loop invariant computations out of loops" - msgstr "Выносить инвариантные вычисления за пределы циклов" - --#: common.opt:1523 -+#: common.opt:1527 - #, fuzzy - msgid "Use the RTL dead code elimination pass" - msgstr "Выполнить оптимизацию удаления мертвых команд записи в память" - --#: common.opt:1527 -+#: common.opt:1531 - #, fuzzy - msgid "Use the RTL dead store elimination pass" - msgstr "Выполнить оптимизацию удаления мертвых команд записи в память" - --#: common.opt:1531 -+#: common.opt:1535 - msgid "Enable/Disable the traditional scheduling in loops that already passed modulo scheduling" - msgstr "Включить/отменить обычное планирование для конвейеризованных циклов" - --#: common.opt:1535 -+#: common.opt:1539 - msgid "Support synchronous non-call exceptions" - msgstr "Поддерживать синхронные исключения вне вызовов" - --#: common.opt:1539 -+#: common.opt:1543 - msgid "When possible do not generate stack frames" - msgstr "По возможности не создавать кадры стека" - --#: common.opt:1543 -+#: common.opt:1547 - #, fuzzy --#| msgid "Enable loop optimizations on tree level" - msgid "Enable all optimization info dumps on stderr" - msgstr "Включить оптимизации циклов на древовидном представлении" - --#: common.opt:1547 -+#: common.opt:1551 - msgid "-fopt-info[-=filename]\tDump compiler optimization details" - msgstr "" - --#: common.opt:1551 -+#: common.opt:1555 - msgid "Do the full register move optimization pass" - msgstr "Выполнить полную оптимизацию перемещения регистров" - --#: common.opt:1555 -+#: common.opt:1559 - msgid "Optimize sibling and tail recursive calls" - msgstr "Оптимизировать парные вызовы и хвостовую рекурсию" - --#: common.opt:1559 -+#: common.opt:1563 - #, fuzzy - msgid "Perform partial inlining" - msgstr "Выполнить inline-подстановки на ранних проходах оптимизации" - --#: common.opt:1563 common.opt:1567 -+#: common.opt:1567 common.opt:1571 - msgid "Report on memory allocation before interprocedural optimization" - msgstr "" - --#: common.opt:1571 -+#: common.opt:1575 - msgid "Pack structure members together without holes" - msgstr "Паковать поля структур без дыр" - --#: common.opt:1575 -+#: common.opt:1579 - #, fuzzy - msgid "-fpack-struct=\tSet initial maximum structure member alignment" - msgstr "Установить начальное максимальное выравнивание для элементов структур" - --#: common.opt:1579 -+#: common.opt:1583 - msgid "Return small aggregates in memory, not registers" - msgstr "Возвращать короткие агрегатные значения в памяти, а не в регистрах" - --#: common.opt:1583 -+#: common.opt:1587 - msgid "Perform loop peeling" - msgstr "Выполнить раскатку циклов" - --#: common.opt:1587 -+#: common.opt:1591 - msgid "Enable machine specific peephole optimizations" - msgstr "Выполнить машинно-зависимые оптимизации" - --#: common.opt:1591 -+#: common.opt:1595 - msgid "Enable an RTL peephole pass before sched2" - msgstr "Выполнить машинно-зависимые оптимизации перед вторым планированием" - --#: common.opt:1595 -+#: common.opt:1599 - msgid "Generate position-independent code if possible (large mode)" - msgstr "Генерировать позиционно-независимый код, если возможно (режим large)" - --#: common.opt:1599 -+#: common.opt:1603 - msgid "Generate position-independent code for executables if possible (large mode)" - msgstr "Генерировать позиционно-независимый код для выполняемых модулей, если возможно (режим large)" - --#: common.opt:1603 -+#: common.opt:1607 - msgid "Generate position-independent code if possible (small mode)" - msgstr "Генерировать позиционно-независимый код, если возможно (режим small)" - --#: common.opt:1607 -+#: common.opt:1611 - msgid "Generate position-independent code for executables if possible (small mode)" - msgstr "Генерировать позиционно-независимый код для выполняемых модулей, если возможно (режим small)" - --#: common.opt:1611 -+#: common.opt:1615 - #, fuzzy - msgid "Specify a plugin to load" - msgstr "Задать ключи GNAT" - --#: common.opt:1615 -+#: common.opt:1619 - msgid "-fplugin-arg--[=]\tSpecify argument = for plugin " - msgstr "" - --#: common.opt:1619 -+#: common.opt:1623 - #, fuzzy - msgid "Run predictive commoning optimization." - msgstr "Выполнить оптимизацию перемещения регистров" - --#: common.opt:1623 -+#: common.opt:1627 - msgid "Generate prefetch instructions, if available, for arrays in loops" - msgstr "Генерировать команды предвыборки элементов массивов, если они поддерживаются" - --#: common.opt:1627 -+#: common.opt:1631 - msgid "Enable basic program profiling code" - msgstr "Включить генерацию базового кода для профилирования" - --#: common.opt:1631 -+#: common.opt:1635 - msgid "Insert arc-based program profiling code" - msgstr "Вставлять код для профилирования по дугам управляющего графа программы" - --#: common.opt:1635 -+#: common.opt:1639 - msgid "Set the top-level directory for storing the profile data." - msgstr "" - --#: common.opt:1640 -+#: common.opt:1644 - msgid "Enable correction of flow inconsistent profile data input" - msgstr "" - --#: common.opt:1644 -+#: common.opt:1648 - msgid "Enable common options for generating profile info for profile feedback directed optimizations" - msgstr "Активировать ключи генерации данных профилирования для выполнения соответствующих оптимизаций" - --#: common.opt:1648 -+#: common.opt:1652 - #, fuzzy - msgid "Enable common options for generating profile info for profile feedback directed optimizations, and set -fprofile-dir=" - msgstr "Активировать ключи генерации данных профилирования для выполнения соответствующих оптимизаций" - --#: common.opt:1652 -+#: common.opt:1656 - msgid "Enable common options for performing profile feedback directed optimizations" - msgstr "Активировать ключи оптимизаций, основанных на данных профилирования" - --#: common.opt:1656 -+#: common.opt:1660 - #, fuzzy - msgid "Enable common options for performing profile feedback directed optimizations, and set -fprofile-dir=" - msgstr "Активировать ключи оптимизаций, основанных на данных профилирования" - --#: common.opt:1660 -+#: common.opt:1664 - msgid "Insert code to profile values of expressions" - msgstr "Вставлять код для профилирования значений выражений" - --#: common.opt:1664 -+#: common.opt:1668 - #, fuzzy --#| msgid "internal consistency failure" - msgid "Report on consistency of profile" - msgstr "обнаружена несогласованность внутреннего представления gcc" - --#: common.opt:1671 -+#: common.opt:1675 - #, fuzzy - msgid "-frandom-seed=\tMake compile reproducible using " - msgstr "Компилировать воспроизводимым образом, используя <строку> для генерации случайных чисел" - --#: common.opt:1681 -+#: common.opt:1685 - msgid "Record gcc command line switches in the object file." - msgstr "" - --#: common.opt:1685 -+#: common.opt:1689 - msgid "Return small aggregates in registers" - msgstr "Возвращать короткие агрегатные в регистрах" - --#: common.opt:1689 -+#: common.opt:1693 - msgid "Enables a register move optimization" - msgstr "Выполнить оптимизацию перемещения регистров" - --#: common.opt:1693 -+#: common.opt:1697 - msgid "Perform a register renaming optimization pass" - msgstr "Выполнить оптимизацию переименования регистров" - --#: common.opt:1697 -+#: common.opt:1701 - msgid "Reorder basic blocks to improve code placement" - msgstr "Переупорядочить блоки для улучшения размещения кода" - --#: common.opt:1701 -+#: common.opt:1705 - msgid "Reorder basic blocks and partition into hot and cold sections" - msgstr "Переупорядочить блоки и партиции в hot и cold разделы" - --#: common.opt:1705 -+#: common.opt:1709 - msgid "Reorder functions to improve code placement" - msgstr "Переупорядочить функции для улучшения размещения кода" - --#: common.opt:1709 -+#: common.opt:1713 - msgid "Add a common subexpression elimination pass after loop optimizations" - msgstr "Выполнить экономию общих подвыражений еще и после оптимизации циклов" - --#: common.opt:1717 -+#: common.opt:1721 - msgid "Disable optimizations that assume default FP rounding behavior" - msgstr "Отменить оптимизации, предполагающие стандартное округление вещественных значений" - --#: common.opt:1721 -+#: common.opt:1725 - msgid "Enable scheduling across basic blocks" - msgstr "Планировать команды в рамках нескольких блоков" - --#: common.opt:1725 -+#: common.opt:1729 - msgid "Enable register pressure sensitive insn scheduling" - msgstr "" - --#: common.opt:1729 -+#: common.opt:1733 - msgid "Allow speculative motion of non-loads" - msgstr "Разрешить спекулятивный перенос команд, кроме чтения" - --#: common.opt:1733 -+#: common.opt:1737 - msgid "Allow speculative motion of some loads" - msgstr "Разрешить спекулятивный перенос некоторых команд чтения" - --#: common.opt:1737 -+#: common.opt:1741 - msgid "Allow speculative motion of more loads" - msgstr "Разрешить более активный спекулятивный перенос команд чтения" - --#: common.opt:1741 -+#: common.opt:1745 - #, fuzzy - msgid "-fsched-verbose=\tSet the verbosity level of the scheduler" - msgstr "Установить уровень подробности сообщений от планировщика" - --#: common.opt:1745 -+#: common.opt:1749 - msgid "If scheduling post reload, do superblock scheduling" - msgstr "При планировании после распределения регистров, использовать метод суперблоков" - --#: common.opt:1753 -+#: common.opt:1757 - msgid "Reschedule instructions before register allocation" - msgstr "Планировать код перед распределением регистров" - --#: common.opt:1757 -+#: common.opt:1761 - msgid "Reschedule instructions after register allocation" - msgstr "Планировать код после распределения регистров" - --#: common.opt:1764 -+#: common.opt:1768 - msgid "Schedule instructions using selective scheduling algorithm" - msgstr "" - --#: common.opt:1768 -+#: common.opt:1772 - msgid "Run selective scheduling after reload" - msgstr "" - --#: common.opt:1772 -+#: common.opt:1776 - msgid "Perform software pipelining of inner loops during selective scheduling" - msgstr "" - --#: common.opt:1776 -+#: common.opt:1780 - msgid "Perform software pipelining of outer loops during selective scheduling" - msgstr "" - --#: common.opt:1780 -+#: common.opt:1784 - msgid "Reschedule pipelined regions without pipelining" - msgstr "" - --#: common.opt:1786 -+#: common.opt:1790 - msgid "Allow premature scheduling of queued insns" - msgstr "Разрешить предварительное планирование отложенных команд" - --#: common.opt:1790 -+#: common.opt:1794 - #, fuzzy - msgid "-fsched-stalled-insns=\tSet number of queued insns that can be prematurely scheduled" - msgstr "Число отложенных команд, подлежащих предварительному планированию" - --#: common.opt:1798 -+#: common.opt:1802 - msgid "Set dependence distance checking in premature scheduling of queued insns" - msgstr "Включить проверку дальности зависимостей при предварительном планировании отложенных команд" - --#: common.opt:1802 -+#: common.opt:1806 - #, fuzzy - msgid "-fsched-stalled-insns-dep=\tSet dependence distance checking in premature scheduling of queued insns" - msgstr "Включить проверку дальности зависимостей при предварительном планировании отложенных команд" - --#: common.opt:1806 -+#: common.opt:1810 - #, fuzzy - msgid "Enable the group heuristic in the scheduler" - msgstr "Установить уровень подробности сообщений от планировщика" - --#: common.opt:1810 -+#: common.opt:1814 - msgid "Enable the critical path heuristic in the scheduler" - msgstr "" - --#: common.opt:1814 -+#: common.opt:1818 - msgid "Enable the speculative instruction heuristic in the scheduler" - msgstr "" - --#: common.opt:1818 -+#: common.opt:1822 - #, fuzzy - msgid "Enable the rank heuristic in the scheduler" - msgstr "Установить уровень подробности сообщений от планировщика" - --#: common.opt:1822 -+#: common.opt:1826 - msgid "Enable the last instruction heuristic in the scheduler" - msgstr "" - --#: common.opt:1826 -+#: common.opt:1830 - msgid "Enable the dependent count heuristic in the scheduler" - msgstr "" - --#: common.opt:1830 -+#: common.opt:1834 - msgid "Access data in the same section from shared anchor points" - msgstr "" - --#: common.opt:1842 -+#: common.opt:1846 - msgid "Turn on Redundant Extensions Elimination pass." - msgstr "" - --#: common.opt:1846 -+#: common.opt:1850 - #, fuzzy - msgid "Show column numbers in diagnostics, when available. Default on" - msgstr "Показывать номера колонок в диагностических сообщений. По умолчанию включено" - --#: common.opt:1850 -+#: common.opt:1854 - msgid "Emit function prologues only before parts of the function that need it," - msgstr "" - --#: common.opt:1855 -+#: common.opt:1859 - msgid "Disable optimizations observable by IEEE signaling NaNs" - msgstr "Отменить оптимизации, влияющие на поведение сигнализирующих NaN по IEEE" - --#: common.opt:1859 -+#: common.opt:1863 - msgid "Disable floating point optimizations that ignore the IEEE signedness of zero" - msgstr "" - --#: common.opt:1863 -+#: common.opt:1867 - msgid "Convert floating point constants to single precision constants" - msgstr "Преобразовывать вещественные константы к значениям одинарной точности" - --#: common.opt:1867 -+#: common.opt:1871 - msgid "Split lifetimes of induction variables when loops are unrolled" - msgstr "Разбивать диапазоны жизни индуктивных переменных при развертке циклов" - --#: common.opt:1871 -+#: common.opt:1875 - #, fuzzy - msgid "Generate discontiguous stack frames" - msgstr "Генерировать APCS-совместимые кадры стека" - --#: common.opt:1875 -+#: common.opt:1879 - msgid "Split wide types into independent registers" - msgstr "" - --#: common.opt:1879 -+#: common.opt:1883 - msgid "Apply variable expansion when loops are unrolled" - msgstr "Выполнять расширение переменных при развертке циклов" - --#: common.opt:1883 -+#: common.opt:1887 - #, fuzzy - msgid "-fstack-check=[no|generic|specific]\tInsert stack checking code into the program" - msgstr "Генерировать код для проверки стека" - --#: common.opt:1887 -+#: common.opt:1891 - #, fuzzy - msgid "Insert stack checking code into the program. Same as -fstack-check=specific" - msgstr "Генерировать код для проверки стека" - --#: common.opt:1894 -+#: common.opt:1898 - #, fuzzy - msgid "-fstack-limit-register=\tTrap if the stack goes past " - msgstr "Прерывание при переполнении стека, <регистр> задает границу стека" - --#: common.opt:1898 -+#: common.opt:1902 - #, fuzzy - msgid "-fstack-limit-symbol=\tTrap if the stack goes past symbol " - msgstr "Прерывание при переполнении стека, <символ> задает границу стека" - --#: common.opt:1902 -+#: common.opt:1906 - msgid "Use propolice as a stack protection method" - msgstr "Использовать propolice как метод защиты стека" - --#: common.opt:1906 -+#: common.opt:1910 - msgid "Use a stack protection method for every function" - msgstr "Использовать защиту стека для каждой функции" - --#: common.opt:1910 -+#: common.opt:1914 - #, fuzzy - msgid "Output stack usage information on a per-function basis" - msgstr "Включить использование r30" - --#: common.opt:1922 -+#: common.opt:1926 - msgid "Assume strict aliasing rules apply" - msgstr "Предполагать строгое соблюдение правил перекрытия данных в памяти" - --#: common.opt:1926 -+#: common.opt:1930 - #, fuzzy - msgid "Treat signed overflow as undefined" - msgstr "Трактовать отсутствующие заголовки как генерируемые файлы" - --#: common.opt:1930 -+#: common.opt:1934 - msgid "Implement __atomic operations via libcalls to legacy __sync functions" - msgstr "" - --#: common.opt:1934 -+#: common.opt:1938 - msgid "Check for syntax errors, then stop" - msgstr "Проверить код на наличие синтаксических ошибок и завершить работу" - --#: common.opt:1938 -+#: common.opt:1942 - msgid "Create data files needed by \"gcov\"" - msgstr "Создать файлы данных для \"gcov\"" - --#: common.opt:1942 -+#: common.opt:1946 - msgid "Perform jump threading optimizations" - msgstr "Выполнить протягивание переходов" - --#: common.opt:1946 -+#: common.opt:1950 - msgid "Report the time taken by each compiler pass" - msgstr "Показать время, затраченное на каждый проход оптимизации" - --#: common.opt:1950 -+#: common.opt:1954 - #, fuzzy - msgid "-ftls-model=[global-dynamic|local-dynamic|initial-exec|local-exec]\tSet the default thread-local storage code generation model" - msgstr "Модель генерации кода для данных, локальных для потов, по умолчанию" - --#: common.opt:1953 -+#: common.opt:1957 - #, fuzzy, c-format - msgid "unknown TLS model %qs" - msgstr "неизвестная машинный режим %qs" - --#: common.opt:1969 -+#: common.opt:1973 - msgid "Reorder top level functions, variables, and asms" - msgstr "" - --#: common.opt:1973 -+#: common.opt:1977 - msgid "Perform superblock formation via tail duplication" - msgstr "Формировать суперблоки методом дублирования хвостов" - --#: common.opt:1980 -+#: common.opt:1984 - msgid "Assume floating-point operations can trap" - msgstr "Предполагать возможность прерываний при плавающих операциях" - --#: common.opt:1984 -+#: common.opt:1988 - msgid "Trap for signed overflow in addition, subtraction and multiplication" - msgstr "Прерывания при знаковых операциях сложения, вычитания, умножения" - --#: common.opt:1988 -+#: common.opt:1992 - msgid "Enable SSA-CCP optimization on trees" - msgstr "Включить SSA-оптимизацию распространения констант на древовидном представлении" - --#: common.opt:1992 -+#: common.opt:1996 - #, fuzzy - msgid "Enable SSA-BIT-CCP optimization on trees" - msgstr "Включить SSA-оптимизацию распространения констант на древовидном представлении" - --#: common.opt:2000 -+#: common.opt:2004 - msgid "Enable loop header copying on trees" - msgstr "Включить копирование заголовков циклов в древовидном представлении" - --#: common.opt:2004 -+#: common.opt:2008 - msgid "Enable coalescing of copy-related user variables that are inlined" - msgstr "" - --#: common.opt:2008 -+#: common.opt:2012 - msgid "Enable coalescing of all copy-related user variables" - msgstr "" - --#: common.opt:2012 -+#: common.opt:2016 - msgid "Replace SSA temporaries with better names in copies" - msgstr "Переименовывать временные SSA-переменные при копировании для более близкого соответствия программным переменным" - --#: common.opt:2016 -+#: common.opt:2020 - msgid "Enable copy propagation on trees" - msgstr "Выполнять распространение копий в древовидном представлении" - --#: common.opt:2024 -+#: common.opt:2028 - #, fuzzy - msgid "Transform condition stores into unconditional ones" - msgstr "Преобразовывать условные переходы в условно выполняемый код" - --#: common.opt:2028 -+#: common.opt:2032 - #, fuzzy - msgid "Perform conversions of switch initializations." - msgstr "Преобразовывать условные переходы в условно выполняемый код" - --#: common.opt:2032 -+#: common.opt:2036 - msgid "Enable SSA dead code elimination optimization on trees" - msgstr "Выполнить удаление мертвого SSA-кода на древовидном представлении" - --#: common.opt:2036 -+#: common.opt:2040 - msgid "Enable dominator optimizations" - msgstr "Включить оптимизации доминаторов" - --#: common.opt:2040 -+#: common.opt:2044 - #, fuzzy - msgid "Enable tail merging on trees" - msgstr "Включить копирование заголовков циклов в древовидном представлении" - --#: common.opt:2044 -+#: common.opt:2048 - msgid "Enable dead store elimination" - msgstr "Выполнить оптимизацию удаления мертвых команд записи в память" - --#: common.opt:2048 -+#: common.opt:2052 - #, fuzzy - msgid "Enable forward propagation on trees" - msgstr "Выполнять распространение копий в древовидном представлении" - --#: common.opt:2052 -+#: common.opt:2056 - msgid "Enable Full Redundancy Elimination (FRE) on trees" - msgstr "Выполнить полный набор оптимизаций удаления избыточного кода на древовидном представлении" - --#: common.opt:2056 -+#: common.opt:2060 - #, fuzzy - msgid "Enable string length optimizations on trees" - msgstr "Включить SSA-оптимизацию распространения констант на древовидном представлении" - --#: common.opt:2060 -+#: common.opt:2064 - #, fuzzy - msgid "Enable loop distribution on trees" - msgstr "Выполнить векторизацию циклов на древовидном представлении" - --#: common.opt:2064 -+#: common.opt:2068 - msgid "Enable loop distribution for patterns transformed into a library call" - msgstr "" - --#: common.opt:2068 -+#: common.opt:2072 - msgid "Enable loop invariant motion on trees" - msgstr "Выполнить вынесение инвариантных вычислений за пределы циклов на древовидном представлении" - --#: common.opt:2072 -+#: common.opt:2076 - msgid "Enable loop interchange transforms. Same as -floop-interchange" - msgstr "" - --#: common.opt:2076 -+#: common.opt:2080 - msgid "Create canonical induction variables in loops" - msgstr "Создавать канонические индуктивные переменные в циклах" - --#: common.opt:2080 -+#: common.opt:2084 - msgid "Enable loop optimizations on tree level" - msgstr "Включить оптимизации циклов на древовидном представлении" - --#: common.opt:2084 -+#: common.opt:2088 - #, fuzzy - msgid "Enable automatic parallelization of loops" - msgstr "Включить автоматическую конкретизацию шаблонов" - --#: common.opt:2088 -+#: common.opt:2092 - #, fuzzy - msgid "Enable hoisting loads from conditional pointers." - msgstr "Использовать условные команды move" - --#: common.opt:2092 -+#: common.opt:2096 - msgid "Enable SSA-PRE optimization on trees" - msgstr "Включить оптимизации SSA-PRE на древовидном представлении" - --#: common.opt:2096 -+#: common.opt:2100 - msgid "In SSA-PRE optimization on trees, enable partial-partial redundancy elimination" - msgstr "" - --#: common.opt:2100 -+#: common.opt:2104 - #, fuzzy - msgid "Perform function-local points-to analysis on trees." - msgstr "Выполнить межпроцедурное распространение констант" - --#: common.opt:2104 -+#: common.opt:2108 - #, fuzzy - msgid "Enable reassociation on tree level" - msgstr "Включить оптимизации циклов на древовидном представлении" - --#: common.opt:2112 -+#: common.opt:2116 - msgid "Enable SSA code sinking on trees" - msgstr "Выполнить погружение SSA-кода на древовидном представлении" - --#: common.opt:2116 -+#: common.opt:2120 - msgid "Perform straight-line strength reduction" - msgstr "" - --#: common.opt:2120 -+#: common.opt:2124 - msgid "Perform scalar replacement of aggregates" - msgstr "Выполнить замену скаляров для агрегатных значений" - --#: common.opt:2124 -+#: common.opt:2128 - msgid "Replace temporary expressions in the SSA->normal pass" - msgstr "Выполнить замену временных выражений на проходе SSA->normal" - --#: common.opt:2128 -+#: common.opt:2132 - msgid "Perform live range splitting during the SSA->normal pass" - msgstr "Выполнить разбиение диапазонов жизни значений на проходе SSA->normal" - --#: common.opt:2132 -+#: common.opt:2136 - msgid "Perform Value Range Propagation on trees" - msgstr "Выполнить оптимизацию распространения диапазонов значений на древовидном представлении" - --#: common.opt:2136 -+#: common.opt:2140 - msgid "Compile whole compilation unit at a time" - msgstr "Компилировать весь модуль целиком (а не по функциям)" - --#: common.opt:2140 -+#: common.opt:2144 - msgid "Perform loop unrolling when iteration count is known" - msgstr "Выполнить развертку циклов с известным числом итераций" - --#: common.opt:2144 -+#: common.opt:2148 - msgid "Perform loop unrolling for all loops" - msgstr "Выполнить развертку всех циклов" - --#: common.opt:2151 -+#: common.opt:2155 - msgid "Allow loop optimizations to assume that the loops behave in normal way" - msgstr "При оптимизации циклов предполагать нормальное поведение цикла" - --#: common.opt:2155 -+#: common.opt:2159 - msgid "Allow optimization for floating-point arithmetic which may change the" - msgstr "" - --#: common.opt:2160 -+#: common.opt:2164 - msgid "Same as -fassociative-math for expressions which include division." - msgstr "" - --#: common.opt:2168 -+#: common.opt:2172 - msgid "Allow math optimizations that may violate IEEE or ISO standards" - msgstr "Разрешить оптимизации плавающих вычислений, которые могут противоречить стандартам IEEE или ISO" - --#: common.opt:2172 -+#: common.opt:2176 - msgid "Perform loop unswitching" - msgstr "Выполнить декомпозицию циклов, содержащих условные ветвления" - --#: common.opt:2176 -+#: common.opt:2180 - msgid "Just generate unwind tables for exception handling" - msgstr "Генерировать unwind-таблицы только для обработки исключений" - --#: common.opt:2180 -+#: common.opt:2184 - msgid "Use the bfd linker instead of the default linker" - msgstr "" - --#: common.opt:2184 -+#: common.opt:2188 - msgid "Use the gold linker instead of the default linker" - msgstr "" - --#: common.opt:2196 -+#: common.opt:2200 - msgid "Perform variable tracking" - msgstr "Выполнить отслеживание переменных" - --#: common.opt:2204 -+#: common.opt:2208 - #, fuzzy - msgid "Perform variable tracking by annotating assignments" - msgstr "Выполнить отслеживание переменных" - --#: common.opt:2210 -+#: common.opt:2214 - msgid "Toggle -fvar-tracking-assignments" - msgstr "" - --#: common.opt:2218 -+#: common.opt:2222 - msgid "Perform variable tracking and also tag variables that are uninitialized" - msgstr "" - --#: common.opt:2222 -+#: common.opt:2226 - msgid "Enable loop vectorization on trees" - msgstr "Выполнить векторизацию циклов на древовидном представлении" - --#: common.opt:2226 -+#: common.opt:2230 - #, fuzzy - msgid "-ftree-vectorizer-verbose=\tThis switch is deprecated. Use -fopt-info instead." - msgstr "Установить степень подробности сообщений при векторизации циклов" - --#: common.opt:2230 -+#: common.opt:2234 - #, fuzzy - msgid "Enable basic block vectorization (SLP) on trees" - msgstr "Выполнить векторизацию циклов на древовидном представлении" - --#: common.opt:2234 -+#: common.opt:2238 - #, fuzzy - msgid "Enable use of cost model in vectorization" - msgstr "Использовать команду DB" - --#: common.opt:2238 -+#: common.opt:2242 - msgid "Enable loop versioning when doing loop vectorization on trees" - msgstr "Создавать версии циклов при векторизации" - --#: common.opt:2242 -+#: common.opt:2246 - #, fuzzy - msgid "Enable copy propagation of scalar-evolution information." - msgstr "Выполнять распространение копий для записей и загрузок" - --#: common.opt:2252 -+#: common.opt:2256 - msgid "Add extra commentary to assembler output" - msgstr "Добавить комментарии к ассемблерному коду" - --#: common.opt:2256 -+#: common.opt:2260 - msgid "-fvisibility=[default|internal|hidden|protected]\tSet the default symbol visibility" - msgstr "" - --#: common.opt:2259 -+#: common.opt:2263 - #, fuzzy, c-format - msgid "unrecognized visibility value %qs" - msgstr "некорректный тип видимости \"%s\"" - --#: common.opt:2275 -+#: common.opt:2279 - msgid "Use expression value profiles in optimizations" - msgstr "Использовать данные профилирования значений при оптимизациях" - --#: common.opt:2279 -+#: common.opt:2283 - msgid "Construct webs and split unrelated uses of single variable" - msgstr "Снять зависимости между различными использованиями одной и той же переменной" - --#: common.opt:2283 -+#: common.opt:2287 - #, fuzzy - msgid "Enable conditional dead code elimination for builtin calls" - msgstr "Выполнить удаление мертвого SSA-кода на древовидном представлении" - --#: common.opt:2287 -+#: common.opt:2291 - msgid "Perform whole program optimizations" - msgstr "Выполнить оптимизации на уровне всей программы" - --#: common.opt:2291 -+#: common.opt:2295 - msgid "Assume signed arithmetic overflow wraps around" - msgstr "Предполагать циклический перенос при арифметических переполнениях" - --#: common.opt:2295 -+#: common.opt:2299 - msgid "Put zero initialized data in the bss section" - msgstr "Помещать данные, инициализированные нулями, в секцию bss" - --#: common.opt:2299 -+#: common.opt:2303 - msgid "Generate debug information in default format" - msgstr "Генерировать отладочную информацию в формате по умолчанию" - --#: common.opt:2303 -+#: common.opt:2307 - msgid "Generate debug information in COFF format" - msgstr "Генерировать отладочную информацию в формате COFF" - --#: common.opt:2307 -+#: common.opt:2311 - #, fuzzy - msgid "Generate debug information in DWARF v2 (or later) format" - msgstr "Генерировать отладочную информацию в формате DWARF версии 2" - --#: common.opt:2311 -+#: common.opt:2315 - msgid "Generate debug information in default extended format" - msgstr "Генерировать отладочную информацию в расширенном формате по умолчанию" - --#: common.opt:2315 -+#: common.opt:2319 - msgid "Don't generate DWARF pubnames and pubtypes sections." - msgstr "" - --#: common.opt:2319 -+#: common.opt:2323 - msgid "Generate DWARF pubnames and pubtypes sections." - msgstr "" - --#: common.opt:2323 -+#: common.opt:2327 - msgid "Don't record gcc command line switches in DWARF DW_AT_producer." - msgstr "" - --#: common.opt:2327 -+#: common.opt:2331 - msgid "Record gcc command line switches in DWARF DW_AT_producer." - msgstr "" - --#: common.opt:2331 -+#: common.opt:2335 - #, fuzzy --#| msgid "Generate debug information in default format" - msgid "Don't generate debug information in separate .dwo files" - msgstr "Генерировать отладочную информацию в формате по умолчанию" - --#: common.opt:2335 -+#: common.opt:2339 - #, fuzzy --#| msgid "Generate debug information in default format" - msgid "Generate debug information in separate .dwo files" - msgstr "Генерировать отладочную информацию в формате по умолчанию" - --#: common.opt:2339 -+#: common.opt:2343 - msgid "Generate debug information in STABS format" - msgstr "Генерировать отладочную информацию в формате STABS" - --#: common.opt:2343 -+#: common.opt:2347 - msgid "Generate debug information in extended STABS format" - msgstr "Генерировать отладочную информацию в расширенном формате STABS" - --#: common.opt:2347 -+#: common.opt:2351 - msgid "Emit DWARF additions beyond selected version" - msgstr "" - --#: common.opt:2351 -+#: common.opt:2355 - msgid "Don't emit DWARF additions beyond selected version" - msgstr "" - --#: common.opt:2355 -+#: common.opt:2359 - #, fuzzy - msgid "Toggle debug information generation" - msgstr "Генерировать отладочную информацию в формате VMS" - --#: common.opt:2359 -+#: common.opt:2363 - msgid "Generate debug information in VMS format" - msgstr "Генерировать отладочную информацию в формате VMS" - --#: common.opt:2363 -+#: common.opt:2367 - msgid "Generate debug information in XCOFF format" - msgstr "Генерировать отладочную информацию в формате XCOFF" - --#: common.opt:2367 -+#: common.opt:2371 - msgid "Generate debug information in extended XCOFF format" - msgstr "Генерировать отладочную информацию в расширенном формате XCOFF" - --#: common.opt:2374 -+#: common.opt:2378 - #, fuzzy - msgid "-iplugindir=\tSet to be the default plugin directory" - msgstr "Считать <каталог> корневым каталогом системы" - --#: common.opt:2378 -+#: common.opt:2382 - #, fuzzy - msgid "-imultiarch \tSet to be the multiarch include subdirectory" - msgstr "Считать <каталог> корневым каталогом системы" - --#: common.opt:2400 -+#: common.opt:2404 - #, fuzzy - msgid "-o \tPlace output into " - msgstr "Записать результат в <файл>" - --#: common.opt:2404 -+#: common.opt:2408 - msgid "Enable function profiling" - msgstr "Включить профилирование функций" - --#: common.opt:2414 -+#: common.opt:2418 - msgid "Like -pedantic but issue them as errors" - msgstr "Как -pedantic, но выдавать ошибки, а не предупреждения" - --#: common.opt:2454 -+#: common.opt:2458 - msgid "Do not display functions compiled or elapsed time" - msgstr "Не отображать время компиляции функций" - --#: common.opt:2486 -+#: common.opt:2490 - msgid "Enable verbose output" - msgstr "Включить подробную выдачу" - --#: common.opt:2490 -+#: common.opt:2494 - msgid "Display the compiler's version" - msgstr "Показать версию компилятора" - --#: common.opt:2494 -+#: common.opt:2498 - msgid "Suppress warnings" - msgstr "Подавить выдачу предупреждений" - --#: common.opt:2504 -+#: common.opt:2508 - #, fuzzy - msgid "Create a shared library" - msgstr "Поддерживать разделяемые библиотеки на основе ID" - --#: common.opt:2543 -+#: common.opt:2547 - #, fuzzy - msgid "Create a position independent executable" - msgstr "Генерировать позиционно-независимый код для выполняемых модулей, если возможно (режим large)" - --#: go/gofrontend/expressions.cc:102 c-family/c-common.c:1777 cp/cvt.c:1149 -+#: go/gofrontend/expressions.cc:102 c-family/c-common.c:1782 cp/cvt.c:1149 - #: cp/cvt.c:1395 - #, gcc-internal-format - msgid "value computed is not used" -@@ -13362,7 +13335,7 @@ - msgstr "" - - #. Warn about and ignore all others for now, but store them. --#: attribs.c:426 c-family/c-common.c:8019 objc/objc-act.c:4952 -+#: attribs.c:426 c-family/c-common.c:8041 objc/objc-act.c:4952 - #: objc/objc-act.c:6922 objc/objc-act.c:8109 objc/objc-act.c:8160 - #, fuzzy, gcc-internal-format - msgid "%qE attribute directive ignored" -@@ -13383,7 +13356,6 @@ - #. type. Ignore it. - #: attribs.c:452 - #, fuzzy, gcc-internal-format --#| msgid "%qE attribute ignored" - msgid "attribute ignored" - msgstr "атрибут %qE проигнорирован" - -@@ -13551,19 +13523,17 @@ - - #: builtins.c:5764 - #, fuzzy, gcc-internal-format --#| msgid "__builtin_eh_return not supported on this target" - msgid "__builtin_thread_pointer is not supported on this target" - msgstr "__builtin_eh_return не поддерживается для этой платформы" - - #: builtins.c:5784 - #, fuzzy, gcc-internal-format --#| msgid "__builtin_eh_return not supported on this target" - msgid "__builtin_set_thread_pointer is not supported on this target" - msgstr "__builtin_eh_return не поддерживается для этой платформы" - - #. All valid uses of __builtin_va_arg_pack () are removed during - #. inlining. --#: builtins.c:6025 expr.c:10184 -+#: builtins.c:6025 expr.c:10185 - #, fuzzy, gcc-internal-format - msgid "%Kinvalid use of %<__builtin_va_arg_pack ()%>" - msgstr "неверный аргумент для %<__builtin_frame_address%>" -@@ -13650,17 +13620,17 @@ - msgid "function call has aggregate value" - msgstr "функция возвращает агрегатное значение" - --#: cfgexpand.c:1238 function.c:971 varasm.c:1966 -+#: cfgexpand.c:1238 function.c:971 varasm.c:1964 - #, gcc-internal-format - msgid "size of variable %q+D is too large" - msgstr "размер переменной %q+D слишком велик" - --#: cfgexpand.c:4487 -+#: cfgexpand.c:4542 - #, fuzzy, gcc-internal-format - msgid "stack protector not protecting local variables: variable length buffer" - msgstr "локальные переменные не защищены: буфер переменного размера" - --#: cfgexpand.c:4491 -+#: cfgexpand.c:4546 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "stack protector not protecting function: all local arrays are less than %d bytes long" - msgstr "функция не защищена: отсутствует буфер размера не менее %d байт" -@@ -13742,7 +13712,6 @@ - - #: cfghooks.c:293 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "%s does not support duplicate_block" - msgid "%s does not support dump_bb_for_graph" - msgstr "%s не поддерживает duplicate_block" - -@@ -13848,19 +13817,16 @@ - - #: cfgloop.c:1363 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "Enable loop header copying on trees" - msgid "loop with header %d not in loop tree" - msgstr "Включить копирование заголовков циклов в древовидном представлении" - - #: cfgloop.c:1380 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "bb %d do not belong to loop %d" - msgid "bb %d does not belong to loop %d" - msgstr "блок %d не принадлежит циклу %d" - - #: cfgloop.c:1392 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "size of loop %d should be %d, not %d" - msgid "bb %d has father loop %d, should be loop %d" - msgstr "размер цикла %d должен быть %d, а не %d" - -@@ -13964,169 +13930,162 @@ - msgid "%d exits recorded for loop %d (having %d exits)" - msgstr "нет записи о единственном выходе из цикла %d" - --#: cfgrtl.c:2092 -+#: cfgrtl.c:2090 - #, gcc-internal-format, gfc-internal-format - msgid "BB_RTL flag not set for block %d" - msgstr "для блока %d не установлен флаг BB_RTL" - --#: cfgrtl.c:2099 -+#: cfgrtl.c:2097 - #, gcc-internal-format, gfc-internal-format - msgid "insn %d basic block pointer is %d, should be %d" - msgstr "" - --#: cfgrtl.c:2110 -+#: cfgrtl.c:2108 - #, gcc-internal-format, gfc-internal-format - msgid "insn %d in header of bb %d has non-NULL basic block" - msgstr "" - --#: cfgrtl.c:2118 -+#: cfgrtl.c:2116 - #, gcc-internal-format, gfc-internal-format - msgid "insn %d in footer of bb %d has non-NULL basic block" - msgstr "" - --#: cfgrtl.c:2141 -+#: cfgrtl.c:2139 - #, gcc-internal-format - msgid "verify_flow_info: REG_BR_PROB does not match cfg %wi %i" - msgstr "verify_flow_info: REG_BR_PROB не соответствует CFG %wi %i" - --#: cfgrtl.c:2160 -+#: cfgrtl.c:2158 - #, gcc-internal-format - msgid "EDGE_CROSSING incorrectly set across same section" - msgstr "" - --#: cfgrtl.c:2165 -+#: cfgrtl.c:2163 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "fallthru edge crosses section boundary (bb %i)" - msgid "fallthru edge crosses section boundary in bb %i" - msgstr "сквозная дуга пересекает границу секции (блок %i)" - --#: cfgrtl.c:2171 -+#: cfgrtl.c:2169 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "EH edge crosses section boundary in bb %i" - msgstr "сквозная дуга пересекает границу секции (блок %i)" - --#: cfgrtl.c:2178 -+#: cfgrtl.c:2176 - #, gcc-internal-format - msgid "EDGE_CROSSING missing across section boundary" - msgstr "" - --#: cfgrtl.c:2205 -+#: cfgrtl.c:2203 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "missing REG_EH_REGION note in the end of bb %i" - msgid "missing REG_EH_REGION note at the end of bb %i" - msgstr "отсутствует пометка REG_EH_REGION в конце блока %i" - --#: cfgrtl.c:2210 -+#: cfgrtl.c:2208 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "too many outgoing branch edges from bb %i" - msgid "too many exception handling edges in bb %i" - msgstr "слишком много переходов, исходящих из блока %i" - --#: cfgrtl.c:2218 -+#: cfgrtl.c:2216 - #, gcc-internal-format, gfc-internal-format - msgid "too many outgoing branch edges from bb %i" - msgstr "слишком много переходов, исходящих из блока %i" - --#: cfgrtl.c:2223 -+#: cfgrtl.c:2221 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "fallthru edge after unconditional jump %i" - msgid "fallthru edge after unconditional jump in bb %i" - msgstr "сквозная дуга после безусловного перехода %i" - --#: cfgrtl.c:2228 -+#: cfgrtl.c:2226 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "wrong number of branch edges after unconditional jump in bb %i" - msgstr "некорректное число ветвлений после безусловного перехода %i" - --#: cfgrtl.c:2235 -+#: cfgrtl.c:2233 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "wrong amount of branch edges after conditional jump %i" - msgid "wrong amount of branch edges after conditional jump in bb %i" - msgstr "некорректное число ветвлений после условного перехода %i" - --#: cfgrtl.c:2241 -+#: cfgrtl.c:2239 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "call edges for non-call insn in bb %i" - msgid "abnormal call edges for non-call insn in bb %i" - msgstr "дуги вызова для не-call инструкции в блоке %i" - --#: cfgrtl.c:2246 -+#: cfgrtl.c:2244 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "call edges for non-call insn in bb %i" - msgid "sibcall edges for non-call insn in bb %i" - msgstr "дуги вызова для не-call инструкции в блоке %i" - --#: cfgrtl.c:2256 -+#: cfgrtl.c:2254 - #, gcc-internal-format, gfc-internal-format - msgid "abnormal edges for no purpose in bb %i" - msgstr "ненужные аномальные дуги в блоке %i" - --#: cfgrtl.c:2268 -+#: cfgrtl.c:2266 - #, gcc-internal-format, gfc-internal-format - msgid "insn %d inside basic block %d but block_for_insn is NULL" - msgstr "RTL-инструкция %d - внутри блока %d, а block_for_insn=NULL" - --#: cfgrtl.c:2272 -+#: cfgrtl.c:2270 - #, gcc-internal-format, gfc-internal-format - msgid "insn %d inside basic block %d but block_for_insn is %i" - msgstr "RTL-инструкция %d - внутри блока %d, а block_for_insn=%i" - --#: cfgrtl.c:2286 cfgrtl.c:2296 -+#: cfgrtl.c:2284 cfgrtl.c:2294 - #, gcc-internal-format, gfc-internal-format - msgid "NOTE_INSN_BASIC_BLOCK is missing for block %d" - msgstr "отсутствует NOTE_INSN_BASIC_BLOCK для блока %d" - --#: cfgrtl.c:2309 -+#: cfgrtl.c:2307 - #, gcc-internal-format, gfc-internal-format - msgid "NOTE_INSN_BASIC_BLOCK %d in middle of basic block %d" - msgstr "NOTE_INSN_BASIC_BLOCK %d в середине блока %d" - --#: cfgrtl.c:2319 -+#: cfgrtl.c:2317 - #, gcc-internal-format, gfc-internal-format - msgid "in basic block %d:" - msgstr "в блоке %d" - --#: cfgrtl.c:2371 cfgrtl.c:2461 -+#: cfgrtl.c:2369 cfgrtl.c:2459 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "insn %d outside of basic blocks has non-NULL bb field" - msgstr "RTL-инструкция - вне блока" - --#: cfgrtl.c:2379 -+#: cfgrtl.c:2377 - #, gcc-internal-format, gfc-internal-format - msgid "end insn %d for block %d not found in the insn stream" - msgstr "заключительная инструкция %d блока %d не найдена в списке инструкций" - --#: cfgrtl.c:2392 -+#: cfgrtl.c:2390 - #, gcc-internal-format, gfc-internal-format - msgid "insn %d is in multiple basic blocks (%d and %d)" - msgstr "инструкция %d в нескольких блоках (%d и %d)" - --#: cfgrtl.c:2404 -+#: cfgrtl.c:2402 - #, gcc-internal-format, gfc-internal-format - msgid "head insn %d for block %d not found in the insn stream" - msgstr "головная RTL-инструкция %d для блока %d не найдена" - --#: cfgrtl.c:2421 -+#: cfgrtl.c:2419 - #, gcc-internal-format, gfc-internal-format - msgid "missing barrier after block %i" - msgstr "отсутствует барьер после блока %i" - --#: cfgrtl.c:2437 -+#: cfgrtl.c:2435 - #, gcc-internal-format, gfc-internal-format - msgid "verify_flow_info: Incorrect blocks for fallthru %i->%i" - msgstr "verify_flow_info: Некорректные блоки для сквозного перехода %i->%i" - --#: cfgrtl.c:2446 -+#: cfgrtl.c:2444 - #, gcc-internal-format, gfc-internal-format - msgid "verify_flow_info: Incorrect fallthru %i->%i" - msgstr "verify_flow_info: Некорректный сквозной переход %i->%i" - --#: cfgrtl.c:2479 -+#: cfgrtl.c:2477 - #, gcc-internal-format - msgid "basic blocks not laid down consecutively" - msgstr "блоки не были размещены последовательно" - --#: cfgrtl.c:2516 -+#: cfgrtl.c:2514 - #, gcc-internal-format, gfc-internal-format - msgid "number of bb notes in insn chain (%d) != n_basic_blocks (%d)" - msgstr "число меток блоков в списке RTL-инструкций (%d) != n_basic_blocks (%d)" -@@ -14396,7 +14355,7 @@ - msgid "no arguments" - msgstr "отсутствуют аргументы" - --#: collect2.c:1284 opts.c:794 -+#: collect2.c:1284 opts.c:797 - #, fuzzy, gcc-internal-format - msgid "LTO support has not been enabled in this configuration" - msgstr "-m%s в данной конфигурации не поддерживается" -@@ -14451,12 +14410,12 @@ - msgid "cannot find '%s'" - msgstr "не удалось найти '%s'" - --#: collect2.c:1921 collect2.c:2448 collect2.c:2644 gcc.c:2749 -+#: collect2.c:1921 collect2.c:2448 collect2.c:2644 gcc.c:2750 - #, fuzzy, gcc-internal-format - msgid "pex_init failed: %m" - msgstr "ошибка в pex_init" - --#: collect2.c:1930 collect2.c:2457 collect2.c:2652 gcc.c:7188 -+#: collect2.c:1930 collect2.c:2457 collect2.c:2652 gcc.c:7191 - #, fuzzy, gcc-internal-format - msgid "%s: %m" - msgstr "%s: %s" -@@ -14696,7 +14655,7 @@ - msgid "global constructors not supported on this target" - msgstr "глобальные конструкторы не поддерживаются для этой платформы" - --#: diagnostic.c:1145 -+#: diagnostic.c:1148 - #, gcc-internal-format, gfc-internal-format - msgid "in %s, at %s:%d" - msgstr "в %s, в %s:%d" -@@ -14723,7 +14682,6 @@ - - #: dumpfile.c:831 - #, fuzzy, gcc-internal-format --#| msgid "ignoring unknown option %q.*s in %<-fdump-%s%>" - msgid "unknown option %q.*s in %<-fopt-info-%s%>" - msgstr "проигнорирован неопознанная опция %q.*s в %<-fdump-%s%>" - -@@ -14742,22 +14700,22 @@ - msgid "non-delegitimized UNSPEC %s (%d) found in variable location" - msgstr "" - --#: emit-rtl.c:2612 -+#: emit-rtl.c:2616 - #, gcc-internal-format - msgid "invalid rtl sharing found in the insn" - msgstr "Некорректное разделение rtl-кода в инструкции" - --#: emit-rtl.c:2614 -+#: emit-rtl.c:2618 - #, gcc-internal-format - msgid "shared rtx" - msgstr "разделяемый rtl-код" - --#: emit-rtl.c:2616 -+#: emit-rtl.c:2620 - #, gcc-internal-format - msgid "internal consistency failure" - msgstr "обнаружена несогласованность внутреннего представления gcc" - --#: emit-rtl.c:3741 -+#: emit-rtl.c:3749 - #, gcc-internal-format - msgid "ICE: emit_insn used where emit_jump_insn needed:\n" - msgstr "Внутренняя ошибка: использование emit_insn вместо emit_jump_insn:\n" -@@ -14767,57 +14725,57 @@ - msgid "abort in %s, at %s:%d" - msgstr "аварийный выход в %s, на %s:%d" - --#: except.c:2026 -+#: except.c:2075 - #, gcc-internal-format - msgid "argument of %<__builtin_eh_return_regno%> must be constant" - msgstr "аргумент %<__builtin_eh_return_regno%> должен быть константой" - --#: except.c:2163 -+#: except.c:2212 - #, gcc-internal-format - msgid "__builtin_eh_return not supported on this target" - msgstr "__builtin_eh_return не поддерживается для этой платформы" - --#: except.c:3222 except.c:3247 -+#: except.c:3271 except.c:3296 - #, gcc-internal-format, gfc-internal-format - msgid "region_array is corrupted for region %i" - msgstr "испорчен region_array для региона %i" - --#: except.c:3235 except.c:3266 -+#: except.c:3284 except.c:3315 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "lp_array is corrupted for lp %i" - msgstr "испорчен region_array для региона %i" - --#: except.c:3252 -+#: except.c:3301 - #, gcc-internal-format, gfc-internal-format - msgid "outer block of region %i is wrong" - msgstr "неправильный внешний блок региона %i" - --#: except.c:3257 -+#: except.c:3306 - #, gcc-internal-format, gfc-internal-format - msgid "negative nesting depth of region %i" - msgstr "отрицательная глубина вложенности региона %i" - --#: except.c:3271 -+#: except.c:3320 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "region of lp %i is wrong" - msgstr "неправильный внешний блок региона %i" - --#: except.c:3298 -+#: except.c:3347 - #, gcc-internal-format, gfc-internal-format - msgid "tree list ends on depth %i" - msgstr "лист дерева на глубине %i" - --#: except.c:3303 -+#: except.c:3352 - #, fuzzy, gcc-internal-format - msgid "region_array does not match region_tree" - msgstr "массив не соответствует дереву регионов" - --#: except.c:3308 -+#: except.c:3357 - #, fuzzy, gcc-internal-format - msgid "lp_array does not match region_tree" - msgstr "массив не соответствует дереву регионов" - --#: except.c:3315 -+#: except.c:3364 - #, gcc-internal-format - msgid "verify_eh_tree failed" - msgstr "процедура verify_eh_tree выявила ошибки" -@@ -14857,12 +14815,12 @@ - msgid "local frame unavailable (naked function?)" - msgstr "глобальная регистровая переменная %qD использована во вложенной функции" - --#: expr.c:10191 -+#: expr.c:10192 - #, fuzzy, gcc-internal-format - msgid "%Kcall to %qs declared with attribute error: %s" - msgstr "%Jфункция %qD повторно декларирована с атрибутом noinline" - --#: expr.c:10198 -+#: expr.c:10199 - #, fuzzy, gcc-internal-format - msgid "%Kcall to %qs declared with attribute warning: %s" - msgstr "%Jфункция %qD повторно декларирована с атрибутом noinline" -@@ -14897,47 +14855,47 @@ - msgid "assuming signed overflow does not occur when negating a division" - msgstr "" - --#: fold-const.c:3437 fold-const.c:3449 -+#: fold-const.c:3450 fold-const.c:3462 - #, gcc-internal-format, gfc-internal-format - msgid "comparison is always %d due to width of bit-field" - msgstr "при данной ширине битового поля результат сравнения - всегда %d" - --#: fold-const.c:4849 tree-ssa-reassoc.c:1943 -+#: fold-const.c:4862 tree-ssa-reassoc.c:1944 - #, gcc-internal-format - msgid "assuming signed overflow does not occur when simplifying range test" - msgstr "" - --#: fold-const.c:5285 fold-const.c:5299 -+#: fold-const.c:5298 fold-const.c:5312 - #, gcc-internal-format, gfc-internal-format - msgid "comparison is always %d" - msgstr "результат сравнения - всегда %d" - --#: fold-const.c:5432 -+#: fold-const.c:5445 - #, gcc-internal-format - msgid "% of unmatched not-equal tests is always 1" - msgstr "%<или%> от двух сравнений на неравенство с разными величинами - всегда 1" - --#: fold-const.c:5437 -+#: fold-const.c:5450 - #, gcc-internal-format - msgid "% of mutually exclusive equal-tests is always 0" - msgstr "%<или%> от двух взаимно исключающих сравнений на равенство - всегда 0" - --#: fold-const.c:8729 -+#: fold-const.c:8742 - #, gcc-internal-format - msgid "assuming signed overflow does not occur when reducing constant in comparison" - msgstr "" - --#: fold-const.c:8887 -+#: fold-const.c:8900 - #, gcc-internal-format - msgid "assuming signed overflow does not occur when changing X +- C1 cmp C2 to X cmp C1 +- C2" - msgstr "" - --#: fold-const.c:9150 -+#: fold-const.c:9163 - #, gcc-internal-format - msgid "assuming signed overflow does not occur when combining constants around a comparison" - msgstr "" - --#: fold-const.c:14564 -+#: fold-const.c:14577 - #, gcc-internal-format - msgid "fold check: original tree changed by fold" - msgstr "проверка fold: исходное дерево изменено функцией fold" -@@ -14962,142 +14920,142 @@ - msgid "argument %q+D might be clobbered by % or %" - msgstr "аргумент %qD мог быть испорчен вызовами `longjmp' или `vfork'" - --#: function.c:4631 -+#: function.c:4620 - #, gcc-internal-format - msgid "function returns an aggregate" - msgstr "функция возвращает агрегатное значение" - --#: function.c:4993 -+#: function.c:4982 - #, gcc-internal-format - msgid "unused parameter %q+D" - msgstr "параметр %q+D не используется" - --#: gcc.c:1804 gcc.c:1824 -+#: gcc.c:1805 gcc.c:1825 - #, gcc-internal-format, gfc-internal-format - msgid "specs %%include syntax malformed after %ld characters" - msgstr "некорректный синтаксис спецификации %%include после %ld символов" - --#: gcc.c:1850 gcc.c:1859 gcc.c:1869 gcc.c:1879 -+#: gcc.c:1851 gcc.c:1860 gcc.c:1870 gcc.c:1880 - #, gcc-internal-format, gfc-internal-format - msgid "specs %%rename syntax malformed after %ld characters" - msgstr "некорректный синтаксис спецификации %%rename после %ld символов" - --#: gcc.c:1889 -+#: gcc.c:1890 - #, gcc-internal-format, gfc-internal-format - msgid "specs %s spec was not found to be renamed" - msgstr "спецификация %s, которую нужно переименовать, не найдена" - --#: gcc.c:1896 -+#: gcc.c:1897 - #, fuzzy, gcc-internal-format - msgid "%s: attempt to rename spec %qs to already defined spec %qs" - msgstr "%s: попытка переименовать '%s в уже определённую спецификацию '%s'" - --#: gcc.c:1917 -+#: gcc.c:1918 - #, gcc-internal-format, gfc-internal-format - msgid "specs unknown %% command after %ld characters" - msgstr "неопознанная команда %% после %ld символов" - --#: gcc.c:1928 gcc.c:1941 -+#: gcc.c:1929 gcc.c:1942 - #, gcc-internal-format, gfc-internal-format - msgid "specs file malformed after %ld characters" - msgstr "синтаксис файла спецификаций нарушен после %ld символов" - --#: gcc.c:1993 -+#: gcc.c:1994 - #, gcc-internal-format - msgid "spec file has no spec for linking" - msgstr "в файле спецификаций отсутствует спецификация для компоновки" - --#: gcc.c:2538 -+#: gcc.c:2539 - #, fuzzy, gcc-internal-format - msgid "system path %qs is not absolute" - msgstr "путь '%s' в файловой системе не является абсолютным" - --#: gcc.c:2626 -+#: gcc.c:2627 - #, gcc-internal-format - msgid "-pipe not supported" - msgstr "ключ -pipe не поддерживается" - --#: gcc.c:2788 -+#: gcc.c:2789 - #, fuzzy, gcc-internal-format - msgid "failed to get exit status: %m" - msgstr "не удалось получить код возврата" - --#: gcc.c:2794 -+#: gcc.c:2795 - #, fuzzy, gcc-internal-format - msgid "failed to get process times: %m" - msgstr "не удалось вычислить время обработки" - --#: gcc.c:2820 -+#: gcc.c:2821 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "%s (program %s)" - msgstr "программы: %s\n" - --#: gcc.c:3251 opts-common.c:986 opts-common.c:1058 -+#: gcc.c:3252 opts-common.c:1019 opts-common.c:1091 - #, fuzzy, gcc-internal-format - msgid "unrecognized command line option %qs" - msgstr "некорректный ключ \"%s\"" - --#: gcc.c:3506 -+#: gcc.c:3507 - #, gcc-internal-format - msgid "%qs is an unknown -save-temps option" - msgstr "" - --#: gcc.c:3967 -+#: gcc.c:3968 - #, fuzzy, gcc-internal-format - msgid "-pipe ignored because -save-temps specified" - msgstr "предупреждение: ключ -pipe игнорируется, т.к. задан ключ -save-temps" - --#: gcc.c:4055 -+#: gcc.c:4056 - #, fuzzy, gcc-internal-format - msgid "%<-x %s%> after last input file has no effect" - msgstr "предупреждение: '-x %s' не имеет смысла за последним входным файлом" - --#: gcc.c:4217 -+#: gcc.c:4218 - #, gcc-internal-format - msgid "unable to locate default linker script %qs in the library search paths" - msgstr "" - --#: gcc.c:4421 -+#: gcc.c:4422 - #, fuzzy, gcc-internal-format - msgid "switch %qs does not start with %<-%>" - msgstr "ключ '%s' не начинается с '-'" - --#: gcc.c:4424 -+#: gcc.c:4425 - #, gcc-internal-format - msgid "spec-generated switch is just %<-%>" - msgstr "" - --#: gcc.c:4515 -+#: gcc.c:4516 - #, gcc-internal-format, gfc-internal-format - msgid "could not open temporary response file %s" - msgstr "не удалось открыть временный файл ответа %s" - --#: gcc.c:4521 -+#: gcc.c:4522 - #, gcc-internal-format, gfc-internal-format - msgid "could not write to temporary response file %s" - msgstr "не удалось записать во временный файл ответа %s" - --#: gcc.c:4527 -+#: gcc.c:4528 - #, gcc-internal-format, gfc-internal-format - msgid "could not close temporary response file %s" - msgstr "не удалось закрыть временный файл ответа %s" - --#: gcc.c:4650 -+#: gcc.c:4651 - #, fuzzy, gcc-internal-format - msgid "spec %qs invalid" - msgstr "спецификация '%s' некорректна" - --#: gcc.c:4799 -+#: gcc.c:4800 - #, fuzzy, gcc-internal-format - msgid "spec %qs has invalid %<%%0%c%>" - msgstr "спецификация '%s' имеет некорректный '%%0%c'" - --#: gcc.c:5118 -+#: gcc.c:5119 - #, fuzzy, gcc-internal-format - msgid "spec %qs has invalid %<%%W%c%>" - msgstr "спецификация '%s' имеет некорректный '%%W%c'" - --#: gcc.c:5140 -+#: gcc.c:5141 - #, fuzzy, gcc-internal-format - msgid "spec %qs has invalid %<%%x%c%>" - msgstr "спецификация '%s' имеет некорректный '%%x%c'" -@@ -15105,222 +15063,221 @@ - #. Catch the case where a spec string contains something like - #. '%{foo:%*}'. i.e. there is no * in the pattern on the left - #. hand side of the :. --#: gcc.c:5341 -+#: gcc.c:5342 - #, fuzzy, gcc-internal-format - msgid "spec failure: %<%%*%> has not been initialized by pattern match" - msgstr "ошибка спецификации: элемент '%%*' не инициализирован при сопоставлении" - --#: gcc.c:5384 -+#: gcc.c:5385 - #, fuzzy, gcc-internal-format - msgid "spec failure: unrecognized spec option %qc" - msgstr "ошибка спецификации: неопознанный ключ '%c'" - --#: gcc.c:5446 -+#: gcc.c:5447 - #, fuzzy, gcc-internal-format - msgid "unknown spec function %qs" - msgstr "неизвестная функция '%s' в спецификации" - --#: gcc.c:5476 -+#: gcc.c:5477 - #, fuzzy, gcc-internal-format - msgid "error in args to spec function %qs" - msgstr "ошибка в аргументах spec-функции '%s'" - --#: gcc.c:5527 -+#: gcc.c:5528 - #, gcc-internal-format - msgid "malformed spec function name" - msgstr "некорректное имя spec-функции" - - #. ) --#: gcc.c:5530 -+#: gcc.c:5531 - #, gcc-internal-format - msgid "no arguments for spec function" - msgstr "не заданы аргументы spec-функции" - --#: gcc.c:5549 -+#: gcc.c:5550 - #, gcc-internal-format - msgid "malformed spec function arguments" - msgstr "некорректные аргументы spec-функции" - --#: gcc.c:5810 -+#: gcc.c:5811 - #, fuzzy, gcc-internal-format - msgid "braced spec %qs is invalid at %qc" - msgstr "ошибка в спецификации '%s' в скобках на символе '%c'" - --#: gcc.c:5898 -+#: gcc.c:5899 - #, fuzzy, gcc-internal-format - msgid "braced spec body %qs is invalid" - msgstr "ошибка в спецификации '%s' в скобках" - --#: gcc.c:6151 -+#: gcc.c:6152 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "%s: could not determine length of compare-debug file %s" - msgstr "не удалось записать файл отзыва %s" - --#: gcc.c:6162 -+#: gcc.c:6163 - #, gcc-internal-format, gfc-internal-format - msgid "%s: -fcompare-debug failure (length)" - msgstr "" - --#: gcc.c:6172 gcc.c:6213 -+#: gcc.c:6173 gcc.c:6214 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "%s: could not open compare-debug file %s" - msgstr "%s:ошибка открытия выходного файла '%s'\n" - --#: gcc.c:6192 gcc.c:6229 -+#: gcc.c:6193 gcc.c:6230 - #, gcc-internal-format, gfc-internal-format - msgid "%s: -fcompare-debug failure" - msgstr "" - --#: gcc.c:6304 -+#: gcc.c:6305 - #, fuzzy, gcc-internal-format - msgid "atexit failed" - msgstr "ошибка в pex_init" - --#: gcc.c:6453 -+#: gcc.c:6454 - #, gcc-internal-format - msgid "spec failure: more than one arg to SYSROOT_SUFFIX_SPEC" - msgstr "ошибка спецификации: задано более одного аргумента для SYSROOT_SUFFIX_SPEC" - --#: gcc.c:6477 -+#: gcc.c:6478 - #, gcc-internal-format - msgid "spec failure: more than one arg to SYSROOT_HEADERS_SUFFIX_SPEC" - msgstr "ошибка спецификации: задано более одного аргумента для SYSROOT_HEADERS_SUFFIX_SPEC" - --#: gcc.c:6643 -+#: gcc.c:6645 - #, fuzzy, gcc-internal-format - msgid "unrecognized command line option %<-%s%>" - msgstr "некорректный ключ \"%s\"" - - #. The error status indicates that only one set of fixed - #. headers should be built. --#: gcc.c:6729 -+#: gcc.c:6731 - #, gcc-internal-format - msgid "not configured with sysroot headers suffix" - msgstr "суффикс системных заголовков не сконфигурирован" - --#: gcc.c:6812 -+#: gcc.c:6814 - #, gcc-internal-format - msgid "no input files" - msgstr "не заданы входные файлы" - --#: gcc.c:6861 -+#: gcc.c:6863 - #, fuzzy, gcc-internal-format - msgid "cannot specify -o with -c, -S or -E with multiple files" - msgstr "нельзя использовать -o с -c или -S и несколькими файлами" - --#: gcc.c:6891 -+#: gcc.c:6893 - #, gcc-internal-format, gfc-internal-format - msgid "%s: %s compiler not installed on this system" - msgstr "%s: компилятор %s не установлен" - --#: gcc.c:6913 -+#: gcc.c:6915 - #, gcc-internal-format - msgid "recompiling with -fcompare-debug" - msgstr "" - --#: gcc.c:6929 -+#: gcc.c:6931 - #, gcc-internal-format - msgid "during -fcompare-debug recompilation" - msgstr "" - --#: gcc.c:6938 -+#: gcc.c:6940 - #, fuzzy, gcc-internal-format - msgid "comparing final insns dumps" - msgstr "результат сравнения - всегда %d" - --#: gcc.c:7044 -+#: gcc.c:7046 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "-fuse-linker-plugin, but %s not found" - msgstr "нет поля %qs" - --#: gcc.c:7076 -+#: gcc.c:7079 - #, gcc-internal-format, gfc-internal-format - msgid "%s: linker input file unused because linking not done" - msgstr "%s: входные файлы компоновки не использованы, поскольку компоновка не выполнялась" - --#: gcc.c:7117 -+#: gcc.c:7120 - #, gcc-internal-format, gfc-internal-format - msgid "language %s not recognized" - msgstr "некорректное задание языка %s" - --#: gcc.c:7344 -+#: gcc.c:7347 - #, fuzzy, gcc-internal-format - msgid "multilib spec %qs is invalid" - msgstr "описание мультибиблиотеки '%s' некорректно" - --#: gcc.c:7538 -+#: gcc.c:7541 - #, fuzzy, gcc-internal-format - msgid "multilib exclusions %qs is invalid" - msgstr "исключения '%s' в мультибиблиотеке некорректны" - --#: gcc.c:7602 -+#: gcc.c:7605 - #, fuzzy, gcc-internal-format - msgid "multilib select %qs %qs is invalid" - msgstr "выбор мультибиблиотеки '%s' некорректен" - --#: gcc.c:7758 -+#: gcc.c:7761 - #, fuzzy, gcc-internal-format - msgid "multilib select %qs is invalid" - msgstr "выбор мультибиблиотеки '%s' некорректен" - --#: gcc.c:7797 -+#: gcc.c:7800 - #, fuzzy, gcc-internal-format - msgid "multilib exclusion %qs is invalid" - msgstr "исключение '%s' в мультибиблиотеке некорректно" - --#: gcc.c:8003 -+#: gcc.c:8006 - #, fuzzy, gcc-internal-format - msgid "environment variable %qs not defined" - msgstr "переменная окружения \"%s\" не определена" - --#: gcc.c:8115 gcc.c:8120 -+#: gcc.c:8118 gcc.c:8123 - #, fuzzy, gcc-internal-format - msgid "invalid version number %qs" - msgstr "некорректный номер версии '%s'" - --#: gcc.c:8163 -+#: gcc.c:8166 - #, gcc-internal-format, gfc-internal-format - msgid "too few arguments to %%:version-compare" - msgstr "слишком мало аргументов в %%:version-compare" - --#: gcc.c:8169 -+#: gcc.c:8172 - #, gcc-internal-format, gfc-internal-format - msgid "too many arguments to %%:version-compare" - msgstr "слишком много аргументов в %%:version-compare" - --#: gcc.c:8210 -+#: gcc.c:8213 - #, fuzzy, gcc-internal-format - msgid "unknown operator %qs in %%:version-compare" - msgstr "Неизвестный оператор '%s' в %%:version-compare" - --#: gcc.c:8333 -+#: gcc.c:8336 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "too many arguments to %%:compare-debug-dump-opt" - msgstr "слишком много аргументов в %%:version-compare" - --#: gcc.c:8405 -+#: gcc.c:8408 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "too many arguments to %%:compare-debug-self-opt" - msgstr "слишком много аргументов в %%:version-compare" - --#: gcc.c:8440 -+#: gcc.c:8443 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "too few arguments to %%:compare-debug-auxbase-opt" - msgstr "слишком мало аргументов в %%:version-compare" - --#: gcc.c:8443 -+#: gcc.c:8446 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "too many arguments to %%:compare-debug-auxbase-opt" - msgstr "слишком много аргументов в %%:version-compare" - --#: gcc.c:8450 -+#: gcc.c:8453 - #, gcc-internal-format, gfc-internal-format - msgid "argument to %%:compare-debug-auxbase-opt does not end in .gk" - msgstr "" - --#: gcc.c:8524 -+#: gcc.c:8527 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "too few arguments to function" - msgid "too few arguments to %%:replace-extension" - msgstr "слишком мало аргументов функции" - -@@ -15340,13 +15297,13 @@ - msgid "can%'t write padding to PCH file: %m" - msgstr "ошибка записи заполнителя в PCH файл: %m" - --#: ggc-common.c:615 ggc-common.c:623 ggc-common.c:630 ggc-common.c:633 --#: ggc-common.c:643 ggc-common.c:646 ggc-page.c:2439 -+#: ggc-common.c:681 ggc-common.c:689 ggc-common.c:696 ggc-common.c:699 -+#: ggc-common.c:709 ggc-common.c:712 ggc-page.c:2439 - #, fuzzy, gcc-internal-format - msgid "can%'t read PCH file: %m" - msgstr "ошибка чтения PCH файла: %m" - --#: ggc-common.c:638 -+#: ggc-common.c:704 - #, gcc-internal-format - msgid "had to relocate PCH" - msgstr "пришлось переместить PCH" -@@ -15498,7 +15455,7 @@ - #. Fatal error here. We do not want to support compiling ltrans units with - #. different version of compiler or different flags than the WPA unit, so - #. this should never happen. --#: ipa-reference.c:1148 -+#: ipa-reference.c:1146 - #, gcc-internal-format - msgid "ipa reference summary is missing in ltrans unit" - msgstr "" -@@ -15690,27 +15647,27 @@ - msgid "invalid branch to/from an OpenMP structured block" - msgstr " входит в try-блок" - --#: opts-common.c:997 -+#: opts-common.c:1030 - #, gcc-internal-format - msgid "command line option %qs is not supported by this configuration" - msgstr "ключ %qs для этой конфигурации не поддерживается" - --#: opts-common.c:1007 -+#: opts-common.c:1040 - #, fuzzy, gcc-internal-format - msgid "missing argument to %qs" - msgstr "отсутствует аргумент для \"%s\"" - --#: opts-common.c:1013 -+#: opts-common.c:1046 - #, fuzzy, gcc-internal-format - msgid "argument to %qs should be a non-negative integer" - msgstr "аргумент \"%s\" должен быть неотрицательным целым числом" - --#: opts-common.c:1028 -+#: opts-common.c:1061 - #, fuzzy, gcc-internal-format - msgid "unrecognized argument in option %qs" - msgstr "некорректный ключ \"%s\"" - --#: opts-common.c:1044 -+#: opts-common.c:1077 - #, fuzzy, gcc-internal-format - msgid "valid arguments to %qs are: %s" - msgstr "некорректный аргумент атрибута %qs" -@@ -15766,137 +15723,137 @@ - msgid "%<-femit-struct-debug-detailed=dir:...%> must allow at least as much as %<-femit-struct-debug-detailed=ind:...%>" - msgstr "" - --#: opts.c:542 -+#: opts.c:544 - #, fuzzy, gcc-internal-format - msgid "argument to %<-O%> should be a non-negative integer, %, % or %" - msgstr "аргумент \"%s\" должен быть неотрицательным целым числом" - --#: opts.c:669 -+#: opts.c:672 - #, gcc-internal-format - msgid "section anchors must be disabled when unit-at-a-time is disabled" - msgstr "" - --#: opts.c:673 -+#: opts.c:676 - #, gcc-internal-format - msgid "toplevel reorder must be disabled when unit-at-a-time is disabled" - msgstr "" - --#: opts.c:679 -+#: opts.c:682 - #, fuzzy, gcc-internal-format - msgid "transactional memory is not supported with non-call exceptions" - msgstr "-m%s в данной конфигурации не поддерживается" - --#: opts.c:694 -+#: opts.c:697 - #, gcc-internal-format - msgid "section anchors must be disabled when toplevel reorder is disabled" - msgstr "" - --#: opts.c:729 config/darwin.c:3061 config/sh/sh.c:936 -+#: opts.c:732 config/darwin.c:3061 config/sh/sh.c:933 - #, fuzzy, gcc-internal-format - msgid "-freorder-blocks-and-partition does not work with exceptions on this architecture" - msgstr "-freorder-blocks-and-partition не работает для заданной архитектуры" - --#: opts.c:744 config/sh/sh.c:944 -+#: opts.c:747 config/sh/sh.c:941 - #, fuzzy, gcc-internal-format - msgid "-freorder-blocks-and-partition does not support unwind info on this architecture" - msgstr "-freorder-blocks-and-partition не работает для заданной архитектуры" - --#: opts.c:761 config/pa/pa.c:526 -+#: opts.c:764 config/pa/pa.c:526 - #, gcc-internal-format - msgid "-freorder-blocks-and-partition does not work on this architecture" - msgstr "-freorder-blocks-and-partition не работает для заданной архитектуры" - --#: opts.c:797 -+#: opts.c:800 - #, gcc-internal-format - msgid "-fno-fat-lto-objects are supported only with linker plugin." - msgstr "" - --#: opts.c:805 -+#: opts.c:808 - #, gcc-internal-format - msgid "only one -flto-partition value can be specified" - msgstr "" - --#: opts.c:816 -+#: opts.c:819 - #, fuzzy, gcc-internal-format - msgid "%<-fsplit-stack%> is not supported by this compiler configuration" - msgstr "%s для этой конфигурации не поддерживается" - --#: opts.c:1193 -+#: opts.c:1196 - #, gcc-internal-format - msgid "unrecognized include_flags 0x%x passed to print_specific_help" - msgstr "" - --#: opts.c:1373 -+#: opts.c:1376 - #, gcc-internal-format - msgid "--help argument %q.*s is ambiguous, please be more specific" - msgstr "" - --#: opts.c:1382 -+#: opts.c:1385 - #, fuzzy, gcc-internal-format - msgid "unrecognized argument to --help= option: %q.*s" - msgstr "предупреждение: неизвестный аргумент ключа --help=: %.*s\n" - --#: opts.c:1547 -+#: opts.c:1550 - #, gcc-internal-format, gfc-internal-format - msgid "structure alignment must be a small power of two, not %d" - msgstr "выравнивание структуры должно быть небольшой степенью двойки, а не %d" - --#: opts.c:1664 -+#: opts.c:1667 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "unknown stack check parameter \"%s\"" - msgstr "параметр %q+D не используется" - --#: opts.c:1701 -+#: opts.c:1704 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "dwarf version %d is not supported" - msgstr "выражение для границы стека не поддерживается" - --#: opts.c:1791 -+#: opts.c:1794 - #, gcc-internal-format, gfc-internal-format - msgid "%s: --param arguments should be of the form NAME=VALUE" - msgstr "%s: аргументы --param должны иметь вид ИМЯ=ЗНАЧЕНИЕ" - --#: opts.c:1797 -+#: opts.c:1800 - #, gcc-internal-format - msgid "invalid --param value %qs" - msgstr "некорректное значение ключа --param %qs" - --#: opts.c:1915 -+#: opts.c:1918 - #, gcc-internal-format - msgid "target system does not support debug output" - msgstr "целевая платформа не поддерживает вывод отладочной информации" - --#: opts.c:1924 -+#: opts.c:1927 - #, gcc-internal-format, gfc-internal-format - msgid "debug format \"%s\" conflicts with prior selection" - msgstr "отладочный формат \"%s\" противоречит предыдущему выбору" - --#: opts.c:1940 -+#: opts.c:1943 - #, gcc-internal-format, gfc-internal-format - msgid "unrecognised debug output level \"%s\"" - msgstr "некорректный уровень отладочной информации \"%s\"" - --#: opts.c:1942 -+#: opts.c:1945 - #, gcc-internal-format, gfc-internal-format - msgid "debug output level %s is too high" - msgstr "уровень отладочной информации %s слишком высок" - --#: opts.c:1962 -+#: opts.c:1965 - #, gcc-internal-format - msgid "getting core file size maximum limit: %m" - msgstr "исходный максимальный размер core-файла: %m" - --#: opts.c:1965 -+#: opts.c:1968 - #, gcc-internal-format - msgid "setting core file size limit to maximum: %m" - msgstr "установлен максимальный размер core-файла: %m" - --#: opts.c:2010 -+#: opts.c:2013 - #, gcc-internal-format, gfc-internal-format - msgid "unrecognized gcc debugging option: %c" - msgstr "некорректный ключ отладки: %c" - --#: opts.c:2036 -+#: opts.c:2039 - #, gcc-internal-format, gfc-internal-format - msgid "-Werror=%s: no option -%s" - msgstr "" -@@ -16157,8 +16114,8 @@ - msgstr "нельзя использовать '%s' как %s регистр" - - #: reginfo.c:750 config/ia64/ia64.c:5897 config/ia64/ia64.c:5904 --#: config/pa/pa.c:428 config/pa/pa.c:435 config/sh/sh.c:9362 --#: config/sh/sh.c:9369 config/spu/spu.c:4908 config/spu/spu.c:4915 -+#: config/pa/pa.c:428 config/pa/pa.c:435 config/sh/sh.c:9359 -+#: config/sh/sh.c:9366 config/spu/spu.c:4908 config/spu/spu.c:4915 - #, gcc-internal-format, gfc-internal-format - msgid "unknown register name: %s" - msgstr "неизвестное имя регистра: %s" -@@ -16238,42 +16195,42 @@ - msgid "output operand is constant in %" - msgstr "выходной операнд % - константа" - --#: rtl.c:738 -+#: rtl.c:742 - #, gcc-internal-format, gfc-internal-format - msgid "RTL check: access of elt %d of '%s' with last elt %d in %s, at %s:%d" - msgstr "RTL: доступ к эл-ту %d '%s' последним элементом %d; функция %s, в %s:%d" - --#: rtl.c:748 -+#: rtl.c:752 - #, gcc-internal-format, gfc-internal-format - msgid "RTL check: expected elt %d type '%c', have '%c' (rtx %s) in %s, at %s:%d" - msgstr "RTL: ожидался эл-т %d типа '%c', имеется '%c' (rtx %s); функция %s, в %s:%d" - --#: rtl.c:758 -+#: rtl.c:762 - #, gcc-internal-format, gfc-internal-format - msgid "RTL check: expected elt %d type '%c' or '%c', have '%c' (rtx %s) in %s, at %s:%d" - msgstr "RTL: ожидался эл-т %d типа '%c' или '%c', имеется '%c' (rtx %s); функция %s, в %s:%d" - --#: rtl.c:767 -+#: rtl.c:771 - #, gcc-internal-format, gfc-internal-format - msgid "RTL check: expected code '%s', have '%s' in %s, at %s:%d" - msgstr "RTL: ожидался код '%s', обнаружено '%s'; функция %s, в %s:%d" - --#: rtl.c:777 -+#: rtl.c:781 - #, gcc-internal-format, gfc-internal-format - msgid "RTL check: expected code '%s' or '%s', have '%s' in %s, at %s:%d" - msgstr "RTL: ожидался код '%s' или '%s', обнаружено '%s'; функция %s, в %s:%d" - --#: rtl.c:804 -+#: rtl.c:808 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "RTL check: attempt to treat non-block symbol as a block symbol in %s, at %s:%d" - msgstr "RTL: доступ к эл-ту %d '%s' последним элементом %d; функция %s, в %s:%d" - --#: rtl.c:814 -+#: rtl.c:818 - #, gcc-internal-format, gfc-internal-format - msgid "RTL check: access of elt %d of vector with last elt %d in %s, at %s:%d" - msgstr "RTL: доступ к эл-ту %d вектора с числом эл-тов %d; функция %s, в %s:%d" - --#: rtl.c:825 -+#: rtl.c:829 - #, gcc-internal-format, gfc-internal-format - msgid "RTL flag check: %s used with unexpected rtx code '%s' in %s, at %s:%d" - msgstr "RTL флаги: %s использован с неподходящим rtx-кодом '%s' в %s, в %s:%d" -@@ -16510,7 +16467,6 @@ - - #: symtab.c:686 - #, fuzzy, gcc-internal-format --#| msgid "verify_cgraph_node failed" - msgid "verify_symtab_node failed" - msgstr "процедура verify_cgraph_node выявила ошибки" - -@@ -16706,7 +16662,6 @@ - - #: toplev.c:1547 - #, fuzzy, gcc-internal-format --#| msgid "-fdata-sections not supported for this target" - msgid "-fsanitize=address not supported for this target" - msgstr "-fdata-sections не поддерживается для этой целевой машины" - -@@ -16730,7 +16685,7 @@ - msgid "% function call not within outer transaction or %" - msgstr "" - --#: trans-mem.c:676 trans-mem.c:4569 -+#: trans-mem.c:676 trans-mem.c:4570 - #, gcc-internal-format - msgid "unsafe function call %qD within atomic transaction" - msgstr "" -@@ -16745,7 +16700,7 @@ - msgid "unsafe indirect function call within atomic transaction" - msgstr "inline-функции, переопределённые как extern, не подлежат подстановке" - --#: trans-mem.c:694 trans-mem.c:4502 -+#: trans-mem.c:694 trans-mem.c:4503 - #, gcc-internal-format - msgid "unsafe function call %qD within % function" - msgstr "" -@@ -16760,7 +16715,7 @@ - msgid "unsafe indirect function call within % function" - msgstr "" - --#: trans-mem.c:719 trans-mem.c:4541 -+#: trans-mem.c:719 trans-mem.c:4542 - #, fuzzy, gcc-internal-format - msgid "asm not allowed in atomic transaction" - msgstr "пространство имён %qD не допускается в using-декларации" -@@ -16795,7 +16750,7 @@ - msgid "outer transaction in % function" - msgstr "" - --#: trans-mem.c:4169 -+#: trans-mem.c:4170 - #, fuzzy, gcc-internal-format - msgid "%Kasm not allowed in % function" - msgstr "атрибуты не допускаются при определении функции" -@@ -16845,7 +16800,7 @@ - msgid "MODIFY_EXPR not expected while having tuples" - msgstr "" - --#: tree-cfg.c:2613 tree-ssa.c:879 -+#: tree-cfg.c:2613 tree-ssa.c:876 - #, gcc-internal-format - msgid "address taken, but ADDRESSABLE bit not set" - msgstr "адрес был взят, а бит ADDRESSABLE не установлен" -@@ -17262,13 +17217,11 @@ - - #: tree-cfg.c:4109 - #, fuzzy, gcc-internal-format --#| msgid "% label not within a switch statement" - msgid "invalid default case label in switch statement" - msgstr "метка % вне оператора switch" - - #: tree-cfg.c:4121 - #, fuzzy, gcc-internal-format --#| msgid "case label not within a switch statement" - msgid "invalid case label in switch statement" - msgstr "case-метка вне оператора switch" - -@@ -17279,19 +17232,16 @@ - - #: tree-cfg.c:4138 - #, fuzzy, gcc-internal-format --#| msgid "case label not within a switch statement" - msgid "type mismatch for case label in switch statement" - msgstr "case-метка вне оператора switch" - - #: tree-cfg.c:4148 - #, fuzzy, gcc-internal-format --#| msgid "case label not within a switch statement" - msgid "type precision mismatch in switch statement" - msgstr "case-метка вне оператора switch" - - #: tree-cfg.c:4157 - #, fuzzy, gcc-internal-format --#| msgid "case label not within a switch statement" - msgid "case labels not sorted in switch statement" - msgstr "case-метка вне оператора switch" - -@@ -17335,7 +17285,7 @@ - msgid "incompatible types in PHI argument %u" - msgstr "несовместимые типы в присваивании" - --#: tree-cfg.c:4433 tree-cfg.c:4727 -+#: tree-cfg.c:4433 tree-cfg.c:4738 - #, fuzzy, gcc-internal-format - msgid "verify_gimple failed" - msgstr "процедура verify_stmts выявила ошибки" -@@ -17350,150 +17300,148 @@ - msgid "location references block not in block tree" - msgstr "" - --#: tree-cfg.c:4594 -+#: tree-cfg.c:4605 - #, fuzzy, gcc-internal-format - msgid "gimple_bb (phi) is set to a wrong basic block" - msgstr "bb_for_stmt (phi) указывает не на тот блок" - --#: tree-cfg.c:4603 -+#: tree-cfg.c:4614 - #, fuzzy, gcc-internal-format --#| msgid "from this location" - msgid "PHI node with location" - msgstr "в этом месте" - --#: tree-cfg.c:4614 tree-cfg.c:4663 -+#: tree-cfg.c:4625 tree-cfg.c:4674 - #, gcc-internal-format - msgid "incorrect sharing of tree nodes" - msgstr "недопустимое разделение узлов дерева" - --#: tree-cfg.c:4622 -+#: tree-cfg.c:4633 - #, gcc-internal-format - msgid "virtual PHI with argument locations" - msgstr "" - --#: tree-cfg.c:4651 -+#: tree-cfg.c:4662 - #, fuzzy, gcc-internal-format - msgid "gimple_bb (stmt) is set to a wrong basic block" - msgstr "bb_for_stmt (stmt) указывает не на тот блок" - --#: tree-cfg.c:4687 -+#: tree-cfg.c:4698 - #, fuzzy, gcc-internal-format - msgid "in statement" - msgstr "ожидался оператор" - --#: tree-cfg.c:4702 -+#: tree-cfg.c:4713 - #, gcc-internal-format - msgid "statement marked for throw, but doesn%'t" - msgstr "оператор помечен как throw, но не является таковым" - --#: tree-cfg.c:4709 -+#: tree-cfg.c:4720 - #, gcc-internal-format - msgid "statement marked for throw in middle of block" - msgstr "оператор помечен как throw в середине блока" - --#: tree-cfg.c:4751 -+#: tree-cfg.c:4762 - #, fuzzy, gcc-internal-format - msgid "ENTRY_BLOCK has IL associated with it" - msgstr "с ENTRY_BLOCK ассоциирован список операторов" - --#: tree-cfg.c:4757 -+#: tree-cfg.c:4768 - #, fuzzy, gcc-internal-format - msgid "EXIT_BLOCK has IL associated with it" - msgstr "с EXIT_BLOCK ассоциирован список операторов" - --#: tree-cfg.c:4764 -+#: tree-cfg.c:4775 - #, gcc-internal-format, gfc-internal-format - msgid "fallthru to exit from bb %d" - msgstr "сквозной выход из блока %d" - --#: tree-cfg.c:4788 -+#: tree-cfg.c:4799 - #, gcc-internal-format - msgid "nonlocal label " - msgstr "" - --#: tree-cfg.c:4797 -+#: tree-cfg.c:4808 - #, gcc-internal-format - msgid "EH landing pad label " - msgstr "" - --#: tree-cfg.c:4806 tree-cfg.c:4815 tree-cfg.c:4840 -+#: tree-cfg.c:4817 tree-cfg.c:4826 tree-cfg.c:4851 - #, gcc-internal-format - msgid "label " - msgstr "" - --#: tree-cfg.c:4830 -+#: tree-cfg.c:4841 - #, gcc-internal-format, gfc-internal-format - msgid "control flow in the middle of basic block %d" - msgstr "инструкция управления потоком выполнения внутри блока %d" - --#: tree-cfg.c:4863 -+#: tree-cfg.c:4874 - #, gcc-internal-format, gfc-internal-format - msgid "fallthru edge after a control statement in bb %d" - msgstr "сквозная дуга после оператора управления в блоке %d" - --#: tree-cfg.c:4876 -+#: tree-cfg.c:4887 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "true/false edge after a non-GIMPLE_COND in bb %d" - msgstr "дуга true/false после не COND_EXPR в блоке %d" - --#: tree-cfg.c:4899 tree-cfg.c:4921 tree-cfg.c:4938 tree-cfg.c:5007 -+#: tree-cfg.c:4910 tree-cfg.c:4932 tree-cfg.c:4949 tree-cfg.c:5018 - #, gcc-internal-format, gfc-internal-format - msgid "wrong outgoing edge flags at end of bb %d" - msgstr "некорректные флаги выходной дуги в конце блока %d" - --#: tree-cfg.c:4909 -+#: tree-cfg.c:4920 - #, gcc-internal-format, gfc-internal-format - msgid "explicit goto at end of bb %d" - msgstr "явный переход goto в конце блока %d" - --#: tree-cfg.c:4943 -+#: tree-cfg.c:4954 - #, gcc-internal-format, gfc-internal-format - msgid "return edge does not point to exit in bb %d" - msgstr "дуга return не указывает на конец блока %d" - --#: tree-cfg.c:4973 -+#: tree-cfg.c:4984 - #, fuzzy, gcc-internal-format - msgid "found default case not at the start of case vector" - msgstr "случай default - не в конце case-вектора" - --#: tree-cfg.c:4981 -+#: tree-cfg.c:4992 - #, fuzzy, gcc-internal-format - msgid "case labels not sorted: " - msgstr "case-метки не отсортированы" - --#: tree-cfg.c:4998 -+#: tree-cfg.c:5009 - #, gcc-internal-format, gfc-internal-format - msgid "extra outgoing edge %d->%d" - msgstr "лишняя исходящая дуга %d->%d" - --#: tree-cfg.c:5021 -+#: tree-cfg.c:5032 - #, gcc-internal-format, gfc-internal-format - msgid "missing edge %i->%i" - msgstr "отсутствует дуга %i->%i" - --#: tree-cfg.c:7803 -+#: tree-cfg.c:7814 - #, fuzzy, gcc-internal-format - msgid "% function does return" - msgstr "%Hвыход из функции с атрибутом %" - --#: tree-cfg.c:7823 -+#: tree-cfg.c:7834 - #, fuzzy, gcc-internal-format - msgid "control reaches end of non-void function" - msgstr "%Hуправление достигает конца не-void функции" - --#: tree-cfg.c:7963 -+#: tree-cfg.c:7974 - #, fuzzy, gcc-internal-format - msgid "ignoring return value of %qD, declared with attribute warn_unused_result" - msgstr "%Hрезультат %qD, декларированной с атрибутом warn_unused_result, игнорируется" - --#: tree-cfg.c:7968 -+#: tree-cfg.c:7979 - #, fuzzy, gcc-internal-format - msgid "ignoring return value of function declared with attribute warn_unused_result" - msgstr "%Hрезультат функции, декларированной с атрибутом warn_unused_result, игнорируется" - - #: tree-diagnostic.c:202 - #, fuzzy, gcc-internal-format --#| msgid "redefinition of %q+D" - msgid "in definition of macro %qs" - msgstr "переопределение %q+D" - -@@ -17502,122 +17450,122 @@ - msgid "in expansion of macro %qs" - msgstr "" - --#: tree-eh.c:4368 -+#: tree-eh.c:4396 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "BB %i has multiple EH edges" - msgstr "блок %i не может выдавать исключений, но имеет EH-дуги" - --#: tree-eh.c:4380 -+#: tree-eh.c:4408 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "BB %i can not throw but has an EH edge" - msgstr "блок %i не может выдавать исключений, но имеет EH-дуги" - --#: tree-eh.c:4388 -+#: tree-eh.c:4416 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "BB %i last statement has incorrectly set lp" - msgstr "в последнем операторе блока %i некорректно установлен регион" - --#: tree-eh.c:4394 -+#: tree-eh.c:4422 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i is missing an EH edge" - msgstr "" - --#: tree-eh.c:4400 -+#: tree-eh.c:4428 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "Incorrect EH edge %i->%i" - msgstr "ненужная EH-дуга %i->%i" - --#: tree-eh.c:4434 tree-eh.c:4453 -+#: tree-eh.c:4462 tree-eh.c:4481 - #, gcc-internal-format, gfc-internal-format - msgid "BB %i is missing an edge" - msgstr "" - --#: tree-eh.c:4470 -+#: tree-eh.c:4498 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "BB %i too many fallthru edges" - msgstr "некорректная RTL-инструкция в сквозной дуге" - --#: tree-eh.c:4479 -+#: tree-eh.c:4507 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "BB %i has incorrect edge" - msgstr "в последнем операторе блока %i некорректно установлен регион" - --#: tree-eh.c:4485 -+#: tree-eh.c:4513 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "BB %i has incorrect fallthru edge" - msgstr "некорректная RTL-инструкция в сквозной дуге" - --#: tree-inline.c:3012 -+#: tree-inline.c:3022 - #, fuzzy, gcc-internal-format - msgid "function %q+F can never be copied because it receives a non-local goto" - msgstr "inline-подстановка функции %q+F невозможна, поскольку имеют нелокальные переходы в эту функцию" - --#: tree-inline.c:3026 -+#: tree-inline.c:3036 - #, fuzzy, gcc-internal-format - msgid "function %q+F can never be copied because it saves address of local label in a static variable" - msgstr "inline-подстановка функции %q+F невозможна, поскольку функция использует переменные переменного размера" - --#: tree-inline.c:3066 -+#: tree-inline.c:3076 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses alloca (override using the always_inline attribute)" - msgstr "inline-подстановка функции %q+F невозможна, поскольку функция использует alloca (задайте атрибут always_inline)" - --#: tree-inline.c:3080 -+#: tree-inline.c:3090 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses setjmp" - msgstr "inline-подстановка функции %q+F невозможна, поскольку функция использует setjmp" - --#: tree-inline.c:3094 -+#: tree-inline.c:3104 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses variable argument lists" - msgstr "inline-подстановка функции %q+F невозможна, поскольку функция использует списки из переменного числа аргументов" - --#: tree-inline.c:3106 -+#: tree-inline.c:3116 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses setjmp-longjmp exception handling" - msgstr "inline-подстановка функции %q+F невозможна, поскольку функция содержит обработку исключительных ситуаций setjmp-longjmp" - --#: tree-inline.c:3114 -+#: tree-inline.c:3124 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses non-local goto" - msgstr "inline-подстановка функции %q+F невозможна, поскольку функция использует не локальный goto" - --#: tree-inline.c:3126 -+#: tree-inline.c:3136 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses __builtin_return or __builtin_apply_args" - msgstr "inline-подстановка функции %q+F невозможна, поскольку функция использует __builtin_return или __builtin_apply_args" - --#: tree-inline.c:3146 -+#: tree-inline.c:3156 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it contains a computed goto" - msgstr "inline-подстановка функции %q+F невозможна, поскольку функция использует вычисляемый goto" - --#: tree-inline.c:3249 -+#: tree-inline.c:3259 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it is suppressed using -fno-inline" - msgstr "подстановка функций %q+F невозможна, т.к. задан ключ -fno-inline" - --#: tree-inline.c:3257 -+#: tree-inline.c:3267 - #, gcc-internal-format - msgid "function %q+F can never be inlined because it uses attributes conflicting with inlining" - msgstr "подстановка функции %q+F невозможна, т.к. она имеет атрибуты, препятствующие inline-подстановке" - --#: tree-inline.c:3842 -+#: tree-inline.c:3852 - #, fuzzy, gcc-internal-format - msgid "inlining failed in call to always_inline %q+F: %s" - msgstr "inline-подстановка при вызове %q+F не выполнена: %s" - --#: tree-inline.c:3844 tree-inline.c:3859 -+#: tree-inline.c:3854 tree-inline.c:3869 - #, gcc-internal-format - msgid "called from here" - msgstr "которая вызвана здесь" - --#: tree-inline.c:3857 -+#: tree-inline.c:3867 - #, gcc-internal-format - msgid "inlining failed in call to %q+F: %s" - msgstr "inline-подстановка при вызове %q+F не выполнена: %s" - --#: tree-into-ssa.c:3209 tree-outof-ssa.c:774 tree-outof-ssa.c:831 -+#: tree-into-ssa.c:3226 tree-outof-ssa.c:774 tree-outof-ssa.c:831 - #: tree-ssa-coalesce.c:934 tree-ssa-live.c:1282 - #, gcc-internal-format - msgid "SSA corruption" -@@ -17648,6 +17596,16 @@ - msgid "unimplemented functionality" - msgstr "нереализованная функциональность" - -+#: tree-ssa-loop-niter.c:2557 -+#, fuzzy, gcc-internal-format -+msgid "iteration %E invokes undefined behavior" -+msgstr "операция над %qE может дать неопределенный результат" -+ -+#: tree-ssa-loop-niter.c:2559 -+#, gcc-internal-format -+msgid "containing loop" -+msgstr "" -+ - #: tree-ssa-operands.c:975 - #, gcc-internal-format - msgid "virtual definition of statement not up-to-date" -@@ -17683,142 +17641,142 @@ - msgid "stmt volatile flag not up-to-date" - msgstr "" - --#: tree-ssa-uninit.c:1943 tree-ssa.c:1668 -+#: tree-ssa-uninit.c:1946 tree-ssa.c:1665 - #, fuzzy, gcc-internal-format - msgid "%qD may be used uninitialized in this function" - msgstr "%H%qD, возможно, используется без инициализации в данной функции" - --#: tree-ssa.c:625 -+#: tree-ssa.c:622 - #, gcc-internal-format - msgid "expected an SSA_NAME object" - msgstr "ожидался объект SSA_NAME" - --#: tree-ssa.c:631 -+#: tree-ssa.c:628 - #, gcc-internal-format - msgid "found an SSA_NAME that had been released into the free pool" - msgstr "найден объект SSA_NAME, помещенный в пул свободной памяти" - --#: tree-ssa.c:638 -+#: tree-ssa.c:635 - #, gcc-internal-format - msgid "type mismatch between an SSA_NAME and its symbol" - msgstr "несоответствие типа между SSA_NAME и символом" - --#: tree-ssa.c:644 -+#: tree-ssa.c:641 - #, gcc-internal-format - msgid "found a virtual definition for a GIMPLE register" - msgstr "найдено виртуальное определение для GIMPLE-регистра" - --#: tree-ssa.c:650 -+#: tree-ssa.c:647 - #, gcc-internal-format - msgid "virtual SSA name for non-VOP decl" - msgstr "" - --#: tree-ssa.c:656 -+#: tree-ssa.c:653 - #, gcc-internal-format - msgid "found a real definition for a non-register" - msgstr "найдено действительное определение для не-регистра" - --#: tree-ssa.c:663 -+#: tree-ssa.c:660 - #, gcc-internal-format - msgid "found a default name with a non-empty defining statement" - msgstr "" - --#: tree-ssa.c:693 -+#: tree-ssa.c:690 - #, gcc-internal-format - msgid "RESULT_DECL should be read only when DECL_BY_REFERENCE is set" - msgstr "" - --#: tree-ssa.c:699 -+#: tree-ssa.c:696 - #, gcc-internal-format, gfc-internal-format - msgid "SSA_NAME created in two different blocks %i and %i" - msgstr "SSA_NAME создано в двух разных блоках %i и %i" - --#: tree-ssa.c:708 tree-ssa.c:1020 -+#: tree-ssa.c:705 tree-ssa.c:1017 - #, gcc-internal-format - msgid "SSA_NAME_DEF_STMT is wrong" - msgstr "некорректное SSA_NAME_DEF_STMT" - --#: tree-ssa.c:760 -+#: tree-ssa.c:757 - #, gcc-internal-format - msgid "missing definition" - msgstr "отсутствует определение" - --#: tree-ssa.c:766 -+#: tree-ssa.c:763 - #, gcc-internal-format, gfc-internal-format - msgid "definition in block %i does not dominate use in block %i" - msgstr "определение в блоке %i не должно доминировать над использованием в блоке %i" - --#: tree-ssa.c:774 -+#: tree-ssa.c:771 - #, gcc-internal-format, gfc-internal-format - msgid "definition in block %i follows the use" - msgstr "определение в блоке %i следует за использованием" - --#: tree-ssa.c:781 -+#: tree-ssa.c:778 - #, gcc-internal-format - msgid "SSA_NAME_OCCURS_IN_ABNORMAL_PHI should be set" - msgstr "должен быть установлен флаг SSA_NAME_OCCURS_IN_ABNORMAL_PHI" - --#: tree-ssa.c:789 -+#: tree-ssa.c:786 - #, gcc-internal-format - msgid "no immediate_use list" - msgstr "отсутствует список immediate_use" - --#: tree-ssa.c:801 -+#: tree-ssa.c:798 - #, gcc-internal-format - msgid "wrong immediate use list" - msgstr "некорректный список immediate use" - --#: tree-ssa.c:835 -+#: tree-ssa.c:832 - #, gcc-internal-format - msgid "incoming edge count does not match number of PHI arguments" - msgstr "число входящих дуг не соответствует числу аргументов PHI" - --#: tree-ssa.c:849 -+#: tree-ssa.c:846 - #, gcc-internal-format, gfc-internal-format - msgid "PHI argument is missing for edge %d->%d" - msgstr "отсутствует PHI-аргумент для дуги %d->%d" - --#: tree-ssa.c:858 -+#: tree-ssa.c:855 - #, gcc-internal-format - msgid "PHI argument is not SSA_NAME, or invariant" - msgstr "аргумент PHI не является SSA_NAME или инвариантом" - --#: tree-ssa.c:886 -+#: tree-ssa.c:883 - #, gcc-internal-format, gfc-internal-format - msgid "wrong edge %d->%d for PHI argument" - msgstr "некорректная дуга %d->%d для аргумента PHI" - --#: tree-ssa.c:967 -+#: tree-ssa.c:964 - #, gcc-internal-format, gfc-internal-format - msgid "AUX pointer initialized for edge %d->%d" - msgstr "инициализирован указатель AUX для дуги %d->%d" - --#: tree-ssa.c:992 -+#: tree-ssa.c:989 - #, fuzzy, gcc-internal-format - msgid "stmt (%p) marked modified after optimization pass: " - msgstr "оператор (%p) помечен как измененный после прохода оптимизации : " - --#: tree-ssa.c:1049 -+#: tree-ssa.c:1046 - #, gcc-internal-format - msgid "verify_ssa failed" - msgstr "процедура verify_ssa выявила ошибки" - --#: tree-ssa.c:1631 varasm.c:322 -+#: tree-ssa.c:1628 varasm.c:321 - #, fuzzy, gcc-internal-format - msgid "%qD was declared here" - msgstr " имя `%#D' объявлено здесь" - --#: tree-ssa.c:1663 -+#: tree-ssa.c:1660 - #, fuzzy, gcc-internal-format - msgid "%qD is used uninitialized in this function" - msgstr "%H%qD используется без инициализации в данной функции" - --#: tree-ssa.c:1700 -+#: tree-ssa.c:1697 - #, fuzzy, gcc-internal-format - msgid "%qE is used uninitialized in this function" - msgstr "%H%qD используется без инициализации в данной функции" - --#: tree-ssa.c:1705 -+#: tree-ssa.c:1702 - #, fuzzy, gcc-internal-format - msgid "%qE may be used uninitialized in this function" - msgstr "%H%qD, возможно, используется без инициализации в данной функции" -@@ -17938,24 +17896,24 @@ - msgid "%q+D redeclared without dllimport attribute: previous dllimport ignored" - msgstr "%q+D повторно декларирован(а) без атрибута dllimport: предшествующая декларация с dllimport игнорируется" - --#: tree.c:5610 tree.c:5622 tree.c:5632 c-family/c-common.c:6380 --#: c-family/c-common.c:6399 c-family/c-common.c:6417 c-family/c-common.c:6445 --#: c-family/c-common.c:6473 c-family/c-common.c:6501 c-family/c-common.c:6517 --#: c-family/c-common.c:6536 c-family/c-common.c:6553 c-family/c-common.c:6577 --#: c-family/c-common.c:6600 c-family/c-common.c:6617 c-family/c-common.c:6645 --#: c-family/c-common.c:6666 c-family/c-common.c:6687 c-family/c-common.c:6714 --#: c-family/c-common.c:6745 c-family/c-common.c:6782 c-family/c-common.c:6809 --#: c-family/c-common.c:6869 c-family/c-common.c:6954 c-family/c-common.c:6984 --#: c-family/c-common.c:7038 c-family/c-common.c:7496 c-family/c-common.c:7514 --#: c-family/c-common.c:7576 c-family/c-common.c:7619 c-family/c-common.c:7690 --#: c-family/c-common.c:7818 c-family/c-common.c:7886 c-family/c-common.c:7944 --#: c-family/c-common.c:7992 c-family/c-common.c:8155 c-family/c-common.c:8176 --#: c-family/c-common.c:8288 c-family/c-common.c:8312 c-family/c-common.c:8619 --#: c-family/c-common.c:8642 c-family/c-common.c:8681 c-family/c-common.c:8759 --#: c-family/c-common.c:8906 config/darwin.c:1997 config/arm/arm.c:5119 --#: config/arm/arm.c:5147 config/arm/arm.c:5164 config/avr/avr.c:7789 --#: config/h8300/h8300.c:5463 config/h8300/h8300.c:5487 config/i386/i386.c:4965 --#: config/i386/i386.c:34737 config/ia64/ia64.c:737 -+#: tree.c:5610 tree.c:5622 tree.c:5632 c-family/c-common.c:6385 -+#: c-family/c-common.c:6404 c-family/c-common.c:6422 c-family/c-common.c:6450 -+#: c-family/c-common.c:6478 c-family/c-common.c:6506 c-family/c-common.c:6522 -+#: c-family/c-common.c:6537 c-family/c-common.c:6558 c-family/c-common.c:6575 -+#: c-family/c-common.c:6599 c-family/c-common.c:6622 c-family/c-common.c:6639 -+#: c-family/c-common.c:6667 c-family/c-common.c:6688 c-family/c-common.c:6709 -+#: c-family/c-common.c:6736 c-family/c-common.c:6767 c-family/c-common.c:6804 -+#: c-family/c-common.c:6831 c-family/c-common.c:6891 c-family/c-common.c:6976 -+#: c-family/c-common.c:7006 c-family/c-common.c:7060 c-family/c-common.c:7518 -+#: c-family/c-common.c:7536 c-family/c-common.c:7598 c-family/c-common.c:7641 -+#: c-family/c-common.c:7712 c-family/c-common.c:7840 c-family/c-common.c:7908 -+#: c-family/c-common.c:7966 c-family/c-common.c:8014 c-family/c-common.c:8177 -+#: c-family/c-common.c:8198 c-family/c-common.c:8310 c-family/c-common.c:8334 -+#: c-family/c-common.c:8641 c-family/c-common.c:8664 c-family/c-common.c:8703 -+#: c-family/c-common.c:8781 c-family/c-common.c:8928 config/darwin.c:1997 -+#: config/arm/arm.c:5119 config/arm/arm.c:5147 config/arm/arm.c:5164 -+#: config/avr/avr.c:7789 config/h8300/h8300.c:5463 config/h8300/h8300.c:5487 -+#: config/i386/i386.c:4965 config/i386/i386.c:34737 config/ia64/ia64.c:737 - #: config/rs6000/rs6000.c:24907 config/spu/spu.c:3743 - #: ada/gcc-interface/utils.c:6189 lto/lto-lang.c:222 - #, gcc-internal-format -@@ -18137,137 +18095,137 @@ - msgid "variable tracking size limit exceeded" - msgstr "" - --#: varasm.c:315 -+#: varasm.c:314 - #, gcc-internal-format - msgid "%+D causes a section type conflict" - msgstr "%+D создает конфликт типов секций" - --#: varasm.c:318 -+#: varasm.c:317 - #, fuzzy, gcc-internal-format - msgid "%+D causes a section type conflict with %D" - msgstr "%+D создает конфликт типов секций" - --#: varasm.c:960 -+#: varasm.c:959 - #, gcc-internal-format - msgid "alignment of %q+D is greater than maximum object file alignment. Using %d" - msgstr "выравнивание %q+D превышает максимальное выравнивание в объектном файле. Используется %d" - --#: varasm.c:1200 varasm.c:1209 -+#: varasm.c:1198 varasm.c:1207 - #, gcc-internal-format - msgid "register name not specified for %q+D" - msgstr "не задано имя регистра для %q+D" - --#: varasm.c:1211 -+#: varasm.c:1209 - #, gcc-internal-format - msgid "invalid register name for %q+D" - msgstr "некорректное имя регистра для %q+D" - --#: varasm.c:1213 -+#: varasm.c:1211 - #, gcc-internal-format - msgid "data type of %q+D isn%'t suitable for a register" - msgstr "данные типа %q+D нельзя поместить на регистр" - --#: varasm.c:1216 -+#: varasm.c:1214 - #, fuzzy, gcc-internal-format - msgid "the register specified for %q+D cannot be accessed by the current target" - msgstr "регистр, заданный для %q+D, не годится для этого типа данных" - --#: varasm.c:1219 -+#: varasm.c:1217 - #, fuzzy, gcc-internal-format - msgid "the register specified for %q+D is not general enough to be used as a register variable" - msgstr "регистр назначен для двух глобальных регистровых переменных" - --#: varasm.c:1222 -+#: varasm.c:1220 - #, gcc-internal-format - msgid "register specified for %q+D isn%'t suitable for data type" - msgstr "регистр, заданный для %q+D, не годится для этого типа данных" - --#: varasm.c:1232 -+#: varasm.c:1230 - #, gcc-internal-format - msgid "global register variable has initial value" - msgstr "глобальная регистровая переменная имеет начальное значение" - --#: varasm.c:1236 -+#: varasm.c:1234 - #, gcc-internal-format - msgid "optimization may eliminate reads and/or writes to register variables" - msgstr "оптимизация может удалить чтения или записи регистровых переменных" - --#: varasm.c:1274 -+#: varasm.c:1272 - #, gcc-internal-format - msgid "register name given for non-register variable %q+D" - msgstr "имя регистра задано для нерегистровой переменной %q+D" - --#: varasm.c:1820 -+#: varasm.c:1818 - #, gcc-internal-format - msgid "thread-local COMMON data not implemented" - msgstr "поддержка локально-поточных COMMON-данных не реализована" - --#: varasm.c:1852 -+#: varasm.c:1850 - #, gcc-internal-format - msgid "requested alignment for %q+D is greater than implemented alignment of %wu" - msgstr "запрошенное выравнивание для %q+D превышает поддерживаемое выравнивание для %wu" - --#: varasm.c:1940 c/c-decl.c:4353 -+#: varasm.c:1938 c/c-decl.c:4353 - #, gcc-internal-format - msgid "storage size of %q+D isn%'t known" - msgstr "размер %q+D в памяти неизвестен" - --#: varasm.c:4605 -+#: varasm.c:4590 - #, fuzzy, gcc-internal-format - msgid "initializer for integer/fixed-point value is too complicated" - msgstr "слишком сложное инициализирующее выражение для целого" - --#: varasm.c:4610 -+#: varasm.c:4595 - #, gcc-internal-format - msgid "initializer for floating value is not a floating constant" - msgstr "инициализирующее выражение для плавающего не является плавающей константой" - --#: varasm.c:4918 -+#: varasm.c:4903 - #, fuzzy, gcc-internal-format - msgid "invalid initial value for member %qE" - msgstr "некорректное начальное значение для элемента %qs" - --#: varasm.c:5270 -+#: varasm.c:5255 - #, gcc-internal-format - msgid "weak declaration of %q+D must be public" - msgstr "weak декларация %q+D должна быть public" - --#: varasm.c:5272 -+#: varasm.c:5257 - #, gcc-internal-format - msgid "weak declaration of %q+D not supported" - msgstr "weak декларация %q+D не поддерживается" - --#: varasm.c:5301 varasm.c:5598 -+#: varasm.c:5286 varasm.c:5583 - #, gcc-internal-format - msgid "only weak aliases are supported in this configuration" - msgstr "в данной конфигурации поддерживаются только слабые алиасы" - --#: varasm.c:5490 -+#: varasm.c:5475 - #, fuzzy, gcc-internal-format - msgid "weakref is not supported in this configuration" - msgstr "%Jweakref в данной конфигурации не поддерживается" - --#: varasm.c:5513 varasm.c:5595 -+#: varasm.c:5498 varasm.c:5580 - #, fuzzy, gcc-internal-format - msgid "ifunc is not supported in this configuration" - msgstr "-m%s в данной конфигурации не поддерживается" - --#: varasm.c:5572 -+#: varasm.c:5557 - #, gcc-internal-format - msgid "weakref %q+D ultimately targets itself" - msgstr "слабая ссылка %q+D в конечном счёте направлена на себя" - --#: varasm.c:5581 -+#: varasm.c:5566 - #, fuzzy, gcc-internal-format - msgid "weakref %q+D must have static linkage" - msgstr "недопустимая декларация статического элемента-функции %qD" - --#: varasm.c:5588 -+#: varasm.c:5573 - #, fuzzy, gcc-internal-format - msgid "alias definitions not supported in this configuration" - msgstr "%Jв данной конфигурации определения алиасов не поддерживаются" - --#: varasm.c:5807 config/sol2.c:155 config/i386/winnt.c:254 -+#: varasm.c:5792 config/sol2.c:155 config/i386/winnt.c:254 - #, gcc-internal-format - msgid "visibility attribute not supported in this configuration; ignored" - msgstr "атрибут видимости не поддерживается в данной конфигурации; определение игнорируется" -@@ -18293,1316 +18251,1314 @@ - msgid "bytecode stream: tag %s is not in the expected range [%s, %s]" - msgstr "" - --#: c-family/c-common.c:911 -+#: c-family/c-common.c:916 - #, gcc-internal-format - msgid "%qD is not defined outside of function scope" - msgstr "%qD не определено вне функции" - --#: c-family/c-common.c:961 -+#: c-family/c-common.c:966 - #, gcc-internal-format - msgid "string length %qd is greater than the length %qd ISO C%d compilers are required to support" - msgstr "строка имеет длину %qd, превышающую максимальную длину %qd, которую должны поддерживать компиляторы по стандарту ISO C%d" - --#: c-family/c-common.c:1280 c/c-typeck.c:9864 cp/typeck.c:4158 -+#: c-family/c-common.c:1285 c/c-typeck.c:9864 cp/typeck.c:4158 - #, gcc-internal-format - msgid "left shift count is negative" - msgstr "сдвиг влево на отрицательное число позиций" - --#: c-family/c-common.c:1281 c/c-typeck.c:9812 cp/typeck.c:4112 -+#: c-family/c-common.c:1286 c/c-typeck.c:9812 cp/typeck.c:4112 - #, gcc-internal-format - msgid "right shift count is negative" - msgstr "сдвиг вправо на отрицательное число позиций" - --#: c-family/c-common.c:1286 c/c-typeck.c:9871 cp/typeck.c:4165 -+#: c-family/c-common.c:1291 c/c-typeck.c:9871 cp/typeck.c:4165 - #, gcc-internal-format - msgid "left shift count >= width of type" - msgstr "величина сдвига влево больше или равна ширине данного типа" - --#: c-family/c-common.c:1287 c/c-typeck.c:9823 cp/typeck.c:4119 -+#: c-family/c-common.c:1292 c/c-typeck.c:9823 cp/typeck.c:4119 - #, gcc-internal-format - msgid "right shift count >= width of type" - msgstr "величина сдвига вправо больше или равна ширине данного типа" - --#: c-family/c-common.c:1508 c-family/c-common.c:1520 cp/semantics.c:6865 -+#: c-family/c-common.c:1513 c-family/c-common.c:1525 cp/semantics.c:6867 - #, gcc-internal-format - msgid "overflow in constant expression" - msgstr "переполнение при вычислении константного выражения" - --#: c-family/c-common.c:1543 -+#: c-family/c-common.c:1548 - #, gcc-internal-format - msgid "integer overflow in expression" - msgstr "переполнение при вычислении целочисленного выражения" - --#: c-family/c-common.c:1548 -+#: c-family/c-common.c:1553 - #, gcc-internal-format - msgid "floating point overflow in expression" - msgstr "переполнение при вычислении выражения с плавающей точкой" - --#: c-family/c-common.c:1552 -+#: c-family/c-common.c:1557 - #, fuzzy, gcc-internal-format - msgid "fixed-point overflow in expression" - msgstr "переполнение при вычислении выражения с плавающей точкой" - --#: c-family/c-common.c:1556 -+#: c-family/c-common.c:1561 - #, gcc-internal-format - msgid "vector overflow in expression" - msgstr "переполнение при вычислении векторного выражения" - --#: c-family/c-common.c:1562 -+#: c-family/c-common.c:1567 - #, fuzzy, gcc-internal-format - msgid "complex integer overflow in expression" - msgstr "переполнение при вычислении целочисленного выражения" - --#: c-family/c-common.c:1565 -+#: c-family/c-common.c:1570 - #, fuzzy, gcc-internal-format - msgid "complex floating point overflow in expression" - msgstr "переполнение при вычислении выражения с плавающей точкой" - --#: c-family/c-common.c:1608 -+#: c-family/c-common.c:1613 - #, gcc-internal-format - msgid "logical % applied to non-boolean constant" - msgstr "" - --#: c-family/c-common.c:1611 -+#: c-family/c-common.c:1616 - #, gcc-internal-format - msgid "logical % applied to non-boolean constant" - msgstr "" - --#: c-family/c-common.c:1675 -+#: c-family/c-common.c:1680 - #, fuzzy, gcc-internal-format - msgid "logical % of collectively exhaustive tests is always true" - msgstr "%<или%> от двух взаимно исключающих сравнений на равенство - всегда 0" - --#: c-family/c-common.c:1679 -+#: c-family/c-common.c:1684 - #, fuzzy, gcc-internal-format - msgid "logical % of mutually exclusive tests is always false" - msgstr "%<или%> от двух взаимно исключающих сравнений на равенство - всегда 0" - --#: c-family/c-common.c:1811 -+#: c-family/c-common.c:1816 - #, gcc-internal-format - msgid "type-punning to incomplete type might break strict-aliasing rules" - msgstr "приведение к неполному типу может нарушить правила перекрытия объектов в памяти" - --#: c-family/c-common.c:1826 -+#: c-family/c-common.c:1831 - #, gcc-internal-format - msgid "dereferencing type-punned pointer will break strict-aliasing rules" - msgstr "доступ по указателю с приведением типа нарушает правила перекрытия объектов в памяти" - --#: c-family/c-common.c:1833 c-family/c-common.c:1851 -+#: c-family/c-common.c:1838 c-family/c-common.c:1856 - #, gcc-internal-format - msgid "dereferencing type-punned pointer might break strict-aliasing rules" - msgstr "доступ по указателю с приведением типа может нарушить правила перекрытия объектов в памяти" - --#: c-family/c-common.c:1985 -+#: c-family/c-common.c:1990 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the destination; did you mean to remove the addressof?" - msgstr "" - --#: c-family/c-common.c:1992 -+#: c-family/c-common.c:1997 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the destination; did you mean to provide an explicit length?" - msgstr "" - --#: c-family/c-common.c:1997 -+#: c-family/c-common.c:2002 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the destination; did you mean to dereference it?" - msgstr "" - --#: c-family/c-common.c:2009 -+#: c-family/c-common.c:2014 - #, gcc-internal-format - msgid "argument to % in %qD call is the same pointer type %qT as the destination; expected %qT or an explicit length" - msgstr "" - --#: c-family/c-common.c:2025 -+#: c-family/c-common.c:2030 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the source; did you mean to remove the addressof?" - msgstr "" - --#: c-family/c-common.c:2032 -+#: c-family/c-common.c:2037 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the source; did you mean to provide an explicit length?" - msgstr "" - --#: c-family/c-common.c:2037 -+#: c-family/c-common.c:2042 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the source; did you mean to dereference it?" - msgstr "" - --#: c-family/c-common.c:2049 -+#: c-family/c-common.c:2054 - #, gcc-internal-format - msgid "argument to % in %qD call is the same pointer type %qT as the source; expected %qT or an explicit length" - msgstr "" - --#: c-family/c-common.c:2065 -+#: c-family/c-common.c:2070 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the first source; did you mean to remove the addressof?" - msgstr "" - --#: c-family/c-common.c:2072 -+#: c-family/c-common.c:2077 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the first source; did you mean to provide an explicit length?" - msgstr "" - --#: c-family/c-common.c:2077 -+#: c-family/c-common.c:2082 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the first source; did you mean to dereference it?" - msgstr "" - --#: c-family/c-common.c:2089 -+#: c-family/c-common.c:2094 - #, gcc-internal-format - msgid "argument to % in %qD call is the same pointer type %qT as the first source; expected %qT or an explicit length" - msgstr "" - --#: c-family/c-common.c:2105 -+#: c-family/c-common.c:2110 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the second source; did you mean to remove the addressof?" - msgstr "" - --#: c-family/c-common.c:2112 -+#: c-family/c-common.c:2117 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the second source; did you mean to provide an explicit length?" - msgstr "" - --#: c-family/c-common.c:2117 -+#: c-family/c-common.c:2122 - #, gcc-internal-format - msgid "argument to % in %qD call is the same expression as the second source; did you mean to dereference it?" - msgstr "" - --#: c-family/c-common.c:2129 -+#: c-family/c-common.c:2134 - #, gcc-internal-format - msgid "argument to % in %qD call is the same pointer type %qT as the second source; expected %qT or an explicit length" - msgstr "" - --#: c-family/c-common.c:2161 -+#: c-family/c-common.c:2166 - #, gcc-internal-format - msgid "first argument of %q+D should be %" - msgstr "первый аргумент функции %q+D должен иметь тип %" - --#: c-family/c-common.c:2170 -+#: c-family/c-common.c:2175 - #, gcc-internal-format - msgid "second argument of %q+D should be %" - msgstr "второй аргумент функции %q+D должен иметь тип %" - --#: c-family/c-common.c:2179 -+#: c-family/c-common.c:2184 - #, gcc-internal-format - msgid "third argument of %q+D should probably be %" - msgstr "третий аргумент функции %q+D должен, по-видимому, иметь тип %" - --#: c-family/c-common.c:2190 -+#: c-family/c-common.c:2195 - #, gcc-internal-format - msgid "%q+D takes only zero or two arguments" - msgstr "%q+D может быть функцией с двумя аргументами, либо функцией без аргументов" - --#: c-family/c-common.c:2239 -+#: c-family/c-common.c:2244 - #, gcc-internal-format - msgid "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts" - msgstr "" - --#: c-family/c-common.c:2278 -+#: c-family/c-common.c:2283 - #, fuzzy, gcc-internal-format - msgid "__builtin_shuffle last argument must be an integer vector" - msgstr "первый аргумент должен быть 5-битным знаковым литеральным значением" - --#: c-family/c-common.c:2286 -+#: c-family/c-common.c:2291 - #, fuzzy, gcc-internal-format - msgid "__builtin_shuffle arguments must be vectors" - msgstr "второй аргумент %<__builtin_longjmp%> должен быть 1" - --#: c-family/c-common.c:2292 -+#: c-family/c-common.c:2297 - #, fuzzy, gcc-internal-format - msgid "__builtin_shuffle argument vectors must be of the same type" - msgstr "аргумент `%s' должен быть 2-битным беззнаковым литеральным значением" - --#: c-family/c-common.c:2302 -+#: c-family/c-common.c:2307 - #, gcc-internal-format - msgid "__builtin_shuffle number of elements of the argument vector(s) and the mask vector should be the same" - msgstr "" - --#: c-family/c-common.c:2311 -+#: c-family/c-common.c:2316 - #, gcc-internal-format - msgid "__builtin_shuffle argument vector(s) inner type must have the same size as inner type of the mask" - msgstr "" - --#: c-family/c-common.c:2505 -+#: c-family/c-common.c:2510 - #, gcc-internal-format - msgid "negative integer implicitly converted to unsigned type" - msgstr "неявное приведение отрицательного целого значения к беззнаковому типу" - --#: c-family/c-common.c:2511 -+#: c-family/c-common.c:2516 - #, gcc-internal-format - msgid "conversion of unsigned constant value to negative integer" - msgstr "" - --#: c-family/c-common.c:2605 -+#: c-family/c-common.c:2610 - #, fuzzy, gcc-internal-format - msgid "conversion to %qT from %qT may change the sign of the result" - msgstr "преобразование %qE из %qT в %qT неоднозначно" - --#: c-family/c-common.c:2674 -+#: c-family/c-common.c:2679 - #, fuzzy, gcc-internal-format - msgid "conversion to %qT from boolean expression" - msgstr "преобразование %qE из %qT в %qT неоднозначно" - --#: c-family/c-common.c:2681 -+#: c-family/c-common.c:2686 - #, fuzzy, gcc-internal-format - msgid "conversion to %qT alters %qT constant value" - msgstr "преобразование из %qT в %qT неоднозначно" - --#: c-family/c-common.c:2700 -+#: c-family/c-common.c:2705 - #, fuzzy, gcc-internal-format - msgid "conversion to %qT from %qT may alter its value" - msgstr "преобразование %qE из %qT в %qT неоднозначно" - --#: c-family/c-common.c:2730 -+#: c-family/c-common.c:2735 - #, gcc-internal-format - msgid "large integer implicitly truncated to unsigned type" - msgstr "неявное приведение большого целого значения к беззнаковому типу" - --#: c-family/c-common.c:2736 c-family/c-common.c:2743 c-family/c-common.c:2751 -+#: c-family/c-common.c:2741 c-family/c-common.c:2748 c-family/c-common.c:2756 - #, gcc-internal-format - msgid "overflow in implicit constant conversion" - msgstr "переполнение при неявном преобразовании константы" - --#: c-family/c-common.c:2923 -+#: c-family/c-common.c:2928 - #, gcc-internal-format - msgid "operation on %qE may be undefined" - msgstr "операция над %qE может дать неопределенный результат" - --#: c-family/c-common.c:3234 -+#: c-family/c-common.c:3239 - #, gcc-internal-format - msgid "case label does not reduce to an integer constant" - msgstr "значение case-метки неприводимо к целочисленной константе" - --#: c-family/c-common.c:3274 -+#: c-family/c-common.c:3279 - #, gcc-internal-format - msgid "case label value is less than minimum value for type" - msgstr "значение case-метки меньше чем минимальное значение данного типа" - --#: c-family/c-common.c:3282 -+#: c-family/c-common.c:3287 - #, gcc-internal-format - msgid "case label value exceeds maximum value for type" - msgstr "значение с больше чем максимальное значение данного типа" - --#: c-family/c-common.c:3290 -+#: c-family/c-common.c:3295 - #, gcc-internal-format - msgid "lower value in case label range less than minimum value for type" - msgstr "нижняя граница диапазона case-метки меньше чем минимальное значение данного типа" - --#: c-family/c-common.c:3299 -+#: c-family/c-common.c:3304 - #, gcc-internal-format - msgid "upper value in case label range exceeds maximum value for type" - msgstr "верхняя граница диапазона case-метки больше чем максимальное значение данного типа" - --#: c-family/c-common.c:3378 -+#: c-family/c-common.c:3383 - #, gcc-internal-format - msgid "GCC cannot support operators with integer types and fixed-point types that have too many integral and fractional bits together" - msgstr "" - --#: c-family/c-common.c:3881 -+#: c-family/c-common.c:3886 - #, fuzzy, gcc-internal-format - msgid "invalid operands to binary %s (have %qT and %qT)" - msgstr "неверные операнды бинарной операции %s" - --#: c-family/c-common.c:4142 -+#: c-family/c-common.c:4147 - #, gcc-internal-format - msgid "comparison is always false due to limited range of data type" - msgstr "из-за ограниченности диапазона типа данных, результат сравнения всегда ложь" - --#: c-family/c-common.c:4145 -+#: c-family/c-common.c:4150 - #, gcc-internal-format - msgid "comparison is always true due to limited range of data type" - msgstr "из-за ограниченности диапазона типа данных, результат сравнения всегда истина" - --#: c-family/c-common.c:4230 -+#: c-family/c-common.c:4235 - #, gcc-internal-format - msgid "comparison of unsigned expression >= 0 is always true" - msgstr "результат сравнения `беззнаковое выражение >=0' всегда истина" - --#: c-family/c-common.c:4237 -+#: c-family/c-common.c:4242 - #, gcc-internal-format - msgid "comparison of unsigned expression < 0 is always false" - msgstr "результат сравнения `беззнаковое выражение < 0' всегда ложь" - --#: c-family/c-common.c:4279 -+#: c-family/c-common.c:4284 - #, gcc-internal-format - msgid "pointer of type % used in arithmetic" - msgstr "в арифметическом выражении использован указатель %" - --#: c-family/c-common.c:4285 -+#: c-family/c-common.c:4290 - #, gcc-internal-format - msgid "pointer to a function used in arithmetic" - msgstr "в арифметическом выражении использован указатель на функцию" - --#: c-family/c-common.c:4291 -+#: c-family/c-common.c:4296 - #, gcc-internal-format - msgid "pointer to member function used in arithmetic" - msgstr "в арифметическом выражении использован указатель на элемент-функцию" - --#: c-family/c-common.c:4503 -+#: c-family/c-common.c:4508 - #, fuzzy, gcc-internal-format - msgid "the address of %qD will always evaluate as %" - msgstr "адрес %qD всегда будет %<истина%>" - --#: c-family/c-common.c:4598 cp/semantics.c:592 cp/typeck.c:7906 -+#: c-family/c-common.c:4603 cp/semantics.c:592 cp/typeck.c:7906 - #, gcc-internal-format - msgid "suggest parentheses around assignment used as truth value" - msgstr "присваивание, используемое как логическое выражение, рекомендуется " - --#: c-family/c-common.c:4677 c/c-decl.c:3686 c/c-typeck.c:10883 -+#: c-family/c-common.c:4682 c/c-decl.c:3686 c/c-typeck.c:10883 - #, gcc-internal-format - msgid "invalid use of %" - msgstr "неверное употребление спецификатора %" - --#: c-family/c-common.c:4870 -+#: c-family/c-common.c:4875 - #, gcc-internal-format - msgid "invalid application of % to a function type" - msgstr "недопустимое применение % к типу функции" - --#: c-family/c-common.c:4880 -+#: c-family/c-common.c:4885 - #, fuzzy, gcc-internal-format - msgid "ISO C++ does not permit % applied to a function type" - msgstr "ISO C++ не поддерживает назначенные инициализаторы" - --#: c-family/c-common.c:4883 -+#: c-family/c-common.c:4888 - #, fuzzy, gcc-internal-format - msgid "ISO C does not permit %<_Alignof%> applied to a function type" - msgstr "ISO C++ не поддерживает назначенные инициализаторы" - --#: c-family/c-common.c:4894 -+#: c-family/c-common.c:4899 - #, gcc-internal-format - msgid "invalid application of %qs to a void type" - msgstr "недопустимое применение %qs к типу void" - --#: c-family/c-common.c:4903 -+#: c-family/c-common.c:4908 - #, fuzzy, gcc-internal-format - msgid "invalid application of %qs to incomplete type %qT" - msgstr "некорректное применение %qs к неполному типу %qT " - --#: c-family/c-common.c:4911 -+#: c-family/c-common.c:4916 - #, fuzzy, gcc-internal-format - msgid "invalid application of %qs to array type %qT of incomplete element type" - msgstr "некорректное применение %qs к неполному типу %qT " - --#: c-family/c-common.c:4951 -+#: c-family/c-common.c:4956 - #, gcc-internal-format - msgid "%<__alignof%> applied to a bit-field" - msgstr "%<__alignof%> применено к битовому полю" - --#: c-family/c-common.c:5664 -+#: c-family/c-common.c:5669 - #, gcc-internal-format - msgid "cannot disable built-in function %qs" - msgstr "невозможно отменить внутреннюю функцию %s" - --#: c-family/c-common.c:5855 -+#: c-family/c-common.c:5860 - #, gcc-internal-format - msgid "pointers are not permitted as case values" - msgstr "в конструкции case нельзя употреблять указатели" - --#: c-family/c-common.c:5862 -+#: c-family/c-common.c:5867 - #, gcc-internal-format - msgid "range expressions in switch statements are non-standard" - msgstr "диапазоны в операторе switch не поддерживаются ISO C" - --#: c-family/c-common.c:5888 -+#: c-family/c-common.c:5893 - #, gcc-internal-format - msgid "empty range specified" - msgstr "пустой диапазон" - --#: c-family/c-common.c:5948 -+#: c-family/c-common.c:5953 - #, gcc-internal-format - msgid "duplicate (or overlapping) case value" - msgstr "повтор (или перекрытие) case-значений" - --#: c-family/c-common.c:5950 -+#: c-family/c-common.c:5955 - #, fuzzy, gcc-internal-format - msgid "this is the first entry overlapping that value" - msgstr "%Jэто первое case-значение, с которым перекрывается данное значение" - --#: c-family/c-common.c:5954 -+#: c-family/c-common.c:5959 - #, gcc-internal-format - msgid "duplicate case value" - msgstr "повтор case-значения," - --#: c-family/c-common.c:5955 -+#: c-family/c-common.c:5960 - #, fuzzy, gcc-internal-format - msgid "previously used here" - msgstr "%Jкоторое ранее использовано здесь" - --#: c-family/c-common.c:5959 -+#: c-family/c-common.c:5964 - #, gcc-internal-format - msgid "multiple default labels in one switch" - msgstr "несколько меток default в операторе switch" - --#: c-family/c-common.c:5961 -+#: c-family/c-common.c:5966 - #, fuzzy, gcc-internal-format - msgid "this is the first default label" - msgstr "%Jэто первая метка default" - --#: c-family/c-common.c:6013 -+#: c-family/c-common.c:6018 - #, fuzzy, gcc-internal-format - msgid "case value %qs not in enumerated type" - msgstr "%Jcase-значение %qs не принадлежит к перечислимому типу" - --#: c-family/c-common.c:6018 -+#: c-family/c-common.c:6023 - #, fuzzy, gcc-internal-format - msgid "case value %qs not in enumerated type %qT" - msgstr "%Jcase-значение %qs не принадлежит к перечислимому типу %qT" - --#: c-family/c-common.c:6077 -+#: c-family/c-common.c:6082 - #, fuzzy, gcc-internal-format - msgid "switch missing default case" - msgstr "%Hоператор switch без метки default" - --#: c-family/c-common.c:6149 -+#: c-family/c-common.c:6154 - #, fuzzy, gcc-internal-format - msgid "enumeration value %qE not handled in switch" - msgstr "%Hв переключателе пропущено значение %qE перечислимого типа" - --#: c-family/c-common.c:6175 -+#: c-family/c-common.c:6180 - #, gcc-internal-format - msgid "taking the address of a label is non-standard" - msgstr "взятие адреса метки не поддерживается ISO C/C++" - --#: c-family/c-common.c:6369 -+#: c-family/c-common.c:6374 - #, gcc-internal-format - msgid "%qE attribute ignored for field of type %qT" - msgstr "атрибут %qE для поля типа %qT проигнорирован" - --#: c-family/c-common.c:6464 c-family/c-common.c:6492 -+#: c-family/c-common.c:6469 c-family/c-common.c:6497 - #, fuzzy, gcc-internal-format - msgid "%qE attribute conflicts with attribute %s" - msgstr "атрибут %qs допустим только для переменных" - --#: c-family/c-common.c:6622 lto/lto-lang.c:227 -+#: c-family/c-common.c:6644 lto/lto-lang.c:227 - #, fuzzy, gcc-internal-format - msgid "%qE attribute has no effect on unit local functions" - msgstr "%qE атрибут действует только в public-объектах" - --#: c-family/c-common.c:6776 -+#: c-family/c-common.c:6798 - #, gcc-internal-format - msgid "%qE attribute have effect only on public objects" - msgstr "%qE атрибут действует только в public-объектах" - --#: c-family/c-common.c:6890 -+#: c-family/c-common.c:6912 - #, fuzzy, gcc-internal-format - msgid "destructor priorities are not supported" - msgstr "\"трамплины\" не поддерживаются" - --#: c-family/c-common.c:6892 -+#: c-family/c-common.c:6914 - #, fuzzy, gcc-internal-format - msgid "constructor priorities are not supported" - msgstr "\"трамплины\" не поддерживаются" - --#: c-family/c-common.c:6910 -+#: c-family/c-common.c:6932 - #, gcc-internal-format, gfc-internal-format - msgid "destructor priorities from 0 to %d are reserved for the implementation" - msgstr "" - --#: c-family/c-common.c:6915 -+#: c-family/c-common.c:6937 - #, gcc-internal-format, gfc-internal-format - msgid "constructor priorities from 0 to %d are reserved for the implementation" - msgstr "" - --#: c-family/c-common.c:6923 -+#: c-family/c-common.c:6945 - #, gcc-internal-format, gfc-internal-format - msgid "destructor priorities must be integers from 0 to %d inclusive" - msgstr "" - --#: c-family/c-common.c:6926 -+#: c-family/c-common.c:6948 - #, gcc-internal-format, gfc-internal-format - msgid "constructor priorities must be integers from 0 to %d inclusive" - msgstr "" - --#: c-family/c-common.c:7082 -+#: c-family/c-common.c:7104 - #, fuzzy, gcc-internal-format - msgid "unknown machine mode %qE" - msgstr "неизвестная машинный режим %qs" - --#: c-family/c-common.c:7111 -+#: c-family/c-common.c:7133 - #, gcc-internal-format - msgid "specifying vector types with __attribute__ ((mode)) is deprecated" - msgstr "задание векторного типа с __attribute__ ((mode)) не будет поддерживаться в будущих версиях" - --#: c-family/c-common.c:7114 -+#: c-family/c-common.c:7136 - #, gcc-internal-format - msgid "use __attribute__ ((vector_size)) instead" - msgstr "используйте вместо него __attribute__ ((vector_size))" - --#: c-family/c-common.c:7123 -+#: c-family/c-common.c:7145 - #, gcc-internal-format - msgid "unable to emulate %qs" - msgstr "эмуляция %qs невозможна" - --#: c-family/c-common.c:7134 -+#: c-family/c-common.c:7156 - #, gcc-internal-format - msgid "invalid pointer mode %qs" - msgstr "неизвестная машинный режим %qs для указателя" - --#: c-family/c-common.c:7151 -+#: c-family/c-common.c:7173 - #, gcc-internal-format - msgid "signedness of type and machine mode %qs don%'t match" - msgstr "" - --#: c-family/c-common.c:7162 -+#: c-family/c-common.c:7184 - #, gcc-internal-format - msgid "no data type for mode %qs" - msgstr "тип данных, соответствующий режиму %qs, не существует" - --#: c-family/c-common.c:7172 -+#: c-family/c-common.c:7194 - #, gcc-internal-format - msgid "cannot use mode %qs for enumeral types" - msgstr "использование режима %qs для перечислимых типов недопустимо" - --#: c-family/c-common.c:7199 -+#: c-family/c-common.c:7221 - #, gcc-internal-format - msgid "mode %qs applied to inappropriate type" - msgstr "режим %qs применен к неподходящему типу" - --#: c-family/c-common.c:7231 -+#: c-family/c-common.c:7253 - #, fuzzy, gcc-internal-format - msgid "section attribute cannot be specified for local variables" - msgstr "%Jатрибут section недопустим для локальных переменных" - --#: c-family/c-common.c:7242 config/bfin/bfin.c:4737 config/bfin/bfin.c:4788 -+#: c-family/c-common.c:7264 config/bfin/bfin.c:4737 config/bfin/bfin.c:4788 - #: config/bfin/bfin.c:4815 config/bfin/bfin.c:4828 - #, gcc-internal-format - msgid "section of %q+D conflicts with previous declaration" - msgstr "атрибут section, заданный для %q+D, противоречит предшествующей декларации" - --#: c-family/c-common.c:7250 -+#: c-family/c-common.c:7272 - #, fuzzy, gcc-internal-format - msgid "section of %q+D cannot be overridden" - msgstr "`%#D' и `%#D' не могут быть перегружены" - --#: c-family/c-common.c:7258 -+#: c-family/c-common.c:7280 - #, gcc-internal-format - msgid "section attribute not allowed for %q+D" - msgstr "атрибут section для %q+D недопустим" - --#: c-family/c-common.c:7265 -+#: c-family/c-common.c:7287 - #, fuzzy, gcc-internal-format - msgid "section attributes are not supported for this target" - msgstr "%Jатрибут section для данной платформы не поддерживается" - --#: c-family/c-common.c:7284 -+#: c-family/c-common.c:7306 - #, fuzzy, gcc-internal-format - msgid "requested alignment is not an integer constant" - msgstr "выравнивание не является константой" - --#: c-family/c-common.c:7291 -+#: c-family/c-common.c:7313 - #, gcc-internal-format - msgid "requested alignment is not a power of 2" - msgstr "выравнивание не является степенью числа 2" - --#: c-family/c-common.c:7296 -+#: c-family/c-common.c:7318 - #, gcc-internal-format - msgid "requested alignment is too large" - msgstr "выравнивание слишком велико" - --#: c-family/c-common.c:7379 -+#: c-family/c-common.c:7401 - #, fuzzy, gcc-internal-format, gfc-internal-format --#| msgid "requested alignment is too large" - msgid "requested alignment %d is larger than %d" - msgstr "выравнивание слишком велико" - --#: c-family/c-common.c:7436 -+#: c-family/c-common.c:7458 - #, gcc-internal-format - msgid "alignment may not be specified for %q+D" - msgstr "нельзя задавать выравнивание для %q+D" - --#: c-family/c-common.c:7454 -+#: c-family/c-common.c:7476 - #, gcc-internal-format - msgid "alignment for %q+D was previously specified as %d and may not be decreased" - msgstr "" - --#: c-family/c-common.c:7458 -+#: c-family/c-common.c:7480 - #, fuzzy, gcc-internal-format - msgid "alignment for %q+D must be at least %d" - msgstr "аргумент `%s' должен быть 2-битным беззнаковым литеральным значением" - --#: c-family/c-common.c:7483 -+#: c-family/c-common.c:7505 - #, fuzzy, gcc-internal-format - msgid "inline function %q+D declared weak" - msgstr "вложенная функция %q+D объявлена, но нигде не определена" - --#: c-family/c-common.c:7488 -+#: c-family/c-common.c:7510 - #, fuzzy, gcc-internal-format - msgid "indirect function %q+D cannot be declared weak" - msgstr "недопустимая декларация функции %qs как %" - --#: c-family/c-common.c:7525 -+#: c-family/c-common.c:7547 - #, fuzzy, gcc-internal-format - msgid "%q+D defined both normally and as %qE attribute" - msgstr "%q+D определено как обычное имя и как alias" - --#: c-family/c-common.c:7533 -+#: c-family/c-common.c:7555 - #, fuzzy, gcc-internal-format - msgid "weak %q+D cannot be defined %qE" - msgstr "декларация %q+#D недопустима," - --#: c-family/c-common.c:7550 -+#: c-family/c-common.c:7572 - #, fuzzy, gcc-internal-format - msgid "attribute %qE argument not a string" - msgstr "аргумент атрибута %qs не является строковой константой" - --#: c-family/c-common.c:7626 -+#: c-family/c-common.c:7648 - #, fuzzy, gcc-internal-format - msgid "indirect function %q+D cannot be declared weakref" - msgstr "недопустимая декларация функции %qs как %" - --#: c-family/c-common.c:7648 -+#: c-family/c-common.c:7670 - #, fuzzy, gcc-internal-format - msgid "weakref attribute must appear before alias attribute" - msgstr "%Jатрибут weakref должен задаваться до атрибута alias" - --#: c-family/c-common.c:7677 -+#: c-family/c-common.c:7699 - #, gcc-internal-format - msgid "%qE attribute ignored on non-class types" - msgstr "атрибут %qE для не классовых типов игнорируется" - --#: c-family/c-common.c:7683 -+#: c-family/c-common.c:7705 - #, fuzzy, gcc-internal-format - msgid "%qE attribute ignored because %qT is already defined" - msgstr "атрибут %qE для не классовых типов игнорируется" - --#: c-family/c-common.c:7696 -+#: c-family/c-common.c:7718 - #, gcc-internal-format - msgid "visibility argument not a string" - msgstr "аргумент атрибута visibility не является текстовой строкой" - --#: c-family/c-common.c:7708 -+#: c-family/c-common.c:7730 - #, gcc-internal-format - msgid "%qE attribute ignored on types" - msgstr "атрибут %qE для типов игнорируется" - --#: c-family/c-common.c:7724 -+#: c-family/c-common.c:7746 - #, gcc-internal-format - msgid "visibility argument must be one of \"default\", \"hidden\", \"protected\" or \"internal\"" - msgstr "аргумент атрибута visibility должен быть \"default\", \"hidden\", \"protected\" или \"internal\"" - --#: c-family/c-common.c:7735 -+#: c-family/c-common.c:7757 - #, fuzzy, gcc-internal-format - msgid "%qD redeclared with different visibility" - msgstr "%J%qD повторно декларирован как символ другого вида" - --#: c-family/c-common.c:7738 c-family/c-common.c:7742 -+#: c-family/c-common.c:7760 c-family/c-common.c:7764 - #, gcc-internal-format - msgid "%qD was declared %qs which implies default visibility" - msgstr "" - --#: c-family/c-common.c:7826 -+#: c-family/c-common.c:7848 - #, gcc-internal-format - msgid "tls_model argument not a string" - msgstr "аргумент атрибута tls_model не является текстовой строкой" - --#: c-family/c-common.c:7839 -+#: c-family/c-common.c:7861 - #, gcc-internal-format - msgid "tls_model argument must be one of \"local-exec\", \"initial-exec\", \"local-dynamic\" or \"global-dynamic\"" - msgstr "аргумент атрибута tls_model должен быть \"local-exec\", \"initial-exec\", \"local-dynamic\" или \"global-dynamic\"" - --#: c-family/c-common.c:7859 c-family/c-common.c:7965 c-family/c-common.c:8950 -+#: c-family/c-common.c:7881 c-family/c-common.c:7987 c-family/c-common.c:8970 - #: config/m32c/m32c.c:2926 - #, fuzzy, gcc-internal-format - msgid "%qE attribute applies only to functions" - msgstr "%J%qE: атрибут допустим только для функций" - --#: c-family/c-common.c:7865 c-family/c-common.c:7971 c-family/c-common.c:8956 -+#: c-family/c-common.c:7887 c-family/c-common.c:7993 c-family/c-common.c:8976 - #, fuzzy, gcc-internal-format - msgid "can%'t set %qE attribute after definition" - msgstr "%Jатрибут %qE нельзя установить после определения объекта" - --#: c-family/c-common.c:7911 -+#: c-family/c-common.c:7933 - #, gcc-internal-format - msgid "alloc_size parameter outside range" - msgstr "" - --#: c-family/c-common.c:8029 -+#: c-family/c-common.c:8051 - #, fuzzy, gcc-internal-format - msgid "%qE attribute duplicated" - msgstr "атрибут %qE проигнорирован" - --#: c-family/c-common.c:8031 -+#: c-family/c-common.c:8053 - #, fuzzy, gcc-internal-format - msgid "%qE attribute follows %qE" - msgstr "атрибут %qE для %qE проигнорирован" - --#: c-family/c-common.c:8130 -+#: c-family/c-common.c:8152 - #, fuzzy, gcc-internal-format - msgid "type was previously declared %qE" - msgstr "это предыдущее определение `%#D'" - --#: c-family/c-common.c:8183 -+#: c-family/c-common.c:8205 - #, fuzzy, gcc-internal-format - msgid "%qE argument not an identifier" - msgstr "аргумент атрибута cleanup - не идентификатор" - --#: c-family/c-common.c:8194 -+#: c-family/c-common.c:8216 - #, fuzzy, gcc-internal-format - msgid "%qD is not compatible with %qD" - msgstr "отсутствует декларация %qD в %qD" - --#: c-family/c-common.c:8197 -+#: c-family/c-common.c:8219 - #, fuzzy, gcc-internal-format - msgid "transaction_wrap argument is not a function" - msgstr "аргумент атрибута cleanup - не функция" - --#: c-family/c-common.c:8245 -+#: c-family/c-common.c:8267 - #, fuzzy, gcc-internal-format - msgid "deprecated message is not a string" - msgstr "аргумент атрибута %qs не является строковой константой" - --#: c-family/c-common.c:8286 -+#: c-family/c-common.c:8308 - #, gcc-internal-format - msgid "%qE attribute ignored for %qE" - msgstr "атрибут %qE для %qE проигнорирован" - --#: c-family/c-common.c:8346 -+#: c-family/c-common.c:8368 - #, gcc-internal-format - msgid "invalid vector type for attribute %qE" - msgstr "неверно задан векторный тип для атрибута %qE" - --#: c-family/c-common.c:8352 ada/gcc-interface/utils.c:6307 -+#: c-family/c-common.c:8374 ada/gcc-interface/utils.c:6307 - #: ada/gcc-interface/utils.c:6401 - #, gcc-internal-format - msgid "vector size not an integral multiple of component size" - msgstr "размер вектора не кратен размеру компонент" - --#: c-family/c-common.c:8358 ada/gcc-interface/utils.c:6313 -+#: c-family/c-common.c:8380 ada/gcc-interface/utils.c:6313 - #: ada/gcc-interface/utils.c:6407 - #, gcc-internal-format - msgid "zero vector size" - msgstr "нулевой размер вектора" - --#: c-family/c-common.c:8366 ada/gcc-interface/utils.c:6321 -+#: c-family/c-common.c:8388 ada/gcc-interface/utils.c:6321 - #: ada/gcc-interface/utils.c:6414 - #, gcc-internal-format - msgid "number of components of the vector not a power of two" - msgstr "число компонент вектора не является степенью двойки" - --#: c-family/c-common.c:8394 ada/gcc-interface/utils.c:6048 -+#: c-family/c-common.c:8416 ada/gcc-interface/utils.c:6048 - #, gcc-internal-format - msgid "nonnull attribute without arguments on a non-prototype" - msgstr "непустой атрибут без аргументов допустим только в прототипах" - --#: c-family/c-common.c:8408 ada/gcc-interface/utils.c:6062 -+#: c-family/c-common.c:8430 ada/gcc-interface/utils.c:6062 - #, gcc-internal-format, gfc-internal-format - msgid "nonnull argument has invalid operand number (argument %lu)" - msgstr "в непустом аргументе задан неверный номер операнда (аргумент %lu)" - --#: c-family/c-common.c:8430 ada/gcc-interface/utils.c:6084 -+#: c-family/c-common.c:8452 ada/gcc-interface/utils.c:6084 - #, gcc-internal-format, gfc-internal-format - msgid "nonnull argument with out-of-range operand number (argument %lu, operand %lu)" - msgstr "непустой аргумент содержит номер операнда вне диапазона (аргумент %lu, операнд %lu)" - --#: c-family/c-common.c:8438 ada/gcc-interface/utils.c:6093 -+#: c-family/c-common.c:8460 ada/gcc-interface/utils.c:6093 - #, gcc-internal-format, gfc-internal-format - msgid "nonnull argument references non-pointer operand (argument %lu, operand %lu)" - msgstr "непустой аргумент ссылается на операнд, не являющийся указателем (аргумент %lu, операнд %lu)" - --#: c-family/c-common.c:8533 -+#: c-family/c-common.c:8555 - #, fuzzy, gcc-internal-format - msgid "not enough variable arguments to fit a sentinel" - msgstr "слишком мало аргументов функции" - --#: c-family/c-common.c:8547 -+#: c-family/c-common.c:8569 - #, fuzzy, gcc-internal-format - msgid "missing sentinel in function call" - msgstr "Запретить вызовы функций относительно PC" - --#: c-family/c-common.c:8588 -+#: c-family/c-common.c:8610 - #, gcc-internal-format, gfc-internal-format - msgid "null argument where non-null required (argument %lu)" - msgstr "пустой аргумент в позиции, где требуется непустой (аргумент %lu)" - --#: c-family/c-common.c:8653 -+#: c-family/c-common.c:8675 - #, gcc-internal-format - msgid "cleanup argument not an identifier" - msgstr "аргумент атрибута cleanup - не идентификатор" - --#: c-family/c-common.c:8660 -+#: c-family/c-common.c:8682 - #, gcc-internal-format - msgid "cleanup argument not a function" - msgstr "аргумент атрибута cleanup - не функция" - --#: c-family/c-common.c:8697 -+#: c-family/c-common.c:8719 - #, gcc-internal-format - msgid "%qE attribute requires prototypes with named arguments" - msgstr "в атрибуте %qE требуется прототип с именованными аргументами" - --#: c-family/c-common.c:8705 -+#: c-family/c-common.c:8727 - #, gcc-internal-format - msgid "%qE attribute only applies to variadic functions" - msgstr "атрибут %qE допустим только для функций с переменным числом аргументом" - --#: c-family/c-common.c:8717 ada/gcc-interface/utils.c:6135 -+#: c-family/c-common.c:8739 ada/gcc-interface/utils.c:6135 - #, gcc-internal-format - msgid "requested position is not an integer constant" - msgstr "заданная позиция не является целой константой" - --#: c-family/c-common.c:8725 ada/gcc-interface/utils.c:6142 -+#: c-family/c-common.c:8747 ada/gcc-interface/utils.c:6142 - #, gcc-internal-format - msgid "requested position is less than zero" - msgstr "заданная позиция меньше нуля" - --#: c-family/c-common.c:8843 -+#: c-family/c-common.c:8865 - #, gcc-internal-format, gfc-internal-format - msgid "bad option %s to optimize attribute" - msgstr "" - --#: c-family/c-common.c:8846 -+#: c-family/c-common.c:8868 - #, gcc-internal-format, gfc-internal-format - msgid "bad option %s to pragma attribute" - msgstr "" - --#: c-family/c-common.c:9075 -+#: c-family/c-common.c:9095 - #, fuzzy, gcc-internal-format - msgid "not enough arguments to function %qE" - msgstr "слишком мало аргументов в вызове функции %qE" - --#: c-family/c-common.c:9081 c-family/c-common.c:10007 c/c-typeck.c:2954 -+#: c-family/c-common.c:9101 c-family/c-common.c:10027 c/c-typeck.c:2954 - #, gcc-internal-format - msgid "too many arguments to function %qE" - msgstr "слишком много аргументов в вызове функции %qE" - --#: c-family/c-common.c:9111 c-family/c-common.c:9157 -+#: c-family/c-common.c:9131 c-family/c-common.c:9177 - #, fuzzy, gcc-internal-format - msgid "non-floating-point argument in call to function %qE" - msgstr "не плавающий аргумент в вызове функции %qs" - --#: c-family/c-common.c:9134 -+#: c-family/c-common.c:9154 - #, fuzzy, gcc-internal-format - msgid "non-floating-point arguments in call to function %qE" - msgstr "не плавающий аргумент в вызове функции %qs" - --#: c-family/c-common.c:9150 -+#: c-family/c-common.c:9170 - #, fuzzy, gcc-internal-format - msgid "non-const integer argument %u in call to function %qE" - msgstr "не плавающий аргумент в вызове функции %qs" - --#: c-family/c-common.c:9170 -+#: c-family/c-common.c:9190 - #, fuzzy, gcc-internal-format - msgid "non-integer argument 3 in call to function %qE" - msgstr "не плавающий аргумент в вызове функции %qs" - --#: c-family/c-common.c:9496 -+#: c-family/c-common.c:9516 - #, gcc-internal-format - msgid "cannot apply % to static data member %qD" - msgstr "недопустимое применение % к статическому элементу данных %qD" - --#: c-family/c-common.c:9501 -+#: c-family/c-common.c:9521 - #, fuzzy, gcc-internal-format - msgid "cannot apply % when % is overloaded" - msgstr "недопустимое применение % к статическому элементу данных %qD" - --#: c-family/c-common.c:9508 -+#: c-family/c-common.c:9528 - #, fuzzy, gcc-internal-format - msgid "cannot apply % to a non constant address" - msgstr "некорректное использование нестатической функции-элемента %qD" - --#: c-family/c-common.c:9521 cp/typeck.c:5289 -+#: c-family/c-common.c:9541 cp/typeck.c:5289 - #, gcc-internal-format - msgid "attempt to take address of bit-field structure member %qD" - msgstr "взятие адреса от битового поля структуры %qD" - --#: c-family/c-common.c:9573 -+#: c-family/c-common.c:9593 - #, gcc-internal-format - msgid "index %E denotes an offset greater than size of %qT" - msgstr "" - --#: c-family/c-common.c:9613 -+#: c-family/c-common.c:9633 - #, gcc-internal-format - msgid "the omitted middle operand in ?: will always be %, suggest explicit middle operand" - msgstr "" - --#: c-family/c-common.c:9634 -+#: c-family/c-common.c:9654 - #, fuzzy, gcc-internal-format - msgid "assignment of member %qD in read-only object" - msgstr "присваивание позиции в памяти, доступной только на чтение" - --#: c-family/c-common.c:9636 -+#: c-family/c-common.c:9656 - #, fuzzy, gcc-internal-format - msgid "increment of member %qD in read-only object" - msgstr "инкрементация позиции в памяти, доступной только на чтение" - --#: c-family/c-common.c:9638 -+#: c-family/c-common.c:9658 - #, fuzzy, gcc-internal-format - msgid "decrement of member %qD in read-only object" - msgstr "декрементация позиции в памяти, доступной только на чтение" - --#: c-family/c-common.c:9640 -+#: c-family/c-common.c:9660 - #, fuzzy, gcc-internal-format - msgid "member %qD in read-only object used as % output" - msgstr "доступная только на чтение позиция памяти использована как выходной операнд %" - --#: c-family/c-common.c:9644 -+#: c-family/c-common.c:9664 - #, gcc-internal-format - msgid "assignment of read-only member %qD" - msgstr "присваивание элементу %qD, доступному только на чтение" - --#: c-family/c-common.c:9645 -+#: c-family/c-common.c:9665 - #, gcc-internal-format - msgid "increment of read-only member %qD" - msgstr "инкрементация элемента %qD, доступного только на чтение" - --#: c-family/c-common.c:9646 -+#: c-family/c-common.c:9666 - #, gcc-internal-format - msgid "decrement of read-only member %qD" - msgstr "декрементация элемента %qD, доступного только на чтение" - --#: c-family/c-common.c:9647 -+#: c-family/c-common.c:9667 - #, gcc-internal-format - msgid "read-only member %qD used as % output" - msgstr "доступный только на чтение элемент %qD использован как выходной операнд %" - --#: c-family/c-common.c:9651 -+#: c-family/c-common.c:9671 - #, gcc-internal-format - msgid "assignment of read-only variable %qD" - msgstr "присваивание переменной %qD, доступной только на чтение" - --#: c-family/c-common.c:9652 -+#: c-family/c-common.c:9672 - #, gcc-internal-format - msgid "increment of read-only variable %qD" - msgstr "инкрементация переменной %qD, доступной только на чтение" - --#: c-family/c-common.c:9653 -+#: c-family/c-common.c:9673 - #, gcc-internal-format - msgid "decrement of read-only variable %qD" - msgstr "декрементация переменной %qD, доступной только на чтение" - --#: c-family/c-common.c:9654 -+#: c-family/c-common.c:9674 - #, gcc-internal-format - msgid "read-only variable %qD used as % output" - msgstr "доступная только на чтение переменная %qD использована как выходной операнд %" - --#: c-family/c-common.c:9657 -+#: c-family/c-common.c:9677 - #, fuzzy, gcc-internal-format - msgid "assignment of read-only parameter %qD" - msgstr "присваивание элементу %qD, доступному только на чтение" - --#: c-family/c-common.c:9658 -+#: c-family/c-common.c:9678 - #, fuzzy, gcc-internal-format - msgid "increment of read-only parameter %qD" - msgstr "инкрементация элемента %qD, доступного только на чтение" - --#: c-family/c-common.c:9659 -+#: c-family/c-common.c:9679 - #, fuzzy, gcc-internal-format - msgid "decrement of read-only parameter %qD" - msgstr "декрементация элемента %qD, доступного только на чтение" - --#: c-family/c-common.c:9660 -+#: c-family/c-common.c:9680 - #, fuzzy, gcc-internal-format - msgid "read-only parameter %qD use as % output" - msgstr "доступный только на чтение элемент %qD использован как выходной операнд %" - --#: c-family/c-common.c:9665 -+#: c-family/c-common.c:9685 - #, fuzzy, gcc-internal-format - msgid "assignment of read-only named return value %qD" - msgstr "присваивание переменной %qD, доступной только на чтение" - --#: c-family/c-common.c:9667 -+#: c-family/c-common.c:9687 - #, fuzzy, gcc-internal-format - msgid "increment of read-only named return value %qD" - msgstr "присваивание переменной %qD, доступной только на чтение" - --#: c-family/c-common.c:9669 -+#: c-family/c-common.c:9689 - #, fuzzy, gcc-internal-format - msgid "decrement of read-only named return value %qD" - msgstr "присваивание переменной %qD, доступной только на чтение" - --#: c-family/c-common.c:9671 -+#: c-family/c-common.c:9691 - #, fuzzy, gcc-internal-format - msgid "read-only named return value %qD used as %output" - msgstr "доступная только на чтение переменная %qD использована как выходной операнд %" - --#: c-family/c-common.c:9676 -+#: c-family/c-common.c:9696 - #, fuzzy, gcc-internal-format - msgid "assignment of function %qD" - msgstr "вызов не функции %qD" - --#: c-family/c-common.c:9677 -+#: c-family/c-common.c:9697 - #, fuzzy, gcc-internal-format - msgid "increment of function %qD" - msgstr "вызов не функции %qD" - --#: c-family/c-common.c:9678 -+#: c-family/c-common.c:9698 - #, fuzzy, gcc-internal-format - msgid "decrement of function %qD" - msgstr "вызов не функции %qD" - --#: c-family/c-common.c:9679 -+#: c-family/c-common.c:9699 - #, fuzzy, gcc-internal-format - msgid "function %qD used as % output" - msgstr "доступная только на чтение позиция памяти использована как выходной операнд %" - --#: c-family/c-common.c:9682 c/c-typeck.c:3902 -+#: c-family/c-common.c:9702 c/c-typeck.c:3902 - #, fuzzy, gcc-internal-format - msgid "assignment of read-only location %qE" - msgstr "присваивание позиции в памяти, доступной только на чтение" - --#: c-family/c-common.c:9683 c/c-typeck.c:3905 -+#: c-family/c-common.c:9703 c/c-typeck.c:3905 - #, fuzzy, gcc-internal-format - msgid "increment of read-only location %qE" - msgstr "инкрементация позиции в памяти, доступной только на чтение" - --#: c-family/c-common.c:9684 c/c-typeck.c:3908 -+#: c-family/c-common.c:9704 c/c-typeck.c:3908 - #, fuzzy, gcc-internal-format - msgid "decrement of read-only location %qE" - msgstr "декрементация позиции в памяти, доступной только на чтение" - --#: c-family/c-common.c:9685 -+#: c-family/c-common.c:9705 - #, fuzzy, gcc-internal-format - msgid "read-only location %qE used as % output" - msgstr "доступная только на чтение позиция памяти использована как выходной операнд %" - --#: c-family/c-common.c:9699 -+#: c-family/c-common.c:9719 - #, fuzzy, gcc-internal-format - msgid "lvalue required as left operand of assignment" - msgstr "некорректная левая часть в присваивании" - --#: c-family/c-common.c:9702 -+#: c-family/c-common.c:9722 - #, gcc-internal-format - msgid "lvalue required as increment operand" - msgstr "" - --#: c-family/c-common.c:9705 -+#: c-family/c-common.c:9725 - #, gcc-internal-format - msgid "lvalue required as decrement operand" - msgstr "" - --#: c-family/c-common.c:9708 -+#: c-family/c-common.c:9728 - #, gcc-internal-format - msgid "lvalue required as unary %<&%> operand" - msgstr "" - --#: c-family/c-common.c:9711 -+#: c-family/c-common.c:9731 - #, fuzzy, gcc-internal-format - msgid "lvalue required in asm statement" - msgstr "неверное lvalue-выражение в операторе asm" - --#: c-family/c-common.c:9728 -+#: c-family/c-common.c:9748 - #, fuzzy, gcc-internal-format - msgid "invalid type argument (have %qT)" - msgstr "неверный аргумент для %qs" - --#: c-family/c-common.c:9732 -+#: c-family/c-common.c:9752 - #, fuzzy, gcc-internal-format - msgid "invalid type argument of array indexing (have %qT)" - msgstr "неверный аргумент для %qs" - --#: c-family/c-common.c:9737 -+#: c-family/c-common.c:9757 - #, fuzzy, gcc-internal-format - msgid "invalid type argument of unary %<*%> (have %qT)" - msgstr "неверный аргумент для %qs" - --#: c-family/c-common.c:9742 -+#: c-family/c-common.c:9762 - #, fuzzy, gcc-internal-format - msgid "invalid type argument of %<->%> (have %qT)" - msgstr "неверный аргумент для %qs" - --#: c-family/c-common.c:9747 -+#: c-family/c-common.c:9767 - #, fuzzy, gcc-internal-format - msgid "invalid type argument of implicit conversion (have %qT)" - msgstr "неверный аргумент для %qs" - --#: c-family/c-common.c:9877 cp/init.c:2373 -+#: c-family/c-common.c:9897 cp/init.c:2373 - #, fuzzy, gcc-internal-format - msgid "size of array is too large" - msgstr "размер массива %qs слишком велик" - --#: c-family/c-common.c:9925 c-family/c-common.c:9981 c/c-typeck.c:3185 -+#: c-family/c-common.c:9945 c-family/c-common.c:10001 c/c-typeck.c:3185 - #, gcc-internal-format - msgid "too few arguments to function %qE" - msgstr "слишком мало аргументов в вызове функции %qE" - --#: c-family/c-common.c:9942 config/mep/mep.c:6175 c/c-typeck.c:5687 -+#: c-family/c-common.c:9962 config/mep/mep.c:6175 c/c-typeck.c:5687 - #, gcc-internal-format - msgid "incompatible type for argument %d of %qE" - msgstr "несовместимый тип аргумента %d функции %qE" - --#: c-family/c-common.c:10074 -+#: c-family/c-common.c:10094 - #, fuzzy, gcc-internal-format - msgid "incorrect number of arguments to function %qE" - msgstr "слишком мало аргументов в вызове функции %qE" - --#: c-family/c-common.c:10082 -+#: c-family/c-common.c:10102 - #, fuzzy, gcc-internal-format - msgid "argument 1 of %qE must be a non-void pointer type" - msgstr "использование шаблона класса %qT в качестве выражения" - --#: c-family/c-common.c:10091 -+#: c-family/c-common.c:10111 - #, fuzzy, gcc-internal-format - msgid "argument 1 of %qE must be a pointer to a constant size type" - msgstr "%Hпервый аргумент %D должен быть указателем, второй - целой константой" - --#: c-family/c-common.c:10102 -+#: c-family/c-common.c:10122 - #, fuzzy, gcc-internal-format - msgid "argument 1 of %qE must be a pointer to a nonzero size object" - msgstr "%Hпервый аргумент %D должен быть указателем, второй - целой константой" - --#: c-family/c-common.c:10117 -+#: c-family/c-common.c:10137 - #, fuzzy, gcc-internal-format - msgid "argument %d of %qE must be a pointer type" - msgstr "использование шаблона класса %qT в качестве выражения" - --#: c-family/c-common.c:10124 -+#: c-family/c-common.c:10144 - #, fuzzy, gcc-internal-format - msgid "size mismatch in argument %d of %qE" - msgstr "при передаче аргумента %P функции `%+D'" - --#: c-family/c-common.c:10140 -+#: c-family/c-common.c:10160 - #, fuzzy, gcc-internal-format - msgid "invalid memory model argument %d of %qE" - msgstr "несовместимый тип аргумента %d функции %qE" - --#: c-family/c-common.c:10147 -+#: c-family/c-common.c:10167 - #, fuzzy, gcc-internal-format - msgid "non-integer memory model argument %d of %qE" - msgstr "несовместимый тип аргумента %d функции %qE" - --#: c-family/c-common.c:10674 -+#: c-family/c-common.c:10694 - #, gcc-internal-format - msgid "array subscript has type %" - msgstr "индекс массива имеет тип %" - --#: c-family/c-common.c:10709 c-family/c-common.c:10712 -+#: c-family/c-common.c:10729 c-family/c-common.c:10732 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around %<+%> inside %<<<%>" - msgstr "рекомендуется окружать скобками + или -, используемые в операндах операций сдвига" - --#: c-family/c-common.c:10715 c-family/c-common.c:10718 -+#: c-family/c-common.c:10735 c-family/c-common.c:10738 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around %<-%> inside %<<<%>" - msgstr "рекомендуется окружать скобками + или -, используемые в операндах операций сдвига" - --#: c-family/c-common.c:10724 c-family/c-common.c:10727 -+#: c-family/c-common.c:10744 c-family/c-common.c:10747 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around %<+%> inside %<>>%>" - msgstr "рекомендуется окружать скобками + или -, используемые в операндах операций сдвига" - --#: c-family/c-common.c:10730 c-family/c-common.c:10733 -+#: c-family/c-common.c:10750 c-family/c-common.c:10753 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around %<-%> inside %<>>%>" - msgstr "рекомендуется окружать скобками + или -, используемые в операндах операций сдвига" - --#: c-family/c-common.c:10739 c-family/c-common.c:10742 -+#: c-family/c-common.c:10759 c-family/c-common.c:10762 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around %<&&%> within %<||%>" - msgstr "рекомендуется окружать скобками выражение &&, используемое в операнде ||" - --#: c-family/c-common.c:10749 c-family/c-common.c:10753 -+#: c-family/c-common.c:10769 c-family/c-common.c:10773 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around arithmetic in operand of %<|%>" - msgstr "рекомендуется окружать скобками арифметическую операцию, используемую в операнде |" - --#: c-family/c-common.c:10757 c-family/c-common.c:10760 -+#: c-family/c-common.c:10777 c-family/c-common.c:10780 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around comparison in operand of %<|%>" - msgstr "рекомендуется окружать скобками сравнение, используемое в операнде |" - --#: c-family/c-common.c:10765 -+#: c-family/c-common.c:10785 - #, gcc-internal-format - msgid "suggest parentheses around operand of % or change %<|%> to %<||%> or % to %<~%>" - msgstr "" - --#: c-family/c-common.c:10773 c-family/c-common.c:10777 -+#: c-family/c-common.c:10793 c-family/c-common.c:10797 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around arithmetic in operand of %<^%>" - msgstr "рекомендуется окружать скобками арифметическую операцию, используемую в операнде ^" - --#: c-family/c-common.c:10781 c-family/c-common.c:10784 -+#: c-family/c-common.c:10801 c-family/c-common.c:10804 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around comparison in operand of %<^%>" - msgstr "рекомендуется окружать скобками сравнение, используемое в операнде ^" - --#: c-family/c-common.c:10790 c-family/c-common.c:10793 -+#: c-family/c-common.c:10810 c-family/c-common.c:10813 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around %<+%> in operand of %<&%>" - msgstr "рекомендуется окружать скобками + или -, используемые в операнде &" - --#: c-family/c-common.c:10796 c-family/c-common.c:10799 -+#: c-family/c-common.c:10816 c-family/c-common.c:10819 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around %<-%> in operand of %<&%>" - msgstr "рекомендуется окружать скобками + или -, используемые в операнде &" - --#: c-family/c-common.c:10803 c-family/c-common.c:10806 -+#: c-family/c-common.c:10823 c-family/c-common.c:10826 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around comparison in operand of %<&%>" - msgstr "рекомендуется окружать скобками сравнение, используемое в операнде &" - --#: c-family/c-common.c:10811 -+#: c-family/c-common.c:10831 - #, gcc-internal-format - msgid "suggest parentheses around operand of % or change %<&%> to %<&&%> or % to %<~%>" - msgstr "" - --#: c-family/c-common.c:10818 c-family/c-common.c:10821 -+#: c-family/c-common.c:10838 c-family/c-common.c:10841 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around comparison in operand of %<==%>" - msgstr "рекомендуется окружать скобками сравнение, используемое в операнде |" - --#: c-family/c-common.c:10826 c-family/c-common.c:10829 -+#: c-family/c-common.c:10846 c-family/c-common.c:10849 - #, fuzzy, gcc-internal-format - msgid "suggest parentheses around comparison in operand of %" - msgstr "рекомендуется окружать скобками сравнение, используемое в операнде |" - --#: c-family/c-common.c:10839 c-family/c-common.c:10845 -+#: c-family/c-common.c:10859 c-family/c-common.c:10865 - #, fuzzy, gcc-internal-format - msgid "comparisons like % do not have their mathematical meaning" - msgstr "сравнения вида X<=Y<=Z трактуются в C не так, как в математике" - --#: c-family/c-common.c:10861 -+#: c-family/c-common.c:10881 - #, gcc-internal-format - msgid "label %q+D defined but not used" - msgstr "метка %q+D определена, но не используется" - --#: c-family/c-common.c:10863 -+#: c-family/c-common.c:10883 - #, gcc-internal-format - msgid "label %q+D declared but not defined" - msgstr "метка %q+D декларирована, но не определена" - --#: c-family/c-common.c:10879 -+#: c-family/c-common.c:10899 - #, gcc-internal-format - msgid "division by zero" - msgstr "деление на ноль" - --#: c-family/c-common.c:10911 -+#: c-family/c-common.c:10931 - #, fuzzy, gcc-internal-format - msgid "comparison between types %qT and %qT" - msgstr "сравнение между типами `%#T' и `%#T'" - --#: c-family/c-common.c:10962 -+#: c-family/c-common.c:10982 - #, gcc-internal-format - msgid "comparison between signed and unsigned integer expressions" - msgstr "сравнение знакового и беззнакового целых выражений" - --#: c-family/c-common.c:11013 -+#: c-family/c-common.c:11033 - #, gcc-internal-format - msgid "promoted ~unsigned is always non-zero" - msgstr "" - --#: c-family/c-common.c:11016 -+#: c-family/c-common.c:11036 - #, gcc-internal-format - msgid "comparison of promoted ~unsigned with constant" - msgstr "сравнение ~unsigned с константой" - --#: c-family/c-common.c:11026 -+#: c-family/c-common.c:11046 - #, gcc-internal-format - msgid "comparison of promoted ~unsigned with unsigned" - msgstr "сравнение ~unsigned с unsigned" - --#: c-family/c-common.c:11204 -+#: c-family/c-common.c:11224 - #, fuzzy, gcc-internal-format - msgid "typedef %qD locally defined but not used" - msgstr "%q+D определена, но нигде не используется" - --#: c-family/c-common.c:11443 -+#: c-family/c-common.c:11463 - #, fuzzy, gcc-internal-format - msgid "index value is out of bound" - msgstr "индекс размерности %d выходит за границы в %L" - --#: c-family/c-common.c:11481 c-family/c-common.c:11531 --#: c-family/c-common.c:11546 -+#: c-family/c-common.c:11501 c-family/c-common.c:11551 -+#: c-family/c-common.c:11566 - #, fuzzy, gcc-internal-format --#| msgid "conversion from %qT to %qT is ambiguous" - msgid "conversion of scalar %qT to vector %qT involves truncation" - msgstr "преобразование из %qT в %qT неоднозначно" - -@@ -20223,37 +20179,37 @@ - msgid "can%'t write to %s: %m" - msgstr "ошибка записи в %s: %m" - --#: c-family/c-pch.c:191 -+#: c-family/c-pch.c:193 - #, gcc-internal-format - msgid "can%'t write %s: %m" - msgstr "ошибка записи %s: %m" - --#: c-family/c-pch.c:219 c-family/c-pch.c:260 c-family/c-pch.c:311 -+#: c-family/c-pch.c:221 c-family/c-pch.c:262 c-family/c-pch.c:313 - #, gcc-internal-format - msgid "can%'t read %s: %m" - msgstr "ошибка чтения %s: %m" - --#: c-family/c-pch.c:417 -+#: c-family/c-pch.c:419 - #, gcc-internal-format - msgid "pch_preprocess pragma should only be used with -fpreprocessed" - msgstr "прагма pch_preprocess может использоваться только с ключом -fpreprocessed" - --#: c-family/c-pch.c:418 -+#: c-family/c-pch.c:420 - #, gcc-internal-format - msgid "use #include instead" - msgstr "используйте директиву #include" - --#: c-family/c-pch.c:424 -+#: c-family/c-pch.c:426 - #, gcc-internal-format - msgid "%s: couldn%'t open PCH file: %m" - msgstr "%s: ошибка открытия PCH файла %m" - --#: c-family/c-pch.c:429 -+#: c-family/c-pch.c:431 - #, gcc-internal-format - msgid "use -Winvalid-pch for more information" - msgstr "для получения более подробной диагностики задайте -Winvalid-pch" - --#: c-family/c-pch.c:430 -+#: c-family/c-pch.c:432 - #, gcc-internal-format, gfc-internal-format - msgid "%s: PCH file was invalid" - msgstr "%s: PCH-файл был некорректен" -@@ -20736,7 +20692,6 @@ - - #: config/darwin.c:2689 - #, fuzzy, gcc-internal-format --#| msgid "visibility attribute not supported in this configuration; ignored" - msgid "protected visibility attribute not supported in this configuration; ignored" - msgstr "атрибут видимости не поддерживается в данной конфигурации; определение игнорируется" - -@@ -20873,19 +20828,16 @@ - - #: config/aarch64/aarch64-builtins.c:1032 - #, fuzzy, gcc-internal-format --#| msgid "incompatible type for argument %d of %qE" - msgid "incompatible type for argument %d, expected %" - msgstr "несовместимый тип аргумента %d функции %qE" - - #: config/aarch64/aarch64.c:3643 - #, fuzzy, gcc-internal-format --#| msgid "Enable function profiling" - msgid "function profiling" - msgstr "Включить профилирование функций" - - #: config/aarch64/aarch64.c:4623 - #, fuzzy, gcc-internal-format --#| msgid "missing filename after %qs" - msgid "missing feature modifier after %qs" - msgstr "не задано имя файла после %qs" - -@@ -20897,7 +20849,6 @@ - - #: config/aarch64/aarch64.c:4675 - #, fuzzy, gcc-internal-format --#| msgid "missing path after %qs" - msgid "missing arch name in -march=%qs" - msgstr "не задан маршрут после %qs" - -@@ -20909,7 +20860,6 @@ - - #: config/aarch64/aarch64.c:4724 - #, fuzzy, gcc-internal-format --#| msgid "missing path after %qs" - msgid "missing cpu name in -mcpu=%qs" - msgstr "не задан маршрут после %qs" - -@@ -20938,13 +20888,11 @@ - - #: config/aarch64/aarch64.c:6421 - #, fuzzy, gcc-internal-format --#| msgid "operand number out of range" - msgid "lane out of range" - msgstr "номер операнда вне диапазона" - - #: config/aarch64/aarch64.c:6431 - #, fuzzy, gcc-internal-format --#| msgid "constant argument out of range for %qs" - msgid "constant out of range" - msgstr "константный аргумент для %qs вне диапазона" - -@@ -21180,195 +21128,193 @@ - #: config/i386/i386.c:34639 config/i386/i386.c:34690 config/i386/i386.c:34762 - #: config/m68k/m68k.c:729 config/mcore/mcore.c:3046 config/mep/mep.c:3887 - #: config/mep/mep.c:3901 config/mep/mep.c:3975 config/rl78/rl78.c:480 --#: config/rs6000/rs6000.c:24833 config/rx/rx.c:2571 config/sh/sh.c:9515 --#: config/sh/sh.c:9533 config/sh/sh.c:9562 config/sh/sh.c:9644 --#: config/sh/sh.c:9667 config/spu/spu.c:3685 config/stormy16/stormy16.c:2207 -+#: config/rs6000/rs6000.c:24833 config/rx/rx.c:2571 config/sh/sh.c:9512 -+#: config/sh/sh.c:9530 config/sh/sh.c:9559 config/sh/sh.c:9641 -+#: config/sh/sh.c:9664 config/spu/spu.c:3685 config/stormy16/stormy16.c:2207 - #: config/v850/v850.c:2082 - #, fuzzy, gcc-internal-format - msgid "%qE attribute only applies to functions" - msgstr "атрибут %qs допустим только для функций" - --#: config/arm/arm.c:19315 -+#: config/arm/arm.c:19325 - #, gcc-internal-format - msgid "unable to compute real location of stacked parameter" - msgstr "невозможно вычислить фактическое положение параметра в стеке" - --#: config/arm/arm.c:21257 -+#: config/arm/arm.c:21267 - #, fuzzy, gcc-internal-format - msgid "argument must be a constant" - msgstr "аргумент %qD не является константой" - - #. @@@ better error message --#: config/arm/arm.c:21632 config/arm/arm.c:21736 -+#: config/arm/arm.c:21642 config/arm/arm.c:21746 - #, gcc-internal-format - msgid "selector must be an immediate" - msgstr "селектор должен быть непосредственным значением" - --#: config/arm/arm.c:21640 config/arm/arm.c:21685 config/arm/arm.c:21743 --#: config/arm/arm.c:21752 -+#: config/arm/arm.c:21650 config/arm/arm.c:21695 config/arm/arm.c:21753 -+#: config/arm/arm.c:21762 - #, gcc-internal-format - msgid "the range of selector should be in 0 to 7" - msgstr "" - --#: config/arm/arm.c:21645 config/arm/arm.c:21754 -+#: config/arm/arm.c:21655 config/arm/arm.c:21764 - #, gcc-internal-format - msgid "the range of selector should be in 0 to 3" - msgstr "" - --#: config/arm/arm.c:21650 config/arm/arm.c:21756 -+#: config/arm/arm.c:21660 config/arm/arm.c:21766 - #, gcc-internal-format - msgid "the range of selector should be in 0 to 1" - msgstr "" - --#: config/arm/arm.c:21822 -+#: config/arm/arm.c:21832 - #, gcc-internal-format - msgid "mask must be an immediate" - msgstr "маска должна быть непосредственным значением" - --#: config/arm/arm.c:21827 -+#: config/arm/arm.c:21837 - #, fuzzy, gcc-internal-format - msgid "the range of mask should be in 0 to 255" - msgstr "аргумент атрибута %qs не является целой константой" - --#: config/arm/arm.c:22015 -+#: config/arm/arm.c:22025 - #, gcc-internal-format - msgid "the range of count should be in 0 to 32. please check the intrinsic _mm_rori_pi16 in code." - msgstr "" - --#: config/arm/arm.c:22017 -+#: config/arm/arm.c:22027 - #, gcc-internal-format - msgid "the range of count should be in 0 to 32. please check the intrinsic _mm_rori_pi32 in code." - msgstr "" - --#: config/arm/arm.c:22019 -+#: config/arm/arm.c:22029 - #, gcc-internal-format - msgid "the range of count should be in 0 to 32. please check the intrinsic _mm_ror_pi16 in code." - msgstr "" - --#: config/arm/arm.c:22021 -+#: config/arm/arm.c:22031 - #, gcc-internal-format - msgid "the range of count should be in 0 to 32. please check the intrinsic _mm_ror_pi32 in code." - msgstr "" - --#: config/arm/arm.c:22027 -+#: config/arm/arm.c:22037 - #, gcc-internal-format - msgid "the range of count should be in 0 to 64. please check the intrinsic _mm_rori_si64 in code." - msgstr "" - --#: config/arm/arm.c:22029 -+#: config/arm/arm.c:22039 - #, gcc-internal-format - msgid "the range of count should be in 0 to 64. please check the intrinsic _mm_ror_si64 in code." - msgstr "" - --#: config/arm/arm.c:22034 -+#: config/arm/arm.c:22044 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srli_pi16 in code." - msgstr "" - --#: config/arm/arm.c:22036 -+#: config/arm/arm.c:22046 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srli_pi32 in code." - msgstr "" - --#: config/arm/arm.c:22038 -+#: config/arm/arm.c:22048 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srli_si64 in code." - msgstr "" - --#: config/arm/arm.c:22040 -+#: config/arm/arm.c:22050 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_slli_pi16 in code." - msgstr "" - --#: config/arm/arm.c:22042 -+#: config/arm/arm.c:22052 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_slli_pi32 in code." - msgstr "" - --#: config/arm/arm.c:22044 -+#: config/arm/arm.c:22054 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_slli_si64 in code." - msgstr "" - --#: config/arm/arm.c:22046 -+#: config/arm/arm.c:22056 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srai_pi16 in code." - msgstr "" - --#: config/arm/arm.c:22048 -+#: config/arm/arm.c:22058 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srai_pi32 in code." - msgstr "" - --#: config/arm/arm.c:22050 -+#: config/arm/arm.c:22060 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srai_si64 in code." - msgstr "" - --#: config/arm/arm.c:22052 -+#: config/arm/arm.c:22062 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srl_pi16 in code." - msgstr "" - --#: config/arm/arm.c:22054 -+#: config/arm/arm.c:22064 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srl_pi32 in code." - msgstr "" - --#: config/arm/arm.c:22056 -+#: config/arm/arm.c:22066 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_srl_si64 in code." - msgstr "" - --#: config/arm/arm.c:22058 -+#: config/arm/arm.c:22068 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_sll_pi16 in code." - msgstr "" - --#: config/arm/arm.c:22060 -+#: config/arm/arm.c:22070 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_sll_pi32 in code." - msgstr "" - --#: config/arm/arm.c:22062 -+#: config/arm/arm.c:22072 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_sll_si64 in code." - msgstr "" - --#: config/arm/arm.c:22064 -+#: config/arm/arm.c:22074 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_sra_pi16 in code." - msgstr "" - --#: config/arm/arm.c:22066 -+#: config/arm/arm.c:22076 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_sra_pi32 in code." - msgstr "" - --#: config/arm/arm.c:22068 -+#: config/arm/arm.c:22078 - #, gcc-internal-format - msgid "the count should be no less than 0. please check the intrinsic _mm_sra_si64 in code." - msgstr "" - --#: config/arm/arm.c:22787 -+#: config/arm/arm.c:22797 - #, gcc-internal-format - msgid "no low registers available for popping high registers" - msgstr "нет свободных low-регистров для выталкивания high-регистров" - --#: config/arm/arm.c:23012 -+#: config/arm/arm.c:23022 - #, gcc-internal-format - msgid "interrupt Service Routines cannot be coded in Thumb mode" - msgstr "подпрограммы Service Routines для прерываний не могут использоваться в режиме Thumb" - - #: config/avr/avr-c.c:65 config/avr/avr-c.c:190 - #, fuzzy, gcc-internal-format --#| msgid "%qs expects a constant argument" - msgid "%qs expects 1 argument but %d given" - msgstr "для %qs требуется константный аргумент" - - #: config/avr/avr-c.c:76 - #, fuzzy, gcc-internal-format --#| msgid "%qs expects a constant argument" - msgid "%qs expects a fixed-point value as argument" - msgstr "для %qs требуется константный аргумент" - -@@ -21379,25 +21325,21 @@ - - #: config/avr/avr-c.c:107 config/avr/avr-c.c:173 config/avr/avr-c.c:230 - #, fuzzy, gcc-internal-format --#| msgid "no matching template for %qD found" - msgid "no matching fixed-point overload found for %qs" - msgstr "нет подходящего шаблона для %qD" - - #: config/avr/avr-c.c:124 - #, fuzzy, gcc-internal-format --#| msgid "%qs expects a constant argument" - msgid "%qs expects 2 arguments but %d given" - msgstr "для %qs требуется константный аргумент" - - #: config/avr/avr-c.c:136 config/avr/avr-c.c:201 - #, fuzzy, gcc-internal-format --#| msgid "%qs expects a constant argument" - msgid "%qs expects a fixed-point value as first argument" - msgstr "для %qs требуется константный аргумент" - - #: config/avr/avr-c.c:144 - #, fuzzy, gcc-internal-format --#| msgid "%qs expects a constant argument" - msgid "%qs expects an integer value as second argument" - msgstr "для %qs требуется константный аргумент" - -@@ -21501,22 +21443,27 @@ - msgid "MCU %qs supported for assembler only" - msgstr "MCU %qs поддерживается только для ассемблера" - --#: config/avr/avr.c:11718 -+#: config/avr/avr.c:10816 -+#, fuzzy, gcc-internal-format -+msgid "conversion from address space %qs to address space %qs" -+msgstr "преобразование из %s в %s в %L" -+ -+#: config/avr/avr.c:11778 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "%s expects a compile time integer constant" - msgstr "Неожиданное окончание модуля в строковой константе" - --#: config/avr/avr.c:11732 -+#: config/avr/avr.c:11792 - #, fuzzy, gcc-internal-format, gfc-internal-format - msgid "%s expects a compile time long integer constant as first argument" - msgstr "для %qs требуется константный аргумент" - --#: config/avr/avr.c:11760 -+#: config/avr/avr.c:11820 - #, gcc-internal-format, gfc-internal-format - msgid "rounding to %d bits has no effect for fixed-point value with %d fractional bits" - msgstr "" - --#: config/avr/avr.c:11769 -+#: config/avr/avr.c:11829 - #, gcc-internal-format - msgid "rounding result will always be 0" - msgstr "" -@@ -21832,7 +21779,6 @@ - - #: config/h8300/h8300.c:320 - #, fuzzy, gcc-internal-format --#| msgid "-f%s not supported: ignored" - msgid "-msx is not supported in coff" - msgstr "ключ -f%s не поддерживается; игнорируется" - -@@ -21843,13 +21789,11 @@ - - #: config/h8300/h8300.c:348 - #, fuzzy, gcc-internal-format --#| msgid "-mn is used without -mh or -ms" - msgid "-mn is used without -mh or -ms or -msx" - msgstr "-mn без -mh или -ms" - - #: config/h8300/h8300.c:354 - #, fuzzy, gcc-internal-format --#| msgid "-ms2600 is used without -ms" - msgid "-mexr is used without -ms" - msgstr "-ms2600 без -ms" - -@@ -21860,7 +21804,6 @@ - - #: config/h8300/h8300.c:366 - #, fuzzy, gcc-internal-format --#| msgid "-mn is used without -mh or -ms" - msgid "-mexr is used without -ms or -msx" - msgstr "-mn без -mh или -ms" - -@@ -21897,7 +21840,6 @@ - - #: config/i386/i386.c:3160 - #, fuzzy, gcc-internal-format --#| msgid "code model %qs not supported in the %s bit mode" - msgid "address mode %qs not supported in the %s bit mode" - msgstr "модель кодирования %s не поддерживается в %s-битном режиме" - -@@ -22236,7 +22178,6 @@ - - #: config/i386/i386.c:29135 - #, fuzzy, gcc-internal-format --#| msgid "previous declaration of %q+D" - msgid "previous declaration of %D" - msgstr "предыдущая декларация %q+D" - -@@ -22247,7 +22188,6 @@ - - #: config/i386/i386.c:29695 - #, fuzzy, gcc-internal-format --#| msgid "argument to %qs must be a 2-bit unsigned literal" - msgid "Parameter to builtin must be a string constant or literal" - msgstr "аргумент %qs должен быть 2-битным беззнаковым литеральным значением" - -@@ -22358,7 +22298,6 @@ - - #: config/i386/i386.c:42160 - #, fuzzy, gcc-internal-format --#| msgid "Unknown architecture '%s'" - msgid "Unknown architecture specific memory model" - msgstr "неизвестная архитектура '%s'" - -@@ -22437,13 +22376,13 @@ - msgid "%qE attribute requires a string constant argument" - msgstr "аргументом атрибута %qs должна быть целая константа" - --#: config/ia64/ia64.c:5885 config/pa/pa.c:416 config/sh/sh.c:9351 -+#: config/ia64/ia64.c:5885 config/pa/pa.c:416 config/sh/sh.c:9348 - #: config/spu/spu.c:4897 - #, gcc-internal-format - msgid "value of -mfixed-range must have form REG1-REG2" - msgstr "значение ключа -mfixed-range имеет вид РЕГ1-РЕГ2" - --#: config/ia64/ia64.c:5912 config/pa/pa.c:443 config/sh/sh.c:9377 -+#: config/ia64/ia64.c:5912 config/pa/pa.c:443 config/sh/sh.c:9374 - #: config/spu/spu.c:4923 - #, gcc-internal-format, gfc-internal-format - msgid "%s-%s is an empty range" -@@ -22515,7 +22454,7 @@ - msgstr "%Jатрибут section для данной платформы не поддерживается" - - #. The argument must be a constant integer. --#: config/m32c/m32c.c:2934 config/sh/sh.c:9570 config/sh/sh.c:9676 -+#: config/m32c/m32c.c:2934 config/sh/sh.c:9567 config/sh/sh.c:9673 - #, fuzzy, gcc-internal-format - msgid "%qE attribute argument not an integer constant" - msgstr "аргумент атрибута %qs не является целой константой" -@@ -22562,7 +22501,6 @@ - - #: config/m68k/m68k.c:621 - #, fuzzy, gcc-internal-format --#| msgid "stack limits not supported on this target" - msgid "-fstack-limit- options are not supported on this cpu" - msgstr "проверка выхода за границу стека не поддерживается для этой платформы" - -@@ -22855,24 +22793,33 @@ - msgid "unexpected %d byte cop instruction" - msgstr "предикативная инструкция для архитектуры Thumb" - --#: config/microblaze/microblaze.c:1311 -+#: config/microblaze/microblaze.c:1676 - #, fuzzy, gcc-internal-format --#| msgid "-fstack-protector not supported for this target" - msgid "-fPIC/-fpic not supported for this target" - msgstr "-fstack-protector не поддерживается для этой целевой платформы" - --#: config/microblaze/microblaze.c:1323 -+#: config/microblaze/microblaze.c:1688 - #, fuzzy, gcc-internal-format - msgid "%qs is an invalid argument to -mcpu=" - msgstr "некорректный аргумент внутренней функции" - --#: config/microblaze/microblaze.c:1372 -+#: config/microblaze/microblaze.c:1737 - #, gcc-internal-format - msgid "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater" - msgstr "" - --#: config/microblaze/microblaze.c:1384 -+#: config/microblaze/microblaze.c:1753 - #, gcc-internal-format -+msgid "-mxl-reorder can be used only with -mcpu=v8.30.a or greater" -+msgstr "" -+ -+#: config/microblaze/microblaze.c:1759 -+#, gcc-internal-format -+msgid "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a" -+msgstr "" -+ -+#: config/microblaze/microblaze.c:1764 -+#, gcc-internal-format - msgid "-mxl-multiply-high requires -mno-xl-soft-mul" - msgstr "" - -@@ -23008,7 +22955,6 @@ - - #: config/mips/mips.c:16621 - #, fuzzy, gcc-internal-format --#| msgid "Generate position-independent code if possible (large mode)" - msgid "cannot generate position-independent code for %qs" - msgstr "Генерировать позиционно-независимый код, если возможно (режим large)" - -@@ -23370,7 +23316,6 @@ - - #: config/rs6000/rs6000.c:2547 - #, fuzzy, gcc-internal-format --#| msgid "Do not use PowerPC instruction set" - msgid "not configured for SPE instruction set" - msgstr "Не использовать систему команд PowerPC" - -@@ -23785,7 +23730,6 @@ - - #: config/rs6000/e500.h:37 - #, fuzzy, gcc-internal-format --#| msgid "AltiVec and E500 instructions cannot coexist" - msgid "AltiVec and SPE instructions cannot coexist" - msgstr "Команды AltiVec и E500 несовместимы" - -@@ -23983,63 +23927,63 @@ - msgid "%qs uses dynamic stack allocation" - msgstr "" - --#: config/sh/sh.c:906 -+#: config/sh/sh.c:903 - #, gcc-internal-format - msgid "ignoring -fschedule-insns because of exception handling bug" - msgstr "" - --#: config/sh/sh.c:923 -+#: config/sh/sh.c:920 - #, gcc-internal-format - msgid "unwind tables currently require either a frame pointer or -maccumulate-outgoing-args for correctness" - msgstr "для корректной поддержки таблиц раскрутки стека требуется либо указатель кадра, либо -maccumulate-outgoing-args" - --#: config/sh/sh.c:8284 -+#: config/sh/sh.c:8281 - #, gcc-internal-format - msgid "__builtin_saveregs not supported by this subtarget" - msgstr "__builtin_saveregs для этой платформы не поддерживается" - --#: config/sh/sh.c:9439 -+#: config/sh/sh.c:9436 - #, fuzzy, gcc-internal-format - msgid "%qE attribute only applies to interrupt functions" - msgstr "атрибут %qs применим только к функциям обработки прерываний" - --#: config/sh/sh.c:9509 -+#: config/sh/sh.c:9506 - #, fuzzy, gcc-internal-format - msgid "%qE attribute is supported only for SH2A" - msgstr "атрибут %qs не поддерживается на данной платформе" - --#: config/sh/sh.c:9539 -+#: config/sh/sh.c:9536 - #, gcc-internal-format - msgid "attribute interrupt_handler is not compatible with -m5-compact" - msgstr "атрибут interrupt_handler несовместим с -m5-compact" - --#: config/sh/sh.c:9556 -+#: config/sh/sh.c:9553 - #, fuzzy, gcc-internal-format - msgid "%qE attribute only applies to SH2A" - msgstr "атрибут %qs допустим только для функций" - --#: config/sh/sh.c:9578 -+#: config/sh/sh.c:9575 - #, fuzzy, gcc-internal-format - msgid "%qE attribute argument should be between 0 to 255" - msgstr "аргумент атрибута %qs не является целой константой" - - #. The argument must be a constant string. --#: config/sh/sh.c:9651 -+#: config/sh/sh.c:9648 - #, fuzzy, gcc-internal-format - msgid "%qE attribute argument not a string constant" - msgstr "аргумент атрибута %qs не является строковой константой" - --#: config/sh/sh.c:12341 -+#: config/sh/sh.c:12338 - #, gcc-internal-format - msgid "r0 needs to be available as a call-clobbered register" - msgstr "" - --#: config/sh/sh.c:12362 -+#: config/sh/sh.c:12359 - #, fuzzy, gcc-internal-format - msgid "need a second call-clobbered general purpose register" - msgstr "Использовать регистр BK как регистр общего назначения" - --#: config/sh/sh.c:12370 -+#: config/sh/sh.c:12367 - #, fuzzy, gcc-internal-format - msgid "need a call-clobbered target register" - msgstr "Использовать регистр BK как регистр общего назначения" -@@ -24358,7 +24302,6 @@ - - #: config/vms/vms-c.c:328 - #, fuzzy, gcc-internal-format --#| msgid "invalid constant in %<#pragma pack%> - ignored" - msgid "invalid constant in %<#pragma %s%>" - msgstr "некорректная константа в %<#pragma pack%> - директива проигнорирована" - -@@ -24775,7 +24718,7 @@ - msgstr "метка %q+D определена, но не используется" - - #: c/c-decl.c:3111 c/c-decl.c:3383 c/c-typeck.c:6979 cp/class.c:1339 --#: cp/class.c:2928 -+#: cp/class.c:2932 - #, fuzzy, gcc-internal-format - msgid "%qD declared here" - msgstr "%q+D объявлено здесь" -@@ -24943,7 +24886,7 @@ - msgid "variable %qD has initializer but incomplete type" - msgstr "переменная %qD инициализирована, хотя имеет неполный тип" - --#: c/c-decl.c:4150 cp/decl.c:4529 cp/decl.c:12970 -+#: c/c-decl.c:4150 cp/decl.c:4529 cp/decl.c:12961 - #, gcc-internal-format - msgid "inline function %q+D given attribute noinline" - msgstr "inline функция %q+D с атрибутом noinline" -@@ -25078,7 +25021,7 @@ - msgid "variable length array %qE is used" - msgstr "используется массив переменного размера %qD" - --#: c/c-decl.c:4857 cp/decl.c:8274 -+#: c/c-decl.c:4857 cp/decl.c:8277 - #, gcc-internal-format - msgid "variable length array is used" - msgstr "" -@@ -25163,7 +25106,7 @@ - msgid "storage class specified for unnamed parameter" - msgstr "класс хранения в декларации параметра %qs" - --#: c/c-decl.c:5143 cp/decl.c:9283 -+#: c/c-decl.c:5143 cp/decl.c:9279 - #, gcc-internal-format - msgid "storage class specified for typename" - msgstr "класс хранения задан для имени типа" -@@ -25312,7 +25255,7 @@ - msgid "function definition has qualified void return type" - msgstr "в определении функции задан квалифицированный void-тип возвращаемого значения" - --#: c/c-decl.c:5635 cp/decl.c:9411 -+#: c/c-decl.c:5635 cp/decl.c:9407 - #, gcc-internal-format - msgid "type qualifiers ignored on function return type" - msgstr "квалификаторы в описании типа возвращаемого значения функции " -@@ -25423,7 +25366,7 @@ - msgid "a member of a structure or union cannot have a variably modified type" - msgstr "элемент данных не может иметь тип %qT модифицируемого размера" - --#: c/c-decl.c:5915 cp/decl.c:8516 -+#: c/c-decl.c:5915 cp/decl.c:8519 - #, gcc-internal-format - msgid "variable or field %qE declared void" - msgstr "переменная или поле %qE объявлено void" -@@ -25846,7 +25789,7 @@ - msgid "argument %qD doesn%'t match prototype" - msgstr "аргумент %qD не соответствует прототипу" - --#: c/c-decl.c:8396 cp/decl.c:13848 -+#: c/c-decl.c:8396 cp/decl.c:13839 - #, gcc-internal-format - msgid "no return statement in function returning non-void" - msgstr "в функции, которая должна возвращать значение, отсутствует оператор return" -@@ -25914,7 +25857,7 @@ - msgid "two or more data types in declaration specifiers" - msgstr "два или более типа в декларации" - --#: c/c-decl.c:8924 cp/parser.c:22803 -+#: c/c-decl.c:8924 cp/parser.c:22807 - #, gcc-internal-format - msgid "% is too long for GCC" - msgstr "GCC не поддерживает тип %" -@@ -26044,7 +25987,7 @@ - msgid "unknown type name %qE" - msgstr "неизвестное имя регистра: %s" - --#: c/c-parser.c:1484 c/c-parser.c:8618 cp/parser.c:28127 -+#: c/c-parser.c:1484 c/c-parser.c:8618 cp/parser.c:28131 - #, gcc-internal-format - msgid "expected declaration specifiers" - msgstr "ожидались спецификаторы декларации" -@@ -26054,7 +25997,7 @@ - msgid "expected %<;%>, identifier or %<(%>" - msgstr "ожидался идентификатор или %<(%>" - --#: c/c-parser.c:1527 cp/parser.c:24553 cp/parser.c:24627 -+#: c/c-parser.c:1527 cp/parser.c:24557 cp/parser.c:24631 - #, fuzzy, gcc-internal-format - msgid "prefix attributes are ignored for methods" - msgstr "атрибут %qE для %qE проигнорирован" -@@ -26102,7 +26045,7 @@ - msgid "ISO C90 does not support %<_Static_assert%>" - msgstr "ISO C90 не поддерживает тип %" - --#: c/c-parser.c:1860 c/c-parser.c:3388 c/c-parser.c:8673 cp/parser.c:27998 -+#: c/c-parser.c:1860 c/c-parser.c:3388 c/c-parser.c:8673 cp/parser.c:28002 - #, gcc-internal-format - msgid "expected string literal" - msgstr "ожидался строковый литерал" -@@ -26134,13 +26077,13 @@ - #: c/c-parser.c:7409 c/c-parser.c:7417 c/c-parser.c:7446 c/c-parser.c:7459 - #: c/c-parser.c:7764 c/c-parser.c:7888 c/c-parser.c:8316 c/c-parser.c:8351 - #: c/c-parser.c:8404 c/c-parser.c:8457 c/c-parser.c:8473 c/c-parser.c:8519 --#: c/c-parser.c:8798 c/c-parser.c:9873 c/c-parser.c:10676 cp/parser.c:23013 --#: cp/parser.c:25397 cp/parser.c:25427 cp/parser.c:25497 cp/parser.c:27718 -+#: c/c-parser.c:8798 c/c-parser.c:9873 c/c-parser.c:10676 cp/parser.c:23017 -+#: cp/parser.c:25401 cp/parser.c:25431 cp/parser.c:25501 cp/parser.c:27722 - #, gcc-internal-format - msgid "expected identifier" - msgstr "ожидался идентификатор" - --#: c/c-parser.c:2295 cp/parser.c:14837 -+#: c/c-parser.c:2295 cp/parser.c:14839 - #, gcc-internal-format - msgid "comma at end of enumerator list" - msgstr "запятая в конце списка значений перечислимого типа" -@@ -26469,77 +26412,77 @@ - msgid "no type or storage class may be specified here," - msgstr "для %qs задан класс хранения" - --#: c/c-parser.c:8320 c/c-parser.c:8377 cp/parser.c:25457 -+#: c/c-parser.c:8320 c/c-parser.c:8377 cp/parser.c:25461 - #, gcc-internal-format - msgid "unknown property attribute" - msgstr "" - --#: c/c-parser.c:8341 cp/parser.c:25417 -+#: c/c-parser.c:8341 cp/parser.c:25421 - #, fuzzy, gcc-internal-format - msgid "missing %<=%> (after % attribute)" - msgstr "отсутствует %<(%> после %<#pragma pack%> - директива проигнорирована" - --#: c/c-parser.c:8344 cp/parser.c:25420 -+#: c/c-parser.c:8344 cp/parser.c:25424 - #, fuzzy, gcc-internal-format - msgid "missing %<=%> (after % attribute)" - msgstr "отсутствует %<(%> после %<#pragma pack%> - директива проигнорирована" - --#: c/c-parser.c:8358 cp/parser.c:25435 -+#: c/c-parser.c:8358 cp/parser.c:25439 - #, fuzzy, gcc-internal-format - msgid "the % attribute may only be specified once" - msgstr "%Jатрибут section недопустим для локальных переменных" - --#: c/c-parser.c:8363 cp/parser.c:25441 -+#: c/c-parser.c:8363 cp/parser.c:25445 - #, gcc-internal-format - msgid "setter name must terminate with %<:%>" - msgstr "" - --#: c/c-parser.c:8370 cp/parser.c:25449 -+#: c/c-parser.c:8370 cp/parser.c:25453 - #, fuzzy, gcc-internal-format - msgid "the % attribute may only be specified once" - msgstr "%Jатрибут адресного пространства для функций недопустим" - --#: c/c-parser.c:8556 cp/parser.c:28042 -+#: c/c-parser.c:8556 cp/parser.c:28046 - #, gcc-internal-format - msgid "%<#pragma omp barrier%> may only be used in compound statements" - msgstr "" - --#: c/c-parser.c:8567 cp/parser.c:28057 -+#: c/c-parser.c:8567 cp/parser.c:28061 - #, gcc-internal-format - msgid "%<#pragma omp flush%> may only be used in compound statements" - msgstr "" - --#: c/c-parser.c:8578 cp/parser.c:28073 -+#: c/c-parser.c:8578 cp/parser.c:28077 - #, gcc-internal-format - msgid "%<#pragma omp taskwait%> may only be used in compound statements" - msgstr "" - --#: c/c-parser.c:8589 cp/parser.c:28089 -+#: c/c-parser.c:8589 cp/parser.c:28093 - #, gcc-internal-format - msgid "%<#pragma omp taskyield%> may only be used in compound statements" - msgstr "" - --#: c/c-parser.c:8602 cp/parser.c:28117 -+#: c/c-parser.c:8602 cp/parser.c:28121 - #, gcc-internal-format - msgid "%<#pragma omp section%> may only be used in %<#pragma omp sections%> construct" - msgstr "" - --#: c/c-parser.c:8608 cp/parser.c:28032 -+#: c/c-parser.c:8608 cp/parser.c:28036 - #, fuzzy, gcc-internal-format - msgid "%<#pragma GCC pch_preprocess%> must be first" - msgstr "некорректный формат #pragma GCC pch_preprocess, директива проигнорирована" - --#: c/c-parser.c:8773 cp/parser.c:25705 -+#: c/c-parser.c:8773 cp/parser.c:25709 - #, fuzzy, gcc-internal-format - msgid "too many %qs clauses" - msgstr "слишком много входных файлов" - --#: c/c-parser.c:8875 cp/parser.c:25820 -+#: c/c-parser.c:8875 cp/parser.c:25824 - #, fuzzy, gcc-internal-format - msgid "collapse argument needs positive constant integer expression" - msgstr "сравнение знакового и беззнакового целых выражений" - --#: c/c-parser.c:8941 cp/parser.c:25871 -+#: c/c-parser.c:8941 cp/parser.c:25875 - #, fuzzy, gcc-internal-format - msgid "expected % or %" - msgstr "ожидалось %<,%> или %<;%>" -@@ -26554,42 +26497,42 @@ - msgid "% value must be positive" - msgstr "" - --#: c/c-parser.c:9192 cp/parser.c:26090 -+#: c/c-parser.c:9192 cp/parser.c:26094 - #, fuzzy, gcc-internal-format - msgid "expected %<+%>, %<*%>, %<-%>, %<&%>, %<^%>, %<|%>, %<&&%>, %<||%>, % or %" - msgstr "ожидалось %<:%>, %<,%>, %<;%>, %<}%> или %<__attribute__%>" - --#: c/c-parser.c:9281 cp/parser.c:26175 -+#: c/c-parser.c:9281 cp/parser.c:26179 - #, gcc-internal-format - msgid "schedule % does not take a % parameter" - msgstr "" - --#: c/c-parser.c:9285 cp/parser.c:26178 -+#: c/c-parser.c:9285 cp/parser.c:26182 - #, gcc-internal-format - msgid "schedule % does not take a % parameter" - msgstr "" - --#: c/c-parser.c:9303 cp/parser.c:26194 -+#: c/c-parser.c:9303 cp/parser.c:26198 - #, fuzzy, gcc-internal-format - msgid "invalid schedule kind" - msgstr "некорректный операнд const_double" - --#: c/c-parser.c:9431 cp/parser.c:26326 -+#: c/c-parser.c:9431 cp/parser.c:26330 - #, gcc-internal-format - msgid "expected %<#pragma omp%> clause" - msgstr "" - --#: c/c-parser.c:9440 cp/parser.c:26335 -+#: c/c-parser.c:9440 cp/parser.c:26339 - #, fuzzy, gcc-internal-format - msgid "%qs is not valid for %qs" - msgstr "%qs не является корректным выходным файлом" - --#: c/c-parser.c:9732 cp/parser.c:26619 -+#: c/c-parser.c:9732 cp/parser.c:26623 - #, fuzzy, gcc-internal-format - msgid "invalid form of %<#pragma omp atomic%>" - msgstr "некорректный операнд для %<__fpreg%>" - --#: c/c-parser.c:9772 c/c-parser.c:9790 cp/parser.c:26650 cp/parser.c:26667 -+#: c/c-parser.c:9772 c/c-parser.c:9790 cp/parser.c:26654 cp/parser.c:26671 - #, fuzzy, gcc-internal-format - msgid "invalid operator for %<#pragma omp atomic%>" - msgstr "некорректный операнд для %<__fpreg%>" -@@ -26599,7 +26542,7 @@ - msgid "expected %<(%> or end of line" - msgstr "некорректный операнд" - --#: c/c-parser.c:9932 cp/parser.c:26939 -+#: c/c-parser.c:9932 cp/parser.c:26943 - #, fuzzy, gcc-internal-format - msgid "for statement expected" - msgstr "перед `*' должно быть имя типа" -@@ -26614,12 +26557,12 @@ - msgid "not enough perfectly nested loops" - msgstr "" - --#: c/c-parser.c:10119 cp/parser.c:27284 -+#: c/c-parser.c:10119 cp/parser.c:27288 - #, gcc-internal-format - msgid "collapsed loops not perfectly nested" - msgstr "" - --#: c/c-parser.c:10157 cp/parser.c:27125 cp/parser.c:27163 cp/pt.c:12692 -+#: c/c-parser.c:10157 cp/parser.c:27129 cp/parser.c:27167 cp/pt.c:12687 - #, fuzzy, gcc-internal-format - msgid "iteration variable %qD should not be firstprivate" - msgstr "instance-переменная %qs объявлена как private" -@@ -26644,27 +26587,27 @@ - msgid "% %qE has incomplete type" - msgstr "%Jпараметр %u имеет неполный тип" - --#: c/c-parser.c:10823 cp/parser.c:27928 -+#: c/c-parser.c:10823 cp/parser.c:27932 - #, gcc-internal-format - msgid "%<__transaction_cancel%> without transactional memory support enabled" - msgstr "" - --#: c/c-parser.c:10829 cp/parser.c:27934 -+#: c/c-parser.c:10829 cp/parser.c:27938 - #, gcc-internal-format - msgid "%<__transaction_cancel%> within a %<__transaction_relaxed%>" - msgstr "" - --#: c/c-parser.c:10838 cp/parser.c:27943 -+#: c/c-parser.c:10838 cp/parser.c:27947 - #, gcc-internal-format - msgid "outer %<__transaction_cancel%> not within outer %<__transaction_atomic%>" - msgstr "" - --#: c/c-parser.c:10840 cp/parser.c:27946 -+#: c/c-parser.c:10840 cp/parser.c:27950 - #, gcc-internal-format - msgid " or a % function" - msgstr "" - --#: c/c-parser.c:10846 cp/parser.c:27952 -+#: c/c-parser.c:10846 cp/parser.c:27956 - #, gcc-internal-format - msgid "%<__transaction_cancel%> not within %<__transaction_atomic%>" - msgstr "" -@@ -26807,19 +26750,16 @@ - - #: c/c-typeck.c:2746 - #, fuzzy, gcc-internal-format --#| msgid "called object %qE is not a function" - msgid "called object %qE is not a function or function pointer" - msgstr "вызываемый объект %qE не является функцией" - - #: c/c-typeck.c:2751 - #, fuzzy, gcc-internal-format --#| msgid "called object %qE is not a function" - msgid "called object %qD is not a function or function pointer" - msgstr "вызываемый объект %qE не является функцией" - - #: c/c-typeck.c:2757 - #, fuzzy, gcc-internal-format --#| msgid "called object %qE is not a function" - msgid "called object is not a function or function pointer" - msgstr "вызываемый объект %qE не является функцией" - -@@ -27473,7 +27413,6 @@ - - #: c/c-typeck.c:6975 - #, fuzzy, gcc-internal-format --#| msgid "missing initializer for member %qD" - msgid "missing initializer for field %qD of %qT" - msgstr "отсутствует инициализатор для элемента %qD" - -@@ -27977,7 +27916,6 @@ - - #: cp/call.c:4239 - #, fuzzy, gcc-internal-format --#| msgid "%s" - msgid "%qs" - msgstr "%s" - -@@ -28008,7 +27946,6 @@ - - #: cp/call.c:4433 - #, fuzzy, gcc-internal-format --#| msgid "enumeral mismatch in conditional expression: %qT vs %qT" - msgid "incompatible vector types in conditional expression: %qT, %qT and %qT" - msgstr "несоответствие перечислимых типов в условном выражении: %qT vs %qT" - -@@ -28223,107 +28160,107 @@ - msgid " (you can disable this with -fno-deduce-init-list)" - msgstr "" - --#: cp/call.c:7153 -+#: cp/call.c:7156 - #, gcc-internal-format - msgid "could not find class$ field in java interface type %qT" - msgstr "не найдено поле класса в интерфейсном типе java %qT" - --#: cp/call.c:7414 -+#: cp/call.c:7417 - #, gcc-internal-format - msgid "call to non-function %qD" - msgstr "вызов не функции %qD" - --#: cp/call.c:7459 cp/typeck.c:2680 -+#: cp/call.c:7462 cp/typeck.c:2680 - #, gcc-internal-format - msgid "cannot call constructor %<%T::%D%> directly" - msgstr "" - --#: cp/call.c:7461 -+#: cp/call.c:7464 - #, gcc-internal-format - msgid " for a function-style cast, remove the redundant %<::%D%>" - msgstr "" - --#: cp/call.c:7578 -+#: cp/call.c:7581 - #, fuzzy, gcc-internal-format - msgid "no matching function for call to %<%T::operator %T(%A)%#V%>" - msgstr "нет подходящей функции для вызова %<%T::%s(%A)%#V%>" - --#: cp/call.c:7591 -+#: cp/call.c:7594 - #, gcc-internal-format - msgid "no matching function for call to %<%T::%s(%A)%#V%>" - msgstr "нет подходящей функции для вызова %<%T::%s(%A)%#V%>" - --#: cp/call.c:7616 -+#: cp/call.c:7619 - #, gcc-internal-format - msgid "call of overloaded %<%s(%A)%> is ambiguous" - msgstr "вызов перегруженной %<%s(%A)%> имеет неоднозначную трактовку" - --#: cp/call.c:7645 -+#: cp/call.c:7661 - #, gcc-internal-format - msgid "cannot call member function %qD without object" - msgstr "некорректный вызов элемента-функции %qD без объекта" - --#: cp/call.c:8410 -+#: cp/call.c:8428 - #, gcc-internal-format - msgid "passing %qT chooses %qT over %qT" - msgstr "при передаче %qT предпочтение отдается %qT, а не %qT" - --#: cp/call.c:8412 cp/name-lookup.c:5552 -+#: cp/call.c:8430 cp/name-lookup.c:5547 - #, gcc-internal-format - msgid " in call to %qD" - msgstr " в вызове %qD" - --#: cp/call.c:8470 -+#: cp/call.c:8488 - #, gcc-internal-format - msgid "choosing %qD over %qD" - msgstr "предпочтение отдается %qD (а не %qD)" - --#: cp/call.c:8471 -+#: cp/call.c:8489 - #, gcc-internal-format - msgid " for conversion from %qT to %qT" - msgstr " при преобразовании из %qT в %qT," - --#: cp/call.c:8474 -+#: cp/call.c:8492 - #, gcc-internal-format - msgid " because conversion sequence for the argument is better" - msgstr " поскольку это дает лучшую последовательность преобразований аргумента" - --#: cp/call.c:8628 -+#: cp/call.c:8646 - #, fuzzy, gcc-internal-format - msgid "default argument mismatch in overload resolution" - msgstr "отсутствует аргумент по умолчанию для параметра %P функции %q+#D" - --#: cp/call.c:8631 -+#: cp/call.c:8649 - #, fuzzy, gcc-internal-format - msgid " candidate 1: %q+#F" - msgstr "претендент: %+#D" - --#: cp/call.c:8633 -+#: cp/call.c:8651 - #, fuzzy, gcc-internal-format - msgid " candidate 2: %q+#F" - msgstr "претендент: %+#D" - --#: cp/call.c:8677 -+#: cp/call.c:8695 - #, gcc-internal-format - msgid "ISO C++ says that these are ambiguous, even though the worst conversion for the first is better than the worst conversion for the second:" - msgstr "" - --#: cp/call.c:8841 -+#: cp/call.c:8859 - #, fuzzy, gcc-internal-format - msgid "could not convert %qE from %qT to %qT" - msgstr "ошибка преобразования %qE в %qT" - --#: cp/call.c:9034 -+#: cp/call.c:9052 - #, gcc-internal-format - msgid "a temporary bound to %qD only persists until the constructor exits" - msgstr "" - --#: cp/call.c:9150 -+#: cp/call.c:9168 - #, fuzzy, gcc-internal-format - msgid "invalid initialization of non-const reference of type %qT from an rvalue of type %qT" - msgstr "некорректная инициализация неконстантной ссылки типа %qT из временного выражения типа %qT" - --#: cp/call.c:9154 -+#: cp/call.c:9172 - #, gcc-internal-format - msgid "invalid initialization of reference of type %qT from expression of type %qT" - msgstr "некорректная инициализация ссылки типа %qT из выражения типа %qT" -@@ -28433,351 +28370,350 @@ - msgid "no unique final overrider for %qD in %qT" - msgstr "отсутствует уникальное переопределение %qD в %qT" - --#: cp/class.c:2648 -+#: cp/class.c:2652 - #, fuzzy, gcc-internal-format - msgid "%q+#D marked final, but is not virtual" - msgstr "%q+D определена, но нигде не используется" - --#: cp/class.c:2650 -+#: cp/class.c:2654 - #, gcc-internal-format - msgid "%q+#D marked override, but does not override" - msgstr "" - - #. Here we know it is a hider, and no overrider exists. --#: cp/class.c:2719 -+#: cp/class.c:2723 - #, gcc-internal-format - msgid "%q+D was hidden" - msgstr "%q+D скрыто" - --#: cp/class.c:2720 -+#: cp/class.c:2724 - #, gcc-internal-format - msgid " by %q+D" - msgstr " методом %q+D" - --#: cp/class.c:2763 cp/decl2.c:1365 -+#: cp/class.c:2767 cp/decl2.c:1365 - #, fuzzy, gcc-internal-format - msgid "%q+#D invalid; an anonymous union can only have non-static data members" - msgstr "`%#D' некорректно; в анонимном объединении допустимы только нестатические элементы" - --#: cp/class.c:2766 -+#: cp/class.c:2770 - #, fuzzy, gcc-internal-format - msgid "%q+#D invalid; an anonymous struct can only have non-static data members" - msgstr "`%#D' некорректно; в анонимном объединении допустимы только нестатические элементы" - --#: cp/class.c:2774 cp/decl2.c:1371 -+#: cp/class.c:2778 cp/decl2.c:1371 - #, fuzzy, gcc-internal-format - msgid "private member %q+#D in anonymous union" - msgstr "private-элемент `%#D' в анонимном объединении" - --#: cp/class.c:2776 -+#: cp/class.c:2780 - #, fuzzy, gcc-internal-format - msgid "private member %q+#D in anonymous struct" - msgstr "private-элемент `%#D' в анонимном объединении" - --#: cp/class.c:2781 cp/decl2.c:1373 -+#: cp/class.c:2785 cp/decl2.c:1373 - #, fuzzy, gcc-internal-format - msgid "protected member %q+#D in anonymous union" - msgstr "protected-элемент `%#D' в анонимном объединении" - --#: cp/class.c:2783 -+#: cp/class.c:2787 - #, fuzzy, gcc-internal-format - msgid "protected member %q+#D in anonymous struct" - msgstr "protected-элемент `%#D' в анонимном объединении" - --#: cp/class.c:2927 -+#: cp/class.c:2931 - #, gcc-internal-format - msgid "the ellipsis in %qD is not inherited" - msgstr "" - --#: cp/class.c:3103 -+#: cp/class.c:3106 - #, fuzzy, gcc-internal-format - msgid "bit-field %q+#D with non-integral type" - msgstr "битовое поле `%#D' не целочисленного типа" - --#: cp/class.c:3119 -+#: cp/class.c:3122 - #, gcc-internal-format - msgid "bit-field %q+D width not an integer constant" - msgstr "ширина битового поля %q+D не является целой константой" - --#: cp/class.c:3124 -+#: cp/class.c:3127 - #, gcc-internal-format - msgid "negative width in bit-field %q+D" - msgstr "отрицательная ширина битового поля %q+D" - --#: cp/class.c:3129 -+#: cp/class.c:3132 - #, gcc-internal-format - msgid "zero width for bit-field %q+D" - msgstr "нулевая ширина битового поля %q+D" - --#: cp/class.c:3135 -+#: cp/class.c:3138 - #, gcc-internal-format - msgid "width of %q+D exceeds its type" - msgstr "ширина поля %q+D превышает ширину его типа" - --#: cp/class.c:3139 -+#: cp/class.c:3142 - #, gcc-internal-format - msgid "%q+D is too small to hold all values of %q#T" - msgstr "%q+D слишком мало для представления всех значений типа %q#T" - --#: cp/class.c:3198 -+#: cp/class.c:3201 - #, gcc-internal-format - msgid "member %q+#D with constructor not allowed in union" - msgstr "элемент %q+#D с конструктором не допускается в объединении" - --#: cp/class.c:3201 -+#: cp/class.c:3204 - #, gcc-internal-format - msgid "member %q+#D with destructor not allowed in union" - msgstr "элемент %q+#D с деструктором не допускается в объединении" - --#: cp/class.c:3203 -+#: cp/class.c:3206 - #, gcc-internal-format - msgid "member %q+#D with copy assignment operator not allowed in union" - msgstr "элемент %q+#D с операцией присваивания путем копирования не допускается в объединении" - --#: cp/class.c:3207 -+#: cp/class.c:3210 - #, gcc-internal-format - msgid "unrestricted unions only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/class.c:3244 -+#: cp/class.c:3247 - #, gcc-internal-format - msgid "multiple fields in union %qT initialized" - msgstr "инициализация нескольких полей в объединении %qT" - --#: cp/class.c:3329 -+#: cp/class.c:3332 - #, gcc-internal-format - msgid "%q+D may not be static because it is a member of a union" - msgstr "%q+D может быть не статическим, поскольку это элемент объединения" - --#: cp/class.c:3334 -+#: cp/class.c:3337 - #, gcc-internal-format - msgid "%q+D may not have reference type %qT because it is a member of a union" - msgstr "%q+D может не иметь ссылочного типа %qT, поскольку это элемент объединения" - --#: cp/class.c:3345 -+#: cp/class.c:3348 - #, gcc-internal-format - msgid "field %q+D invalidly declared function type" - msgstr "поле %q+D ошибочно декларировано с типом функции" - --#: cp/class.c:3351 -+#: cp/class.c:3354 - #, gcc-internal-format - msgid "field %q+D invalidly declared method type" - msgstr "поле %q+D ошибочно декларировано с типом метода" - --#: cp/class.c:3407 -+#: cp/class.c:3410 - #, gcc-internal-format - msgid "ignoring packed attribute because of unpacked non-POD field %q+#D" - msgstr "атрибут packed проигнорирован для неупакованного не-POD поля %q+#D" - --#: cp/class.c:3504 -+#: cp/class.c:3507 - #, gcc-internal-format - msgid "field %q+#D with same name as class" - msgstr "поле %q+#D с тем же именем, что и класс" - --#: cp/class.c:3527 -+#: cp/class.c:3530 - #, gcc-internal-format - msgid "%q#T has pointer data members" - msgstr "%q+#T содержит элементы данных типа указатель" - --#: cp/class.c:3532 -+#: cp/class.c:3535 - #, gcc-internal-format - msgid " but does not override %<%T(const %T&)%>" - msgstr " но не переопределяет %<%T(const %T&)%>" - --#: cp/class.c:3534 -+#: cp/class.c:3537 - #, gcc-internal-format - msgid " or %" - msgstr " или %" - --#: cp/class.c:3538 -+#: cp/class.c:3541 - #, gcc-internal-format - msgid " but does not override %" - msgstr " но не переопределяет %" - --#: cp/class.c:4009 -+#: cp/class.c:4012 - #, gcc-internal-format - msgid "offset of empty base %qT may not be ABI-compliant and maychange in a future version of GCC" - msgstr "смещение пустой базы %qT может быть несовместимо с ABI и может быть изменено в будущих версиях GCC" - --#: cp/class.c:4136 -+#: cp/class.c:4139 - #, gcc-internal-format - msgid "class %qT will be considered nearly empty in a future version of GCC" - msgstr "класс %qT будет рассматриваться как почти пустой в будущих версиях GCC" - --#: cp/class.c:4218 -+#: cp/class.c:4221 - #, gcc-internal-format - msgid "initializer specified for non-virtual method %q+D" - msgstr "инициализатор задан для невиртуального метода %q+D" - --#: cp/class.c:4645 -+#: cp/class.c:4648 - #, gcc-internal-format - msgid "method overrides both % and %qE methods" - msgstr "" - --#: cp/class.c:4666 -+#: cp/class.c:4669 - #, gcc-internal-format - msgid "method declared %qE overriding %qE method" - msgstr "" - --#: cp/class.c:5132 cp/semantics.c:5826 -+#: cp/class.c:5135 cp/semantics.c:5828 - #, fuzzy, gcc-internal-format - msgid "enclosing class of constexpr non-static member function %q+#D is not a literal type" - msgstr "%qs не является именем типа" - --#: cp/class.c:5157 -+#: cp/class.c:5160 - #, fuzzy, gcc-internal-format - msgid "%q+T is not literal because:" - msgstr "%q#T не является классом" - --#: cp/class.c:5159 -+#: cp/class.c:5162 - #, fuzzy, gcc-internal-format - msgid " %q+T has a non-trivial destructor" - msgstr "базовый класс %q#T имеет невиртуальный деструктор" - --#: cp/class.c:5164 -+#: cp/class.c:5167 - #, gcc-internal-format - msgid " %q+T is not an aggregate, does not have a trivial default constructor, and has no constexpr constructor that is not a copy or move constructor" - msgstr "" - --#: cp/class.c:5200 -+#: cp/class.c:5203 - #, fuzzy, gcc-internal-format - msgid " base class %qT of %q+T is non-literal" - msgstr "%qs не является именем типа" - --#: cp/class.c:5214 -+#: cp/class.c:5217 - #, fuzzy, gcc-internal-format - msgid " non-static data member %q+D has non-literal type" - msgstr "`%#D' не является нестатическим элементом %qT" - --#: cp/class.c:5332 -+#: cp/class.c:5335 - #, gcc-internal-format - msgid "non-static reference %q+#D in class without a constructor" - msgstr "нестатическая ссылка %q+#D в классе без конструктора" - --#: cp/class.c:5337 -+#: cp/class.c:5340 - #, gcc-internal-format - msgid "non-static const member %q+#D in class without a constructor" - msgstr "нестатический константный элемент %q+#D в классе без конструктора" - - #. If the function is defaulted outside the class, we just - #. give the synthesis error. --#: cp/class.c:5363 -+#: cp/class.c:5366 - #, gcc-internal-format - msgid "%q+D declared to take const reference, but implicit declaration would take non-const" - msgstr "" - --#: cp/class.c:5587 -+#: cp/class.c:5590 - #, gcc-internal-format - msgid "offset of virtual base %qT is not ABI-compliant and may change in a future version of GCC" - msgstr "смещение виртуальной базы %qT несовместимо с ABI и может быть изменено в будущих версиях GCC" - --#: cp/class.c:5688 -+#: cp/class.c:5691 - #, gcc-internal-format - msgid "direct base %qT inaccessible in %qT due to ambiguity" - msgstr "непосредственная база %qT недоступна в %qT из-за неоднозначности" - --#: cp/class.c:5700 -+#: cp/class.c:5703 - #, gcc-internal-format - msgid "virtual base %qT inaccessible in %qT due to ambiguity" - msgstr "виртуальная база %qT недоступна в %qT из-за неоднозначности" - --#: cp/class.c:5886 -+#: cp/class.c:5889 - #, gcc-internal-format - msgid "size assigned to %qT may not be ABI-compliant and may change in a future version of GCC" - msgstr "размер, присвоенный %qT, может быть несовместим с ABI и может быть изменен в будущих версиях GCC" - --#: cp/class.c:5926 -+#: cp/class.c:5929 - #, gcc-internal-format - msgid "the offset of %qD may not be ABI-compliant and may change in a future version of GCC" - msgstr "смещение %qD может быть несовместимо с ABI и может быть изменено в будущих версиях GCC" - --#: cp/class.c:5954 -+#: cp/class.c:5957 - #, gcc-internal-format - msgid "offset of %q+D is not ABI-compliant and may change in a future version of GCC" - msgstr "смещение %q+D несовместимо с ABI и может измениться в будущих версиях GCC" - --#: cp/class.c:5964 -+#: cp/class.c:5967 - #, gcc-internal-format - msgid "%q+D contains empty classes which may cause base classes to be placed at different locations in a future version of GCC" - msgstr "%q+D содержит пустые классы; поэтому базовые классы могут размещены иначе в будущих версиях GCC" - --#: cp/class.c:6052 -+#: cp/class.c:6055 - #, gcc-internal-format - msgid "layout of classes derived from empty class %qT may change in a future version of GCC" - msgstr "представление классов, производных от пустого класса %qT, может измениться в будущих версиях GCC" - --#: cp/class.c:6220 cp/decl.c:12134 cp/parser.c:18856 -+#: cp/class.c:6223 cp/decl.c:12125 cp/parser.c:18860 - #, gcc-internal-format - msgid "redefinition of %q#T" - msgstr "повторное определение %q#T" - --#: cp/class.c:6369 -+#: cp/class.c:6372 - #, gcc-internal-format - msgid "%q#T has virtual functions and accessible non-virtual destructor" - msgstr "%q#T содержит виртуальные функции, но невиртуальный деструктор" - --#: cp/class.c:6395 -+#: cp/class.c:6398 - #, fuzzy, gcc-internal-format --#| msgid "type transparent class %qT does not have any fields" - msgid "type transparent %q#T does not have any fields" - msgstr "в типе прозрачного класса %qT нет никаких полей" - --#: cp/class.c:6401 -+#: cp/class.c:6404 - #, gcc-internal-format - msgid "type transparent class %qT has base classes" - msgstr "" - --#: cp/class.c:6405 -+#: cp/class.c:6408 - #, gcc-internal-format - msgid "type transparent class %qT has virtual functions" - msgstr "в типе прозрачного класса %qT есть виртуальные функции" - --#: cp/class.c:6411 -+#: cp/class.c:6414 - #, gcc-internal-format - msgid "type transparent %q#T cannot be made transparent because the type of the first field has a different ABI from the class overall" - msgstr "" - --#: cp/class.c:6562 -+#: cp/class.c:6565 - #, gcc-internal-format - msgid "trying to finish struct, but kicked out due to previous parse errors" - msgstr "не удалось завершить структуру из-за предыдущих грамматических ошибок" - --#: cp/class.c:7071 -+#: cp/class.c:7074 - #, gcc-internal-format - msgid "language string %<\"%E\"%> not recognized" - msgstr "некорректная строка %<\"%E\"%>, задающая язык" - --#: cp/class.c:7160 -+#: cp/class.c:7163 - #, gcc-internal-format - msgid "cannot resolve overloaded function %qD based on conversion to type %qT" - msgstr "ошибка при выборе перегруженной функции %qD при преобразовании к типу %qT" - --#: cp/class.c:7280 -+#: cp/class.c:7283 - #, gcc-internal-format - msgid "no matches converting function %qD to type %q#T" - msgstr "нет способа для преобразования функции %qD к типу %q#T" - --#: cp/class.c:7308 -+#: cp/class.c:7311 - #, gcc-internal-format - msgid "converting overloaded function %qD to type %q#T is ambiguous" - msgstr "преобразование перегруженной функции %qD к типу %q#T неоднозначно" - --#: cp/class.c:7335 -+#: cp/class.c:7338 - #, gcc-internal-format - msgid "assuming pointer to member %qD" - msgstr "предполагается указатель на элемент %qD" - --#: cp/class.c:7338 -+#: cp/class.c:7341 - #, gcc-internal-format - msgid "(a pointer to member can only be formed with %<&%E%>)" - msgstr "(указатель на элемент можно получить только при помощи %<&%E%>)" - --#: cp/class.c:7413 cp/class.c:7447 -+#: cp/class.c:7416 cp/class.c:7450 - #, gcc-internal-format - msgid "not enough type information" - msgstr "недостаточная информация о типе" - --#: cp/class.c:7430 cp/cvt.c:173 cp/cvt.c:199 cp/cvt.c:248 -+#: cp/class.c:7433 cp/cvt.c:173 cp/cvt.c:199 cp/cvt.c:248 - #, gcc-internal-format - msgid "cannot convert %qE from type %qT to type %qT" - msgstr "ошибка преобразования %qE из типа %qT в тип %qT" -@@ -28787,12 +28723,12 @@ - #. A name N used in a class S shall refer to the same declaration - #. in its context and when re-evaluated in the completed scope of - #. S. --#: cp/class.c:7742 cp/decl.c:1325 -+#: cp/class.c:7745 cp/decl.c:1325 - #, gcc-internal-format - msgid "declaration of %q#D" - msgstr "декларация %q#D" - --#: cp/class.c:7743 -+#: cp/class.c:7746 - #, gcc-internal-format - msgid "changes meaning of %qD from %q+#D" - msgstr "делает трактовку %qD отличной от %q+#D" -@@ -29919,233 +29855,233 @@ - msgid "function %q#D is initialized like a variable" - msgstr "функция %q#D инициализирована как переменная" - --#: cp/decl.c:6883 -+#: cp/decl.c:6886 - #, gcc-internal-format - msgid "non-local variable %qD declared %<__thread%> needs dynamic initialization" - msgstr "" - --#: cp/decl.c:6886 -+#: cp/decl.c:6889 - #, fuzzy, gcc-internal-format - msgid "non-local variable %qD declared %<__thread%> has a non-trivial destructor" - msgstr "базовый класс %q#T имеет невиртуальный деструктор" - --#: cp/decl.c:6892 -+#: cp/decl.c:6895 - #, gcc-internal-format - msgid "C++11 % allows dynamic initialization and destruction" - msgstr "" - --#: cp/decl.c:7119 -+#: cp/decl.c:7122 - #, fuzzy, gcc-internal-format - msgid "initializer fails to determine size of %qT" - msgstr "при инициализации не удалось определить размер %qD" - --#: cp/decl.c:7123 -+#: cp/decl.c:7126 - #, fuzzy, gcc-internal-format - msgid "array size missing in %qT" - msgstr "не задан размер массива для %qD" - --#: cp/decl.c:7126 -+#: cp/decl.c:7129 - #, fuzzy, gcc-internal-format - msgid "zero-size array %qT" - msgstr "массив %qD имеет нулевой размер" - --#: cp/decl.c:7142 -+#: cp/decl.c:7145 - #, gcc-internal-format - msgid "destructor for alien class %qT cannot be a member" - msgstr "деструктор чужого класса %qT не может быть элементом" - --#: cp/decl.c:7144 -+#: cp/decl.c:7147 - #, gcc-internal-format - msgid "constructor for alien class %qT cannot be a member" - msgstr "конструктор чужого класса %qT не может быть элементом" - --#: cp/decl.c:7168 -+#: cp/decl.c:7171 - #, fuzzy, gcc-internal-format - msgid "%qD declared as a % variable" - msgstr "%qD декларирован как % %s" - --#: cp/decl.c:7170 -+#: cp/decl.c:7173 - #, fuzzy, gcc-internal-format - msgid "%qD declared as an % variable" - msgstr "%qD декларирован как % %s" - --#: cp/decl.c:7172 -+#: cp/decl.c:7175 - #, fuzzy, gcc-internal-format - msgid "% and % function specifiers on %qD invalid in variable declaration" - msgstr "спецификаторы % и % для функции %qD некорректны в декларации %s" - --#: cp/decl.c:7177 -+#: cp/decl.c:7180 - #, fuzzy, gcc-internal-format - msgid "%qD declared as a % parameter" - msgstr "%qD декларирован как % %s" - --#: cp/decl.c:7179 -+#: cp/decl.c:7182 - #, fuzzy, gcc-internal-format - msgid "%qD declared as an % parameter" - msgstr "%qD декларирован как % %s" - --#: cp/decl.c:7181 -+#: cp/decl.c:7184 - #, fuzzy, gcc-internal-format - msgid "% and % function specifiers on %qD invalid in parameter declaration" - msgstr "спецификаторы % и % для функции %qD некорректны в декларации %s" - --#: cp/decl.c:7186 -+#: cp/decl.c:7189 - #, fuzzy, gcc-internal-format - msgid "%qD declared as a % type" - msgstr "%qD декларирован как % %s" - --#: cp/decl.c:7188 -+#: cp/decl.c:7191 - #, fuzzy, gcc-internal-format - msgid "%qD declared as an % type" - msgstr "%qD декларирован как % %s" - --#: cp/decl.c:7190 -+#: cp/decl.c:7193 - #, fuzzy, gcc-internal-format - msgid "% and % function specifiers on %qD invalid in type declaration" - msgstr "спецификаторы % и % для функции %qD некорректны в декларации %s" - --#: cp/decl.c:7195 -+#: cp/decl.c:7198 - #, fuzzy, gcc-internal-format - msgid "%qD declared as a % field" - msgstr "%qD декларирован как % %s" - --#: cp/decl.c:7197 -+#: cp/decl.c:7200 - #, fuzzy, gcc-internal-format - msgid "%qD declared as an % field" - msgstr "%qD декларирован как % %s" - --#: cp/decl.c:7199 -+#: cp/decl.c:7202 - #, fuzzy, gcc-internal-format - msgid "% and % function specifiers on %qD invalid in field declaration" - msgstr "спецификаторы % и % для функции %qD некорректны в декларации %s" - --#: cp/decl.c:7206 -+#: cp/decl.c:7209 - #, gcc-internal-format - msgid "%q+D declared as a friend" - msgstr "%q+D декларировано как friend" - --#: cp/decl.c:7212 -+#: cp/decl.c:7215 - #, gcc-internal-format - msgid "%q+D declared with an exception specification" - msgstr "%q+D декларировано со спецификацией исключительной ситуации" - --#: cp/decl.c:7246 -+#: cp/decl.c:7249 - #, gcc-internal-format - msgid "definition of %qD is not in namespace enclosing %qT" - msgstr "определение %qD вне пространства имён, объемлющего %qT" - --#: cp/decl.c:7286 -+#: cp/decl.c:7289 - #, gcc-internal-format - msgid "static member function %q#D declared with type qualifiers" - msgstr "статическая функция-член %q#D объявлена с квалификаторами типа" - --#: cp/decl.c:7385 -+#: cp/decl.c:7388 - #, gcc-internal-format - msgid "defining explicit specialization %qD in friend declaration" - msgstr "определение явной специализации %qD в friend-декларации" - - #. Something like `template friend void f()'. --#: cp/decl.c:7395 -+#: cp/decl.c:7398 - #, gcc-internal-format - msgid "invalid use of template-id %qD in declaration of primary template" - msgstr "некорректное использование идентификатора шаблона %qD в декларации первичного шаблона" - --#: cp/decl.c:7425 -+#: cp/decl.c:7428 - #, gcc-internal-format - msgid "default arguments are not allowed in declaration of friend template specialization %qD" - msgstr "аргументы по умолчанию не допускаются в декларации специализации friend-шаблона %qD" - --#: cp/decl.c:7433 -+#: cp/decl.c:7436 - #, gcc-internal-format - msgid "% is not allowed in declaration of friend template specialization %qD" - msgstr "не допускается использовать % в декларации специализации friend-шаблона %qD" - --#: cp/decl.c:7475 -+#: cp/decl.c:7478 - #, gcc-internal-format - msgid "cannot declare %<::main%> to be a template" - msgstr "недопустимая декларация %<::main%> как шаблона" - --#: cp/decl.c:7477 -+#: cp/decl.c:7480 - #, gcc-internal-format - msgid "cannot declare %<::main%> to be inline" - msgstr "недопустимая декларация %<::main%> как inline-функции" - --#: cp/decl.c:7479 -+#: cp/decl.c:7482 - #, gcc-internal-format - msgid "cannot declare %<::main%> to be static" - msgstr "недопустимая декларация %<::main%> как статической функции" - --#: cp/decl.c:7507 -+#: cp/decl.c:7510 - #, gcc-internal-format - msgid "anonymous type with no linkage used to declare function %q#D with linkage" - msgstr "" - --#: cp/decl.c:7511 cp/decl.c:7879 cp/decl2.c:3864 -+#: cp/decl.c:7514 cp/decl.c:7882 cp/decl2.c:3864 - #, gcc-internal-format - msgid "%q+#D does not refer to the unqualified type, so it is not used for linkage" - msgstr "%q+#D не ссылается на неквалифицированный тип, поэтому не используется для связывания" - --#: cp/decl.c:7517 -+#: cp/decl.c:7520 - #, fuzzy, gcc-internal-format - msgid "type %qT with no linkage used to declare function %q#D with linkage" - msgstr "предыдущая декларация `%#D' с привязкой %L" - --#: cp/decl.c:7539 -+#: cp/decl.c:7542 - #, fuzzy, gcc-internal-format - msgid "static member function %qD cannot have cv-qualifier" - msgstr "%sэлемент, функция %qD, не может иметь квалификатор метода - %qT" - --#: cp/decl.c:7540 -+#: cp/decl.c:7543 - #, gcc-internal-format - msgid "non-member function %qD cannot have cv-qualifier" - msgstr "" - --#: cp/decl.c:7556 -+#: cp/decl.c:7559 - #, fuzzy, gcc-internal-format - msgid "literal operator with C linkage" - msgstr "шаблон с привязкой C" - --#: cp/decl.c:7565 -+#: cp/decl.c:7568 - #, fuzzy, gcc-internal-format - msgid "%qD has invalid argument list" - msgstr "некорректный аргумент внутренней функции" - --#: cp/decl.c:7573 -+#: cp/decl.c:7576 - #, gcc-internal-format - msgid "integer suffix %<%s%> shadowed by implementation" - msgstr "" - --#: cp/decl.c:7579 -+#: cp/decl.c:7582 - #, gcc-internal-format - msgid "floating point suffix %<%s%> shadowed by implementation" - msgstr "" - --#: cp/decl.c:7585 -+#: cp/decl.c:7588 - #, fuzzy, gcc-internal-format - msgid "%qD must be a non-member function" - msgstr "%qD должен быть нестатической элементом-функцией" - --#: cp/decl.c:7636 -+#: cp/decl.c:7639 - #, gcc-internal-format - msgid "%<::main%> must return %" - msgstr "%<::main%> должна возвращать %" - --#: cp/decl.c:7678 -+#: cp/decl.c:7681 - #, gcc-internal-format - msgid "definition of implicitly-declared %qD" - msgstr "определение неявно декларированного %qD" - --#: cp/decl.c:7683 -+#: cp/decl.c:7686 - #, fuzzy, gcc-internal-format - msgid "definition of explicitly-defaulted %q+D" - msgstr "определение неявно декларированного %qD" - --#: cp/decl.c:7684 -+#: cp/decl.c:7687 - #, fuzzy, gcc-internal-format - msgid "%q+#D explicitly defaulted here" - msgstr "это предыдущее определение `%#D'" - --#: cp/decl.c:7701 cp/decl2.c:738 -+#: cp/decl.c:7704 cp/decl2.c:738 - #, gcc-internal-format - msgid "no %q#D member function declared in class %qT" - msgstr "нет элемента-функции %q#D в классе %qT" -@@ -30154,886 +30090,879 @@ - #. no linkage can only be used to declare extern "C" - #. entities. Since it's not always an error in the - #. ISO C++ 90 Standard, we only issue a warning. --#: cp/decl.c:7876 -+#: cp/decl.c:7879 - #, gcc-internal-format - msgid "anonymous type with no linkage used to declare variable %q#D with linkage" - msgstr "" - --#: cp/decl.c:7885 -+#: cp/decl.c:7888 - #, gcc-internal-format - msgid "type %qT with no linkage used to declare variable %q#D with linkage" - msgstr "" - --#: cp/decl.c:8008 -+#: cp/decl.c:8011 - #, fuzzy, gcc-internal-format - msgid "in-class initialization of static data member %q#D of incomplete type" - msgstr "некорректная инициализация внутри класса статического элемента данных нецелочисленного типа %qT" - --#: cp/decl.c:8012 -+#: cp/decl.c:8015 - #, fuzzy, gcc-internal-format - msgid "% needed for in-class initialization of static data member %q#D of non-integral type" - msgstr "некорректная инициализация внутри класса статического элемента данных нецелочисленного типа %qT" - --#: cp/decl.c:8015 -+#: cp/decl.c:8018 - #, fuzzy, gcc-internal-format - msgid "in-class initialization of static data member %q#D of non-literal type" - msgstr "некорректная инициализация внутри класса статического элемента данных нецелочисленного типа %qT" - --#: cp/decl.c:8028 -+#: cp/decl.c:8031 - #, gcc-internal-format - msgid "invalid in-class initialization of static data member of non-integral type %qT" - msgstr "некорректная инициализация внутри класса статического элемента данных нецелочисленного типа %qT" - --#: cp/decl.c:8034 -+#: cp/decl.c:8037 - #, gcc-internal-format - msgid "ISO C++ forbids in-class initialization of non-const static member %qD" - msgstr "ISO C++ запрещает инициализацию внутри класса неконстантного статического элемента %qD" - --#: cp/decl.c:8038 -+#: cp/decl.c:8041 - #, gcc-internal-format - msgid "ISO C++ forbids initialization of member constant %qD of non-integral type %qT" - msgstr "ISO C++ запрещает инициализацию элемента-константы %qD нецелочисленного типа %qT" - --#: cp/decl.c:8144 cp/decl.c:8172 -+#: cp/decl.c:8147 cp/decl.c:8175 - #, gcc-internal-format - msgid "size of array %qD has non-integral type %qT" - msgstr "размер массива %qD имеет нецелочисленный тип %qT" - --#: cp/decl.c:8147 cp/decl.c:8174 -+#: cp/decl.c:8150 cp/decl.c:8177 - #, gcc-internal-format - msgid "size of array has non-integral type %qT" - msgstr "размер массива имеет нецелочисленный тип %qT" - --#: cp/decl.c:8224 -+#: cp/decl.c:8227 - #, gcc-internal-format - msgid "size of array %qD is negative" - msgstr "размер массива %qD отрицательный" - --#: cp/decl.c:8226 -+#: cp/decl.c:8229 - #, gcc-internal-format - msgid "size of array is negative" - msgstr "размер массива отрицательный" - --#: cp/decl.c:8240 -+#: cp/decl.c:8243 - #, gcc-internal-format - msgid "ISO C++ forbids zero-size array %qD" - msgstr "ISO C++ запрещает массив нулевого размера %qD" - --#: cp/decl.c:8242 -+#: cp/decl.c:8245 - #, gcc-internal-format - msgid "ISO C++ forbids zero-size array" - msgstr "ISO C++ запрещает массивы нулевого размера" - --#: cp/decl.c:8254 -+#: cp/decl.c:8257 - #, gcc-internal-format - msgid "size of array %qD is not an integral constant-expression" - msgstr "размер массива %qD не является целочисленным константным выражением" - --#: cp/decl.c:8257 -+#: cp/decl.c:8260 - #, gcc-internal-format - msgid "size of array is not an integral constant-expression" - msgstr "размер массива не является целочисленным константным выражением" - --#: cp/decl.c:8263 -+#: cp/decl.c:8266 - #, gcc-internal-format - msgid "ISO C++ forbids variable length array %qD" - msgstr "ISO C++ запрещает массив переменного размера %qD" - --#: cp/decl.c:8265 -+#: cp/decl.c:8268 - #, gcc-internal-format - msgid "ISO C++ forbids variable length array" - msgstr "ISO C++ запрещает массивы переменного размера" - --#: cp/decl.c:8271 -+#: cp/decl.c:8274 - #, gcc-internal-format - msgid "variable length array %qD is used" - msgstr "используется массив переменного размера %qD" - --#: cp/decl.c:8323 -+#: cp/decl.c:8326 - #, gcc-internal-format - msgid "overflow in array dimension" - msgstr "переполнение в размерности массива" - --#: cp/decl.c:8383 -+#: cp/decl.c:8386 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as array of %" - msgstr "имя %qs описано как массив элементов типа void" - --#: cp/decl.c:8391 -+#: cp/decl.c:8394 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as array of void" - msgstr "имя %qs описано как массив элементов типа void" - --#: cp/decl.c:8393 -+#: cp/decl.c:8396 - #, fuzzy, gcc-internal-format - msgid "creating array of void" - msgstr "создание массива элементов типа %qT" - --#: cp/decl.c:8398 -+#: cp/decl.c:8401 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as array of functions" - msgstr "имя %qs описано как массив функций" - --#: cp/decl.c:8400 -+#: cp/decl.c:8403 - #, fuzzy, gcc-internal-format - msgid "creating array of functions" - msgstr "создание массива элементов типа %qT" - --#: cp/decl.c:8405 -+#: cp/decl.c:8408 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as array of references" - msgstr "имя %qs описано как массив функций" - --#: cp/decl.c:8407 -+#: cp/decl.c:8410 - #, fuzzy, gcc-internal-format - msgid "creating array of references" - msgstr "создание массива элементов типа %qT" - --#: cp/decl.c:8412 -+#: cp/decl.c:8415 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as array of function members" - msgstr "имя %qs описано как массив функций" - --#: cp/decl.c:8414 -+#: cp/decl.c:8417 - #, fuzzy, gcc-internal-format - msgid "creating array of function members" - msgstr "имя %qs описано как массив функций" - --#: cp/decl.c:8428 -+#: cp/decl.c:8431 - #, gcc-internal-format - msgid "declaration of %qD as multidimensional array must have bounds for all dimensions except the first" - msgstr "декларация многомерного массива %qD должна определять границы для всех размерностей, кроме первой" - --#: cp/decl.c:8432 -+#: cp/decl.c:8435 - #, gcc-internal-format - msgid "multidimensional array must have bounds for all dimensions except the first" - msgstr "в многомерном массиве должны быть определены границы для всех размерностей, кроме первой" - --#: cp/decl.c:8467 -+#: cp/decl.c:8470 - #, gcc-internal-format - msgid "return type specification for constructor invalid" - msgstr "некорректная спецификация возвращаемого типа в конструкторе" - --#: cp/decl.c:8477 -+#: cp/decl.c:8480 - #, gcc-internal-format - msgid "return type specification for destructor invalid" - msgstr "некорректная спецификация возвращаемого типа в деструкторе" - --#: cp/decl.c:8490 -+#: cp/decl.c:8493 - #, gcc-internal-format - msgid "return type specified for %" - msgstr "тип результата задан для %" - --#: cp/decl.c:8512 -+#: cp/decl.c:8515 - #, gcc-internal-format - msgid "unnamed variable or field declared void" - msgstr "декларация безымянной переменной или поля с типом void" - --#: cp/decl.c:8519 -+#: cp/decl.c:8522 - #, gcc-internal-format - msgid "variable or field declared void" - msgstr "декларация переменной или поля с типом void" - --#: cp/decl.c:8720 -+#: cp/decl.c:8722 - #, gcc-internal-format - msgid "invalid use of qualified-name %<::%D%>" - msgstr "недопустимое использование квалифицированного имени %<::%D%>" - --#: cp/decl.c:8723 -+#: cp/decl.c:8725 - #, gcc-internal-format - msgid "invalid use of qualified-name %<%T::%D%>" - msgstr "недопустимое использование квалифицированного имени %<%T::%D%>" - --#: cp/decl.c:8726 -+#: cp/decl.c:8728 - #, gcc-internal-format - msgid "invalid use of qualified-name %<%D::%D%>" - msgstr "недопустимое использование квалифицированного имени %<%D::%D%>" - --#: cp/decl.c:8735 -+#: cp/decl.c:8737 - #, fuzzy, gcc-internal-format - msgid "%q#T is not a class or a namespace" - msgstr "%qT не является классом или пространством имён" - --#: cp/decl.c:8743 -+#: cp/decl.c:8745 - #, gcc-internal-format - msgid "type %qT is not derived from type %qT" - msgstr "тип %qT не является производным от %qT" - --#: cp/decl.c:8759 cp/decl.c:8851 cp/decl.c:8860 cp/decl.c:10242 -+#: cp/decl.c:8761 cp/decl.c:8853 cp/decl.c:8862 cp/decl.c:10238 - #, gcc-internal-format - msgid "declaration of %qD as non-function" - msgstr "декларация %qD как не-функции" - --#: cp/decl.c:8765 -+#: cp/decl.c:8767 - #, gcc-internal-format - msgid "declaration of %qD as non-member" - msgstr "декларация %qD как не-элемента" - --#: cp/decl.c:8796 -+#: cp/decl.c:8798 - #, gcc-internal-format - msgid "declarator-id missing; using reserved word %qD" - msgstr "декларатор отсутствует; используется зарезервированное слово %qD" - --#: cp/decl.c:8843 -+#: cp/decl.c:8845 - #, gcc-internal-format - msgid "function definition does not declare parameters" - msgstr "определение функции не объявляет параметры" - --#: cp/decl.c:8868 -+#: cp/decl.c:8870 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as %" - msgstr "шаблонная декларация `%#D'" - --#: cp/decl.c:8873 -+#: cp/decl.c:8875 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as parameter" - msgstr "декларация %q+D перекрывает параметр" - --#: cp/decl.c:8906 -+#: cp/decl.c:8908 - #, fuzzy, gcc-internal-format - msgid "% cannot appear in a typedef declaration" - msgstr "идентификатор шаблона недопустим в using-декларации" - --#: cp/decl.c:8914 -+#: cp/decl.c:8916 - #, gcc-internal-format - msgid "two or more data types in declaration of %qs" - msgstr "два или более типа в декларации имени %qs" - --#: cp/decl.c:8920 -+#: cp/decl.c:8922 - #, gcc-internal-format - msgid "conflicting specifiers in declaration of %qs" - msgstr "конфликтующие спецификаторы в декларации %qs" - --#: cp/decl.c:8992 cp/decl.c:8995 cp/decl.c:8998 -+#: cp/decl.c:8994 cp/decl.c:8997 cp/decl.c:9000 - #, gcc-internal-format - msgid "ISO C++ forbids declaration of %qs with no type" - msgstr "ISO C++ запрещает декларации %qs без типа" - --#: cp/decl.c:9009 -+#: cp/decl.c:9011 - #, fuzzy, gcc-internal-format - msgid "%<__int128%> is not supported by this target" - msgstr "__builtin_saveregs не поддерживается для этой целевой платформы" - --#: cp/decl.c:9014 -+#: cp/decl.c:9016 - #, fuzzy, gcc-internal-format - msgid "ISO C++ does not support %<__int128%> for %qs" - msgstr "ISO C++ не поддерживает %" - --#: cp/decl.c:9035 cp/decl.c:9055 -+#: cp/decl.c:9037 cp/decl.c:9057 - #, gcc-internal-format - msgid "% or % invalid for %qs" - msgstr "% или % некорректны для %qs" - --#: cp/decl.c:9037 -+#: cp/decl.c:9039 - #, gcc-internal-format - msgid "% and % specified together for %qs" - msgstr "% и % одновременно заданы для %qs" - --#: cp/decl.c:9039 -+#: cp/decl.c:9041 - #, gcc-internal-format - msgid "% invalid for %qs" - msgstr "недопустимо использовать % для %qs" - --#: cp/decl.c:9041 -+#: cp/decl.c:9043 - #, gcc-internal-format - msgid "% invalid for %qs" - msgstr "недопустимо использовать % для %qs" - --#: cp/decl.c:9043 -+#: cp/decl.c:9045 - #, gcc-internal-format - msgid "% invalid for %qs" - msgstr "недопустимо использовать % для %qs" - --#: cp/decl.c:9045 -+#: cp/decl.c:9047 - #, gcc-internal-format - msgid "% or % invalid for %qs" - msgstr "% или % некорректны для %qs" - --#: cp/decl.c:9047 -+#: cp/decl.c:9049 - #, fuzzy, gcc-internal-format - msgid "%, %, %, or % invalid for %qs" - msgstr "% или % некорректны для %qs" - --#: cp/decl.c:9049 -+#: cp/decl.c:9051 - #, gcc-internal-format - msgid "% or % specified with char for %qs" - msgstr "% или % заданы в описании %qs с типом char" - --#: cp/decl.c:9051 -+#: cp/decl.c:9053 - #, gcc-internal-format - msgid "% and % specified together for %qs" - msgstr "% и % одновременно заданы для %qs" - --#: cp/decl.c:9057 -+#: cp/decl.c:9059 - #, fuzzy, gcc-internal-format - msgid "% or % invalid for %qs" - msgstr "% или % некорректны для %qs" - --#: cp/decl.c:9065 -+#: cp/decl.c:9067 - #, gcc-internal-format - msgid "long, short, signed or unsigned used invalidly for %qs" - msgstr "неверное употребление long, short, signed или unsigned в описании %s" - --#: cp/decl.c:9133 -+#: cp/decl.c:9135 - #, gcc-internal-format - msgid "complex invalid for %qs" - msgstr "спецификатор complex для %qs недопустим" - --#: cp/decl.c:9161 -+#: cp/decl.c:9163 - #, gcc-internal-format - msgid "qualifiers are not allowed on declaration of %" - msgstr "квалификаторы не допускаются в декларации %" - --#: cp/decl.c:9193 -+#: cp/decl.c:9195 - #, gcc-internal-format - msgid "member %qD cannot be declared both virtual and static" - msgstr "элемент %qD не может быть декларирован как virtual и static" - --#: cp/decl.c:9201 -+#: cp/decl.c:9206 - #, gcc-internal-format --msgid "%<%T::%D%> is not a valid declarator" --msgstr "%<%T::%D%> не является корректным декларатором" -- --#: cp/decl.c:9210 --#, gcc-internal-format - msgid "typedef declaration invalid in parameter declaration" - msgstr "typedef-декларация не допускается в декларации параметров" - --#: cp/decl.c:9215 -+#: cp/decl.c:9211 - #, fuzzy, gcc-internal-format - msgid "storage class specified for template parameter %qs" - msgstr "класс хранения в декларации параметра %qs" - --#: cp/decl.c:9221 -+#: cp/decl.c:9217 - #, gcc-internal-format - msgid "storage class specifiers invalid in parameter declarations" - msgstr "спецификаторы класса хранения не допускаются в декларациях параметров" - --#: cp/decl.c:9227 -+#: cp/decl.c:9223 - #, fuzzy, gcc-internal-format - msgid "a parameter cannot be declared %" - msgstr "недопустимая декларация не-элемента %qs как %" - --#: cp/decl.c:9236 -+#: cp/decl.c:9232 - #, fuzzy, gcc-internal-format - msgid "% outside class declaration" - msgstr "virtual вне декларации класса" - --#: cp/decl.c:9254 -+#: cp/decl.c:9250 - #, gcc-internal-format - msgid "multiple storage classes in declaration of %qs" - msgstr "в декларации %qs задано более одного класса хранения" - --#: cp/decl.c:9277 -+#: cp/decl.c:9273 - #, gcc-internal-format - msgid "storage class specified for %qs" - msgstr "для %qs задан класс хранения" - --#: cp/decl.c:9281 -+#: cp/decl.c:9277 - #, gcc-internal-format - msgid "storage class specified for parameter %qs" - msgstr "класс хранения в декларации параметра %qs" - --#: cp/decl.c:9294 -+#: cp/decl.c:9290 - #, gcc-internal-format - msgid "nested function %qs declared %" - msgstr "вложенная функция %qs объявлена %" - --#: cp/decl.c:9298 -+#: cp/decl.c:9294 - #, gcc-internal-format - msgid "top-level declaration of %qs specifies %" - msgstr "имя %qs описано на верхнем уровне с классом хранения %" - --#: cp/decl.c:9305 -+#: cp/decl.c:9301 - #, gcc-internal-format - msgid "function-scope %qs implicitly auto and declared %<__thread%>" - msgstr "имя %qs на уровне функции неявно имеет класс auto и объявлено %<__thread%>" - --#: cp/decl.c:9317 -+#: cp/decl.c:9313 - #, gcc-internal-format - msgid "storage class specifiers invalid in friend function declarations" - msgstr "класс хранения не допускается в декларации friend-функции" - --#: cp/decl.c:9427 -+#: cp/decl.c:9423 - #, gcc-internal-format - msgid "%qs declared as function returning a function" - msgstr "%qs объявлена как функция, возвращающая функцию" - --#: cp/decl.c:9432 -+#: cp/decl.c:9428 - #, gcc-internal-format - msgid "%qs declared as function returning an array" - msgstr "%qs объявлена как функция, возвращающая массив" - --#: cp/decl.c:9438 -+#: cp/decl.c:9434 - #, fuzzy, gcc-internal-format --#| msgid "%qs declared as function returning an array" - msgid "%qs declared as function returning an abstract class type" - msgstr "%qs объявлена как функция, возвращающая массив" - --#: cp/decl.c:9467 -+#: cp/decl.c:9463 - #, gcc-internal-format - msgid "%qs function uses % type specifier without trailing return type" - msgstr "" - --#: cp/decl.c:9473 -+#: cp/decl.c:9469 - #, gcc-internal-format - msgid "%qs function with trailing return type has %qT as its type rather than plain %" - msgstr "" - - #. Not using maybe_warn_cpp0x because this should - #. always be an error. --#: cp/decl.c:9484 -+#: cp/decl.c:9480 - #, gcc-internal-format - msgid "trailing return type only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/decl.c:9487 -+#: cp/decl.c:9483 - #, gcc-internal-format - msgid "%qs function with trailing return type not declared with % type specifier" - msgstr "" - --#: cp/decl.c:9520 -+#: cp/decl.c:9516 - #, gcc-internal-format - msgid "destructor cannot be static member function" - msgstr "деструктор не может быть статической элементом-функцией" - --#: cp/decl.c:9521 -+#: cp/decl.c:9517 - #, fuzzy, gcc-internal-format - msgid "constructor cannot be static member function" - msgstr "деструктор не может быть статической элементом-функцией" - --#: cp/decl.c:9525 -+#: cp/decl.c:9521 - #, gcc-internal-format - msgid "destructors may not be cv-qualified" - msgstr "деструкторы не могут быть cv-квалифицированы" - --#: cp/decl.c:9526 -+#: cp/decl.c:9522 - #, fuzzy, gcc-internal-format - msgid "constructors may not be cv-qualified" - msgstr "деструкторы не могут быть cv-квалифицированы" - --#: cp/decl.c:9543 -+#: cp/decl.c:9539 - #, gcc-internal-format - msgid "constructors cannot be declared virtual" - msgstr "конструкторы нельзя декларировать как virtual" - --#: cp/decl.c:9556 -+#: cp/decl.c:9552 - #, fuzzy, gcc-internal-format - msgid "can%'t initialize friend function %qs" - msgstr "недопустимая инициализация friend-функции %qs" - - #. Cannot be both friend and virtual. --#: cp/decl.c:9560 -+#: cp/decl.c:9556 - #, gcc-internal-format - msgid "virtual functions cannot be friends" - msgstr "виртуальные функции не могут быть friend-функциями" - --#: cp/decl.c:9564 -+#: cp/decl.c:9560 - #, gcc-internal-format - msgid "friend declaration not in class definition" - msgstr "friend-декларация вне определения класса" - --#: cp/decl.c:9566 -+#: cp/decl.c:9562 - #, fuzzy, gcc-internal-format - msgid "can%'t define friend function %qs in a local class definition" - msgstr "недопустимое определение friend-функции %qs в определении локального класса" - --#: cp/decl.c:9587 -+#: cp/decl.c:9583 - #, gcc-internal-format - msgid "destructors may not have parameters" - msgstr "деструкторы не могут иметь параметров" - --#: cp/decl.c:9613 -+#: cp/decl.c:9609 - #, gcc-internal-format - msgid "cannot declare pointer to %q#T" - msgstr "недопустимая декларация указателя на %q#T" - --#: cp/decl.c:9626 cp/decl.c:9633 -+#: cp/decl.c:9622 cp/decl.c:9629 - #, gcc-internal-format - msgid "cannot declare reference to %q#T" - msgstr "недопустимая декларация ссылки на %q#T" - --#: cp/decl.c:9635 -+#: cp/decl.c:9631 - #, gcc-internal-format - msgid "cannot declare pointer to %q#T member" - msgstr "недопустимая декларация указателя на элемент %q#T" - --#: cp/decl.c:9658 -+#: cp/decl.c:9654 - #, fuzzy, gcc-internal-format - msgid "cannot declare reference to qualified function type %qT" - msgstr "недопустимая декларация ссылки на %q#T" - --#: cp/decl.c:9659 -+#: cp/decl.c:9655 - #, fuzzy, gcc-internal-format - msgid "cannot declare pointer to qualified function type %qT" - msgstr "нельзя %s указатель на неполный тип %qT" - --#: cp/decl.c:9733 -+#: cp/decl.c:9729 - #, gcc-internal-format - msgid "cannot declare reference to %q#T, which is not a typedef or a template type argument" - msgstr "Недопустимо определять ссылку на %q#T, которая не будет определением типа или аргументом шаблона" - --#: cp/decl.c:9797 -+#: cp/decl.c:9793 - #, fuzzy, gcc-internal-format - msgid "both % and % cannot be used here" - msgstr "в декларации использованы спецификаторы % и %" - --#: cp/decl.c:9809 -+#: cp/decl.c:9805 - #, gcc-internal-format - msgid "template-id %qD used as a declarator" - msgstr "идентификатор шаблона %qD использован как декларатор" - --#: cp/decl.c:9833 -+#: cp/decl.c:9829 - #, gcc-internal-format - msgid "member functions are implicitly friends of their class" - msgstr "элементы-функции неявно считаются friend-функциями своего класса" - --#: cp/decl.c:9838 -+#: cp/decl.c:9834 - #, gcc-internal-format - msgid "extra qualification %<%T::%> on member %qs" - msgstr "избыточная квалификация %<%T::%> элемента %qs" - --#: cp/decl.c:9868 -+#: cp/decl.c:9864 - #, gcc-internal-format - msgid "cannot define member function %<%T::%s%> within %<%T%>" - msgstr "недопустимая декларация элемента-функции %<%T::%s%> внутри %<%T%>" - --#: cp/decl.c:9870 -+#: cp/decl.c:9866 - #, fuzzy, gcc-internal-format - msgid "cannot declare member function %<%T::%s%> within %<%T%>" - msgstr "недопустимая декларация элемента-функции %<%T::%s%> внутри %<%T%>" - --#: cp/decl.c:9879 -+#: cp/decl.c:9875 - #, gcc-internal-format - msgid "cannot declare member %<%T::%s%> within %qT" - msgstr "недопустимая декларация элемента %<%T::%s%> внутри %qT" - --#: cp/decl.c:9912 -+#: cp/decl.c:9908 - #, gcc-internal-format - msgid "non-parameter %qs cannot be a parameter pack" - msgstr "не параметрический %qs не может содержать параметры" - --#: cp/decl.c:9922 -+#: cp/decl.c:9918 - #, gcc-internal-format - msgid "size of array %qs is too large" - msgstr "размер массива %qs слишком велик" - --#: cp/decl.c:9933 -+#: cp/decl.c:9929 - #, gcc-internal-format - msgid "data member may not have variably modified type %qT" - msgstr "элемент данных не может иметь тип %qT модифицируемого размера" - --#: cp/decl.c:9935 -+#: cp/decl.c:9931 - #, gcc-internal-format - msgid "parameter may not have variably modified type %qT" - msgstr "параметр не может иметь модифицированный тип `%T" - - #. [dcl.fct.spec] The explicit specifier shall only be used in - #. declarations of constructors within a class definition. --#: cp/decl.c:9943 -+#: cp/decl.c:9939 - #, gcc-internal-format - msgid "only declarations of constructors can be %" - msgstr "только декларации конструкторов могут быть %" - --#: cp/decl.c:9951 -+#: cp/decl.c:9947 - #, gcc-internal-format - msgid "non-member %qs cannot be declared %" - msgstr "недопустимая декларация не-элемента %qs как %" - --#: cp/decl.c:9957 -+#: cp/decl.c:9953 - #, gcc-internal-format - msgid "non-object member %qs cannot be declared %" - msgstr "недопустимая декларация не объектного элемента %qs как %" - --#: cp/decl.c:9963 -+#: cp/decl.c:9959 - #, gcc-internal-format - msgid "function %qs cannot be declared %" - msgstr "недопустимая декларация функции %qs как %" - --#: cp/decl.c:9968 -+#: cp/decl.c:9964 - #, gcc-internal-format - msgid "static %qs cannot be declared %" - msgstr "недопустимая декларация статического %qs как %" - --#: cp/decl.c:9973 -+#: cp/decl.c:9969 - #, gcc-internal-format - msgid "const %qs cannot be declared %" - msgstr "недопустимая декларация константного %qs как %" - --#: cp/decl.c:9978 -+#: cp/decl.c:9974 - #, fuzzy, gcc-internal-format - msgid "reference %qs cannot be declared %" - msgstr "недопустимая декларация функции %qs как %" - --#: cp/decl.c:10013 -+#: cp/decl.c:10009 - #, fuzzy, gcc-internal-format - msgid "typedef declared %" - msgstr "параметр %q+D объявлен %" - --#: cp/decl.c:10023 -+#: cp/decl.c:10019 - #, fuzzy, gcc-internal-format - msgid "typedef name may not be a nested-name-specifier" - msgstr "%Jдля typedef-имени недопустимы квалификаторы классов" - --#: cp/decl.c:10042 -+#: cp/decl.c:10038 - #, gcc-internal-format - msgid "ISO C++ forbids nested type %qD with same name as enclosing class" - msgstr "ISO C++ запрещает определять вложенный тип %qD с тем же именем, что и объемлющий класс" - --#: cp/decl.c:10143 -+#: cp/decl.c:10139 - #, gcc-internal-format - msgid "qualified function types cannot be used to declare static member functions" - msgstr "типы квалифицированных функций не могут использоваться для определения статических элементов-функций" - --#: cp/decl.c:10145 -+#: cp/decl.c:10141 - #, gcc-internal-format - msgid "qualified function types cannot be used to declare free functions" - msgstr "типы квалифицированных функций не могут использоваться для определения свободных функций" - --#: cp/decl.c:10172 -+#: cp/decl.c:10168 - #, gcc-internal-format - msgid "type qualifiers specified for friend class declaration" - msgstr "в декларации friend-класса использованы квалификаторы типа" - --#: cp/decl.c:10177 -+#: cp/decl.c:10173 - #, gcc-internal-format - msgid "% specified for friend class declaration" - msgstr "в декларации friend-класса использован квалификатор %" - --#: cp/decl.c:10185 -+#: cp/decl.c:10181 - #, gcc-internal-format - msgid "template parameters cannot be friends" - msgstr "параметры шаблона не могут быть friend" - --#: cp/decl.c:10187 -+#: cp/decl.c:10183 - #, gcc-internal-format - msgid "friend declaration requires class-key, i.e. %" - msgstr "в friend-декларации требуется указание класса: %" - --#: cp/decl.c:10191 -+#: cp/decl.c:10187 - #, gcc-internal-format - msgid "friend declaration requires class-key, i.e. %" - msgstr "в friend-декларации требуется указание класса: %" - --#: cp/decl.c:10204 -+#: cp/decl.c:10200 - #, gcc-internal-format - msgid "trying to make class %qT a friend of global scope" - msgstr "попытка сделать класс %qT \"другом\" глобальной области видимости" - --#: cp/decl.c:10222 -+#: cp/decl.c:10218 - #, gcc-internal-format - msgid "invalid qualifiers on non-member function type" - msgstr "некорректные квалификаторы для типа функции, не являющейся элементом" - --#: cp/decl.c:10232 -+#: cp/decl.c:10228 - #, gcc-internal-format - msgid "abstract declarator %qT used as declaration" - msgstr "абстрактный декларатор %qT использован в качестве декларатора" - --#: cp/decl.c:10261 -+#: cp/decl.c:10257 - #, gcc-internal-format - msgid "cannot use %<::%> in parameter declaration" - msgstr "недопустимое использование %<::%> в декларации параметра" - --#: cp/decl.c:10265 -+#: cp/decl.c:10261 - #, fuzzy, gcc-internal-format - msgid "parameter declared %" - msgstr "параметр %q+D объявлен %" - --#: cp/decl.c:10308 -+#: cp/decl.c:10304 - #, fuzzy, gcc-internal-format - msgid "non-static data member declared %" - msgstr "статический элемент %qD объявлен как %" - - #. Something like struct S { int N::j; }; --#: cp/decl.c:10330 -+#: cp/decl.c:10326 - #, gcc-internal-format - msgid "invalid use of %<::%>" - msgstr "недопустимое использование %<::%>" - --#: cp/decl.c:10352 -+#: cp/decl.c:10348 - #, fuzzy, gcc-internal-format - msgid "declaration of function %qD in invalid context" - msgstr "декларация C-функции `%#D' противоречит" - --#: cp/decl.c:10361 -+#: cp/decl.c:10357 - #, gcc-internal-format - msgid "function %qD declared virtual inside a union" - msgstr "функция %qD объявлена виртуальной внутри объединения" - --#: cp/decl.c:10370 -+#: cp/decl.c:10366 - #, gcc-internal-format - msgid "%qD cannot be declared virtual, since it is always static" - msgstr "%qD не может быть объявлена виртуальной, поскольку она всегда статическая" - --#: cp/decl.c:10386 -+#: cp/decl.c:10382 - #, fuzzy, gcc-internal-format - msgid "expected qualified name in friend declaration for destructor %qD" - msgstr "квалификаторы не допускаются в декларации `operator %T'" - --#: cp/decl.c:10393 -+#: cp/decl.c:10389 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD as member of %qT" - msgstr "декларация %qD перекрывает элемент класса, на который указывает 'this'" - --#: cp/decl.c:10399 -+#: cp/decl.c:10395 - #, fuzzy, gcc-internal-format - msgid "a destructor cannot be %" - msgstr "конструкторы нельзя декларировать как virtual" - --#: cp/decl.c:10405 -+#: cp/decl.c:10401 - #, fuzzy, gcc-internal-format - msgid "expected qualified name in friend declaration for constructor %qD" - msgstr "квалификаторы не допускаются в декларации `operator %T'" - --#: cp/decl.c:10451 -+#: cp/decl.c:10447 - #, gcc-internal-format - msgid "field %qD has incomplete type" - msgstr "поле %qD имеет неполный тип" - --#: cp/decl.c:10453 -+#: cp/decl.c:10449 - #, gcc-internal-format - msgid "name %qT has incomplete type" - msgstr "имя %qT имеет неполный тип" - --#: cp/decl.c:10462 -+#: cp/decl.c:10458 - #, gcc-internal-format - msgid " in instantiation of template %qT" - msgstr " в конкретизации шаблона %qT" - --#: cp/decl.c:10471 -+#: cp/decl.c:10467 - #, fuzzy, gcc-internal-format - msgid "%qE is neither function nor member function; cannot be declared friend" - msgstr "%qs не является ни функцией, ни элементом-функцией; friend-декларация не допускается" - --#: cp/decl.c:10528 -+#: cp/decl.c:10524 - #, fuzzy, gcc-internal-format - msgid "constexpr static data member %qD must have an initializer" - msgstr "`%#D' не является нестатическим элементом %qT" - --#: cp/decl.c:10537 -+#: cp/decl.c:10533 - #, fuzzy, gcc-internal-format - msgid "non-static data member %qE declared %" - msgstr "статический элемент %qD объявлен как %" - --#: cp/decl.c:10587 -+#: cp/decl.c:10583 - #, gcc-internal-format - msgid "storage class % invalid for function %qs" - msgstr "некорректный класс хранения % для функции %qs" - --#: cp/decl.c:10589 -+#: cp/decl.c:10585 - #, gcc-internal-format - msgid "storage class % invalid for function %qs" - msgstr "некорректный класс хранения % для функции %qs" - --#: cp/decl.c:10593 -+#: cp/decl.c:10589 - #, gcc-internal-format - msgid "storage class %<__thread%> invalid for function %qs" - msgstr "некорректный класс хранения %<__thread%> для функции %qs" - --#: cp/decl.c:10596 -+#: cp/decl.c:10592 - #, fuzzy, gcc-internal-format --#| msgid "storage class %<__thread%> invalid for function %qs" - msgid "storage class % invalid for function %qs" - msgstr "некорректный класс хранения %<__thread%> для функции %qs" - --#: cp/decl.c:10601 -+#: cp/decl.c:10597 - #, fuzzy, gcc-internal-format - msgid "virt-specifiers in %qs not allowed outside a class definition" - msgstr "спецификация asm не допускается при определении функции" - --#: cp/decl.c:10612 -+#: cp/decl.c:10608 - #, gcc-internal-format - msgid "% specified invalid for function %qs declared out of global scope" - msgstr "некорректно указано % для функции %qs, объявленной вне глобальной области видимости" - --#: cp/decl.c:10616 -+#: cp/decl.c:10612 - #, gcc-internal-format - msgid "% specifier invalid for function %qs declared out of global scope" - msgstr "некорректно указано % для функции %qs, объявленной вне глобальной области видимости" - --#: cp/decl.c:10624 -+#: cp/decl.c:10620 - #, gcc-internal-format - msgid "virtual non-class function %qs" - msgstr "виртуальная функция %qs не является элементом класса" - --#: cp/decl.c:10631 -+#: cp/decl.c:10627 - #, fuzzy, gcc-internal-format - msgid "%qs defined in a non-class scope" - msgstr "атрибут %qE для не классовых типов игнорируется" - --#: cp/decl.c:10632 -+#: cp/decl.c:10628 - #, fuzzy, gcc-internal-format - msgid "%qs declared in a non-class scope" - msgstr "атрибут %qE для не классовых типов игнорируется" - --#: cp/decl.c:10660 -+#: cp/decl.c:10655 - #, gcc-internal-format - msgid "cannot declare member function %qD to have static linkage" - msgstr "недопустимая декларация статического элемента-функции %qD" - - #. FIXME need arm citation --#: cp/decl.c:10667 -+#: cp/decl.c:10662 - #, gcc-internal-format - msgid "cannot declare static function inside another function" - msgstr "недопустимая декларация статической функции внутри другой функции" - --#: cp/decl.c:10697 -+#: cp/decl.c:10692 - #, gcc-internal-format - msgid "% may not be used when defining (as opposed to declaring) a static data member" - msgstr "слово % недопустимо при определении (в отличие от объявления) статического элемента данных в классе" - --#: cp/decl.c:10704 -+#: cp/decl.c:10699 - #, gcc-internal-format - msgid "static member %qD declared %" - msgstr "статический элемент %qD объявлен как %" - --#: cp/decl.c:10710 -+#: cp/decl.c:10705 - #, gcc-internal-format - msgid "cannot explicitly declare member %q#D to have extern linkage" - msgstr "недопустимая явная extern-декларация элемента %q#D" - --#: cp/decl.c:10717 -+#: cp/decl.c:10712 - #, fuzzy, gcc-internal-format - msgid "declaration of constexpr variable %qD is not a definition" - msgstr "декларация %q#D вне класса не является определением" - --#: cp/decl.c:10730 -+#: cp/decl.c:10725 - #, gcc-internal-format - msgid "%qs initialized and declared %" - msgstr "% декларация %qs с инициализацией" - --#: cp/decl.c:10734 -+#: cp/decl.c:10729 - #, gcc-internal-format - msgid "%qs has both % and initializer" - msgstr "для %qs задан спецификатор % и инициализатор" - --#: cp/decl.c:10880 -+#: cp/decl.c:10874 - #, fuzzy, gcc-internal-format - msgid "default argument %qE uses %qD" - msgstr "аргумент по умолчанию %qE использует локальную переменную %qD" - --#: cp/decl.c:10882 -+#: cp/decl.c:10876 - #, gcc-internal-format - msgid "default argument %qE uses local variable %qD" - msgstr "аргумент по умолчанию %qE использует локальную переменную %qD" - --#: cp/decl.c:10970 -+#: cp/decl.c:10964 - #, fuzzy, gcc-internal-format - msgid "parameter %qD has Java class type" - msgstr "параметр %q+D имеет неполный тип" - --#: cp/decl.c:10998 -+#: cp/decl.c:10992 - #, gcc-internal-format - msgid "parameter %qD invalidly declared method type" - msgstr "некорректная декларация параметра %qD с типом метода" - --#: cp/decl.c:11023 -+#: cp/decl.c:11017 - #, fuzzy, gcc-internal-format - msgid "parameter %qD includes pointer to array of unknown bound %qT" - msgstr "параметр %qD включает %s на массив с неизвестной границей %qT" - --#: cp/decl.c:11025 -+#: cp/decl.c:11019 - #, fuzzy, gcc-internal-format - msgid "parameter %qD includes reference to array of unknown bound %qT" - msgstr "параметр %qD включает %s на массив с неизвестной границей %qT" -@@ -31053,168 +30982,168 @@ - #. or implicitly defined), there's no need to worry about their - #. existence. Theoretically, they should never even be - #. instantiated, but that's hard to forestall. --#: cp/decl.c:11279 -+#: cp/decl.c:11273 - #, gcc-internal-format - msgid "invalid constructor; you probably meant %<%T (const %T&)%>" - msgstr "некорректный конструктор; возможно, вы имели в виду %<%T (const %T&)%>" - --#: cp/decl.c:11401 -+#: cp/decl.c:11395 - #, gcc-internal-format - msgid "%qD may not be declared within a namespace" - msgstr "декларация %qD может не действовать в пространстве имён" - --#: cp/decl.c:11406 -+#: cp/decl.c:11400 - #, gcc-internal-format - msgid "%qD may not be declared as static" - msgstr "%qD можно не определять статической" - --#: cp/decl.c:11432 -+#: cp/decl.c:11426 - #, gcc-internal-format - msgid "%qD must be a nonstatic member function" - msgstr "%qD должен быть нестатической элементом-функцией" - --#: cp/decl.c:11441 -+#: cp/decl.c:11435 - #, gcc-internal-format - msgid "%qD must be either a non-static member function or a non-member function" - msgstr "%qD должен быть либо нестатическим элементом-функцией или функцией-не-элементом" - --#: cp/decl.c:11463 -+#: cp/decl.c:11457 - #, gcc-internal-format - msgid "%qD must have an argument of class or enumerated type" - msgstr "%qD должен иметь аргумент типа класс или перечислимого типа" - --#: cp/decl.c:11492 -+#: cp/decl.c:11486 - #, fuzzy, gcc-internal-format - msgid "conversion to a reference to void will never use a type conversion operator" - msgstr "преобразование к %s%s никогда не будет использовать операцию преобразования типа" - --#: cp/decl.c:11494 -+#: cp/decl.c:11488 - #, fuzzy, gcc-internal-format - msgid "conversion to void will never use a type conversion operator" - msgstr "преобразование к %s%s никогда не будет использовать операцию преобразования типа" - --#: cp/decl.c:11501 -+#: cp/decl.c:11495 - #, fuzzy, gcc-internal-format - msgid "conversion to a reference to the same type will never use a type conversion operator" - msgstr "преобразование к %s%s никогда не будет использовать операцию преобразования типа" - --#: cp/decl.c:11503 -+#: cp/decl.c:11497 - #, fuzzy, gcc-internal-format - msgid "conversion to the same type will never use a type conversion operator" - msgstr "преобразование к %s%s никогда не будет использовать операцию преобразования типа" - --#: cp/decl.c:11511 -+#: cp/decl.c:11505 - #, fuzzy, gcc-internal-format - msgid "conversion to a reference to a base class will never use a type conversion operator" - msgstr "преобразование к %s%s никогда не будет использовать операцию преобразования типа" - --#: cp/decl.c:11513 -+#: cp/decl.c:11507 - #, fuzzy, gcc-internal-format - msgid "conversion to a base class will never use a type conversion operator" - msgstr "преобразование к %s%s никогда не будет использовать операцию преобразования типа" - - #. 13.4.0.3 --#: cp/decl.c:11522 -+#: cp/decl.c:11516 - #, gcc-internal-format - msgid "ISO C++ prohibits overloading operator ?:" - msgstr "ISO C++ не поддерживает перегрузку операции ?:" - --#: cp/decl.c:11527 -+#: cp/decl.c:11521 - #, gcc-internal-format - msgid "%qD must not have variable number of arguments" - msgstr "%qD не может иметь переменное число аргументов" - --#: cp/decl.c:11578 -+#: cp/decl.c:11572 - #, gcc-internal-format - msgid "postfix %qD must take % as its argument" - msgstr "постфиксный %qD должен иметь аргумент типа %" - --#: cp/decl.c:11581 -+#: cp/decl.c:11575 - #, gcc-internal-format - msgid "postfix %qD must take % as its second argument" - msgstr "постфиксный %qD должен иметь второй аргумент типа %" - --#: cp/decl.c:11589 -+#: cp/decl.c:11583 - #, gcc-internal-format - msgid "%qD must take either zero or one argument" - msgstr "%qD должен иметь не более одного аргумента" - --#: cp/decl.c:11591 -+#: cp/decl.c:11585 - #, gcc-internal-format - msgid "%qD must take either one or two arguments" - msgstr "%qD должен иметь один или два аргумента" - --#: cp/decl.c:11613 -+#: cp/decl.c:11607 - #, gcc-internal-format - msgid "prefix %qD should return %qT" - msgstr "префиксный %qD должен возвращать %qT" - --#: cp/decl.c:11619 -+#: cp/decl.c:11613 - #, gcc-internal-format - msgid "postfix %qD should return %qT" - msgstr "постфиксный %qD должен возвращать %qT" - --#: cp/decl.c:11628 -+#: cp/decl.c:11622 - #, gcc-internal-format - msgid "%qD must take %" - msgstr "%qD должен иметь список параметров %" - --#: cp/decl.c:11630 cp/decl.c:11639 -+#: cp/decl.c:11624 cp/decl.c:11633 - #, gcc-internal-format - msgid "%qD must take exactly one argument" - msgstr "%qD должен иметь ровно один аргумент" - --#: cp/decl.c:11641 -+#: cp/decl.c:11635 - #, gcc-internal-format - msgid "%qD must take exactly two arguments" - msgstr "%qD должен иметь ровно два аргумента" - --#: cp/decl.c:11650 -+#: cp/decl.c:11644 - #, gcc-internal-format - msgid "user-defined %qD always evaluates both arguments" - msgstr "пользовательский оператор %qD всегда вычисляет оба аргумента" - --#: cp/decl.c:11664 -+#: cp/decl.c:11658 - #, gcc-internal-format - msgid "%qD should return by value" - msgstr "%qD должен возвращать результат по значению" - --#: cp/decl.c:11675 cp/decl.c:11680 -+#: cp/decl.c:11669 cp/decl.c:11674 - #, gcc-internal-format - msgid "%qD cannot have default arguments" - msgstr "%qD не может иметь аргументов по умолчанию" - --#: cp/decl.c:11741 -+#: cp/decl.c:11732 - #, gcc-internal-format - msgid "using template type parameter %qT after %qs" - msgstr "использование параметра шаблона %qT после %qs" - --#: cp/decl.c:11764 -+#: cp/decl.c:11755 - #, fuzzy, gcc-internal-format - msgid "using alias template specialization %qT after %qs" - msgstr "неоднозначная конкретизация шаблона %qD для %q+D" - --#: cp/decl.c:11767 -+#: cp/decl.c:11758 - #, gcc-internal-format - msgid "using typedef-name %qD after %qs" - msgstr "использование typedef-имени %qD после %qs" - --#: cp/decl.c:11769 -+#: cp/decl.c:11760 - #, fuzzy, gcc-internal-format - msgid "%qD has a previous declaration here" - msgstr "%q+D ранее декларирован здесь" - --#: cp/decl.c:11777 -+#: cp/decl.c:11768 - #, gcc-internal-format - msgid "%qT referred to as %qs" - msgstr "ссылка на %qT как на %qs" - --#: cp/decl.c:11778 cp/decl.c:11785 -+#: cp/decl.c:11769 cp/decl.c:11776 - #, gcc-internal-format - msgid "%q+T has a previous declaration here" - msgstr "%q+T ранее декларирован здесь" - --#: cp/decl.c:11784 -+#: cp/decl.c:11775 - #, gcc-internal-format - msgid "%qT referred to as enum" - msgstr "ссылка на %qT как на enum" -@@ -31226,88 +31155,88 @@ - #. void f(class C); // No template header here - #. - #. then the required template argument is missing. --#: cp/decl.c:11799 -+#: cp/decl.c:11790 - #, gcc-internal-format - msgid "template argument required for %<%s %T%>" - msgstr "для %<%s %T%> нужен аргумент-шаблон" - --#: cp/decl.c:11849 cp/name-lookup.c:3069 -+#: cp/decl.c:11840 cp/name-lookup.c:3062 - #, gcc-internal-format - msgid "%qD has the same name as the class in which it is declared" - msgstr "%qD имеет то же имя, что и класс, в котором он(а) декларируется" - --#: cp/decl.c:11879 cp/name-lookup.c:2561 cp/name-lookup.c:3395 --#: cp/name-lookup.c:3440 cp/parser.c:5076 cp/parser.c:21175 -+#: cp/decl.c:11870 cp/name-lookup.c:2561 cp/name-lookup.c:3390 -+#: cp/name-lookup.c:3435 cp/parser.c:5076 cp/parser.c:21179 - #, gcc-internal-format - msgid "reference to %qD is ambiguous" - msgstr "ссылка на %qD противоречива" - --#: cp/decl.c:11994 -+#: cp/decl.c:11985 - #, gcc-internal-format - msgid "use of enum %q#D without previous declaration" - msgstr "использование перечисления %q#D без предыдущей декларации" - --#: cp/decl.c:12015 -+#: cp/decl.c:12006 - #, gcc-internal-format - msgid "redeclaration of %qT as a non-template" - msgstr "повторная декларация %qT как не-шаблона" - --#: cp/decl.c:12016 -+#: cp/decl.c:12007 - #, gcc-internal-format - msgid "previous declaration %q+D" - msgstr "предыдущая декларация %q+D" - --#: cp/decl.c:12157 -+#: cp/decl.c:12148 - #, gcc-internal-format - msgid "derived union %qT invalid" - msgstr "некорректный производный тип union %qT" - --#: cp/decl.c:12166 -+#: cp/decl.c:12157 - #, gcc-internal-format - msgid "Java class %qT cannot have multiple bases" - msgstr "Java-класс %qT не может иметь несколько базовых классов" - --#: cp/decl.c:12177 -+#: cp/decl.c:12168 - #, gcc-internal-format - msgid "Java class %qT cannot have virtual bases" - msgstr "Java-класс %qT не может иметь виртуальных базовых классов" - --#: cp/decl.c:12197 -+#: cp/decl.c:12188 - #, gcc-internal-format - msgid "base type %qT fails to be a struct or class type" - msgstr "базовый тип %qT не является ни структурой, ни классом" - --#: cp/decl.c:12230 -+#: cp/decl.c:12221 - #, gcc-internal-format - msgid "recursive type %qT undefined" - msgstr "рекурсивный тип %qT не определён" - --#: cp/decl.c:12232 -+#: cp/decl.c:12223 - #, gcc-internal-format - msgid "duplicate base type %qT invalid" - msgstr "некорректное дублирование базового типа %qT" - --#: cp/decl.c:12356 -+#: cp/decl.c:12347 - #, gcc-internal-format - msgid "scoped/unscoped mismatch in enum %q#T" - msgstr "" - --#: cp/decl.c:12359 cp/decl.c:12367 cp/decl.c:12379 cp/parser.c:14742 -+#: cp/decl.c:12350 cp/decl.c:12358 cp/decl.c:12370 cp/parser.c:14744 - #, fuzzy, gcc-internal-format - msgid "previous definition here" - msgstr "%Jэто предыдущее определение" - --#: cp/decl.c:12364 -+#: cp/decl.c:12355 - #, gcc-internal-format - msgid "underlying type mismatch in enum %q#T" - msgstr "" - --#: cp/decl.c:12376 -+#: cp/decl.c:12367 - #, gcc-internal-format - msgid "different underlying type in enum %q#T" - msgstr "" - --#: cp/decl.c:12443 -+#: cp/decl.c:12434 - #, gcc-internal-format - msgid "underlying type %<%T%> of %<%T%> must be an integral type" - msgstr "" -@@ -31316,84 +31245,82 @@ - #. - #. IF no integral type can represent all the enumerator values, the - #. enumeration is ill-formed. --#: cp/decl.c:12577 -+#: cp/decl.c:12568 - #, gcc-internal-format - msgid "no integral type can represent all of the enumerator values for %qT" - msgstr "ни один целочисленный тип не годится для представления всех значений перечислимого типа %qT" - --#: cp/decl.c:12718 -+#: cp/decl.c:12709 - #, gcc-internal-format - msgid "enumerator value for %qD is not an integer constant" - msgstr "значение перечислимого типа для %qD не является константой целого типа" - --#: cp/decl.c:12764 -+#: cp/decl.c:12755 - #, fuzzy, gcc-internal-format - msgid "incremented enumerator value is too large for %" - msgstr "целая константа слишком велика для типа %qs" - --#: cp/decl.c:12776 -+#: cp/decl.c:12767 - #, gcc-internal-format - msgid "overflow in enumeration values at %qD" - msgstr "переполнение в перечисляемых значениях для %qD" - --#: cp/decl.c:12796 -+#: cp/decl.c:12787 - #, fuzzy, gcc-internal-format - msgid "enumerator value %E is too large for underlying type %<%T%>" - msgstr "значение перечислимого типа для %qE не является константой целого типа" - --#: cp/decl.c:12886 -+#: cp/decl.c:12877 - #, gcc-internal-format - msgid "return type %q#T is incomplete" - msgstr "тип результата %q#T неполный" - --#: cp/decl.c:12888 -+#: cp/decl.c:12879 - #, fuzzy, gcc-internal-format - msgid "return type has Java class type %q#T" - msgstr "тип возвращаемого значения не полный" - --#: cp/decl.c:13012 cp/typeck.c:8247 -+#: cp/decl.c:13003 cp/typeck.c:8252 - #, gcc-internal-format - msgid "% should return a reference to %<*this%>" - msgstr "% должен возвращать ссылку на %<*this%>" - --#: cp/decl.c:13108 -+#: cp/decl.c:13099 - #, gcc-internal-format - msgid "no previous declaration for %q+D" - msgstr "отсутствует предварительная декларация %q+D" - --#: cp/decl.c:13329 -+#: cp/decl.c:13320 - #, fuzzy, gcc-internal-format - msgid "invalid function declaration" - msgstr "некорректная декларация элемента-функции" - --#: cp/decl.c:13413 -+#: cp/decl.c:13404 - #, gcc-internal-format - msgid "parameter %qD declared void" - msgstr "параметр %qD объявлен void" - --#: cp/decl.c:13781 -+#: cp/decl.c:13772 - #, fuzzy, gcc-internal-format --#| msgid "no return statement in function returning non-void" - msgid "no return statements in function returning %qT" - msgstr "в функции, которая должна возвращать значение, отсутствует оператор return" - --#: cp/decl.c:13783 cp/typeck.c:8135 -+#: cp/decl.c:13774 cp/typeck.c:8135 - #, fuzzy, gcc-internal-format --#| msgid "function return types not compatible due to %" - msgid "only plain % return type can be deduced to %" - msgstr "типы возвращаемых значений функции несовместимы из-за %" - --#: cp/decl.c:13879 -+#: cp/decl.c:13870 - #, fuzzy, gcc-internal-format - msgid "parameter %q+D set but not used" - msgstr "метка %q+D определена, но не используется" - --#: cp/decl.c:13974 -+#: cp/decl.c:13965 - #, gcc-internal-format - msgid "invalid member function declaration" - msgstr "некорректная декларация элемента-функции" - --#: cp/decl.c:13988 -+#: cp/decl.c:13979 - #, gcc-internal-format - msgid "%qD is already defined in class %qT" - msgstr "%qD уже определена в классе %qT" -@@ -31415,7 +31342,6 @@ - - #: cp/decl2.c:439 - #, fuzzy, gcc-internal-format --#| msgid "deleting array %q#D" - msgid "deleting array %q#E" - msgstr "удаление массива %q#D" - -@@ -31630,97 +31556,97 @@ - msgid "use of %qD before deduction of %" - msgstr "по умолчанию для %q+D принят тип %" - --#: cp/error.c:3327 -+#: cp/error.c:3331 - #, gcc-internal-format - msgid "extended initializer lists only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3332 -+#: cp/error.c:3336 - #, gcc-internal-format - msgid "explicit conversion operators only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3337 -+#: cp/error.c:3341 - #, gcc-internal-format - msgid "variadic templates only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3342 -+#: cp/error.c:3346 - #, gcc-internal-format - msgid "lambda expressions only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3347 -+#: cp/error.c:3351 - #, gcc-internal-format - msgid "C++0x auto only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3351 -+#: cp/error.c:3355 - #, gcc-internal-format - msgid "scoped enums only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3355 -+#: cp/error.c:3359 - #, gcc-internal-format - msgid "defaulted and deleted functions only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3360 -+#: cp/error.c:3364 - #, gcc-internal-format - msgid "inline namespaces only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3365 -+#: cp/error.c:3369 - #, gcc-internal-format - msgid "override controls (override/final) only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3370 -+#: cp/error.c:3374 - #, gcc-internal-format - msgid "non-static data member initializers only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3375 -+#: cp/error.c:3379 - #, gcc-internal-format - msgid "user-defined literals only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3380 -+#: cp/error.c:3384 - #, gcc-internal-format - msgid "delegating constructors only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3385 -+#: cp/error.c:3389 - #, gcc-internal-format - msgid "inheriting constructors only available with -std=c++11 or -std=gnu++11" - msgstr "" - --#: cp/error.c:3390 -+#: cp/error.c:3394 - #, fuzzy, gcc-internal-format - msgid "c++11 attributes only available with -std=c++11 or -std=gnu++11" - msgstr "атрибут %qs допустим только для переменных" - --#: cp/error.c:3439 -+#: cp/error.c:3443 - #, gcc-internal-format - msgid "incomplete type %qT used in nested name specifier" - msgstr "неполный тип %qT использован во вложенном спецификаторе имени" - --#: cp/error.c:3443 -+#: cp/error.c:3447 - #, fuzzy, gcc-internal-format - msgid "reference to %<%T::%D%> is ambiguous" - msgstr "использование %qD неоднозначно" - --#: cp/error.c:3448 cp/typeck.c:2260 -+#: cp/error.c:3452 cp/typeck.c:2260 - #, gcc-internal-format - msgid "%qD is not a member of %qT" - msgstr "%qD не является элементом %qT" - --#: cp/error.c:3452 -+#: cp/error.c:3456 - #, gcc-internal-format - msgid "%qD is not a member of %qD" - msgstr "%qD не является элементом %qD" - --#: cp/error.c:3457 -+#: cp/error.c:3461 - #, gcc-internal-format - msgid "%<::%D%> has not been declared" - msgstr "%<::%D%> не был декларирован" -@@ -32078,7 +32004,6 @@ - - #: cp/init.c:2254 - #, fuzzy, gcc-internal-format --#| msgid "integer overflow in expression" - msgid "integer overflow in array size" - msgstr "переполнение при вычислении целочисленного выражения" - -@@ -32601,77 +32526,77 @@ - msgid "%qD not declared" - msgstr "отсутствует декларация %qD" - --#: cp/name-lookup.c:3218 -+#: cp/name-lookup.c:3211 - #, gcc-internal-format - msgid "using-declaration for non-member at class scope" - msgstr "using-декларация для не-элемента внутри класса" - --#: cp/name-lookup.c:3225 -+#: cp/name-lookup.c:3218 - #, gcc-internal-format - msgid "%<%T::%D%> names destructor" - msgstr "%<%T::%D%> обозначает деструктор" - --#: cp/name-lookup.c:3236 -+#: cp/name-lookup.c:3231 - #, gcc-internal-format - msgid "%<%T::%D%> names constructor in %qT" - msgstr "%<%T::%D%> обозначает конструктор в %qT" - --#: cp/name-lookup.c:3287 -+#: cp/name-lookup.c:3282 - #, gcc-internal-format - msgid "no members matching %<%T::%D%> in %q#T" - msgstr "нет элементов, соответствующих %<%T::%D%>, в %q#T" - --#: cp/name-lookup.c:3374 -+#: cp/name-lookup.c:3369 - #, gcc-internal-format - msgid "declaration of %qD not in a namespace surrounding %qD" - msgstr "декларация %qD вне пространства имён, объемлющего %qD" - --#: cp/name-lookup.c:3382 -+#: cp/name-lookup.c:3377 - #, gcc-internal-format - msgid "explicit qualification in declaration of %qD" - msgstr "явные квалификаторы в декларации %qD" - --#: cp/name-lookup.c:3465 -+#: cp/name-lookup.c:3460 - #, gcc-internal-format - msgid "%qD should have been declared inside %qD" - msgstr "%qD следовало объявить внутри %qD" - --#: cp/name-lookup.c:3509 -+#: cp/name-lookup.c:3504 - #, fuzzy, gcc-internal-format - msgid "%qD attribute requires a single NTBS argument" - msgstr "аргументом атрибута %qs должна быть целая константа" - --#: cp/name-lookup.c:3516 -+#: cp/name-lookup.c:3511 - #, gcc-internal-format - msgid "%qD attribute is meaningless since members of the anonymous namespace get local symbols" - msgstr "" - --#: cp/name-lookup.c:3524 cp/name-lookup.c:3936 -+#: cp/name-lookup.c:3519 cp/name-lookup.c:3931 - #, gcc-internal-format - msgid "%qD attribute directive ignored" - msgstr "атрибут %qD игнорируется" - --#: cp/name-lookup.c:3588 -+#: cp/name-lookup.c:3583 - #, gcc-internal-format - msgid "namespace alias %qD not allowed here, assuming %qD" - msgstr "использование пространства имён %qD здесь недопустимо; предполагается %qD" - --#: cp/name-lookup.c:3924 -+#: cp/name-lookup.c:3919 - #, gcc-internal-format - msgid "strong using only meaningful at namespace scope" - msgstr "strong имеет смысл только в пределах namespace" - --#: cp/name-lookup.c:3928 -+#: cp/name-lookup.c:3923 - #, fuzzy, gcc-internal-format - msgid "current namespace %qD does not enclose strongly used namespace %qD" - msgstr "декларация %qD в %qD, который не объемлет %qD" - --#: cp/name-lookup.c:4267 -+#: cp/name-lookup.c:4262 - #, gcc-internal-format - msgid "maximum limit of %d namespaces searched for %qE" - msgstr "" - --#: cp/name-lookup.c:4277 -+#: cp/name-lookup.c:4272 - #, gcc-internal-format - msgid "suggested alternative:" - msgid_plural "suggested alternatives:" -@@ -32679,22 +32604,22 @@ - msgstr[1] "" - msgstr[2] "" - --#: cp/name-lookup.c:4281 -+#: cp/name-lookup.c:4276 - #, fuzzy, gcc-internal-format - msgid " %qE" - msgstr " `%#D'" - --#: cp/name-lookup.c:5551 -+#: cp/name-lookup.c:5546 - #, gcc-internal-format - msgid "argument dependent lookup finds %q+D" - msgstr "" - --#: cp/name-lookup.c:6088 -+#: cp/name-lookup.c:6083 - #, gcc-internal-format - msgid "XXX entering pop_everything ()\n" - msgstr "XXX вход в pop_everything ()\n" - --#: cp/name-lookup.c:6097 -+#: cp/name-lookup.c:6092 - #, gcc-internal-format - msgid "XXX leaving pop_everything ()\n" - msgstr "XXX выход из pop_everything ()\n" -@@ -32801,7 +32726,6 @@ - - #: cp/parser.c:2591 - #, fuzzy, gcc-internal-format --#| msgid "%qE is not a template" - msgid "%qE is not a class template" - msgstr "%qE не является шаблоном" - -@@ -32820,7 +32744,7 @@ - msgid "floating-point literal cannot appear in a constant-expression" - msgstr "%s не может присутствовать в константном выражении" - --#: cp/parser.c:2633 cp/pt.c:13527 -+#: cp/parser.c:2633 cp/pt.c:13522 - #, gcc-internal-format - msgid "a cast to a type other than an integral or enumeration type cannot appear in a constant-expression" - msgstr "" -@@ -32980,7 +32904,6 @@ - - #: cp/parser.c:3692 - #, fuzzy, gcc-internal-format --#| msgid "floating constant truncated to zero" - msgid "floating literal truncated to zero" - msgstr "деление на ноль плавающей константы" - -@@ -33064,7 +32987,7 @@ - msgid "literal operator suffixes not preceded by %<_%> are reserved for future standardization" - msgstr "" - --#: cp/parser.c:4857 cp/parser.c:16496 -+#: cp/parser.c:4857 cp/parser.c:16498 - #, fuzzy, gcc-internal-format - msgid "expected unqualified-id" - msgstr "ожидался список спецификаторов и квалификаторов" -@@ -33238,7 +33161,6 @@ - - #: cp/parser.c:8885 - #, fuzzy, gcc-internal-format --#| msgid "attributes after parenthesized initializer ignored" - msgid "attributes at the beginning of statement are ignored" - msgstr "атрибуты после инициализатора в скобках проигнорированы" - -@@ -33267,7 +33189,7 @@ - msgid "compound-statement in constexpr function" - msgstr "%qD не является функцией шаблоном" - --#: cp/parser.c:9298 cp/parser.c:23016 -+#: cp/parser.c:9298 cp/parser.c:23020 - #, fuzzy, gcc-internal-format - msgid "expected selection-statement" - msgstr "ожидалась декларация или оператор" -@@ -33297,7 +33219,7 @@ - msgid "inconsistent begin/end types in range-based % statement: %qT and %qT" - msgstr "" - --#: cp/parser.c:9889 cp/parser.c:23019 -+#: cp/parser.c:9889 cp/parser.c:23023 - #, fuzzy, gcc-internal-format - msgid "expected iteration-statement" - msgstr "ожидалась декларация или оператор" -@@ -33313,12 +33235,12 @@ - msgid "ISO C++ forbids computed gotos" - msgstr "ISO C++ не поддерживает вычисляемые goto" - --#: cp/parser.c:10071 cp/parser.c:23022 -+#: cp/parser.c:10071 cp/parser.c:23026 - #, fuzzy, gcc-internal-format - msgid "expected jump-statement" - msgstr "ожидался оператор" - --#: cp/parser.c:10203 cp/parser.c:19157 -+#: cp/parser.c:10203 cp/parser.c:19161 - #, gcc-internal-format - msgid "extra %<;%>" - msgstr "избыточная %<;%>" -@@ -33355,7 +33277,7 @@ - msgid "class definition may not be declared a friend" - msgstr "определение класса не должно содержать friend" - --#: cp/parser.c:11034 cp/parser.c:19551 -+#: cp/parser.c:11034 cp/parser.c:19555 - #, gcc-internal-format - msgid "templates may not be %" - msgstr "" -@@ -33436,12 +33358,12 @@ - msgid "keyword % not implemented, and will be ignored" - msgstr "ключевое слово % не реализовано; игнорируется" - --#: cp/parser.c:12317 cp/parser.c:12415 cp/parser.c:12522 cp/parser.c:17611 -+#: cp/parser.c:12317 cp/parser.c:12415 cp/parser.c:12522 cp/parser.c:17613 - #, fuzzy, gcc-internal-format - msgid "template parameter pack %qD cannot have a default argument" - msgstr "%qD не может иметь аргументов по умолчанию" - --#: cp/parser.c:12321 cp/parser.c:17619 -+#: cp/parser.c:12321 cp/parser.c:17621 - #, fuzzy, gcc-internal-format - msgid "template parameter pack cannot have a default argument" - msgstr "%qD не может иметь аргументов по умолчанию" -@@ -33456,7 +33378,7 @@ - msgid "expected template-id" - msgstr "ожидался оператор" - --#: cp/parser.c:12658 cp/parser.c:22980 -+#: cp/parser.c:12658 cp/parser.c:22984 - #, fuzzy, gcc-internal-format - msgid "expected %<<%>" - msgstr "ожидалось %<{%>" -@@ -33548,163 +33470,163 @@ - msgid "elaborated-type-specifier for a scoped enum must not use the %<%D%> keyword" - msgstr "" - --#: cp/parser.c:14355 -+#: cp/parser.c:14357 - #, fuzzy, gcc-internal-format - msgid "declaration %qD does not declare anything" - msgstr "декларация ничего не описывает" - --#: cp/parser.c:14441 -+#: cp/parser.c:14443 - #, fuzzy, gcc-internal-format - msgid "attributes ignored on uninstantiated type" - msgstr "атрибут %qE для не классовых типов игнорируется" - --#: cp/parser.c:14445 -+#: cp/parser.c:14447 - #, fuzzy, gcc-internal-format - msgid "attributes ignored on template instantiation" - msgstr "класс хранения %qD в конкретизации шаблона" - --#: cp/parser.c:14450 -+#: cp/parser.c:14452 - #, gcc-internal-format - msgid "attributes ignored on elaborated-type-specifier that is not a forward declaration" - msgstr "" - --#: cp/parser.c:14584 -+#: cp/parser.c:14586 - #, fuzzy, gcc-internal-format - msgid "%qD is an enumeration template" - msgstr "%qD не является шаблоном функции" - --#: cp/parser.c:14592 -+#: cp/parser.c:14594 - #, fuzzy, gcc-internal-format - msgid "%qD is not an enumerator-name" - msgstr "%qT не является пространством имён" - --#: cp/parser.c:14655 -+#: cp/parser.c:14657 - #, fuzzy, gcc-internal-format - msgid "expected %<;%> or %<{%>" - msgstr "ожидалось %<,%> или %<;%>" - --#: cp/parser.c:14703 -+#: cp/parser.c:14705 - #, fuzzy, gcc-internal-format - msgid "cannot add an enumerator list to a template instantiation" - msgstr "Включить автоматическую конкретизацию шаблонов" - --#: cp/parser.c:14712 cp/parser.c:18714 -+#: cp/parser.c:14714 cp/parser.c:18718 - #, fuzzy, gcc-internal-format - msgid "declaration of %qD in namespace %qD which does not enclose %qD" - msgstr "декларация %qD в %qD, который не объемлет %qD" - --#: cp/parser.c:14717 cp/parser.c:18719 -+#: cp/parser.c:14719 cp/parser.c:18723 - #, gcc-internal-format - msgid "declaration of %qD in %qD which does not enclose %qD" - msgstr "декларация %qD в %qD, который не объемлет %qD" - --#: cp/parser.c:14740 -+#: cp/parser.c:14742 - #, gcc-internal-format - msgid "multiple definition of %q#T" - msgstr "повторное определение %q#T" - --#: cp/parser.c:14767 -+#: cp/parser.c:14769 - #, gcc-internal-format - msgid "opaque-enum-specifier without name" - msgstr "" - --#: cp/parser.c:14770 -+#: cp/parser.c:14772 - #, gcc-internal-format - msgid "opaque-enum-specifier must use a simple identifier" - msgstr "" - --#: cp/parser.c:14946 -+#: cp/parser.c:14948 - #, fuzzy, gcc-internal-format - msgid "%qD is not a namespace-name" - msgstr "%qT не является пространством имён" - --#: cp/parser.c:14947 -+#: cp/parser.c:14949 - #, fuzzy, gcc-internal-format - msgid "expected namespace-name" - msgstr "ожидалось имя класса" - --#: cp/parser.c:15072 -+#: cp/parser.c:15074 - #, fuzzy, gcc-internal-format - msgid "% definition is not allowed here" - msgstr "#pragma %s уже зарегистрирована" - --#: cp/parser.c:15218 -+#: cp/parser.c:15220 - #, gcc-internal-format - msgid "a template-id may not appear in a using-declaration" - msgstr "идентификатор шаблона недопустим в using-декларации" - --#: cp/parser.c:15258 -+#: cp/parser.c:15260 - #, gcc-internal-format - msgid "access declarations are deprecated in favour of using-declarations; suggestion: add the % keyword" - msgstr "" - --#: cp/parser.c:15323 -+#: cp/parser.c:15325 - #, fuzzy, gcc-internal-format - msgid "types may not be defined in alias template declarations" - msgstr "в описании возвращаемого типа нельзя определять новые типы" - --#: cp/parser.c:15787 -+#: cp/parser.c:15789 - #, fuzzy, gcc-internal-format - msgid "a function-definition is not allowed here" - msgstr "#pragma %s уже зарегистрирована" - --#: cp/parser.c:15799 -+#: cp/parser.c:15801 - #, gcc-internal-format - msgid "an asm-specification is not allowed on a function-definition" - msgstr "спецификация asm не допускается при определении функции" - --#: cp/parser.c:15803 -+#: cp/parser.c:15805 - #, gcc-internal-format - msgid "attributes are not allowed on a function-definition" - msgstr "атрибуты не допускаются при определении функции" - --#: cp/parser.c:15840 -+#: cp/parser.c:15842 - #, gcc-internal-format - msgid "expected constructor, destructor, or type conversion" - msgstr "" - - #. Anything else is an error. --#: cp/parser.c:15875 cp/parser.c:17782 -+#: cp/parser.c:15877 cp/parser.c:17784 - #, fuzzy, gcc-internal-format - msgid "expected initializer" - msgstr "ожидался идентификатор" - --#: cp/parser.c:15895 -+#: cp/parser.c:15897 - #, fuzzy, gcc-internal-format - msgid "invalid type in declaration" - msgstr "пустая декларация" - --#: cp/parser.c:15971 -+#: cp/parser.c:15973 - #, fuzzy, gcc-internal-format - msgid "initializer provided for function" - msgstr "недопустимая инициализация friend-функции %qs" - --#: cp/parser.c:16005 -+#: cp/parser.c:16007 - #, gcc-internal-format - msgid "attributes after parenthesized initializer ignored" - msgstr "атрибуты после инициализатора в скобках проигнорированы" - --#: cp/parser.c:16416 -+#: cp/parser.c:16418 - #, fuzzy, gcc-internal-format - msgid "array bound is not an integer constant" - msgstr "индекс массива не является целым значением" - --#: cp/parser.c:16542 -+#: cp/parser.c:16544 - #, fuzzy, gcc-internal-format - msgid "cannot define member of dependent typedef %qT" - msgstr "создание указателя на элемент ссылочного типа %qT" - --#: cp/parser.c:16546 -+#: cp/parser.c:16548 - #, fuzzy, gcc-internal-format - msgid "%<%T::%E%> is not a type" - msgstr "%<%T::%D%> не является типом" - --#: cp/parser.c:16574 -+#: cp/parser.c:16576 - #, fuzzy, gcc-internal-format - msgid "invalid use of constructor as a template" - msgstr "некорректное использование нестатического элемента данных '%E'" - --#: cp/parser.c:16576 -+#: cp/parser.c:16578 - #, gcc-internal-format - msgid "use %<%T::%D%> instead of %<%T::%D%> to name the constructor in a qualified name" - msgstr "используйте %<%T::%D%> вместо %<%T::%D%> для именования конструктора в имени с квалификатором" -@@ -33713,263 +33635,262 @@ - #. here because we do not have enough - #. information about its original syntactic - #. form. --#: cp/parser.c:16593 -+#: cp/parser.c:16595 - #, fuzzy, gcc-internal-format - msgid "invalid declarator" - msgstr "некорректная декларация %q+D" - --#: cp/parser.c:16660 -+#: cp/parser.c:16662 - #, fuzzy, gcc-internal-format - msgid "expected declarator" - msgstr "ожидались спецификаторы декларации" - --#: cp/parser.c:16763 -+#: cp/parser.c:16765 - #, fuzzy, gcc-internal-format - msgid "%qD is a namespace" - msgstr "%qT не является пространством имён" - --#: cp/parser.c:16765 -+#: cp/parser.c:16767 - #, fuzzy, gcc-internal-format - msgid "cannot form pointer to member of non-class %q#T" - msgstr "создание указателя на элемент не классового типа %qT" - --#: cp/parser.c:16786 -+#: cp/parser.c:16788 - #, fuzzy, gcc-internal-format - msgid "expected ptr-operator" - msgstr "некорректный операнд" - --#: cp/parser.c:16845 -+#: cp/parser.c:16847 - #, fuzzy, gcc-internal-format - msgid "duplicate cv-qualifier" - msgstr "повтор case-значения," - --#: cp/parser.c:16903 -+#: cp/parser.c:16905 - #, fuzzy, gcc-internal-format - msgid "duplicate virt-specifier" - msgstr "повтор case-значения," - --#: cp/parser.c:17065 cp/typeck2.c:448 cp/typeck2.c:1685 -+#: cp/parser.c:17067 cp/typeck2.c:448 cp/typeck2.c:1685 - #, fuzzy, gcc-internal-format - msgid "invalid use of %" - msgstr "недопустимое использование %<::%>" - --#: cp/parser.c:17084 -+#: cp/parser.c:17086 - #, fuzzy, gcc-internal-format - msgid "types may not be defined in template arguments" - msgstr "в описании возвращаемого типа нельзя определять новые типы" - --#: cp/parser.c:17165 -+#: cp/parser.c:17167 - #, fuzzy, gcc-internal-format - msgid "expected type-specifier" - msgstr "ожидался идентификатор" - --#: cp/parser.c:17407 -+#: cp/parser.c:17409 - #, fuzzy, gcc-internal-format - msgid "expected %<,%> or %<...%>" - msgstr "ожидалось %<:%> или %<...%>" - --#: cp/parser.c:17464 -+#: cp/parser.c:17466 - #, fuzzy, gcc-internal-format - msgid "types may not be defined in parameter types" - msgstr "в описании возвращаемого типа нельзя определять новые типы" - --#: cp/parser.c:17590 -+#: cp/parser.c:17592 - #, gcc-internal-format - msgid "deprecated use of default argument for parameter of non-function" - msgstr "устаревшее использование аргумента по умолчанию в качестве параметра не-функции" - --#: cp/parser.c:17594 -+#: cp/parser.c:17596 - #, gcc-internal-format - msgid "default arguments are only permitted for function parameters" - msgstr "аргументы по умолчанию разрешены только для параметров функций" - --#: cp/parser.c:17613 -+#: cp/parser.c:17615 - #, fuzzy, gcc-internal-format - msgid "parameter pack %qD cannot have a default argument" - msgstr "%qD не может иметь аргументов по умолчанию" - --#: cp/parser.c:17621 -+#: cp/parser.c:17623 - #, fuzzy, gcc-internal-format - msgid "parameter pack cannot have a default argument" - msgstr "%qD не может иметь аргументов по умолчанию" - --#: cp/parser.c:17910 -+#: cp/parser.c:17914 - #, gcc-internal-format - msgid "ISO C++ does not allow designated initializers" - msgstr "ISO C++ не поддерживает назначенные инициализаторы" - --#: cp/parser.c:17924 -+#: cp/parser.c:17928 - #, fuzzy, gcc-internal-format - msgid "ISO C++ does not allow C99 designated initializers" - msgstr "ISO C++ не поддерживает назначенные инициализаторы" - --#: cp/parser.c:18032 cp/parser.c:18157 -+#: cp/parser.c:18036 cp/parser.c:18161 - #, fuzzy, gcc-internal-format - msgid "expected class-name" - msgstr "ожидалось имя класса" - --#: cp/parser.c:18337 -+#: cp/parser.c:18341 - #, fuzzy, gcc-internal-format - msgid "expected %<;%> after class definition" - msgstr "%q+D: inline-декларация после определения" - --#: cp/parser.c:18339 -+#: cp/parser.c:18343 - #, fuzzy, gcc-internal-format - msgid "expected %<;%> after struct definition" - msgstr "%q+D: inline-декларация после определения" - --#: cp/parser.c:18341 -+#: cp/parser.c:18345 - #, fuzzy, gcc-internal-format - msgid "expected %<;%> after union definition" - msgstr "Некорректный мусор после определения в %C" - --#: cp/parser.c:18662 -+#: cp/parser.c:18666 - #, fuzzy, gcc-internal-format - msgid "expected %<{%> or %<:%>" - msgstr "ожидалось %<,%> или %<;%>" - --#: cp/parser.c:18673 -+#: cp/parser.c:18677 - #, fuzzy, gcc-internal-format - msgid "cannot specify % for a class" - msgstr "нет файла для класса %s" - --#: cp/parser.c:18681 -+#: cp/parser.c:18685 - #, gcc-internal-format - msgid "global qualification of class name is invalid" - msgstr "" - --#: cp/parser.c:18688 -+#: cp/parser.c:18692 - #, fuzzy, gcc-internal-format - msgid "qualified name does not name a class" - msgstr "в декларации friend нет имени класса или функции" - --#: cp/parser.c:18700 -+#: cp/parser.c:18704 - #, fuzzy, gcc-internal-format - msgid "invalid class name in declaration of %qD" - msgstr "некорректная template-декларация %qD" - --#: cp/parser.c:18733 -+#: cp/parser.c:18737 - #, fuzzy, gcc-internal-format - msgid "extra qualification not allowed" - msgstr "избыточные квалификаторы проигнориованы" - --#: cp/parser.c:18745 -+#: cp/parser.c:18749 - #, fuzzy, gcc-internal-format - msgid "an explicit specialization must be preceded by %