Piotr,
you made my day!!!
Thank you! My Ultrabase just became more useful with your driver.
Any idea how to enable UXA?
II) Module exa: vendor="X.Org Foundation" compiled for 1.6.0, module version = 2.4.0 ABI class: X.Org Video Driver, version 5.0 (II) intel(0): Comparing regs from server start up to After PreInit (WW) intel(0): Register 0x61110 (PORT_HOTPLUG_EN) changed from 0x10000120 to 0x38000120 (WW) intel(0): Register 0x61114 (PORT_HOTPLUG_STAT) changed from 0x10100000 to 0x38100000 (WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00000206 to 0x80000206 (WW) intel(0): PIPEASTAT before: status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS (WW) intel(0): PIPEASTAT after: status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS (WW) intel(0): Register 0x321b (FBC_FENCE_OFF) changed from 0x4b035b00 to 0x3800ba00 (WW) intel(0): Register 0x64110 (DPB_AUX_CH_CTL) changed from 0x00050000 to 0x5d450085 (WW) intel(0): Register 0x64210 (DPC_AUX_CH_CTL) changed from 0x00150085 to 0x4c150085 (WW) intel(0): Register 0x64310 (DPD_AUX_CH_CTL) changed from 0x00050000 to 0x5d450085 (==) Depth 24 pixmap format is 32 bpp (II) do I need RAC? No, I don't. (II) resource ranges after preInit: [0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B] [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] [4] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprD) [5] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD) [6] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprD) [7] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] [8] -1 0 0x00000000 - 0x00000000 (0x1) IX[B] [9] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) [10] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) (II) intel(0): Kernel reported 739328 total, 1 used (II) intel(0): I830CheckAvailableMemory: 2957308 kB available (WW) intel(0): DRI2 requires UXA
Piotr,
you made my day!!!
Thank you! My Ultrabase just became more useful with your driver.
Any idea how to enable UXA?
II) Module exa: vendor="X.Org Foundation" bleMemory: 2957308 kB available
compiled for 1.6.0, module version = 2.4.0
ABI class: X.Org Video Driver, version 5.0
(II) intel(0): Comparing regs from server start up to After PreInit
(WW) intel(0): Register 0x61110 (PORT_HOTPLUG_EN) changed from 0x10000120 to 0x38000120
(WW) intel(0): Register 0x61114 (PORT_HOTPLUG_STAT) changed from 0x10100000 to 0x38100000
(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00000206 to 0x80000206
(WW) intel(0): PIPEASTAT before: status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS
(WW) intel(0): PIPEASTAT after: status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS
(WW) intel(0): Register 0x321b (FBC_FENCE_OFF) changed from 0x4b035b00 to 0x3800ba00
(WW) intel(0): Register 0x64110 (DPB_AUX_CH_CTL) changed from 0x00050000 to 0x5d450085
(WW) intel(0): Register 0x64210 (DPC_AUX_CH_CTL) changed from 0x00150085 to 0x4c150085
(WW) intel(0): Register 0x64310 (DPD_AUX_CH_CTL) changed from 0x00050000 to 0x5d450085
(==) Depth 24 pixmap format is 32 bpp
(II) do I need RAC? No, I don't.
(II) resource ranges after preInit:
[0] -1 0 0xffffffff - 0xffffffff (0x1) MX[B]
[1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B]
[2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B]
[3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B]
[4] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
[5] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
[6] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
[7] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B]
[8] -1 0 0x00000000 - 0x00000000 (0x1) IX[B]
[9] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
[10] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU)
(II) intel(0): Kernel reported 739328 total, 1 used
(II) intel(0): I830CheckAvaila
(WW) intel(0): DRI2 requires UXA