--- binutils-2.20.orig/debian/binutils-gold.overrides +++ binutils-2.20/debian/binutils-gold.overrides @@ -0,0 +1,5 @@ +# don't warn about missing man pages for diverted binaries +binutils-gold binary: binary-without-manpage + +# the API of the shared libs is not public, don't care about the name +binutils-multiarch binary: package-name-doesnt-match-sonames --- binutils-2.20.orig/debian/changelog +++ binutils-2.20/debian/changelog @@ -0,0 +1,3332 @@ +binutils (2.20-0ubuntu1) karmic; urgency=low + + * binutils 2.20 final release. + - Fix PR binutils/10785, memory corruptions. + - gold updates. LP: #453278. + * debian/*.shlibs: Update to the release version. LP: #452526. + * Fix build failure on arm, building from the release tarball. + + -- Matthias Klose Sat, 17 Oct 2009 11:14:00 +0200 + +binutils (2.19.91.20091014-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20091014. + - PR ld/10749, ia64 linker failure. + - PR gas/2117, ia64 assembler fix. + * debian/*.shlibs: Update to the version from the branch. + * Fix build failures for cross build. + + -- Matthias Klose Wed, 14 Oct 2009 14:55:40 +0200 + +binutils (2.19.91.20091006-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20091006. + - cfi_sections changes applied, remove 129_cfi_sections.dpatch. + * debian/*.shlibs: Update to the version from the branch. + * binutils-gold: Build the testsuite as part of the check target + instead of the build target to avoid build failures when the + installed binutils soname is the same as the one which is built + (gas is segfaulting). Just a workaround, not a solution. + + -- Matthias Klose Tue, 06 Oct 2009 18:14:37 +0200 + +binutils (2.19.91.20091005-0ubuntu2) karmic; urgency=low + + * Really re-enable the binutils-gold build on powerpc. + + -- Matthias Klose Tue, 06 Oct 2009 13:53:22 +0200 + +binutils (2.19.91.20091005-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20091005. + - no changes, bump the soname only. + * debian/*.shlibs: Update to the version from the branch. + * Re-enable the binutils-gold build on powerpc. + * Add 129_cfi_sections.dpatch, support for .cfi_sections, taken + from the trunk. LP: #440172. + * Add 150_gold_copyrelocs.dpatch, add -z copyrelocs option for gold. + + -- Matthias Klose Tue, 06 Oct 2009 10:31:58 +0200 + +binutils (2.19.91.20091003-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20091003. + - powerpc fixes. + * debian/*.shlibs: Update to the version from the branch. + * Reenable binutils-gold build on armel (build failures on just + one buildd). + * Disable binutils-gold build on powerpc, fails to build with the + version in the archive. + * binutils-source: Depend on texinfo, zlib1g-dev. + + -- Matthias Klose Tue, 06 Oct 2009 10:16:47 +0200 + +binutils (2.19.91.20091001-0ubuntu2) karmic; urgency=low + + * Don't build binutils-gold for armel, currently ftbfs. + + -- Matthias Klose Thu, 01 Oct 2009 23:54:41 +0200 + +binutils (2.19.91.20091001-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20091001. + - Fix PR ld/9863, regression in testsuite on armel. + - Fix regressions seen in the GCC/libjava testsuite. + * debian/*.shlibs: Update to the version from the branch. + * No need to build libiberty_pic.a twice. + + -- Matthias Klose Thu, 01 Oct 2009 16:53:04 +0200 + +binutils (2.19.91.20090923-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20090923 (last upload + was taken from the trunk).. + * debian/*.shlibs: Update to the version from the branch. + + -- Matthias Klose Wed, 23 Sep 2009 09:44:40 +0200 + +binutils (2.19.91.20090922-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20090922. + * debian/*.shlibs: Update to the version from the branch. + + -- Matthias Klose Tue, 22 Sep 2009 22:01:19 +0200 + +binutils (2.19.91.20090910-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20090910, corresponding + to the 2.19.90 upstream snapshot. + * Fix Thumb-2 shared libraries (Daniel Jacobowitz), patch taken + from the trunk. + * Update binutils-sec64k patch (H.J. Lu). + + -- Matthias Klose Thu, 10 Sep 2009 17:21:56 +0200 + +binutils (2.19.90.20090909-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the 2.20 release branch 20090909. + * debian/*.shlibs: Update to the version from the branch. + + -- Matthias Klose Wed, 09 Sep 2009 10:01:29 +0200 + +binutils (2.19.51.20090827-1ubuntu1) karmic; urgency=low + + * Merge with Debian unstable; remaining changes: + - Build binutils-static and binutils-static-udeb packages. + - Apply patches derived from the binutils HJL release. + + -- Matthias Klose Fri, 28 Aug 2009 13:49:57 +0200 + +binutils (2.19.51.20090827-1) unstable; urgency=low + + * Snapshot, taken from the trunk 20090827. + - Fix PR ld/10518: In linker scripts override a "*" match by any other + wildcard match. Closes: #540751. + * debian/*.shlibs: Update to the version from the trunk. Closes: #540800. + * Add sysroot support for cross builds (Hector Oron). Closes: #522480. + * Update long description of binutils-doc. Closes: #428764. + * Update build-dependency on autoconf. + * Fix some lintian warnings. + + -- Matthias Klose Thu, 27 Aug 2009 17:09:28 +0200 + +binutils (2.19.51.20090805-1ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090805. + * debian/*.shlibs: Update to the version from the trunk. + - Fix PR binutils/10364, strip not failing on unwritable files. + Closes: #276428. + - Fix PR binutils/10363, objdump -T crashing on corrupted file. + Closes: #487963. + * 129_cortex_a8.dpatch: Fix a couple of cortex-a8 erratum bugs. + + -- Matthias Klose Wed, 05 Aug 2009 10:29:44 +0200 + +binutils (2.19.51.20090723-1ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090723. + * debian/*.shlibs: Update to the version from the trunk. + * Apply build-id patch to avoid memory corruption (taken from Fedora). + + -- Matthias Klose Thu, 23 Jul 2009 13:47:19 +0200 + +binutils (2.19.51.20090714-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090714. + - Fix PR gas/10387 (branch instruction with no operand causes gas + to segfault on armel). LP: #396049. + - 128_arm_eabi_align64.dpatch: Remove, integrated upstream. + * debian/*.shlibs: Update to the version from the trunk. + + -- Matthias Klose Tue, 14 Jul 2009 12:48:09 -0400 + +binutils (2.19.51.20090713-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090713. + * debian/*.shlibs: Update to the version from the trunk. + * 128_arm_eabi_align64.dpatch: Adjust expected output to changed objdump + output. LP: #398732. + + -- Matthias Klose Mon, 13 Jul 2009 13:21:56 -0400 + +binutils (2.19.51.20090704-1ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090704. + * debian/*.shlibs: Update to the version from the trunk. + + -- Matthias Klose Sat, 04 Jul 2009 11:46:03 +0200 + +binutils (2.19.51.20090704-1) unstable; urgency=low + + * Snapshot, taken from the trunk 20090704. + - debian/patches/128_arm_eabi_auto_it.dpatch: Remove, applied upstream. + * debian/*.shlibs: Update to the version from the trunk. + * Bump standards version. + + -- Matthias Klose Sat, 04 Jul 2009 10:37:18 +0200 + +binutils (2.19.51.20090622-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090622. + - debian/patches/128_arm_eabi_auto_it.dpatch: Remove, applied upstream. + * debian/*.shlibs: Update to the version from the trunk. + + -- Matthias Klose Tue, 23 Jun 2009 01:36:34 +0200 + +binutils (2.19.51.20090620-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090620. + * debian/*.shlibs: Update to the version from the trunk. + * Build the binutils-gold package on armel. + * Update hjl patches from the binutils-2.19.51.0.10 release. + + -- Matthias Klose Sat, 20 Jun 2009 22:56:32 +0200 + +binutils (2.19.51.20090616reallz0515-0ubuntu1) karmic; urgency=low + + * Reupload snapshot from trunk 20090515. + * Apply proposed patch to augment maximum alignment size to 64 (ARM gas). + * Apply proposed patch for new option for automatically generating IT blocks. + + -- Matthias Klose Wed, 17 Jun 2009 23:02:25 +0000 + +binutils (2.19.51.20090515-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090515. + - Fix PR ld/10152. LP: #375991. + * Revert work-around from last upload. + * debian/*.shlibs: Update to the version from the trunk. + * Build the binutils-gold package again. + + -- Matthias Klose Fri, 15 May 2009 16:34:56 +0200 + +binutils (2.19.51.20090508-0ubuntu2) karmic; urgency=low + + * Revert change for ARM unwind table linker processing. Addresses #375991. + + -- Matthias Klose Wed, 13 May 2009 17:46:20 +0200 + +binutils (2.19.51.20090508-0ubuntu1) karmic; urgency=low + + * Snapshot, taken from the trunk 20090508. + * debian/*.shlibs: Update to the version from the trunk. + + -- Matthias Klose Fri, 08 May 2009 11:22:40 +0200 + +binutils (2.19.51.20090423-0ubuntu2) karmic; urgency=low + + * Snapshot, taken from the trunk 20090423. + * debian/*.shlibs: Update to the version from the trunk. + * Fix build failure when building with -Os. + * debian/patches/013_bash_in_ld_testsuite.dpatch: Update. + + -- Matthias Klose Fri, 24 Apr 2009 12:29:23 +0200 + +binutils (2.19.1-0ubuntu3) jaunty; urgency=low + + * Re-add -a to dpkg-architecture call; the addition of -f is all what's + needed to ignore the dpkg-architecture env set by dpkg-buildpackage (since + we don't care about the DEB_BUILD_* or DEB_HOST_* arches but only about + the TARGET arch). + + -- Loic Minier Tue, 10 Feb 2009 16:42:28 +0100 + +binutils (2.19.1-0ubuntu2) jaunty; urgency=low + + * binutils-source: Make .dpatch files executable. + * Use dpkg-architecture -f instead of -a for cross builds. + * Call pkg_create_dbgsym explicitely to build debug symbols packages. + LP: #322243. + + -- Matthias Klose Tue, 10 Feb 2009 12:05:51 +0100 + +binutils (2.19.1-0ubuntu1) jaunty; urgency=low + + * Binutils 2.19.1 release. + - 128_arm_relocs_against_weak.dpatch 129_scale-DW_CFA_advance_loc.dpatch: + Remove, applied upstream. + * debian/*.shlibs: Update to the release version. + + -- Matthias Klose Wed, 04 Feb 2009 10:14:33 +0100 + +binutils (2.19.0.20090110-0ubuntu1) jaunty; urgency=low + + * Update to the binutils-2_19-branch 20090110. + - Fix PR binutils/7011. LP: #254790. + * debian/*.shlibs: Update to the version from the branch. + + -- Matthias Klose Sat, 10 Jan 2009 13:47:35 +0100 + +binutils (2.19-0ubuntu3) jaunty; urgency=low + + * debian/patches/129_scale-DW_CFA_advance_loc.dpatch: Scale + DW_CFA_advance_loc[124] output values. + * debian/patches/128_arm_relocs_against_weak.dpatch: Fix R_ARM_THM_CALL + relocations against undefined weak symbols in shared libraries. + + -- Matthias Klose Sat, 29 Nov 2008 11:25:22 +0100 + +binutils (2.19-0ubuntu2) jaunty; urgency=low + + * No-change rebuild to remove translations from the binary package, + accidentally included due to a misbuild. + + -- Steve Langasek Fri, 21 Nov 2008 04:35:45 +0000 + +binutils (2.19-0ubuntu1) jaunty; urgency=low + + * Binutils 2.19 release. + * debian/*.shlibs: Update to the release version. + * debian/control: Update to GPL3, reference the GFDL. + * Make lintian more happy. + + -- Matthias Klose Thu, 30 Oct 2008 15:37:05 +0100 + +binutils (2.18.93.20081009-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the 2.19 branch 20081009 (corresponding to the + 2.18.93 upstream snapshot. + * debian/*.shlibs: Update to the version from the branch. + * In gprof(1), remove references to monitor(3) and profil(2). + + -- Matthias Klose Wed, 08 Oct 2008 15:27:50 +0200 + +binutils (2.18.92.20081003-0ubuntu2) intrepid; urgency=low + + * Add build dependency on zlib1g-dev. + + -- Matthias Klose Tue, 07 Oct 2008 12:52:33 +0200 + +binutils (2.18.92.20081003-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the 2.19 branch 20081003 (corresponding to the + 2.18.92 upstream snapshot. + * Stop building binutils-gold for the intrepid release (still + experimental). + * debian/*.shlibs: Update to the version from the branch. + + -- Matthias Klose Fri, 03 Oct 2008 11:16:43 +0000 + +binutils (2.18.91.20080923-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the 2.19 branch 20080923 (corresponding to the + 2.18.91 upstream snapshot. + * debian/*.shlibs: Update to the version from the branch. + * debian/patches/201-hjl-bfd-ref_addr.dpatch: Remove, integrated upstream. + * Fail the build if the testsuite shows regressions compared to the + last (installed) build. + + -- Matthias Klose Tue, 23 Sep 2008 13:22:34 +0200 + +binutils (2.18.90.20080910-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the 2.19 branch 20080910. + - No testsuite regressions on amd64, i386, lpia, sparc. + * debian/*.shlibs: Update to the version from the branch. + * debian/patches/201-hjl-bfd-ref_addr.dpatch: Update. + + -- Matthias Klose Sat, 13 Sep 2008 19:40:31 +0200 + +binutils (2.18.50.20080814-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the trunk 20080814. + * debian/*.shlibs: Update to the version from the trunk. + * debian/patches/201-hjl-bfd-ref_addr.dpatch: Update. + * debian/patches/209-hjl-binutils-error.dpatch: Likewise. + + -- Matthias Klose Thu, 14 Aug 2008 16:37:01 +0000 + +binutils (2.18.50.20080806-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the trunk 20080806. + - Fix PR ld/6656, disable gas generated debug info if compiler generated + debug info is seen. LP: #240884. Closes: #481592. + * debian/*.shlibs: Update to the version from the trunk. + * Build binutils-gold for powerpc. + + -- Matthias Klose Wed, 06 Aug 2008 08:39:52 +0200 + +binutils (2.18.50.20080707-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the trunk 20080707. + * debian/*.shlibs: Update to the version from the trunk. + * include/safe-ctype.h: Add #include of ctype.h before redefining + the ctype.h macros (proposed for the trunk). + + -- Matthias Klose Mon, 07 Jul 2008 10:21:30 +0000 + +binutils (2.18.50.20080610-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the trunk 20080610. + * debian/*.shlibs: Update to the version from the trunk. LP: #237461. + + -- Matthias Klose Tue, 10 Jun 2008 17:18:50 +0200 + +binutils (2.18.50.20080530-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the trunk 20080530. + - gold recognizes -z relro and -z norelro. + * debian/rules: Explicitely set SHELL to /bin/bash, build-depend on bash. + * debian/rules: Fix setting of TARGET for cross builds. + * binutils-static: Remove dependency on libc6. LP: #184582. + + -- Matthias Klose Fri, 30 May 2008 23:55:07 +0200 + +binutils (2.18.50.20080509-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the trunk 20080509. + * Add -Wno-format-security to CFLAGS, CXXFLAGS, due to picky default + hardening options. + * Let gold ignore -z relro and -z norelro for now. + * Build gold with -Wno-error. + + -- Matthias Klose Fri, 09 May 2008 11:09:24 +0200 + +binutils (2.18.50.20080507-0ubuntu1) intrepid; urgency=low + + * Snapshot, taken from the trunk 20080507. + * Remove patches applied upstream: 304_pr4476.dpatch, 305_arm-dis.dpatch, + 306_pr4453.dpatch, 307_ld-pic.dpatch, 308_mips-pic.dpatch, + 311_pr5006.dpatch, 312_pr5011.dpatch, 313_pr5025.dpatch. + * Update patches from the hjl releases: 200-hjl-ld-env (not applied), + 206-hjl-binutils-shr.dpatch (not applied), + * Remove patches from the hjl release: 204-hjl-binutils-tls-relro.dpatch, + 208-hjl-libtool-relink.dpatch, 209-hjl-binutils-error.dpatch, + 210-hjl-binutils-signed.dpatch, + * New patches from the hjl release: 212-hjl-bfd-64k.dpatch. + * debian/*.shlibs: Update to the version from the trunk. + * On amd64, i386, lpia and sparc, build a binutils-gold package, + diverting /usr/bin/ld. + + -- Matthias Klose Wed, 07 May 2008 17:41:05 +0200 + +binutils (2.18.1~cvs20080103-4ubuntu1) hardy; urgency=low + + * Merge with Debian unstable; remaining changes: + - Build binutils-static and binutils-static-udeb packages. + + -- Matthias Klose Tue, 22 Apr 2008 12:02:51 +0200 + +binutils (2.18.1~cvs20080103-4) unstable; urgency=medium + + * debian-rules: Remove libiberty in /usr/lib64; workaround for + `gcc -print-multi-os-directory' printing the symlink. + Closes: #473665, #473591. + * Don't include development fiiles in binutils-spu. + * Fix binutils-spu build on ppc64 (Andreas Jochens). Closes: #474116. + * Build libiberty with -fPIC on mips/mipsel (Aurelian Jarno). + + -- Matthias Klose Sat, 05 Apr 2008 11:21:08 +0200 + +binutils (2.18.1~cvs20080103-3) unstable; urgency=low + + [ Arthur Loiret ] + * Build a binutils for spu-elf target on powerpc and ppc64. + - debian/control: Add a binutils-spu package. + - debian/binutils-spu.{postinst,postrm,shlibs}: Add. + * Add sh64-linux-gnu to multiarch targets. + * Fix cross-compilation support. + * Make lintian happier: + - Use ${source:Version}, ${binary:Version} variables. + - Remove -1 from Build-Depends revisions. + - Bump Standards-Version to 3.7.3. + + [ Matthias Klose ] + * Keep the spu elfscripts in bintutils, remove them from binutils-spu. + * debian/patches/307_ld-pic.dpatch: Fix failing ld-shared tests when built + with gcc-4.3. + + -- Matthias Klose Sat, 29 Mar 2008 20:32:35 +0100 + +binutils (2.18.1~cvs20080103-2) unstable; urgency=low + + * debian/patches/306_pr4453.dpatch: Fix PR binutils/4453, taken from + the trunk (Aurelian Jarno). Closes: #363423. + + -- Matthias Klose Fri, 21 Mar 2008 20:49:17 +0100 + +binutils (2.18.1~cvs20080103-0ubuntu1) hardy; urgency=low + + * Update to 20080103 from the binutils-2_18-branch. + - Set version number to 2.18.0 (smaller than the one from the trunk). + * debian/*.shlibs: Update to version from the branch. + * debian/patches/305_arm-dis.dpatch: Fix segfault when disassembling ARM + code. Closes: #438956. + + -- Matthias Klose Thu, 03 Jan 2008 21:26:56 +0000 + +binutils (2.18.1~cvs20071027-1ubuntu2) hardy; urgency=low + + * Do not include static libraries in the multiarch package. + * Install a libiberty compiled with -fPIC as libiberty_pic.a. + LP: #50512. + * Don't include /usr/lib64 for cross packages. Closes: #450429. + + -- Matthias Klose Fri, 23 Nov 2007 12:14:31 +0000 + +binutils (2.18.1~cvs20071027-1ubuntu1) hardy; urgency=low + + * Update to 20071027 from the binutils-2_18-branch. + - Fix PR ld/4988, assertion failures in ld. Closes: #440015. + * debian/*.shlibs: Update to version from the branch. + * Drop the build dependency on expect-tcl8.3, don't run the + testsuite on hppa. + + -- Matthias Klose Sat, 27 Oct 2007 17:33:13 +0000 + +binutils (2.18-1ubuntu1) hardy; urgency=low + + * Rebuild using gcc-4.2. + + -- Matthias Klose Sun, 21 Oct 2007 08:31:26 +0000 + +binutils (2.18-1) unstable; urgency=low + + [ Matthias Klose ] + * New upstream release. + - Remove patches applied upstream: 100_warning_arm, 400_gcc42_fix, + 401_builddoc. + * debian/*.shlibs: Update to release version. + + -- Matthias Klose Wed, 29 Aug 2007 01:07:31 +0200 + +binutils (2.18-0ubuntu3) gutsy; urgency=low + + * Apply patches for: + - PR binutils/5011, readelf reads past end of buffer. + - PR ld/5025, downgrade error to a warning if .note.gnu.build-id + has been discarded. + + -- Matthias Klose Wed, 19 Sep 2007 00:31:23 +0200 + +binutils (2.18-0ubuntu2) gutsy; urgency=low + + * Apply fix for PR ld/5008, taken from the trunk. + + -- Matthias Klose Sun, 09 Sep 2007 22:08:19 +0200 + +binutils (2.18-0ubuntu1) gutsy; urgency=low + + * Final 2.18 release. + * debian/*.shlibs: Update to release version. + + -- Matthias Klose Wed, 29 Aug 2007 13:22:09 +0200 + +binutils (2.18~cvs20070827-0ubuntu1) gutsy; urgency=low + + * New upstream CVS snapshot, taken from the binutils-2_18-branch. + - Remove patches applied upstream: 311_sse4_intel_mode, 400_gcc42_fix, + 401_builddoc. + * debian/*.shlibs: Update to snapshot version. + + -- Matthias Klose Mon, 27 Aug 2007 19:30:21 +0200 + +binutils (2.18~cvs20070812-0ubuntu1) gutsy; urgency=low + + * New upstream CVS snapshot, taken from the binutils-2_18-branch. + * debian/rules: Support parallel= with comma separated keywords + in DEB_BUILD_OPTIONS. + * debian/rules (clean): Remove stamp files. + * debian/*.shlibs: Update to snapshot version. + * debian/patches/401_builddoc.dpatch: Fix doc build failure on the branch. + * debian/patches/311_sse4_intel_mode.dpatch: Fix SSE4 for Intel mode. + * Update patches: 200-hjl-ld-env (not applied), 203-hjl-binutils-indirect, + 204-hjl-binutils-tls-relro, 209-hjl-binutils-error, + * Remove patches: 201-hjl-bfd-dwarf-dup.dpatch, 201-hjl-bfd-dwarf-dup, + 205-hjl-bfd-kept, 208-hjl-libtool-relink. + * New patches: 210-hjl-binutils-signed, 211-hjl-binutils-weakdef. + + -- Matthias Klose Sun, 12 Aug 2007 12:42:57 +0200 + +binutils (2.17.20070804cvs-0ubuntu1) gutsy; urgency=low + + * New upstream CVS snapshot. + - PR binutils/4888, fixes objcopy --only-keep-debug. Closes: #435444. + * debian/rules: Support parallel= in DEB_BUILD_OPTIONS (see #209008). + * debian/*.shlibs: Update to snapshot version. + * Build using the default compiler on all architectures. + + -- Matthias Klose Sat, 04 Aug 2007 11:29:10 +0000 + +binutils (2.17.20070801cvs-0ubuntu2) gutsy; urgency=low + + * Build-depend on gcc-4.1 on lpia, since we're calling it explicitely. + + -- Adam Conrad Fri, 3 Aug 2007 13:24:26 +1000 + +binutils (2.17.20070801cvs-0ubuntu1) gutsy; urgency=low + + * CVS snapshot 20070801, taken from the trunk. + - Fixes objcopy --only-keep-debug on amd64. + + -- Matthias Klose Wed, 01 Aug 2007 18:46:10 +0200 + +binutils (2.17.20070718cvs-0ubuntu2) gutsy; urgency=low + + * debian/patches/305_ungetc.dpatch: Allow UNGETC to work with empty buffer, + taken from CVS HEAD. + + -- Matthias Klose Fri, 20 Jul 2007 12:47:44 +0200 + +binutils (2.17.20070718cvs-0ubuntu1) gutsy; urgency=low + + * CVS snapshot 20070718, taken from the trunk. + * Fix cross build failure while stripping binaries. Closes: #432907. + + -- Matthias Klose Wed, 18 Jul 2007 15:19:15 +0000 + +binutils (2.17.20070713cvs-0ubuntu2) gutsy; urgency=low + + * Fix build failure with gcc-4.2. + + -- Matthias Klose Tue, 17 Jul 2007 11:09:25 +0000 + +binutils (2.17.20070713cvs-0ubuntu1) gutsy; urgency=low + + * CVS snapshot 20070713, taken from the trunk. + - Remove patches applied upstream: 301_pr4436.dpatch, 302_pr4448.dpatch, + 303_pr4454.dpatch, 305_pr4497.dpatch, 306_ld_demangler_segfault.dpatch, + 307_pr4558.dpatch. + * Update hjl patches: + - Remove 207-hjl-libtool-archive.dpatch. + - Add 201-hjl-bfd-dwarf-dup.dpatch, 209-hjl-binutils-error.dpatch. + - Update 200-hjl-ld-env.dpatch, 201-hjl-bfd-ref_addr.dpatch, + 204-hjl-binutils-tls-relro.dpatch, hjl-binutils-shr.dpatch. + * debian/copyright: Include GPL-3. + * debian/rules: Fix version extraction. + * debian/rules: Honor `noopt' in DEB_BUILD_OPTIONS. Closes LP: #65607. + * debian/patches/013_bash_in_ld_testsuite.dpatch: Use bash in the ld + testsuite. Closes LP: #124435. + + -- Matthias Klose Fri, 13 Jul 2007 15:43:07 +0200 + +binutils (2.17.20070426cvs-7ubuntu2) gutsy; urgency=low + + * Fix PR gas/4558. + + -- Matthias Klose Mon, 28 May 2007 08:48:33 +0000 + +binutils (2.17.20070426cvs-7ubuntu1) gutsy; urgency=low + + * Merge with Debian. + + -- Matthias Klose Fri, 25 May 2007 08:24:08 +0200 + +binutils (2.17cvs20070426-7) unstable; urgency=low + + * 306_ld_demangler_segfault.dpatch: new CVS patch from Alan Modra to fix + segfaults in ld seen when building, e.g. openipmi. + + * debian/copyright: update source location and copyright years. + * debian/rules: idem. + + -- James Troup Wed, 23 May 2007 02:19:09 +0100 + +binutils (2.17cvs20070426-6) unstable; urgency=low + + * Fix PR ld/4497, regression introduced with the fix for PR ld/4454. + Closes: #423496. + * Fix binutils/4476, readelf support for --hash-style=gnu. Closes: #421790. + + -- Matthias Klose Mon, 14 May 2007 10:51:40 +0200 + +binutils (2.17cvs20070426-5) unstable; urgency=low + + * Fix PR ld/4454. + + -- Matthias Klose Sun, 06 May 2007 09:50:29 +0200 + +binutils (2.17cvs20070426-4) unstable; urgency=low + + * Fix PR gas/4448, overstrict check for powerpc lswi. Closes: #421799. + + -- Matthias Klose Wed, 2 May 2007 18:26:03 +0200 + +binutils (2.17cvs20070426-3) unstable; urgency=low + + * Update debian/*.shlibs files. Closes: #421454. + * Fix PR gas/4436, wrong reject in powerpc opcode table checks. + Closes: #421455. + * Fix build failure on arm (Aurelian Jarno). Closes: #421365. + * Compare testsuite results of the installed binutils with the built one. + + -- Matthias Klose Mon, 30 Apr 2007 07:47:09 +0200 + +binutils (2.17.20070426cvs-2ubuntu7) gutsy; urgency=low + + * Fix PR ld/4497, regression introduced with the fix for PR ld/4454. + + -- Matthias Klose Mon, 14 May 2007 08:13:50 +0000 + +binutils (2.17.20070426cvs-2ubuntu6) gutsy; urgency=low + + * Fix binutils/4476, readelf support for --hash-style=gnu. + + -- Matthias Klose Thu, 10 May 2007 07:32:28 +0000 + +binutils (2.17.20070426cvs-2ubuntu5) gutsy; urgency=low + + * Fix PR ld/4454. + + -- Matthias Klose Sun, 06 May 2007 13:02:11 +0000 + +binutils (2.17.20070426cvs-2ubuntu4) gutsy; urgency=low + + * Fix PR gas/4448, overstrict check for powerpc lswi. + + -- Matthias Klose Wed, 2 May 2007 13:42:10 +0200 + +binutils (2.17.20070426cvs-2ubuntu3) gutsy; urgency=low + + * Update debian/*.shlibs files. + * Fix PR gas/4436, wrong reject in powerpc opcode table checks. + + -- Matthias Klose Mon, 30 Apr 2007 08:02:30 +0200 + +binutils (2.17.20070426cvs-2ubuntu2) gutsy; urgency=low + + * Add binutils-udeb as a dist file with priority optional. + + -- Matthias Klose Fri, 27 Apr 2007 17:27:23 +0200 + +binutils (2.17.20070426cvs-2ubuntu1) gutsy; urgency=low + + * Merge with Debian. + + -- Matthias Klose Fri, 27 Apr 2007 10:16:54 +0200 + +binutils (2.17cvs20070426-2) unstable; urgency=low + + * Fix typo preparing the binutils-hppa64 package. Closes: #421199. + * Compare testsuite results of the installed binutils with the built one. + + -- Matthias Klose Fri, 27 Apr 2007 08:06:49 +0200 + +binutils (2.17cvs20070426-1) unstable; urgency=low + + [ James Troup ] + * New upstream CVS snapshot. + * debian/test-suite-compare.py: simplistic comparator for binutils test + suite runs. + + [ Matthias Klose ] + * Merge changes from the experimental uploads: + * debian/patches/121_i386_x86_64_biarch.dpatch: Remove, applied upstream. + * Build a binutils-source package (containing the patched sources). + * Check for a working expect before building the package. + * Configure the multiarch build for x86_64-linux-gnu instead of + x86_64-linux. + * debian/rules: Don't strip binaries if nostrip is in DEB_BUILD_OPTIONS. + * debian/rules: Don't try to strip shell scripts. + * Configure --with-pkgversion to include the distribution name. + * debian/patches/000_print_debian_version.dpatch: Remove. + * debian/control: Build-depend on lsb-release. + * Enable spu target in powerpc and binutils-multiarch build. + * Don't include embedspu in binutils-multiarch on powerpc. + * debian/control: Set priority for source package to optional. + + -- James Troup Fri, 27 Apr 2007 01:29:57 +0100 + +binutils (2.17.20070420cvs-0ubuntu1) gutsy; urgency=low + + * CVS snapshot 20070420, taken from the trunk. + - debian/patches/007_binutils_soversion.dpatch: Remove, applied upstream. + + -- Matthias Klose Fri, 20 Apr 2007 13:46:05 +0200 + +binutils (2.17.20070406cvs-0ubuntu1) toolchain-test; urgency=low + + * CVS snapshot 20070406, taken from the trunk. + * Do not apply: 200-hjl-ld-env. + * Enable spu target in powerpc, ppc64 builds and in the + binutils-multiarch build. + * Don't include embedspu in binutils-multiarch on powerpc, ppc64. + Closes: #411486. + + -- Matthias Klose Fri, 6 Apr 2007 06:57:41 +0200 + +binutils (2.17.20070329cvs-0ubuntu1) toolchain-test; urgency=low + + * CVS snapshot 20070329, taken from the trunk. + * Patches from the hjl 2.17.50.0.13 release: + - 202-hjl-binutils-check-phdr: Remove, applied upstream. + - 205-hjl-bfd-kept.dpatch: Address the link speed issue by caching + the result of _bfd_elf_check_kept_section. + - 206-hjl-binutils-shr.dpatch: Implementation of ELF sharable section + proposal (not applied by default). + - 208-hjl-libtool-relink.dpatch: Avoid unnecessary linker messages + when running "make check". + + -- Matthias Klose Thu, 29 Mar 2007 07:16:28 +0200 + +binutils (2.17.20070321cvs-0ubuntu2) toolchain-test; urgency=low + + * Configure --with-pkgversion, not including the package version, + which may break ld version detection in configure scripts. + * debian/patches/000_cvs_version_string.dpatch: Remove. + * debian/patches/007_binutils_soversion.dpatch: Use date for non-release + builds in soversion. + + -- Matthias Klose Thu, 22 Mar 2007 07:01:14 +0100 + +binutils (2.17.20070321cvs-0ubuntu1) toolchain-test; urgency=low + + * CVS snapshot 20070321, taken from the trunk. + * debian/patches/000_print_{debian,ubuntu}_version.dpatch: Remove. + * debian/control: Build-depend on lsb-release. + * Configure --with-pkgversion to include the distribution name. + * Apply patches from the hjl 2.17.50.0.13 release: + - 200-hjl-ld-env.dpatch: Handle LD_SYMBOLIC and LD_SYMBOLIC_FUNCTIONS + env vars. + - 201-hjl-bfd-ref_addr.dpatch: Support DW_FORM_ref_addr in Dwarf 2 reader + in linker. + - 202-hjl-binutils-check-phdr.dpatch: Fix PR ld/4007: Linker failed + to issue an error on bad section in segment. + - 203-hjl-binutils-indirect.dpatch: PR ld/3351; avoid linker crash on ia64. + - 204-hjl-binutils-tls-relro.dpatch: PR binutils/3281; objcopy changes + PT_GNU_RELRO when there is PT_TLS. + - 207-hjl-libtool-archive.dpatch: Allow linking against an archive when + building a shared library. + * Set Ubuntu maintainer address. + + -- Matthias Klose Wed, 21 Mar 2007 09:17:21 +0100 + +binutils (2.17.20070210cvs-1ubuntu1) toolchain-test; urgency=low + + * Merge with Debian experimental; remaining changes: + - Build binutils-static and binutils-static-udeb packages. + + -- Matthias Klose Mon, 12 Feb 2007 16:03:23 +0100 + +binutils (2.17.20070210cvs-1) experimental; urgency=low + + * CVS snapshot 20070210, taken from the trunk. + * debian/rules: Don't try to strip shell scripts. + + -- Matthias Klose Sat, 10 Feb 2007 15:59:45 +0100 + +binutils (2.17.20070103cvs-2) experimental; urgency=low + + * Overwrite the VERSION string (date) from the snapshot with + a parsable version string (2.17.50), as found on the trunk. + + -- Matthias Klose Fri, 5 Jan 2007 10:06:09 +0100 + +binutils (2.17.20070103cvs-1) experimental; urgency=low + + * binutils snapshot 20070103, taken from + ftp://sourceware.org/pub/binutils/snapshots/ + * Build a binutils-source package (containing the patched sources). + * Check for a working expect before building the package. + * Configure binutils-multiarch for i486-gnu as well. + * Configure the multiarch build for x86_64-linux-gnu instead of + x86_64-linux. + * debian/rules: Don't strip binaries if nostrip is in DEB_BUILD_OPTIONS. + + -- Matthias Klose Thu, 4 Jan 2007 22:13:54 +0100 + +binutils (2.17.20070103cvs-0ubuntu1) feisty; urgency=low + + * binutils snapshot 20070103, taken from + ftp://sourceware.org/pub/binutils/snapshots/ + * Merge with Debian experimental; remaining changes: + - Build binutils-static and binutils-static-udeb packages. + - Build a binutils-source package (containing the patched + sources). + - Check for a working expect before building the package. + - Configure binutils-multiarch for i486-gnu as well. + * Configure the multiarch build for x86_64-linux-gnu instead of + x86_64-linux. + * debian/rules: Don't strip binaries if nostrip is in DEB_BUILD_OPTIONS. + * Strip binaries in binutils-static and in the binutils udeb. + + -- Matthias Klose Thu, 4 Jan 2007 15:17:45 +0100 + +binutils (2.17.20061210cvs-1) experimental; urgency=low + + * CVS snapshot 20061210, taken from the trunk. + * debian/patches/121_i386_x86_64_biarch.dpatch: Remove, applied upstream. + + -- Matthias Klose Sun, 10 Dec 2006 20:43:41 +0100 + +binutils (2.17.20070103cvs-0ubuntu2) feisty; urgency=low + + * Overwrite the VERSION string (date) from the snapshot with + a parsable version string (2.17.50), as found on the trunk. + + -- Matthias Klose Fri, 5 Jan 2007 09:02:06 +0000 + +binutils (2.17.50.0.6-0ubuntu1) feisty; urgency=low + + [Fabio M. Di Nitto] + + * we are supposed to upload to feisty, aren't we? ;) + + [Jeff Bailey] + + * New upstream snapshot from HJ Lu. + * debian/patches/121_i386_x86_64_biarch: Drop, merged upstream. + + -- Fabio M. Di Nitto Tue, 31 Oct 2006 15:43:58 +0100 + +binutils (2.17-3) unstable; urgency=low + + * debian/rules (configure-multi-stamp): drop i486-kfreebsd-gnu again as + it breaks objdump for i386 on amd64. Closes: #380539 + + -- James Troup Tue, 3 Oct 2006 00:53:17 +0100 + +binutils (2.17-2) unstable; urgency=low + + * The "Laisse le Wookie gagner" release. + + * 127_x86_64_i386_biarch.dpatch: new patch from Aurelien Jarno + to add (/usr)/lib32 to the search paths on + amd64. Closes: #369052 + + * debian/rules (configure-multi-stamp): add i486-kfreebsd-gnu at request + of Aurelien Jarno. Closes: #315306 + + -- James Troup Wed, 26 Jul 2006 20:33:13 +0100 + +binutils (2.17-1ubuntu1) edgy; urgency=low + + * New upstream release. + - ld checks for libs in the same order as ld.so does. Ubuntu #40214. + * Synchronise with Debian unstable. + * Remove patch 122_sparc64_UA2005_instruction_set.dpatch, integrated + upstream. + * Remove patch 130_tekhex_buffer_overflow.dpatch, integrated upstream. + * 122_x86_64_i386_biarch.dpatch: New, search libraries in (/usr)/lib32 on + amd64. Closes: #369052. + * Build a binutils-source package; obsoletes toolchain-source package. + + -- Matthias Klose Wed, 28 Jun 2006 10:29:16 +0200 + +binutils (2.17-1) unstable; urgency=low + + * New upstream release. + * 120_mips_xgot_multigot_workaround.dpatch: removed - superseded by a + proper fix upstream. Closes: #274738 + * debian/binutils.shlibs, debian/binutils-multiarch.shlibs, + debian/binutils-hppa64.shlibs: updated SONAME to 2.17. + + -- James Troup Mon, 26 Jun 2006 13:17:36 +0100 + +binutils (2.16.1cvs20060507-1) unstable; urgency=low + + * New upstream CVS snapshot of 'binutils-2_17-branch'. + + * debian/control (Standards-Version): bump to 3.7.2.0. + + -- James Troup Sun, 7 May 2006 19:57:08 +0100 + +binutils (2.16.1cvs20060413-1) unstable; urgency=low + + * New upstream CVS snapshot. + * 120_mips_xgot_multigot_workaround.dpatch: updated to work with CVS + r1.163 of bfd/elfxx-mips.c, pass 'info' instead of 'output_bfd' to + MIPS_ELF_GOT_MAX_SIZE(). + + * Patch from NIIBE Yutaka in #280884: + * debian/rules (configure-multi-stamp): Support m32r-linux. Closes: + #340264 + * debian/rules: Run 'make check' only if build == host. + + * debian/rules: Also don't run 'make check' if nocheck is in + DEB_BUILD_OPTIONS. Based on a patch from Michael Banck + . Closes: #315290 + + * Integrate most of a patch to build arbitrary binutils-$TARGET + cross-packages from #231707. Thanks to Nikita V. Youshchenko + and Josh Triplett . + + * debian/copyright: update to include GFDL. Closes: #81950 + * debian/copyright: update FSF address. + + * debian/rules: move non-architecture specific conflicts (gas, + elf-binutils, modutils (<< 2.4.19-1)) out of a substitued variable and + into the control file. Rename variable to extraConflicts. + * debian/control: likewise. + + -- James Troup Sat, 15 Apr 2006 03:05:41 +0100 + +binutils (2.16.1cvs20060117-1ubuntu2.1) dapper-security; urgency=low + + * SECURITY UPDATE: Crash and possible arbitrary code execution in apps using + libbfd (such as 'strings'). + * Add debian/patches/130_tekhex_buffer_overflow.dpatch: + - Fix buffer overflow on hexadecimal number parsing in the Tektronix Hex + Format BFD library backend. + - Patch ported from CVS HEAD. + * CVE-2006-2362 + + -- Martin Pitt Tue, 6 Jun 2006 11:35:55 +0200 + +binutils (2.16.1cvs20060117-1ubuntu2) dapper; urgency=low + + * [SPARC64] Add support for new UA2005 instruction set: + - Add patch 122_sparc64_UA2005_instruction_set.dpatch. + (Thanks David S. Miller for providing the patch) + + NOTE: the patch is sparc specific and does NOT touch any other code. + It is a plain rebuild on all other arches. + + -- Fabio M. Di Nitto Sat, 25 Feb 2006 07:11:28 +0100 + +binutils (2.16.1cvs20060117-1ubuntu1) dapper; urgency=low + + * Synchronise with Debian untstable. + + -- Matthias Klose Thu, 19 Jan 2006 09:21:47 +0100 + +binutils (2.16.1cvs20060117-1) unstable; urgency=low + + * New upstream CVS snapshot. + + * 118_arm_pass_all.dpatch, 125_fix_tc_arm_cast.dpatch: merged upstream - + removed. + + -- James Troup Wed, 18 Jan 2006 02:25:25 +0000 + +binutils (2.16.1cvs20051214-1ubuntu1) dapper; urgency=low + + * Synchronise with Debian unstable. + + -- Matthias Klose Thu, 15 Dec 2005 00:11:16 +0000 + +binutils (2.16.1cvs20051214-1) unstable; urgency=low + + * New upstream CVS snapshot. + * Fix ld segfaults on ia64. Closes: #342777 + + * 126_fix_PROVIDE_HIDDEN.dpatch: merged upstream - removed. + + -- James Troup Wed, 14 Dec 2005 08:06:37 +0000 + +binutils (2.16.1cvs20051206-1) unstable; urgency=low + + * New upstream CVS snapshot. + * Fixes linking of qemu. Closes: #340328 + + * 126_fix_PROVIDE_HIDDEN.dpatch: new patch from Thiemo Seufer to fix + handling of hidden symbols which were provided by a linker + script. Closes: #342307 + + * debian/control (Standards-Version): updated to 3.6.2.1. + + -- James Troup Sat, 10 Dec 2005 05:23:34 +0000 + +binutils (2.16.1cvs20051117-1ubuntu1) dapper; urgency=low + + * Synchronise with Debian unstable. + + -- Matthias Klose Fri, 18 Nov 2005 14:09:29 +0100 + +binutils (2.16.1cvs20051117-1) unstable; urgency=low + + * New upstream CVS snapshot. + * Fixes c++filt's flushing of stdout which broke gcj. Closes: #339287 + + * debian/control (Build-Depends): switch from expect to expect-tcl8.3 + since tcl8.4's broken threading causes the testsuite to fail entirely + on hppa. Closes: #339509 + + -- James Troup Thu, 17 Nov 2005 13:15:15 +0000 + +binutils (2.16.1cvs20051109-1ubuntu1) dapper; urgency=low + + * Synchronise with Debian unstable. + * Reenable the testsuite on hppa and sparc. + * debian/control: + - Set standards version to 3.6.2 (no changes). + - Add alternative build dependency on expect-tcl8.3. + + -- Matthias Klose Mon, 14 Nov 2005 10:52:27 +0100 + +binutils (2.16.1cvs20051109-1) unstable; urgency=low + + * New upstream CVS snapshot. + * Fixes broken PLT handling on m68k. Closes: #327780 + * Don't compile flex files with -Werror, fixing mips builds. + Closes: #333980 + * Don't check undefined symbols introduced by "ld -u" for TLS. Closes: + #326103 + + * 117_mips_symbolic_link.dpatch: merged upstream - removed. + + * debian/rules: pass --disable-werror on ia64 as current gcc generates + too many false positives. Closes: #336939 + + * 125_fix_tc_arm_cast.dpatch: new patch from Lennert Buytenhek to fix + cast warning and arm builds. Closes: #336175 + + * 121_i386_x86_64_biarch.dpatch: imported from Ubuntu at request of + Daniel Jacobwitz to fix biarch linking on i386/amd64. Closes: + #334626, #334673 + + * debian/rules: remove any reference to pkgstriptranslations - an + Ubuntu-ism that shouldn't have been in the Debian package in the first + place but that isn't needed in Ubuntu any more in any event. + + * debian/rules: MAKEOVERRIDES is now clobbered by the top level + Makefile, so switch to overriding MAKE itself (sic) to pass the + customized VERSION variable/string down to sub-directories for + -multiarch and -hppa64 builds. Thanks to Daniel Silverstone for the + suggestion. + + -- James Troup Fri, 11 Nov 2005 20:38:22 +0000 + +binutils (2.16.1cvs20050902-1) unstable; urgency=low + + * New upstream CVS snapshot. + * Fixes --as-needed on sparc and hppa. Closes: #320697 + * Fixes buffer overflows and other crashes. Closes: #311975 + + * 124_readelf_robustify.dpatch: merged upstream - removed. + * 001_ld_makefile_patch: regenerated with help of wiggle. + + * debian/*.shlibs: update to version 2.16.91. + + * debian/copyright: use canonical GNU URL. Update copyright years. + * debian/rules: update version and copyright. + + * debian/rules (pre-build): not relevant with a CVS snapshot which + doesn't have pre-generated info files - removed. + * debian/rules (clean): don't save info files for the same reason, in + fact explicitly remove them. + * debian/rules (build_stamps): drop pre-build. + + -- James Troup Sat, 3 Sep 2005 00:30:56 +0100 + +binutils (2.16.1-3) unstable; urgency=low + + * debian/rules: remove powerpc libc header hack. + * debian/include/sys/procfs.h: remove. + + * 124_readelf_robustify.dpatch: new patch from Jakub Jelinek to + robustify readelf. Thanks to Thiemo Seufer . + Closes: #318344 + + -- James Troup Wed, 31 Aug 2005 05:03:11 +0100 + +binutils (2.16.1-2ubuntu7) dapper; urgency=low + + * debian/rules: Stop calling pkgstriptranslations, we now get it + for free with the new and improved dpkg-deb diversion hack. + + -- Adam Conrad Wed, 26 Oct 2005 10:39:15 +1000 + +binutils (2.16.1-2ubuntu6) breezy; urgency=low + + * debian/control: Create a new binutils-static-udeb udeb for d-i. + * debian/rules: Copy stuff from -static to -static-udeb for above. + * debian/rules: compress changelog in /usr/share/doc/binutils-static + + -- Adam Conrad Tue, 4 Oct 2005 16:51:06 +1000 + +binutils (2.16.1-2ubuntu5) breezy; urgency=low + + [ Jeff Bailey ] + * debian/control: binutils-static no longer depends on binutils. + * debian/rules: Install the copyright and changelog into + /usr/share/doc/binutils-static. + + [ Adam Conrad ] + * debian/binutils-static.preinst: Make sure that we lose our doc + symlink before we upgrade, or some Very Bad Things could happen. + * debian/rules: Make the above get installed to the right location. + + -- Adam Conrad Tue, 4 Oct 2005 15:45:12 +1000 + +binutils (2.16.1-2ubuntu4) breezy; urgency=low + + The " jbailey: how soon should I expect an upload?" release. + + * debian/patches/122_sparc_hppa_got.dpatch: New patch to allow + --as-needed on sparc, and to avoid issues with duplicate + GLOBAL_OFFSET_TABLES on hppa. + + * debian/patches/00list.sparc: New file, add this patch there. + + * debian/patches/00list.hppa: New file, add this patch there. + + -- Jeff Bailey Wed, 31 Aug 2005 16:46:13 -0400 + +binutils (2.16.1-2ubuntu3) breezy; urgency=low + + * debian/patches/121_i386_x86_64_biarch: New patch to allow + ld to work in an i386/x86_64 biarch configuration. + + -- Jeff Bailey Fri, 5 Aug 2005 16:24:23 +0000 + +binutils (2.16.1-2ubuntu2) breezy; urgency=low + + * debian/rules: Call it /bin/ld_static, not /bin/ld to avoid + confusion. + + -- Jeff Bailey Tue, 26 Jul 2005 01:34:43 +0000 + +binutils (2.16.1-2ubuntu1) breezy; urgency=low + + * debian/rules: Add binutils-static pass. This provides /bin/ld + for use in linking objects that might be needed at boot time + for mounting /usr or /. + Also remove stamps when cleaning. + + -- Jeff Bailey Tue, 26 Jul 2005 00:12:07 +0000 + +binutils (2.16.1-2) unstable; urgency=low + + * debian/include/sys/procfs.h: Include fixed powerpc libc header, to fix + FTBFS on powerpc. Temporary fix, to be removed with glibc-2.3.5. + + -- Matthias Klose Sun, 10 Jul 2005 16:35:17 +0200 + +binutils (2.16.1-1) unstable; urgency=medium + + * New upstream version. + * debian/patches/117_mips_symbolic_link.dpatch: Updated, apply it again. + (Thiemo Seufer). + * debian/patches/130_bfd_doc_makefile.dpatch: Remove, applied upstream. + * debian/control: Build depend on dpkg-dev (>= 1.13.9), needed to determine + the GNU architecture type. + * The symlinks for the tools change to the the new output of + dpkg-architecture -qDEB_HOST_GNU_TYPE (i.e. i386-linux-ld becomes + i486-linux-gnu-ld). + * Change the values for --enable-targets according to the dpkg-architecture + update. + * Configure the hppa64 cross compiler for hppa64-linux-gnu. Adjust + the hppa64 install target. + * debian/*shlibs: Update to version 2.16.1. + * Make restoring of saved pregenerated info files more robust. + + -- Matthias Klose Sat, 9 Jul 2005 14:58:49 +0200 + +binutils (2.16-1) unstable; urgency=low + + * Update to CVS 2.16 branch 20050612. + * debian/patches/130_bfd_doc_makefile.dpatch: New patch to fix + build failure in bfd/doc. + * debian/watch: New file. + + -- Matthias Klose Sun, 12 Jun 2005 12:29:12 +0200 + +binutils (2.16-0) experimental; urgency=low + + * New upstream release. + - Fixes build failure using gcc-4.0 (closes: #299671). + * debian/patches: + - 000_print_debian_version.dpatch: Updated. + - 001_ld_makefile_patch.dpatch, 002_gprof_profile_arcs.dpatch, + 002_gprof_profile_arcs.dpatch: Regenerated. + - 012_check_ldrunpath_length.dpatch: Updated. + - 112_fix_reloc_sizing.dpatch, 113_elf_backend_hide_symbol.dpatch, + 114_mips_delay_slots_in_branch.dpatch, 115_fix_sparc_fmov.dpatch, + 116_ar_nonexistent_files.dpatch: Removed, applied upstream. + - 117_mips_symbolic_link.dpatch: Disabled. Needs an update. + - 118_arm_pass_all.dpatch: Regenerated. + - 119_fix_gas_double_negative.dpatch: Removed, applied upstream. + - 120_mips_xgot_multigot_workaround.dpatch: Updated. + - 121_ia64_unwind_fixes.dpatch, 122_m68k_undefweak_symbols.dpatch: + Removed, applied upstream. + * Merge Ubuntu changes: + - debian/patches: + - 123_dont_add_to_undefs_twice.dpatch: Removed, applied upstream. + - debian/rules: Call pkgstriptranslations if present. + * debian/rules: + - Fix VERSION extraction. + - Save info files before build and restore them in clean target. + * debian/control: + - Add me as an uploader. + + -- Matthias Klose Fri, 6 May 2005 18:43:09 +0200 + +binutils (2.15-6) unstable; urgency=low + + * 123_bfd_overflow_fix.dpatch: new patch from Alan Modra to fix BFD + overflows. Closes: #308625 + + -- James Troup Sat, 21 May 2005 20:20:01 +0100 + +binutils (2.15-5ubuntu2) hoary; urgency=low + + * debian/rules: Call pkgstriptranslations if present (the package does not + use debhelper, thus it does not happen automatically). + + -- Martin Pitt Fri, 18 Mar 2005 13:07:52 +0000 + +binutils (2.15-5ubuntu1) hoary; urgency=low + + * 123_dont_add_to_undefs_twice.dpatch: new patch from Alan Modra (PR338) to + not add symbols to the undefined list twice, causing an assertion failure + in ld when building the kernel on amd64. + + -- Daniel Stone Tue, 7 Dec 2004 09:29:31 +0100 + +binutils (2.15-5) unstable; urgency=low + + * 121_ia64_unwind_fixes.dpatch: new patch from David Mosberger to fix + unwind related bugs. Closes: #278836 + * 122_m68k_undefweak_symbols: new patch from Andreas Schwab to fix undef + weak symbols with non-default visibilty on m68k. Closes: #278388 + + -- James Troup Thu, 25 Nov 2004 00:13:28 +0000 + +binutils (2.15-4) unstable; urgency=low + + * 120_mips_xgot_multigot_workaround.dpatch: new patch from Thiemo Seufer + to make multigot/xgot handling exclusive and fix mozilla builds on + mipsen. Closes: #272149 + + -- James Troup Thu, 23 Sep 2004 22:44:03 +0100 + +binutils (2.15-3) unstable; urgency=low + + * 112_fix_reloc_sizing.dpatch: update patch based on revised change from + Alan Modra. + + * 116_ar_nonexistent_files.dpatch: new patch from Nick Clifton to fix + ar's handling of non-existent files. Closes: #267139 + + * 117_mips_symbolic_link.dpatch: new patch from Thiemo Seufer to fix the + "final link failed: Bad value" error on mips. Closes: #270619 + + * 118_arm_pass_all.dpatch: new kludge patch to fix broken libtool pass_all + handling on arm and other arches. + + * 119_fix_gas_double_negative.dpatch: new patch from Alan Modra via + Daniel Jacobowitz to fix gas' handling of -- and ++. Closes: #266772 + + -- James Troup Thu, 9 Sep 2004 22:24:08 +0100 + +binutils (2.15-2) unstable; urgency=low + + * 112_fix_reloc_sizing.dpatch: new patch from Daniel Jacobowitz to fix + objcopy relocation sections. Closes: #252719 + + * 113_elf_backend_hide_symbol.dpatch: new patch from Alan Modra to fix + ld internal error on hppa. Closes: #254549 + + * 114_mips_delay_slots_in_branch.dpatch: new patch from Thiemo Seufer to + handle delay slots in branch correctly on mips. Closes: #266660 + + * 115_fix_sparc_fmov.dpatch: new patch from Jakub Jelinek via Dave + Miller to fix bogus fmov* SPARC opcodes. Closes: #267824 + + -- James Troup Tue, 31 Aug 2004 22:45:13 +0100 + +binutils (2.15-1) unstable; urgency=low + + * New upstream release. Closes: #248990, #259458 + * Fixes -Wl,-z,defs to correctly abort builds with unresolved + symbols. Closes: #256481 + * Better error message for truncation of bignums in as. + Closes: #219933 + * strip(1) no longer corrupts binaries for architectures it doesn't + recognise. Closes: #211052 + * nm -C /usr/lib/libcrypto++.a no longer segfaults. Closes: #247917 + + * 105_alpha_rpcc_opcode_fix.dpatch, 106_arm_pic.dpatch, + 107_powerpc_ld_segfault.dpatch, 108_m68k_fmoveml_fix.dpatch, + 109_objcopy_keep_debug.dpatch, 110_hppa64_local_symbols.dpatch, + 111_objcopy_vs_unstripped.dpatch, 906_hjl_libtool_dso.dpatch: merged + upstream - removed. + * 012_check_ldrunpath_length.dpatch: resynced with wiggle(1). + + * debian/binutils.shlibs, debian/binutils-hppa64.shlibs, + debian/binutils-multiarch.shlibs: update for 2.15. + + * debian/rules (install): remove gas.info hack as no longer needed + (fixed properly upstream). + * debian/rules (clean): remove gas/doc/as.info which doesn't seem to be + in the upstream tar ball. + + * debian/rules (binary-arch): install $pkg/ChangeLog.linux only if they + exist (because they don't in GNU releases). + + -- James Troup Thu, 29 Jul 2004 22:44:04 +0100 + +binutils (2.14.90.0.7-8) unstable; urgency=low + + * debian/rules: don't use gcc-2.95 on m68k. Thanks to Adam Conrad for + pointing this out. + + -- James Troup Wed, 19 May 2004 10:35:44 +0100 + +binutils (2.14.90.0.7-7) unstable; urgency=low + + * 111_objcopy_vs_unstripped.dpatch: new patch from Alan Modra via Daniel + Jacobowitz to fix objcopy on unstripped libraries on alpha and arm. + Closes: #234021 + + * debian/control (Build-Depends): remove m68k specific build-depends on + gcc-2.95 and libc6-dev (<< 2.3). Many thanks to Michael Schmitz for + testing this. + + -- James Troup Tue, 30 Mar 2004 18:00:54 +0100 + +binutils (2.14.90.0.7-6) unstable; urgency=low + + * 110_hppa64_local_symbols.dpatch: new patch from Randolph Chung to fix + dynamic name generation of local symbols on hppa64 - needed to build + 64-bit hppa kernels. Closes: #238176 + + -- James Troup Fri, 26 Mar 2004 15:52:27 +0000 + +binutils (2.14.90.0.7-5) unstable; urgency=low + + * 109_objcopy_keep_debug.dpatch: new patch from Daniel Jacobowitz + , objcopy --only-keep-debug and readelf SHT_NOBITS + fixes. + + -- James Troup Mon, 26 Jan 2004 16:25:25 +0000 + +binutils (2.14.90.0.7-4) unstable; urgency=low + + * debian/control: add binutils-hppa64 package. + * debian/rules: add support for binutils-hppa64 package and don't enable + hppa64-linux for binutils or binutils-multiarch. + * debian/binutils-hppa64.postinst: new file. + * debian/binutils-hppa64.postrm: likewise. + * debian/binutils-hppa64.shlibs: likewise. + * Above changes largely based on a patch from Matthias Klose + . Closes: #225892 + + * debian/control (Build-Depends): drop bzip2. + + * debian/rules (install-stamp): remove empty /usr/include directory in + binutils. + * debian/rules (install-stamp): remove /usr/share/info/dir* to + workaround install-info brain damage (cf #213524). + + -- James Troup Thu, 22 Jan 2004 21:32:44 +0000 + +binutils (2.14.90.0.7-3) unstable; urgency=low + + * 108_m68k_fmoveml_fix.dpatch: new patch from H.J. Lu + to fix fmoveml disassembly and associated + testsuite regression on m68k. + + -- James Troup Tue, 18 Nov 2003 14:35:23 +0000 + +binutils (2.14.90.0.7-2) unstable; urgency=low + + * 107_powerpc_ld_segfault.dpatch: new patch from Alan Modra + to fix ld segfault on powerpc. Thanks to + Josselin Mouette for the report. Closes: #219187 + + -- James Troup Wed, 5 Nov 2003 13:32:17 +0000 + +binutils (2.14.90.0.7-1) unstable; urgency=low + + * New upstream release. + * 100_null_owner_ld_fix.dpatch, 101_ppc_as_shf_and_rel_fix.dpatch, + 102_alpha_null_got_ld_fix.dpatch, + 103_static_linking_elf_eh_frame.dpatch, + 104_elf_eh_frame_alpha_fix.dpatch: removed; merged upstream. + * debian/rules: update version number. + * debian/binutils.shlibs: likewise. + * debian/binutils-multiarch.shlibs: likewise. + + * 009_signed_char_fix.dpatch: removed; this was fixed upstream correctly + (http://sources.redhat.com/ml/binutils/2003-05/msg00304.html) and this + patch is breaking that fix. Thanks to Daniel Jacobowitz + . + + * 003_gmon_manpage_fix.dpatch -> 002_gprof_profile_arcs.dpatch. + * 014_gprof_manpage_fix.dpatch -> 003_gprof_see_also_monitor.dpatch. + + * 300_alpha_rpcc_opcode_fix.dpatch -> 105_alpha_rpcc_opcode_fix.dpatch + (committed to trunk). + + * debian/rules (configure-multi-stamp): also enable mips64{el,}-linux + for binutils-multiarch. Alphabetize target list. + + * 106_arm_pic: new patch from Phil Blundell and Daniel + Jacobowitz which implements GC for GOT and PLT relocs + in the elf32-arm backend. + + * debian/rules (install-stamp): work around upstream bug which causes + as.info and as.1 to disappear by explicitly calling "make + install-info-am install-am" in builddir-single/gas/doc. + + -- James Troup Sat, 1 Nov 2003 18:14:04 +0000 + +binutils (2.14.90.0.6-5) unstable; urgency=low + + * 104_elf_eh_frame_alpha_fix.dpatch: new patch from H.J. Lu + to fix regressions on alpha caused by + 103_static_linking_elf_eh_frame. Thanks to Thimo Neubauer + for the original report. Closes: #215636 + + -- James Troup Fri, 17 Oct 2003 00:02:09 +0100 + +binutils (2.14.90.0.6-4) unstable; urgency=low + + * 103_static_linking_elf_eh_frame.dpatch: new patch from H.J. Lu + to fix static linking of C++ binaries. + + * 200_alpha_null_got_ld_fix.dpatch: renamed... + * 102_alpha_null_got_ld_fix.dpatch: to this. + + * debian/rules: patch from Guido Guenther to enable + mips64 support. Closes: #213448 + + -- James Troup Sun, 12 Oct 2003 14:26:26 +0100 + +binutils (2.14.90.0.6-3) unstable; urgency=low + + * 100_null_owner_ld_fix.dpatch: new patch from Alan Modra + to fix an ld crash with null owner sections. + Closes: #212029 + + * debian/rules: don't compile with gcc-2.95 on arm; the only failures + are a) testsuite-only (i.e. don't appear to affect real world + applications) and b) fixed by upcoming gcc patches by Phil Blundell + in any event. + * debian/control (Build-Depends): likewise don't build-depend on + gcc-2.95 for arm. + + * 101_ppc_as_shf_and_rel_fix.dpatch: new patch from Alan Modra + to fix an as regression where it refused to + compile utils.S from Linux/PPC 2.6. Closes: #211668 + + -- James Troup Tue, 23 Sep 2003 01:32:08 +0100 + +binutils (2.14.90.0.6-2) unstable; urgency=low + + * debian/rules (CONFLICTS): remove spurious "--", left over from + debhelper based-rules. Fixes build failure on sparc. + + * 200_alpha_null_got_ld_fix.dpatch: new patch from Daniel Jacobowitz + to fix an ld crash on alpha with null .got sections. + Closes: #204615 + + * scripts/dpkg-arch.mk: remove. + * debian/rules: define DEB_BUILD_GNU_TYPE, DEB_HOST_ARCH and + DEB_HOST_GNU_TYPE here instead. + + * debian/rules (binary-indep): use ':' as a separator to chown, rather + than '.' which is a legal character for a username. + * debian/rules (binary-arch): likewise. + + * debian/rules: further trivial cleanups. + + -- James Troup Thu, 18 Sep 2003 22:13:36 +0100 + +binutils (2.14.90.0.6-1) unstable; urgency=low + + * New "upstream" release. + * Fixes core dump of nm -C on certain object files. Closes: #205616 + + * New maintainer. + * debian/control (Maintainer): adjust accordingly. + * debian/copyright: likewise. Update copyright years, URL. + * debian/control (Standards-Version): bump to 3.6.1.0. + + * 011_disable_combreloc_ARM_ONLY.diff: dropped on request of Phil + Blundell - this is obsolete, it was working around a + bug in ld since fixed by Daniel Jacobowitz upstream. + + * 890-elf64_alpha_segfault.diff: dropped as bogus + (http://sources.redhat.com/ml/binutils/2003-04/msg00399.html); rth's + correct fix is already in the upstream source. + + * debian/README.Debian: migrate nearly-obsolete debconf notes to here. + * debian/control (Depends): drop debconf. + * binutils.config, binutils.templates, binutils.templates.ca, + binutils.templates.fr, binutils.templates.ja, + binutils.templates.pt_BR, postrm.debhelper: obsolete, removed. + Closes: #189641, #198222 + + * Migrated from dbs... + * debian/README.build: obsolete; removed. + * debian/rules: remove $(BUILD_TREE)/, $(STAMP_DIR)/, $(unpacked), $(patched) and other references + to DBS. + * debian/rules (clean): remove build tree directories. + * debian/scripts/dbs-build.mk: unused, remove. + * debian/scripts/file2cat: likewise. + + * ... to dpatch. + * debian/rules: include /usr/share/dpatch/dpatch.make. + * debian/rules (configure-single-stamp): depend on patch-stamp. + * debian/rules (configure-multi-stamp): likewise. + * debian/rules (clean): depend on unpatch. Remove debian/patched. + * debian/control (Build-Depends): add dpatch. + + * binutils-doc.postinst, binutils-doc.prerm, + binutils-multiarch.postinst, binutils-multiarch.postrm, + binutils-multiarch.preinst, binutils-multiarch.shlibs, + binutils.postinst, binutils.postrm, binutils.shlibs: new files based + on .deb and packages.d/. + * scripts/dh_split: obsolete, removed. + * debian/packages.d/binutils-dev.in, debian/packages.d/binutils-doc.in, + debian/packages.d/binutils-multiarch.in, + debian/packages.d/binutils.in: likewise. + + * debian/rules: rewritten, de-debhelper-ized. + * debian/control (Build-Depends): drop debhelper and add file. + + -- James Troup Thu, 11 Sep 2003 22:08:18 +0100 + +binutils (2.14.90.0.5-0.2) unstable; urgency=low + + * NMU. + * Rebuild using fixed gcc on sparc (closes: #202924). + + -- Matthias Klose Mon, 28 Jul 2003 20:12:00 +0200 + +binutils (2.14.90.0.5-0.1) unstable; urgency=low + + * NMU. + * New upstream version. + * Remove patches applied upstream: + - debian/patches/500_s390_gas.diff + - debian/patches/905-hppa_visibility.diff + - debian/patches/906-mips_ld_fix.diff + * Updated patch: + - debian/patches/906-hjl_libtool_dso.diff + + -- Matthias Klose Wed, 23 Jul 2003 20:09:51 +0200 + +binutils (2.14.90.0.4-0.1) unstable; urgency=low + + * NMU + * New upstream version. + 1. Work around the brain dead libtool. + * New patches: + - debian/patches/500_s390_gas.diff (closes: #194929). + - debian/patches/905-hppa_visibility.diff (closes: #195203). + - debian/patches/906-mips_ld_fix.diff (closes: #195207). + - debian/patches/906-hjl_libtool_dso.diff + + -- Matthias Klose Sat, 31 May 2003 12:12:10 +0200 + +binutils (2.14.90.0.3-0.1) unstable; urgency=low + + * NMU + * New upstream version. + 1. Update from binutils 2003 0523. + 2. Fix 2 ELF visibility bugs. + 3. Fix ELF/ppc linker bugs. + * Remove patches applied upstream: + - debian/patches/903-hjl_ld-dso-test.diff + - debian/patches/904_hjl_hppa_whitespace.diff + + -- Matthias Klose Sat, 24 May 2003 09:02:54 +0200 + +binutils (2.14.90.0.2-0.1) unstable; urgency=low + + * NMU + * New upstream version. + 1. Update from binutils 2003 0515. + 2. Fix various ELF visibility bugs. + 3. Fix some ia64 linker bugs. + 4. Add more IAS compatibilities to ia64 assembler. + * New patches: + - debian/patches/903-hjl_ld-dso-test.diff (closes: #193505). + - debian/patches/904_hjl_hppa_whitespace.diff. + * Remove patches applied upstream: + - debian/patches/900_binutils-2.14.90.0.1-empty-test.diff + - debian/patches/901-hjl_weaksymfix.diff + + -- Matthias Klose Sun, 18 May 2003 10:50:00 +0200 + +binutils (2.14.90.0.1-0.1) unstable; urgency=low + + * NMU + * New upstream version. + - Fix: MIPS branch-to-global bug (closes: #189031). + - Fix: Crash on alpha with --gdwarf2 and bad file number (closes: #187211). + - Fix: objdump -R BFD ICE on prelinked binaries (closes: #180088). + * New patches: + - debian/patches/900_binutils-2.14.90.0.1-empty-test.diff + - debian/patches/901-hjl_weaksymfix.diff + * Remove patches applied upstream: + - debian/patches/002_ldlex_inflexible_transition.diff + - debian/patches/013_objdump_doc_fix.diff + - debian/patches/850_hppa_stub_fix.diff + - debian/patches/860_m68k_elf.diff + - debian/patches/861_m68k_elf.diff + - debian/patches/870-sparc64-update.diff + - debian/patches/880-alpha-update.diff + * Remove obsolete patch: + - debian/patches/patches/800_hjl_mips_fixes.diff + * Add x86_64 for the i386 binutils package and the binutils-multiarch + package (closes: #189350). + * Set CFLAGS to -g -O2 for build (closes: #181268). + + -- Matthias Klose Tue, 6 May 2003 09:58:14 +0200 + +binutils (2.13.90.0.18-1.7) unstable; urgency=high + + * NMU + * Fixed ld segv (replaced yy_current_buffer by YY_CURRENT_BUFFER) + (Closes: #188876, 188900, 188912) + + -- Julien LEMOINE Mon, 14 Apr 2003 04:45:03 +0200 + +binutils (2.13.90.0.18-1.6) unstable; urgency=high + + * NMU + * [002_ldlex_inflexible_transition.diff] New. Make ld buildable again with + sid's current flex. + + -- J.H.M. Dassen (Ray) Sun, 13 Apr 2003 16:54:46 +0200 + +binutils (2.13.90.0.18-1.5) unstable; urgency=medium + + * NMU + * [890-elf64_alpha_segfault.diff] Patch from Julien LEMOINE + to fix the segfault encountered while building + gal on alpha. (Closes: #185556) + * sid's current flex breaks the building of several packages, including this + one; see #188665. The i386 upload is built using a pbuilder sid chroot + with flex downgraded to the sarge version. + + -- J.H.M. Dassen (Ray) Sun, 13 Apr 2003 13:44:17 +0200 + +binutils (2.13.90.0.18-1.4) unstable; urgency=low + + * NMU + * ld/emulparams/elf64_sparc.sh: Set LIBPATH_SUFFIX instead of suffix + for emulation. Patch from current CVS suggested by Clint Adams, + needed for sparc64 glibc build. + * bfd/elf64-alpha.c: Patch from current CVS suggested by Falk Hueffner, + needed to build xstow, kdegames (#181623), sfs. + * Explicitely fail, when trying to build with glibc-2.3 on arm and + m68k. See #184048 for m68k ld failures. + + -- Matthias Klose Tue, 8 Apr 2003 23:27:46 +0200 + +binutils (2.13.90.0.18-1.3) unstable; urgency=low + + * NMU + * Another fix for ELF/m68k (__bb_exit_func initialization). + + -- Matthias Klose Tue, 18 Mar 2003 00:05:47 +0100 + +binutils (2.13.90.0.18-1.2) unstable; urgency=high + + * NMU + * Apply upstream fix for ELF/m68k. Closes: #182313. + * Use gcc-2.95 on m68k-linux. Built on testing (glibc-2.2). + + -- Matthias Klose Sun, 9 Mar 2003 01:02:39 +0100 + +binutils (2.13.90.0.18-1.1) unstable; urgency=low + + * NMU + * Apply upstream fix for hppa stubs. Closes: #181397 + + -- LaMont Jones Wed, 19 Feb 2003 12:34:58 -0700 + +binutils (2.13.90.0.18-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-01-21) + * Upstream: Fix an ia64 gas bug + * Upstream: Fix some TLS bugs + * Upstream: Fix ELF/ppc bugs + * Upstream: Fix an ELF/m68k bug + * Corrected ARM combreloc disabling patch + (closes: Bug#175204) + * Upstream fixes take care of TEXTREL bug + on powerpc (closes: Bug#176084) + * Fixed shellutils dependency problem + (closes: Bug#175673) + * Removed mention of the monitor manpage + from the gprof manpage (closes: Bug#160654) + + -- Christopher C. Chimelis Sun, 2 Feb 2003 23:17:29 -0500 + +binutils (2.13.90.0.16-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-11-26) + * Upstream: Include /usr/bin/c++filt + * Upstream: Fix "ld -r" with exception handling + + -- Christopher C. Chimelis Mon, 9 Dec 2002 19:14:02 -0500 + +binutils (2.13.90.0.14-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-11-14) + * Upstream: Fix ELF/alpha bugs + * Upstream: Fix an ELF/i386 assembler bug + * Updated package MIPS patch from HJ Lu + * Added s390 patches from Gerhard Tonn. + Actually, the patches to support s390x were + already included upstream, so I just enabled + it in the rules script (closes: Bug#168074, Bug#168974) + * Since powerpc64-linux support was already + added in a prior upload, I'm closing the + wishlist bug for it (closes: Bug#156955) + + -- Christopher C. Chimelis Tue, 20 Nov 2002 05:36:21 -0500 + +binutils (2.13.90.0.10-2) unstable; urgency=low + + * Added two patches from upstream to fix alpha BFD. + (closes: Bug#165633) + + -- Christopher C. Chimelis Sun, 27 Oct 2002 14:21:51 -0400 + +binutils (2.13.90.0.10-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-10-10) + * Upstream: More ELF/PPC linker bug fixes. + * Upstream: Fix an ELF/alpha linker bug. + * Upstream: Fix an ELF/sparc linker bug to support + Solaris. + * Upstream: More TLS updates. + * Updated m68k gcc 3.1 patch since it wasn't applying + cleanly. Is this still needed? + * Added patches to allow building with new bison + (closes: Bug#164436, Bug#164042) + * Should be better for prelink support, which is coming + soon (closes: Bug#161427) + * Removed windres manpage from all packages + (closes: Bug#157415) + * Fixed download location in copyright file + (closes: Bug#158028) + * Added i386-gnu to multiarch build targets + (closes: Bug#157057) + * Add alpha opcode patch from Falk Hueffner + (closes: Bug#164201) + * Remove .la files from packages + (closes: Bug#160455) + + -- Christopher C. Chimelis Mon, 15 Oct 2002 20:22:29 -0400 + +binutils (2.13.90.0.4-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-08-) + * Upstream: Update from binutils 2002 0814 + * Upstream: Fix symbol versioning bugs for gcc 3.2 + * Upstream: Fix mips gas + * Upstream: Fix an x86 TLS bfd bug + * Upstream: Fix an x86 PIC gas bug + + -- Christopher C. Chimelis Thu, 15 Aug 2002 20:13:44 -0400 + +binutils (2.12.90.0.15-2) unstable; urgency=low + + * Fix combreloc disabling patch for ARM + (closes: Bug#156315) + * Remove S390 patch since it is no longer + needed (thanks to Gerhard Tonn for checking + this out) + * Fix BFD version string escaping + (closes: Bug#154989) + * Add SH patch from Yaegashi Takeshi + (closes: Bug#156230) + * Added conflicts for older modutils + (closes: Bug#155324) + * Forgot to apply MIPS patch from HJ Lu + (apologies to MIPS folks) + + -- Christopher C. Chimelis Wed, 14 Aug 2002 13:09:12 -0400 + +binutils (2.12.90.0.15-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-07-17) + * Upstream: Fix an ia64 assembler bug + * Upstream: Fix a symbol versioning bug + * Upstream: You have to apply the modutils patch + enclosed here in order to support System.map + generated by the new nm (bug filed) + * The symbol visibility patch is included + upstream, as is the alpha PLT/GOT patch, so + both removed from my packaging. + * Included patch from upstream to fix RELA targets + (closes: Bug#153729) + + -- Christopher C. Chimelis Thu, 2 Aug 2002 02:24:29 -0400 + +binutils (2.12.90.0.14-2) unstable; urgency=low + + * The "Let's Get This Party Started Right" upload + (since I'm closing as many old bugs as possible) + * Removed sparc patch altogether + * Added a small alpha patch from upstream to fix + some obscure PLT/GOT issues. + * Manpages are now fixed finally -- no more + I (closes: Bug#108369) + * Have not gotten another report of the + debconf message being cut off, so I'm closing + the debconf-related bug. I suspect this may + have been a problem in the debconf front-end + being used, but I have not been able to reproduce + it (closes: Bug#149045) + * Closing a bug report that I had tagged moreinfo + a LONG time ago (over one year), but never got + more info on. I have not heard of this kind + of problem since, nor have I been able to + reproduce it at any time since (closes: Bug#105986). + For interested parties, it revolved around + allowing gcc to show a linker error, but the + reporter didn't know about the -v option for + gcc. There was a linker problem, but it appeared + to be either hardware failure or user error. + * Closing a demangler 'bug' that revolved around + stripping @PLT from symbol names. Since the + PLT suffix is documented, I'm going to close + this bug. Also, it doesn't help that the symbol + in the bug report uses an obsolete mangling style, + so I can't test this even if I wanted to + (closes: Bug#45889) + + -- Christopher C. Chimelis Mon, 22 Jul 2002 12:54:01 -0400 + +binutils (2.12.90.0.14-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-06-27) + * Upstream: Fix a mips assembler bug + * Upstream: Fix an ELF/mips SHF_MERGE bug + * Upstream: Fix a linker bug which leads to the + incorrect Linux 2.2 kernel. + * PE patch removed since it is included + in upstream source now + * Includes some patches which allow for + more true testsuite results from gcc-3.1 + * Fix sparc ld emulation script patches to get + rid of the lib/64 silliness (now uses lib64) + * Removed the L word from the package description + since Debian is no longer linux-only + (closes: Bug#150575) + * The strings dereferencing problem with + some Windows binaries seems to also be fixed now + (closes: Bug#121366) + * Added a patch to only generate an RPATH entry + if LD_RUN_PATH is not empty, for cases where + -rpath isn't specified (closes: Bug#151024) + * Fixed arch detection problem in the build + scripts. + * Fixed bad capitalisation of -g in the objdump + manpage (closes: Bug#152697) + * Added patch from HJ Lu to fix a symbol + visibility issue. + + -- Christopher C. Chimelis Wed, 17 Jul 2002 14:23:42 -0400 + +binutils (2.12.90.0.9-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-05-26). + * Upstream: Supports "-z muldefs" + * Updated PE bfd from CVS to fix auto-import + segfaults (closes: Bug#131407) + * Remove the PE-removing patch for i386 targets + due to the above + + -- Christopher C. Chimelis Thu, 6 Jun 2002 15:52:29 -0400 + +binutils (2.12.90.0.7-1) unstable; urgency=low + + * New upstream version (synced with CVS 2002-04-23). + * Upstream: ELF EH frame bug fix + * Upstream: MIPS ELF visibility bug fix + * Upstream: Bug fixes for ELF/sparc + * Upstream: Bug fixes for ELF/cris + * Upstream: Fix linking a.out relocatable files + with ELF + * Upstream: Fix a PPC altivec assembler bug + * Numerous upstream changes since I have + deliberately not updated in awhile so that + I could stabilise the package for woody + release + * Fixed a glaring typo in the Debian additions + to the version string. + * Upstream incorporated --oformat + documentation patch; removed. + * Added a patch from upstream involving + relative relocs on Alpha + * Removed configure.info-[1-3] from -doc + (closes: Bug#146205) + + -- Christopher C. Chimelis Sun, 5 Apr 2002 04:52:33 -0400 + +binutils (2.12.90.0.1-5) unstable; urgency=high + + * Added a patch to m68k bits for gas to allow + gcc 3.1 to build + * Added Brazilian Portuguese translation for + debconf (closes: Bug#144677) + * Removed unneeded gasp manpage since gasp + was eliminated as a distinct binary + (closes: Bug#144583) + + -- Christopher C. Chimelis Mon, 29 Apr 2002 14:40:21 -0400 + +binutils (2.12.90.0.1-4) unstable; urgency=low + + * Added patch from Gerhardt Tonn + to fix s390 merge problem (closes: Bug#143187) + * Corrected DOW of my last changelog entry :-P + + -- Christopher C. Chimelis Thu, 18 Apr 2002 13:03:49 -0400 + +binutils (2.12.90.0.1-3) unstable; urgency=low + + * Oops...I used dpkg-architecture from dpkg-dev + in the postinst and didn't add a dependency + for it. It was a bad choice anyway and I'm + going to use uname -s instead + (closes: Bug#142744, Bug#142915) + + -- Christopher C. Chimelis Mon, 15 Apr 2002 12:41:10 -0400 + +binutils (2.12.90.0.1-2) unstable; urgency=low + + * Added Catalan debconf translation + (closes: Bug#139740) + * Ensure that info entries are removed from the + texinfo dirfile when binutils-doc is removed + (closes: Bug#126557) + * Ensure that the kernel link debconf warning + only shows up on linux systems + (closes: Bug#142360) + + -- Christopher C. Chimelis Thu, 13 Mar 2002 01:30:22 -0400 + +binutils (2.12.90.0.1-1) unstable; urgency=high + + * New upstream version (synced with CVS 2002-03-07). + * Upstream: Add the .preinit_array/.init_array/.fini_array + support. + * Upstream: Fix eh_frame. + * Upstream: Turn on combreloc by default. + * Upstream: Enable gprof for Linux/mips. + * Turn combreloc off for ARM explicitely until + I can confirm that PIC is not still broken + by using it. + * Remove IA-64 unwind patch and objcopy fix + since they are included in the upstream sources + now. + * Re-enable testsuite run since Randolph did the NMU + on dejagnu (thank you!). + * Appears to fix sparc64 linking problems. I'm + still looking into exactly what was going on with + that (closes: Bug#137850) + * Enabled hppa64-linux support in main binutils + package (closes: Bug#137955) + * Added Japanese debconf template. Thanks to + Tomohiro KUBOTA for supplying that + (closes: Bug#138112) + * Added patch for ld to fix dosemu problems + (closes: Bug#126863) + + -- Christopher C. Chimelis Mon, 11 Mar 2002 14:02:45 -0500 + +binutils (2.11.93.0.2-3) unstable; urgency=high + + * Split translated debconf templates out. + I apparently misunderstood the instructions + on integrating the French translation since + this is my first real attempt at using + debconf (closes: Bug#136295) + * Disable combreloc default on ARM since it + breaks PIC, apparently (closes: Bug#134241) + Please test other ARM bugs against this + version and inform me of the results! + + -- Christopher C. Chimelis Fri, 8 Mar 2002 19:10:10 -0500 + +binutils (2.11.93.0.2-2) unstable; urgency=high + + * Include a patch from upstream to fix stripping + archives containing multiple files with the + same name (like libgcj, unfortunately). + (closes: Bug#107812) + * Include IA64 unwind fix from CVS to fix kernel + linking on IA64. (closes: Bug#135143) + * Added French translation of the debconf + bits. Thanks to Denis Barbier for the + work on that. (closes: Bug#134626) + * Disabled testsuite run until dejagnu is + fixed. I'm leaving the build-dep for dejagnu + in, though, since I know I'll forget to + reinsert it when I do re-enable the testsuite + run. + + -- Christopher C. Chimelis Fri, 22 Feb 2002 14:05:22 -0500 + +binutils (2.11.93.0.2-1) unstable; urgency=high + + * New upstream version (synced with CVS 2002-02-07). + * Upstream: Fix a weak symbol alpha linker bug for glibc. + * Upstream: More support for gcc 3.1. + * Keep on disabling efi-app-ia32 type targets + since the segfault is still unfixed in CVS and + I haven't had the time to go back and really + debug and fix this. + * Updated standards version. + * Corrected some of the lintian problems (all except + the ones involving Changelog.linux, the .comment + section, and the missing manpages for + binutils-multiarch's binaries since that package + depends on binutils, which provides those). + + -- Christopher C. Chimelis Wed, 13 Feb 2002 13:41:47 -0500 + +binutils (2.11.92.0.12.3-7) unstable; urgency=high + + * The "Remind Me To Think Next Time" upload. + * Fix the postinst to only compare versions on + upgrade rather than during configure. + (closes: Bug#133349, Bug#133514) + * Still working on the other bugs...if only + I could get a day off of work... + + -- Christopher C. Chimelis Tue, 12 Feb 2002 06:15:02 -0500 + +binutils (2.11.92.0.12.3-6) unstable; urgency=high + + * The "Make The Bad Man Stop" upload. + * Revert patch to bfd/elf32-sparc.c (already + reverted upstream) that broke UA32 relocs on sparc + and caused bus errors with C++/Java binaries + (closes: Bug#126162) + * Remove i486-mingw32 target from the enabled + in multiarch and removed efi-app-ia32 from the + BFD config for Intel linux targets until I can find + and fixthe segfaults that seem to keep coming up when + reading Windows files and viruses with objdump or + strings. This is only temporary, so I'm not closing + the bugs until the problem gets fixed, but + I am going to bump them down to wishlist, merge + them, and note the above in them. + (debian/patches/010_disable_efi_app_ia32_TEMPORARY.diff + disables the efi-app-ia32 BFD in case someone + wants to revert this change easily) + * Added debconf warning about the kernel linking + situation since it keeps coming up and people + keep initially disagreeing with me about this + being a kernel bug. Also, merged prior warning + about -oformat change into the same debconf warning + (it's two, two, two warnings in one). This makes + the DEBIAN_FRONTEND case bug moot (closes: Bug#131801) + * Added powerpc64-linux target to multiarch since + work is progressing on that target and the machines + are due to hit the shelves Very Soon(TM). + + -- Christopher C. Chimelis Fri, 1 Feb 2002 17:06:29 -0500 + +binutils (2.11.92.0.12.3-5) unstable; urgency=high + + * Fix signed char assumption in i386 disassembly bits + (closes: Bug#126993) + + -- Christopher C. Chimelis Mon, 8 Jan 2002 17:27:17 -0500 + +binutils (2.11.92.0.12.3-4) unstable; urgency=high + + * Go back to enabling archs by enumeration for + multiarch. Apparently, a few aren't enabled + with --enable-targets=all (sparc64-linux, namely). + Besides, multiarch was incredibly large, which + was probably unneeded. + + -- Christopher C. Chimelis Wed, 26 Dec 2001 13:53:49 -0500 + +binutils (2.11.92.0.12.3-3) unstable; urgency=high + + * Include patch from Alan Modra to fix more + refcount problems on hppa. + + -- Christopher C. Chimelis Fri, 7 Dec 2001 05:42:04 -0500 + +binutils (2.11.92.0.12.3-2) unstable; urgency=high + + * Include patch from Alan Modra to fix hppa linking + woes wrt undefined symbols (closes: Bug#121993) + + -- Christopher C. Chimelis Wed, 5 Dec 2001 04:14:51 -0500 + +binutils (2.11.92.0.12.3-1) unstable; urgency=high + + * New upstream version (synced with CVS 2001-11-21) + * Upstream: Fix a linker symbol version bug + for common symbols. + * Upstream: Update handling relocations against + the discarded sections. You may need to apply + the kernel patch enclosed here to your kernel + source. + * Upstream: Support "-march=xxx -mipsN" for mips + gas if they are compatible. + * Upstream: Fix a regression when linking with + non-ELF object files. + * Includes Alan Modra's patch to reduce stub sizes + on HPPA. Should help C++ on HPPA. + * Once again includes a mips patch from HJ Lu. + * My documentation changes were cleaned up and + accepted upstream, so the gas manpage fixes go + away (hurray!). + * Stopped iterating targets for binutils-multiarch + and started enabling all of them. This saves + maintenance time since new targets will be + automatically supported in future uploads + and existing targets that I didn't include + before will be supported from now on. This may + grow build time and the libbfd in the multiarch + package, but it's worth it. + * Also, started using the --enable-64-bit-bfd + flag for configuring multiarch. I don't know + why I didn't realise this wasn't there before + since I test with it all of the time. + + -- Christopher C. Chimelis Fri, 30 Nov 2001 20:11:42 -0500 + +binutils (2.11.92.0.10-4) unstable; urgency=high + + * The "Fingers crossed" upload. + * Enable combreloc by default for s390 again. + Rumour has it that it worked before, but there + was a misunderstanding in the s390 developer + community, hence the disabling in the past. + * Fix the ld texinfo file to not mention the old + oformat invocation (closes: Bug#116182) + * Next upload should include the mips updates and + some powerpc updates. I just need time to test + those out first. + + -- Christopher C. Chimelis Fri, 23 Nov 2001 23:23:22 -0500 + +binutils (2.11.92.0.10-3) unstable; urgency=high + + * Replace HPPA reloc patch with patches from Alan + Modra upstream. + * Add upstream patch to fix quoted -rpath bug + (closes: Bug#107214) + + -- Christopher C. Chimelis Sat, 10 Nov 2001 18:19:05 -0400 + +binutils (2.11.92.0.10-2) unstable; urgency=high + + * Disable -z combreloc enable patch on S/390 + since it's not supported there yet + (closes: Bug#117087) + + -- Christopher C. Chimelis Fri, 26 Oct 2001 00:07:01 -0400 + +binutils (2.11.92.0.10-1) unstable; urgency=high + + * New upstream version (synced with CVS 2001-10-21) + * Upstream: Fix the ELF/PPC linker. + * Upstream: Fix the ELF/cris linker. + * Upstream: Fix ELF strip. + * Includes beginnings of Altivec support + (closes: Bug#98617) + * Fixes use of BookE instruction format on 4xx + PowerPC (closes: Bug#116627) + * Includes patches from Alan Modra to fix hppa + relocations. + * Forgot to close the previous PPC bug with last + upload (closes: Bug#116454) + * Moved to enclosing a bzipped tarball rather than + a gzipped one to save download time for everyone + involved. Build-deps adjusted accordingly. + + -- Christopher C. Chimelis Tue, 23 Oct 2001 03:29:49 -0400 + +binutils (2.11.92.0.7-2) unstable; urgency=high + + * Include a patch from H.J Lu to fix a powerpc + issue not shown in the testsuite results. + + -- Christopher C. Chimelis Fri, 19 Oct 2001 00:49:04 -0400 + +binutils (2.11.92.0.7-1) unstable; urgency=high + + * New upstream release (synced with CVS 2001-10-16) + * Upstream: Fix all breakages introduced in 2.11.92.0.5 + * No mips/ dir patches need to be applied with this one. + Woohoo! + * Removed patches from debian/patches that are already + applied upstream. + * Patched version strings to reflect that this is a + Debian release at the request of upstream (to prevent + confusion, apparently). + * Applied patch from H.J. Lu to fix mips section + misalignment. + * Applied patch from Jakub Jelinek to fix kernel linking + on i386 and possibly other archs (closes: Bug#116041) + * Fixed postinst and prerm for binutils-doc to test that + the files exist before calling install-info. This should + fix the odd circumstance when binutils-doc is packaged on + an arch that doesn't support gprof (or any other dir for + that matter) and, therefore, the docs that are usually + made in that dir aren't made. This is particularly true + with gprof on mips. + + -- Christopher C. Chimelis Wed, 17 Oct 2001 18:56:51 -0400 + +binutils (2.11.92.0.5-3) unstable; urgency=high + + * Enable -z combreloc on all targets. This will make + prelinking possible with the prelink package. Please + test this on all archs prior to upload. If it fails, file + a bug immediately and I'll disable the patch for that + platform. + * Added patches from Alan Modra (from CVS) to fix other + archs after the refcount patch broke them. This supercedes + the powerpc patch, so I replaced that with this. + (closes: Bug#115218) + * Added patch from H.J. Lu (from CVS) to fix IA64 linker + problems as well. + * Added patch from David Kimdon to specify which filename is + causing an error if that filename is a dir (closes: Bug#45832). + * Removed workaround patch for stabs problem on Alpha since + it appears to be causing problems on mips and is no longer + needed on Alpha anyway. + * Now runs the testsuite and includes the results in the + binutils package for reference. + + -- Christopher C. Chimelis Sat, 13 Oct 2001 15:10:20 -0400 + +binutils (2.11.92.0.5-2) unstable; urgency=high + + * Applied fix from H.J. Lu to fix PowerPC target + (closes: Bug#115285). Thanks to Jack Howarth + for forcing the issue upstream. + + -- Christopher C. Chimelis Fri, 12 Oct 2001 23:14:51 -0400 + +binutils (2.11.92.0.5-1) unstable; urgency=high + + * New upstream release (synced with CVS 2001-10-05) + * Upstream: Support gcc 3.1 for IA64. + * Upstream: Support prelink for ELF/PPC. + * Upstream: Fix an ELF/x86 linker bug for Oracle + (closes: Bug#113614) + * Upstream: Fix a weak symbol bug. + * Upstream: Support locale. + + -- Christopher C. Chimelis Tue, 9 Oct 2001 19:53:49 -0400 + +binutils (2.11.90.0.31-2) unstable; urgency=high + + * Applied IA64 patch from CVS to fix gcc issues + on IA64. + + -- Christopher C. Chimelis Mon, 24 Sep 2001 12:45:29 -0400 + +binutils (2.11.90.0.31-1) unstable; urgency=high + + * New upstream source (synced with CVS 2001-08-30) + * Upstream: Fix a MIPS linker bug. + * Now applying mips diffs from H.J. Lu (upstream) + for better MIPS and MIPS64 support. + * Applied patch from Christopher Cramer to fix + gasp .REG issue (closes: Bug#110560) + + -- Christopher C. Chimelis Sat, 1 Sep 2001 23:42:22 -0400 + +binutils (2.11.90.0.29-1) unstable; urgency=high + + * New upstream source (synced with CVS 2001-08-27) + * Upstream: Fix an Alpha assembler bug. + * Upstream: Fix an IA64 linker bug. + * Upstream: Fix a MIPS linker bug. + * Upstream: Support '-z combreloc|nocombreloc' in linker. + + -- Christopher C. Chimelis Thu, 30 Aug 2001 04:48:04 -0400 + +binutils (2.11.90.0.27-4) unstable; urgency=high + + * Argh. Really remove the manpages from multiarch + this time (closes: Bug#110410) + + -- Christopher C. Chimelis Tue, 28 Aug 2001 14:32:34 -0400 + +binutils (2.11.90.0.27-3) unstable; urgency=high + + * Include hppa patch to force error + (closes: Bug#109173) + * Fix manpages - seems that I accidentally included + the multiarch manpages rather than the target + manpages (sorry). + * Partial update to as manpage to denote arch options + and added options for the rest of the targets + Still need to elaborate on them, though. More + changes are forthcoming (closes: Bug#110127) + + -- Christopher C. Chimelis Mon, 27 Aug 2001 10:13:27 -0400 + +binutils (2.11.90.0.27-2) unstable; urgency=high + + * Remove bash dependency...ash's behaviour has + already been modified, so it should be able + to build binutils now (closes: Bug#106992) + * Includes new S/390 patch (closes: Bug#109300) + * Could never reproduce objdump segfault and + never got a reply on the bug report + (closes: Bug#93884) + * Can't reproduce m68k segfault either + (closes: Bug#87714) + + -- Christopher C. Chimelis Mon, 20 Aug 2001 23:07:30 -0400 + +binutils (2.11.90.0.27-1) unstable; urgency=high + + * New upstream source (synced with 20010810 CVS) + * Upstream: Fixed x86 linker bug. + * Reverted a patch to gas to dodge a bug in STABS output + on Alpha using gcc 2.95.4, so alpha can be in sync + with the rest of the archs now. + * Fixes strip problems with busybox (closes: Bug#106593) + * Kernels should compile ok again on i386 + (closes: Bug#107190) + + -- Christopher C. Chimelis Thu, 16 Aug 2001 08:24:49 -0400 + +binutils (2.11.90.0.25-1) unstable; urgency=high + + * New upstream source (synced with 20010726 CVS) + * Upstream: fix i386 assembler bug. + * Upstream: "make check" has 2 failures in the + ld-selective test in ld on Linux/alpha. They + should be marked xfail. Fixed in the next release. + * Removed m68k patch (closes: Bug#106431) + * Man pages appear to be correctly generated now + (closes: Bug#98569, Bug# 98938) + * Added bash build dependency (closes: Bug#106992) + * Should compile ok on powerpc (the last one did + also...don't know why voltaire's build daemon failed). + I won't close this bug until I build it myself + on voltaire or hear back from the autobuilder folks + on PPC. + * Looking into the whole LD_LIBRARY_PATH issue that + keeps being brought up. I think the docs are wrong + because the templates say that it shouldn't obey that + at all. Can we please stop filing duplicate bugs for + this? I would greatly appreciate it... + + -- Christopher C. Chimelis Wed, 1 Aug 2001 07:06:52 -0400 + +binutils (2.11.90.0.24-1) unstable; urgency=high + + * New upstream source (synced with 20010714 CVS) + * DO NOT COMPILE FOR ALPHA. I need to fix gcc 2.95.4 + prior to this release working on Alpha correctly + (long story). + * Upstream: Avoid COPY relocs on i386 + * Upstream: Fix IA64 assembler (please try this and let me know) + * Upstream: Fix a static linking the PIC object files on ia32 + * Upstream: Add the version script support for --export-dynamic + * Upstream: Fix sparc/elf for linux/sparc + * Upstream: Fix alpha/elf for gcc 3.0 + * Supposedly required for gcc-3.0 usage on many platforms + * Add s390 to multiarch list (closes: Bug#98095) + * Supposedly good on mips, but please check. I emailed Ryan + to see if bug 98095 still happens, but never got a reply. + If I get around it, I'll check it myself since my mips + lives once again. + * Retake my package from Matt (next time we agree to an NMU, + please don't change the maintainer name...no wonder I didn't + get any bug reports!) + * Cross-compilation support will be added in the next upload + (I'll be uploading alpha debs with the next release as well, + the alpha problem outweighs cross-compilation support in + priority right now). + + -- Christopher C. Chimelis Thu, 19 Jul 2001 05:12:05 -0400 + +binutils (2.11.90.0.7-2) unstable; urgency=high + + * Applied patch from Alan Modra to fix m68k + assertion problems (closes: Bug#96352) + * Applied srec patch from Richard Henderson for + alpha. + + -- Christopher C. Chimelis Wed, 9 May 2001 03:11:19 -0400 + +binutils (2.11.90.0.7-1) unstable; urgency=high + + * New upstream source (synced with 20010425 CVS) + * Upstream: Fix the -Bsymbolic bug introduced in + binutils 2.11.90.0.5 (closes: Bug#95168) + + -- Christopher C. Chimelis Sun, 29 Apr 2001 20:03:22 -0400 + +binutils (2.11.90.0.5-1) unstable; urgency=high + + * New upstream source (synced with 20010414 CVS) + * Upstream: Fix in IA64 assembler + * Upstream: Change Linux/MIPS to use SVR4 MIPS ABI + rather than IRIX ABI. + * The above change may cause problems for MIPS. + If so, please file a bug and I'll revert those + changes if need be. I suspect that glibc, gcc, + and the kernel may eventually follow suit, though + to fit in with this change (it makes sense... + see the symbol ordering problems threads on the + binutils list for more info). + * Upstream: IA32 gas bug fixed...no further details + provided, unfortunately. + * Reportedly fixes core dumping when trying to link + object files from other platforms (now warns) + (closes: Bug#60502) + * Includes Philip Blundell's ARM PLT patch finally... + sorry for the delay (closes: Bug#94181) + * m68k problems should be fixed by now. Wish I had + gotten more feedback, but I didn't so I'm assuming it + works at this point (closes: Bug#74396) + * Stopped compiling cross-compiler packages until we + work out a better system for the entire toolchain. + Sorry, but it was taking far too long on even fast + machines and I've gotten more complaints about the + current arrangement than I have positive feedback. + (closes: Bug#91120, Bug#91119, Bug#91118, Bug#91117, + Bug#91116, Bug#88311, Bug#78028, Bug#90177) + * Fixed readelf manpage so that it no longer says that + it is a preprocessor for assembly programs + (closes: Bug#90798) + + -- Christopher C. Chimelis Tue, 17 Apr 2001 20:07:14 -0400 + +binutils (2.11.90.0.1-1) unstable; urgency=high + + * New upstream source (synced with 20010309 + CVS). + * Fixed misapplied m68k ld patch. + I am hoping that this almost totally fixes + m68k ELF for now. + * Fixed typo in mips patch and applied another + mips patch from Daniel Jacobowitz. + * Should no longer build same-arch cross + packages. Please let me know if this fix + worked so that I can close the bugs (I have + no access to such an arch at the moment) + * Made urgency high since m68k really needs + this if the bugs are truly fixed. Even if + not, this version is infinitely better on + at least two platforms than prior ones were. + + -- Christopher C. Chimelis Thu, 15 Mar 2001 16:29:32 -0500 + +binutils (2.10.91.0.2-4) unstable; urgency=low + + * Applied m68k ld and bfd patches from + Michael Fedrowitz to hopefully make things + better on m68k. + + -- Christopher C. Chimelis Sun, 11 Mar 2001 20:16:44 -0500 + +binutils (2.10.91.0.2-3) unstable; urgency=low + + * Adjusted the priority of binutils-doc to + optional. + * Added debhelper build-depends (closes: Bug#87690) + * Fixed postinst problem for new binutils + installations (closes: Bug#87911) + + -- Christopher C. Chimelis Thu, 1 Mar 2001 15:06:50 -0500 + +binutils (2.10.91.0.2-2) unstable; urgency=low + + * Add support for SH and IA64 to binutils-multiarch. + * Applied m68k gas patch from Michael Fedrowitz + in hopes that this will fix the grave bug that + has been such a pain to m68k folks. I'll leave + the bug open until it's verified that it works + ok. + * Applied IA-64 printf patch (closes: Bug#82702) + * Kernels appear to be building fine with this + release on all archs available to me + (closes: Bug#77610) + * Added text during postinst that informs users + to modify their i386 kernel Makefiles for the + --oformat change (closes: Bug#86995) + * Incorporated remaining mips diffs that weren't + already applied upstream (closes: Bug#81280) + * Sparc/sparc64 patch seems to be doing fine, so + closing the bug (closes: Bug#86781) + * Added non-linux cross- package support to rules + (closes: Bug#79948) + * Close misc bugs: + Missing info file in binutils-doc (closes: Bug#78754) + + -- Christopher C. Chimelis Thu, 22 Feb 2001 19:36:12 -0500 + +binutils (2.10.91.0.2-1) unstable; urgency=low + + * New upstream version. + * Added weak symbol relocation patch for sparc/sparc64. + * Included m68k ELF fix from Michael Fedrowitz. + * BIG NOTE: any i386 kernels compiled with this will need + to be patched to change the ld option '-oformat' to + '--oformat' (extra hyphen). + + -- Christopher C. Chimelis Tue, 20 Feb 2001 21:32:44 -0500 + +binutils (2.10.1.0.2-1) unstable; urgency=low + + * New upstream release (really prerel, but better than + using a CVS version). + * Should re-add Compaq demangling style to all + tools (alpha-only). + * Again, hopefully fixes m68k ELF support...still have + no idea why or how this was broken before. + + -- Christopher C. Chimelis Mon, 20 Nov 2000 16:25:44 -0500 + +binutils (2.10.0.27-0.cvs20001011.2) unstable; urgency=low + + * Applied another PowerPC patch to correct the + implementation of .protected and .hidden in the + linker. This should also aid in the glibc + transition on PowerPC. + + -- Christopher C. Chimelis Tue, 17 Oct 2000 13:23:40 -0400 + +binutils (2.10.0.27-0.cvs20001011.1) unstable; urgency=low + + * Applied PowerPC weak symbol patch from CVS to aid + in glibc transition on that platform. + + -- Christopher C. Chimelis Sun, 15 Oct 2000 19:12:22 -0400 + +binutils (2.10.0.27-0.cvs20001011) unstable; urgency=low + + * Grabbed a new CVS version since it backs out a + change that prevented current gcc snapshots from + linking properly to libstdc++v3. This may also + solve some other problems related to global + section symbols (feedback appreciated). + * Finally changed my email address in the control + file (how I overlooked this after all of this + time I'll never know). + + -- Christopher C. Chimelis Wed, 11 Oct 2000 08:59:36 -0400 + +binutils (2.10.0.27-0.cvs20001008) unstable; urgency=low + + * Removed configure.info.gz from binutils-doc since + it didn't really belong there. (closes: Bug#72746) + * Update for hppa/hppa64 targets (included testsuite + changes committed on 07-Oct-2000). (closes: Bug#71524) + * Upstream change to elflink.h to hopefully stop + segfaults on some archs when linking binaries to + shared libs. + + -- Christopher C. Chimelis Sun, 8 Oct 2000 16:14:08 -0400 + +binutils (2.10.0.27-0.cvs20000923.1) unstable; urgency=low + + * Fixed rules file so that builds don't fail when compiling the + binary-arch target (added binary-cross to binary-arch). + * Fixed harmless attempt at removing builddir-avr twice. + + -- Christopher C. Chimelis Thu, 28 Sep 2000 10:39:12 -0400 + +binutils (2.10.0.27-0.cvs20000923) unstable; urgency=low + + * CVS snapshot from 2000-09-23. + * Should fix some (most) HPPA issues. + * Adds binutils-m68k cross-assembler. + + -- Christopher C. Chimelis Sun, 24 Sep 2000 10:19:20 -0400 + +binutils (2.10.0.26-2) unstable; urgency=low + + * Added the avr target for Amtel's AVR MCU's + * Applied Frank I. Smith to generate packages for + multiple cross targets: + + Bump rev number, NOP. + + Testing out bumping up the rev number. + + Added powerpc, arm, mipsel cross binutils packages. + + -- Christopher C. Chimelis Fri, 22 Sep 2000 17:31:44 -0400 + +binutils (2.10.0.26-1) unstable; urgency=low + + * New upstream source. + * Added mips-linux, hppa-linux, and hppa64-linux to multiarch targets + + -- Christopher C. Chimelis Sun, 17 Sep 2000 01:05:49 -0400 + +binutils (2.10.0.24-1) unstable; urgency=low + + * New upstream source. + * Fixes ia32 assembler buglet. + * (Hopefully) fixes PPC visibility problems with + glibc 2.2 + + -- Christopher C. Chimelis Thu, 24 Aug 2000 16:52:44 -0400 + +binutils (2.10.0.18-3) unstable; urgency=low + + * Added build depends stuff. + + -- Christopher C. Chimelis Sat, 5 Aug 2000 21:09:04 -0400 + +binutils (2.10.0.18-2) unstable; urgency=low + + * Added proviso to control file saying that -multiarch + should not be installed by the average user. + + -- Christopher C. Chimelis Sat, 29 Jul 2000 20:07:15 -0400 + +binutils (2.10.0.18-1) unstable; urgency=low + + * New upstream source. + * Should address some needed things for glibc 2.2 + (added new DT_XXXX dynamic tags and fixes DT_NEEDED + link bug) + * Reapplied the now-infamous "ObjC patch" until + we can figure out why we still have this problem + (hint hint hint...we really need to do this). + + -- Christopher C. Chimelis Sat, 22 Jul 2000 13:18:27 -0400 + +binutils (2.10.0.9-4) unstable; urgency=low + + * Applied a patch from Ben Collins to fix sparc64 + linker scripts + + -- Christopher C. Chimelis Sat, 8 Jul 2000 07:24:10 -0400 + +binutils (2.10.0.9-3) unstable; urgency=low + + * Applied a patch from the libstdc++ mailing list to + make sure that the linker doesn't eat the eh_frame + section. + + -- Christopher C. Chimelis Fri, 7 Jul 2000 10:26:59 -0400 + +binutils (2.10.0.9-2) unstable; urgency=low + + * Wow, already a bug fix. + * binutils-dev now provides libiberty.h + + -- Christopher C. Chimelis Fri, 23 Jun 2000 19:54:39 -0400 + +binutils (2.10.0.9-1) unstable; urgency=low + + * New upstream version (more linux-specific). + + -- Christopher C. Chimelis Fri, 23 Jun 2000 14:31:04 -0400 + +binutils (2.10-1) unstable; urgency=low + + * New upstream version (finally, a real release!) + + -- Christopher C. Chimelis Wed, 21 Jun 2000 19:08:14 -0400 + +binutils (2.9.5.0.46-1) unstable; urgency=low + + * New upstream source. + * ELF visibility attribute should work correctly now. + * ia32 "jmp" instructions are now assembled differently + to use relocation for global jumps (affects PIC asm + code). + + -- Christopher C. Chimelis Thu, 8 Jun 2000 21:34:42 -0400 + +binutils (2.9.5.0.42-1) unstable; urgency=low + + * New upstream source. + * Includes a testcase for hidden symbol support. + + -- Christopher C. Chimelis Fri, 19 May 2000 20:48:52 -0400 + +binutils (2.9.5.0.41-1) unstable; urgency=high + + * New upstream source. + * Now includes patch to enable hidden symbol support + needed for gcc 3.0 testing. + + -- Christopher C. Chimelis Fri, 5 May 2000 20:38:41 -0400 + +binutils (2.9.5.0.37-1) frozen unstable; urgency=high + + * Was forced to bring the current frozen version up to + upstream 2.9.5.0.37 in order to fix a rather nasty + i386 gas bug and also since the existing ARM patch + applied in 2.9.5.0.31-3 has been superceded upstream + (closes:Bug#62119) + * Includes proper demangler support for Compaq compiler + usage on Alpha (may be superceded upstream shortly, + but is good enough for potato and for Compaq's usage) + (closes:Bug#62079) + * Added cross-compilation support for individual use. + Please note that the binary packages do not support + this. If you require this feature, you need to compile + the source package changing debian/rules. Also, if + you do this, YMMV since things on this front are changing + rapidly upstream and also because cross-compiling from + certain platforms to others may not work (i386->alpha, + for example). (closes:Bug#59246) + * Fixed replaces statement in binutils-multiarch + (closes:Bug#62496) + * Release Manager: I once again beg that this be included + in potato. I've freed up some time to deal with bug + reports quickly if needed. + + -- Christopher C. Chimelis Sat, 29 Apr 2000 04:03:39 -0400 + +binutils (2.9.5.0.31-3) frozen unstable; urgency=high + + * Applied patch to fix broken ARM code generation (closes:Bug#61977) + + -- Christopher C. Chimelis Fri, 7 Apr 2000 15:50:42 -0400 + +binutils (2.9.5.0.31-2) frozen unstable; urgency=high + + * Remove ld from binutils-multiarch since it doesn't want to + link kernels on several archs properly (fixes severity:important bug) + (closes: Bug#61719, Bug#61615, Bug#51625) + + -- Christopher C. Chimelis Mon, 3 Apr 2000 22:48:55 -0400 + +binutils (2.9.5.0.31-1) frozen unstable; urgency=high + + * Yet another patch (this time from H.J. Lu upstream) to fix + the unlink race condition bug. This is VERY important and + needs to be in potato. It also fixes the temp file creation + problem with objcopy on PPC (closes: Bug#60934) + * New upstream release. Fixes a serious Alpha bug along + with a demangler bug and several others (closes: Bug#61121) + * Should fix apt-get upgrade problem...please test + (closes: Bug#56175) + * Release manager: can we squeeze this in? I know it's a + new version, but the ELF bug on Alpha really needs to + be fixed along with the rest of the above and some others + not mentioned here. + + -- Christopher C. Chimelis Wed, 22 Mar 2000 05:05:12 -0500 + +binutils (2.9.5.0.22-5) frozen unstable; urgency=high + + * Applied fixed patch from Colin Phipps to seal the unlink + race condition in bfd/cache.c (closes: Bug#58865, Bug#57831) + * Installed a proper changelog in binutils-doc + (closes: Bug#58522) + * Closes other older bug (closes: Bug#55801) + * Included bbconv.pl in binutils main package in the doc dir + under the gprof subdir (closes: Bug#57521) + + -- Christopher C. Chimelis Tue, 14 Mar 2000 10:32:52 -0500 + +binutils (2.9.5.0.22-4) frozen unstable; urgency=high + + * Patched gprof/hertz.h to allow binutils to actually + build and work on Hurd (closes: Bug#57564) + * Patched bfd/cache.c to avoid a rare, but possible + security problem when as is creating/opening temp + files (closes: Bug#57831) + + -- Christopher C. Chimelis Thu, 17 Feb 2000 10:31:05 -0500 + +binutils (2.9.5.0.22-3) frozen unstable; urgency=high + + * Removed standards.info...do we really need seven + bugs filed for the same problem + (closes: Bug#54521, Bug#54546, Bug#54614, Bug#54682, Bug#55402, Bug#55582, Bug#55602) + * Changed binutils-multiarch extended description + to mention that a cross-assembling gas is not + included (closes: Bug#49308) + * Closing a bug because it related to lack of disk space + (closes: Bug#52714) + + -- Christopher C. Chimelis Wed, 19 Jan 2000 19:28:09 -0500 + +binutils (2.9.5.0.22-2) unstable; urgency=high + + * Added getopt.h include that was omitted in the -taso patch + (closes: Bug#52380) + * Fixed table misalignment when calling objdump --info + (closes: Bug#51517) + * Added Debian changelog to binutils-doc (closes: Bug#52574) + + -- Christopher C. Chimelis Wed, 15 Dec 1999 19:14:05 -0500 + +binutils (2.9.5.0.22-1) unstable; urgency=high + + * New upstream version. + * More MIPS fixes. + * Added support for -taso linker flag for Alpha. + * Reapplied all previous patches. + + -- Christopher C. Chimelis Wed, 7 Dec 1999 01:08:51 -0600 + +binutils (2.9.5.0.19-1) unstable; urgency=high + + * New upstream version + * Fixes some MIPS problems + * Reapplied the ObjC patch (is this ever going to be fixed upstream) + since it's badly needed right now + + -- Christopher C. Chimelis Thu, 4 Nov 1999 15:00:35 -0400 + +binutils (2.9.5.0.16-3) unstable; urgency=low + + * Added support for mipsel-linux in binutils-multiarch + + -- Christopher C. Chimelis Thu, 4 Nov 1999 15:00:35 -0400 + +binutils (2.9.5.0.16-2) unstable; urgency=low + + * Added a replaces field in the control file to fix + previous file overwrite problems (closes: Bug#47518, Bug#47938) + * Verified manpages are up to date (closes: Bug#18483) + * Added m68k-rtems to targets in -multiarch in hopes + that it will actually work as advertised (closes: Bug#47468) + + -- Christopher C. Chimelis Mon, 25 Oct 1999 15:58:55 -0400 + +binutils (2.9.5.0.16-1) unstable; urgency=low + + * New upstream version. + * Massive bugfix upload on the Debian side: + * Fixes changelog problems between all of the binutils + debs (closes: Bug#47133, Bug#47208, Bug#47211) + * Fixes other overwrite problems (closes: Bug#46991, Bug#47024, Bug#46074) + * Multiarch should now make good diversions when + upgrading (closes: Bug#47359) + * Applied patch from Kevin Buhr to fix ld segfaults with + empty archives (closes: Bug#47019) + * Should have fixed info install problems by now + (closes: Bug#35935) + + -- Christopher C. Chimelis Fri, 15 Oct 1999 03:18:55 -0400 + +binutils (2.9.5.0.14-1) unstable; urgency=low + + * New upstream version. + * Thanks to Matthias Klose for the following: + * Separate documentation to binutils-doc package. + * debian/rules: + - Remove extra /usr/share/doc/binutils/changelog.gz file. + - Move bfd docs to binutils-dev package. + - Move upstream changelogs to binutils-doc package. + - Remove standard GNU info files left in /usr/share/info. + - Call dh_installdocs for all packages. + * debian/*{dirs,files}: Remove. Mention explicitely in debian/rules. + + -- Christopher C. Chimelis Wed, 6 Oct 1999 03:18:55 -0400 + +binutils (2.9.5.0.12-2) unstable; urgency=low + + * Applied patch from Matthias Klose to fix many issues including architecture detection. + * Rules file is now much prettier and easier to manage. + * Binutils is now built for i386 rather than i486 in the rules file (oops). + * Added diversion for readelf in binutils-multiarch. + + -- Christopher C. Chimelis Tue, 21 Sep 1999 03:39:08 -0400 + +binutils (2.9.5.0.12-1) unstable; urgency=low + + * Massive bugfix release. + * New upstream source (finally) (closes: Bug#44934) + * Fixes upstream bugs on many platforms. + * Gives powerpc a working binutils again. (closes: Bug#45052) + * Now provides .code16 support on i386 (please test) + * Manpage for objdump should now be complete (closes: Bug#27039) + * Put together manpages for gasp and the new binary readelf (closes: Bug#21918) + * Fixes nm core dump problem (closes: Bug#41999) + * Applied patches from Ben Collins to add sparc64 support (closes: Bug#44426) + * Update Standards version + * FHS compliance + + -- Christopher C. Chimelis Sat, 18 Sept 1999 01:21:05 -0400 + +binutils (2.9.5.0.12-0.2) experimental; urgency=low + + * Added Sparc/Sparc64 changes from Ben Collins (I really need a Sparc one of these days). + * Again, this should be the last experimental before a new release. + + -- Christopher C. Chimelis Fri, 17 Aug 1999 16:32:05 -0400 + +binutils (2.9.5.0.12-0.1) experimental; urgency=low + + * New upstream version. + * Should be the last experimental before a new release. + + -- Christopher C. Chimelis Thu, 9 Aug 1999 23:12:52 -0400 + +binutils (2.9.5.0.10-0.1) experimental; urgency=low + + * New upstream version. + * Didn't apply PPC patches...let me know if still needed + + -- Christopher C. Chimelis Thu, 9 Aug 1999 23:12:52 -0400 + +binutils (2.9.5.0.6-0.1) experimental; urgency=low + + * New upstream version. + * Didn't apply PPC patches...let me know if still needed + + -- Christopher C. Chimelis Thu, 9 Aug 1999 23:12:52 -0400 + +binutils (2.9.4.0.8-0.1) unstable; urgency=low + + * New upstream version. + * Applied as much of the PPC patches as I could. + + -- Christopher C. Chimelis Thu, 15 Jul 1999 12:46:45 -0400 + +binutils (2.9.4.0.3-0.1) unstable; urgency=low + + * New upstream version. + * Apply patch from Richard Henderson to fix PPC's libpath. + * Apply patch from Franz Sirl to fix Richard Henderson. + + -- Daniel Jacobowitz Sun, 6 Jun 1999 01:27:10 -0400 + +binutils (2.9.4.0.2-0.1) unstable; urgency=low + + * New upstream version. 2.9.4.0.1 was hurriedly recalled. + + -- Daniel Jacobowitz Sun, 6 Jun 1999 01:27:10 -0400 + +binutils (2.9.4.0.1-0.1) unstable; urgency=low + + * New upstream version. + + -- Daniel Jacobowitz Sun, 6 Jun 1999 01:27:10 -0400 + +binutils (2.9.1.0.25-2) unstable; urgency=low + + * Added ObjC patch AGAIN...sorry about that + + -- Christopher C. Chimelis Sun, 23 May 1999 15:14:35 -0400 + +binutils (2.9.1.0.25-1) unstable; urgency=low + + * New upstream version - Fixes a PIII asm optimisation bug + + -- Christopher C. Chimelis Sun, 23 May 1999 00:36:55 -0400 + +binutils (2.9.1.0.24-2) unstable; urgency=low + + * Reapplied ObjC patch...apparently it's still needed. + + -- Christopher C. Chimelis Mon, 10 May 1999 19:53:15 -0400 + +binutils (2.9.1.0.24-1) unstable; urgency=low + + * New upstream release - fixes too many little things to mention. + + -- Christopher C. Chimelis Tue, 3 May 1999 16:35:08 -0400 + +binutils (2.9.1.0.23-1) unstable; urgency=low + + * New upstream release - incorporates sparc64 and arm patches. + * Added RPATH patch from Joel Klecker since my last upload failed. + * Removed ObjC patch. Let me know if it is still needed (doubtful, but + still might be). + + -- Christopher C. Chimelis Mon, 5 Apr 1999 13:26:55 -0500 + +binutils (2.9.1.0.22b-2) unstable; urgency=low + + * Added patch from Joel Klecker to finally (properly) fix the rpath issue + (Thanks, Joel!). + + -- Christopher C. Chimelis Fri, 2 Apr 1999 18:14:05 -0600 + +binutils (2.9.1.0.22b-1) unstable; urgency=low + + * Converted package to CVS (so bear with any delays in handling + bug fixes; I'm new to CVS ironically) + * New upstream version (sparc64 and ARM patches again added). + * Added support for mingw32 target in binutils-multiarch + + -- Christopher C. Chimelis Fri, 12 Mar 1999 03:51:44 -0600 + +binutils (2.9.1.0.19a-4) frozen unstable; urgency=high + * Added sparc64 patches from Steve Dunham to fix sparc64 targets + * Modified rules to add support for gcc/egcs by arch. + + -- Christopher C. Chimelis Mon, 1 Feb 1999 15:51:19 -0600 + +binutils (2.9.1.0.19a-3) frozen unstable; urgency=high + + * Reverted a patch to elflink.h that caused problems for + Obj-C code (symbols weren't exported with a size or + type). + + -- Christopher C. Chimelis Thu, 21 Jan 1999 19:25:17 -0600 + +binutils (2.9.1.0.19a-2) frozen unstable; urgency=low + + * Added arm-linux as multiarch target (sorry Jim). + * Uploaded to frozen to fix strange intermittant kernel + compilation problems (Fixes #31434). + * Fixed multiarch's postinst script to check for + c++filt.single before trying to remove it to prevent + warning messages if using g++ from egcs. + * Fixed typo in multiarch's postrm (addr2line) (Fixes: #31533) + * Added links to .so's for clean removal in the future (Fixes: #31536) + + -- Christopher C. Chimelis Fri, 8 Jan 1999 15:28:32 -0600 + +binutils (2.9.1.0.19a-1) unstable; urgency=low + + * New upstream version; fixes some Alpha problems and other archs + should benefit also. + * Added ARM target patch from Corel again (still not in upstream). + + -- Christopher C. Chimelis Mon, 4 Jan 1999 20:24:36 -0600 + +binutils (2.9.1.0.16-1) unstable; urgency=low + + * New upstream version; merges some ARM patches for Netwinders + * Added patch for ARM target from Corel (thanks Jim Pick) + + -- Christopher C. Chimelis Mon, 30 Nov 1998 16:59:25 -0600 + +binutils (2.9.1.0.15-5) frozen unstable; urgency=low + + * Reuploaded to frozen (why it wasn't there earlier....) + + -- Christopher C. Chimelis Mon, 30 Nov 1998 16:37:08 -0600 + +binutils (2.9.1.0.15-4) unstable frozen; urgency=low + + * Removed c++filt diversion in -multiarch to prevent conflicting + diversions when using egcs' g++ (which also wants to divert c++filt) + + -- Christopher C. Chimelis Wed, 25 Nov 1998 18:06:17 -0600 + +binutils (2.9.1.0.15-3) unstable frozen; urgency=low + + * Made Roman's changes "official" (thanks Roman). + + -- Christopher C. Chimelis Mon, 2 Nov 1998 05:46:56 -0600 + +binutils (2.9.1.0.15-2.1) unstable; urgency=low + + * Non-maintainer upload with agreement from Chris. + * Use a different soname for multi-arch libbfd and libopcodes; this + fixes the problem that the single-arch binaries (as and the diverted + ones) will all dump core because they're runtime-linked against the + multi-arch libs. (Fixes: #28656) + * Due to the above, binutils-multiarch also needs ldconfig in postinst + now. + * Fixup diversions once again: Do not even package the ldscripts for the + native architecture, so diversions for files in /usr/lib/ldscripts + aren't necessary. + * Also remove diversions on abort-install. + * Remove now obsolete diversions in preinst. + * Also symlink /usr/doc/binutils-multiarch to binutils, and do not + put /usr/doc/binutils in the package again. + * Put the symlinks libbfd.so and libopcode.so into binutils-dev, so one + can link to them. + + -- Roman Hodek Sat, 31 Oct 1998 11:31:14 +0100 + +binutils (2.9.1.0.15-2) unstable; urgency=low + + * Fixed binutils-multiarch diversions + * Reverted elf.c to .13 version to fix bug in strip + + -- Christopher C. Chimelis Tue, 27 Oct 1998 05:26:28 -0600 + +binutils (2.9.1.0.15-1) unstable; urgency=low + + * New upstream version. + * Moved over to debhelper and updated standards version to 2.4.1.4. + * Adds 3DNow instruction support for AMD processors. + * Fixes MANY Alpha bugs and a few for Sparc, PPC, and m68k reportedly. + * Added binutils-multiarch package to allow for multiple-arch support + (fixes bug #19471). + + -- Christopher C. Chimelis Thu, 14 Oct 1998 19:30:10 -0500 + +binutils (2.9.1.0.13-1) unstable; urgency=low + + * New upstream version, fixes bug #25354. + * Hopefully, all requested docs are included, fixes bug #21325. + * Fixes MANY Alpha problems. + * Reportedly may fix MIPS and Sparc problems also...see changelogs. + * Has been tested on x86's with great success. + + -- Christopher C. Chimelis Mon, 5 Oct 1998 23:02:08 -0500 + +binutils (2.9.1-0.2) frozen unstable; urgency=low + + * Fixed binutils-dev dependencies. + + -- Joel Klecker Tue, 05 May 1998 09:24:04 -0700 + +binutils (2.9.1-0.1) frozen unstable; urgency=medium + + * Non-maintainer release. + * New upstream release. + * Moved docs into subdirs where appropriate. + * Integrated the following changes from J.H.M. Dassen: + * Updated FSF address in copyright file. (lintian). + * Reported lack of "gasp" manpage (# ....), and link it to + undocumented(7). (lintian). + * Added a TODO list. + + -- Joel Klecker Thu, 30 Apr 1998 10:43:42 -0700 + +binutils (2.9-0.3) frozen unstable; urgency=medium + + * Added upstream patch which fixes a problem with strip + and netscape (#17971). + + -- Joel Klecker Tue, 28 Apr 1998 08:58:27 -0700 + +binutils (2.9-0.2) frozen unstable; urgency=low + + * Added more of the upstream docs (#21325). + * Put a changelog.gz symlink in /usr/doc/binutils + to satisfy policy. + + -- Joel Klecker Tue, 21 Apr 1998 09:02:22 -0700 + +binutils (2.9-0.1) frozen unstable; urgency=low + + * Non-maintainer release. + * New upstream release (bugfixes only). + + -- Joel Klecker Sun, 12 Apr 1998 04:11:07 -0700 + +binutils (2.8.1.0.23-1) unstable; urgency=low + + * New upstream version + * -dev replaces libc5-dev (#17840) + * No longer possible to link against shared libbbfd/opcodes (#18121) + + -- Galen Hazelwood Sat, 14 Mar 1998 18:19:10 -0700 + +binutils (2.8.1.0.19-1) unstable; urgency=low + + * New upstream version (#17296) + * Fixed typo in description (#16481) + * Fully replaces libbfd-dev (#16619) + + -- Galen Hazelwood Sun, 25 Jan 1998 15:37:03 -0700 + +binutils (2.8.1.0.17-1) unstable; urgency=low + + * New upstream version + * Rejoined libbfd and binutils packages (#15486) + * Added "SHELL=bash" to rules file (#14528) + * bfd info docs seem to be broken, don't install for now + + -- Galen Hazelwood Sat, 6 Dec 1997 14:55:26 -0700 + +binutils (2.8.1.0.15-1) unstable; urgency=low + + * New upstream version (#14250) + * Updated to Standard 2.3.0.0 + * Restored ansidecl.h to libbfd-dev (#14116) + + -- Galen Hazelwood Thu, 30 Oct 1997 20:04:24 -0700 + +binutils (2.8.1-2) unstable; urgency=low + + * Added 2.8.1.0.4 patch + + -- Galen Hazelwood Thu, 12 Jun 1997 20:49:57 -0600 + +binutils (2.8.1-1) unstable; urgency=low + + * New upstream version + * Added 2.8.1.0.1 patch + + -- Galen Hazelwood Fri, 30 May 1997 14:48:42 -0600 + +binutils (2.8-1) unstable; urgency=low + + * New upstream version + * Smarter debian build environment (automatic version handling) + * Added 2.8.0.3 patch + * Built with libc6 + + -- Galen Hazelwood Sun, 4 May 1997 11:16:12 -0600 + +binutils (2.7.0.9-3) frozen unstable; urgency=low + + * Patched for alpha support + * Distribute libiberty.a with -dev package (#8376) + * libbfd[x]-dev now has standard Provides/Conflicts behavior (#8377) + + -- Galen Hazelwood Fri, 28 Mar 1997 11:45:58 -0700 + +binutils (2.7.0.9-2) unstable; urgency=low + + * Moved 2.7.0.9 out of experimental (no longer unreleased beta) + + -- Galen Hazelwood Sun, 9 Mar 1997 23:43:19 -0700 + +binutils (2.7.0.9-1) experimental; urgency=low + + * New upstream beta version (fixes bug #7336) + * Split shared libraries (bfd) out of binutils (fixes bug #7244) + * No longer builds aout-binutils + + -- Galen Hazelwood Thu, 13 Feb 1997 00:27:18 -0700 + +binutils (2.7-6) unstable; urgency=low + + * Uses dpkg --print-gnu-build-architecture for build + * Demoted aout-binutils to priority "extra" + + -- Galen Hazelwood Mon, 27 Jan 1997 13:34:08 -0700 + +binutils (2.7-5) unstable; urgency=low (HIGH for m68k) + + * Added patch for m68k, will now compile X68 and kernel 2.1.15 + + -- Galen Hazelwood Tue, 31 Dec 1996 22:15:03 -0700 + +binutils (2.7-4) unstable; urgency=low + + * New maintainer + * Updated to new source format + * Fixed typo in script.1 (Fixes bug #4558) + * Fixed typo in as.1 (Fixes bug #5567) + * Postinst now calls ldconfig without explicit pathname (Fixes bug #6151) + + -- Galen Hazelwood Mon, 30 Dec 1996 12:10:25 -0700 + +binutils (2.7-3): + +Remove lib*.so links so the libs are not used for develpment. +gzip manpages + +Changes made by Michael Meskes in consent with David Engel. + +binutils (2.7-2): + +Include shared libraries +Strip shared libraries +Also update AOUT version +Minor changes to debian.rules + +binutils (2.7-1): + +Updated to new upstream version. + +Added a simple extended description (Bug#3574). + +Don't call ldconfig from postrm script (Bug#4246). + + LocalWords: Aurelien Jarno + --- binutils-2.20.orig/debian/control.cross.in +++ binutils-2.20/debian/control.cross.in @@ -0,0 +1,11 @@ +Package: binutils-__TARGET__ +Architecture: any +Depends: binutils, ${shlibs:Depends} +Suggests: binutils-doc (= ${Source-Version}) +Priority: extra +Description: The GNU binary utilities, for __TARGET__ target + This package provides GNU assembler, linker and binary utilities + for __TARGET__ target, for use in a cross-compilation environment. + . + You don't need this package unless you plan to cross-compile programs + for __TARGET__. --- binutils-2.20.orig/debian/binutils-gold.preinst +++ binutils-2.20/debian/binutils-gold.preinst @@ -0,0 +1,10 @@ +#! /bin/sh + +set -e + +if [ install = "$1" -o upgrade = "$1" ]; then + dpkg-divert \ + --package binutils-gold \ + --add --rename \ + --divert /usr/bin/ld.single /usr/bin/ld +fi --- binutils-2.20.orig/debian/binutils-multiarch.preinst +++ binutils-2.20/debian/binutils-multiarch.preinst @@ -0,0 +1,82 @@ +#! /bin/sh + +set -e + +if [ install = "$1" -o upgrade = "$1" ]; then + + for f in size objdump ar strings ranlib objcopy addr2line \ + readelf nm strip gprof; do + dpkg-divert --package binutils-multiarch \ + --add --rename \ + --divert /usr/bin/$f.single /usr/bin/$f + done + + dpkg-divert --package binutils-multiarch \ + --add --rename \ + --divert /usr/lib/libbfd-single.a /usr/lib/libbfd.a + dpkg-divert --package binutils-multiarch \ + --add --rename \ + --divert /usr/lib/libopcodes-single.a /usr/lib/libopcodes.a + + if [ -x /usr/bin/ld.single ]; then + rm -f /usr/bin/ld + dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/bin/ld.single /usr/bin/ld \ + | grep -v '^No diversion' || true + fi + +fi + +# remove obsolete diversions +for f in elf32_sparc elf32ppc elf64alpha elf_i386 m68kelf \ + alpha i386linux m68klinux sparclinux sun4; do + for ext in x xbn xn xr xs xu; do + dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/lib/ldscripts/$f.$ext.single \ + /usr/lib/ldscripts/$f.$ext \ + | grep -v '^No diversion' || true + done +done +dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/lib/libbfd-single-2.9.1.0.15.so.0.0.0 \ + /usr/lib/libbfd-2.9.1.0.15.so.0.0.0 \ + | grep -v '^No diversion' || true +dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/lib/libopcodes-single-2.9.1.0.15.so.0.0.0 \ + /usr/lib/libopcodes-2.9.1.0.15.so.0.0.0 \ + | grep -v '^No diversion' || true +dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/lib/libbfd-single.la \ + /usr/lib/libbfd.la \ + | grep -v '^No diversion' || true +dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/lib/libopcodes-single.la \ + /usr/lib/libopcodes.la \ + | grep -v '^No diversion' || true +dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/include/bfd.single.h /usr/include/bfd.h \ + | grep -v '^No diversion' || true +dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/lib/ldscripts.single /usr/lib/ldscripts \ + | grep -v '^No diversion' || true +if [ -e /usr/bin/c++filt.single ]; then +dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/bin/c++filt.single /usr/bin/c++filt \ + | grep -v '^No diversion' || true +fi + +if [ -e /usr/lib/libbfd-*-multiarch.so.0 ]; then + rm -f libbfd-*-multiarch.so.0; +fi +if [ -e /usr/lib/libopcodes-*-multiarch.so.0 ]; then + rm -f libopcodes-*-multiarch.so.0; +fi --- binutils-2.20.orig/debian/control.gold +++ binutils-2.20/debian/control.gold @@ -0,0 +1,13 @@ + +Package: binutils-gold +Architecture: amd64 i386 lpia powerpc sparc +Priority: extra +Depends: ${shlibs:Depends}, binutils (= ${Source-Version}) +Conflicts: binutils-multiarch +Description: The (experimental) GNU gold linker utility + Gold is a new linker, still in development, which is faster than the + current linker included in binutils. It currently fails to link some + applications and libraries (i.e. won't link usable kernels). + . + This package diverts the GNU linker (ld) with the experimental gold + linker. --- binutils-2.20.orig/debian/README.source +++ binutils-2.20/debian/README.source @@ -0,0 +1,2 @@ +The package uses dpatch to apply patches on top of the upstream source. +See /usr/share/doc/dpatch/README.source.gz. --- binutils-2.20.orig/debian/binutils-spu.postrm +++ binutils-2.20/debian/binutils-spu.postrm @@ -0,0 +1,7 @@ +#! /bin/sh + +set -e + +if [ "$1" = "remove" ]; then + ldconfig +fi --- binutils-2.20.orig/debian/binutils-gold.postrm +++ binutils-2.20/debian/binutils-gold.postrm @@ -0,0 +1,10 @@ +#! /bin/sh + +set -e + +if [ "$1" = "remove" -o "$1" = "abort-install" ]; then + dpkg-divert \ + --package binutils-gold \ + --remove --rename \ + --divert /usr/bin/ld.single /usr/bin/ld +fi --- binutils-2.20.orig/debian/binutils.postrm +++ binutils-2.20/debian/binutils.postrm @@ -0,0 +1,7 @@ +#! /bin/sh + +set -e + +if [ "$1" = "remove" ]; then + ldconfig +fi --- binutils-2.20.orig/debian/binutils.postinst +++ binutils-2.20/debian/binutils.postinst @@ -0,0 +1,7 @@ +#! /bin/sh + +set -e + +if [ "$1" = "configure" ]; then + ldconfig +fi --- binutils-2.20.orig/debian/README.cross +++ binutils-2.20/debian/README.cross @@ -0,0 +1,22 @@ +Cross-binutils debian packages can be built directly from the binutils +source package. + +To build a cross-binutils package: + + o Download and unpack the binutils source package: + + apt-get source binutils + + o Ensure you have the binutils build-dependencies installed: + + apt-get build-dep binutils + + o Then build the cross-binutils package: + + TARGET= fakeroot debian/rules binary-cross + + (substitute your target name, e.g. "arm" or "m68k", instead of + "") + +--- +Nikita Youshchenko --- binutils-2.20.orig/debian/rules +++ binutils-2.20/debian/rules @@ -0,0 +1,1101 @@ +#!/usr/bin/make -f +# debian/rules file - for binutils (2.20) +# Based on sample debian/rules file - for GNU Hello (1.3). +# Copyright 1994,1995 by Ian Jackson. +# Copyright 1998-2007 James Troup. +# Portions Copyright 2008-2009 Canonical Ltd. +# Portions Copyright 2008-2009 Matthias Klose. +# I hereby give you perpetual unlimited permission to copy, +# modify and relicense this file, provided that you do not remove +# my name from the file itself. (I assert my moral right of +# paternity under the Copyright, Designs and Patents Act 1988.) +# This file may have to be extensively modified + +################################################################################ + +include /usr/share/dpatch/dpatch.make + +################################################################################ + +p_bin = binutils +p_dev = $(p_bin)-dev +p_mul = $(p_bin)-multiarch +p_gold = $(p_bin)-gold +p_doc = $(p_bin)-doc +p_static = $(p_bin)-static +p_udeb = $(p_static)-udeb +p_hppa64 = $(p_bin)-hppa64 +p_spu = $(p_bin)-spu +p_src = $(p_bin)-source + +pwd := $(shell pwd) +d = debian/tmp +d_bin = $(d) +d_dev = debian/$(p_dev) +d_mul = debian/$(p_mul) +d_gold = debian/$(p_gold) +d_doc = debian/$(p_doc) +d_static = debian/$(p_static) +d_udeb = debian/$(p_udeb) +d_hppa64 = debian/$(p_hppa64) +d_spu = debian/$(p_spu) +d_src = debian/$(p_src) + +install_dir = install -d -m 755 +install_file = install -m 644 +install_script = install -m 755 +install_binary = install -m 755 -s + +DEB_BUILD_GNU_TYPE := $(shell dpkg-architecture -qDEB_BUILD_GNU_TYPE) +DEB_HOST_ARCH := $(shell dpkg-architecture -qDEB_HOST_ARCH) +DEB_HOST_GNU_TYPE := $(shell dpkg-architecture -qDEB_HOST_GNU_TYPE) + +SHELL = /bin/bash + +ifneq (,$(filter $(DEB_HOST_ARCH), amd64 armel i386 lpia powerpc sparc)) + with_gold = yes +endif + +with_multiarch := yes +with_static := yes + +CC = gcc +CXX = g++ +CFLAGS = -g -O2 -Wno-format-security +STRIP = strip --remove-section=.comment --remove-section=.note +ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE)) + CC = $(DEB_HOST_GNU_TYPE)-gcc + CXX = $(DEB_HOST_GNU_TYPE)-g++ +endif + +ifneq (,$(findstring noopt,$(DEB_BUILD_OPTIONS))) + CFLAGS = -g -O0 -Wno-format-security +endif + +# see LP: #446478, would only fix the testcases +#ifeq ($(DEB_HOST_ARCH),armel) +# CFLAGS += -fno-section-anchors +#endif + +DEB_VERSION = $(shell dpkg-parsechangelog | grep ^Version: | cut -d' ' -f2 | sed 's/.*://') +STATIC_UDEB = $(p_udeb)_$(DEB_VERSION)_$(DEB_HOST_ARCH).udeb + +VERSION = $(shell sed -n 's/^ *VERSION=\(.*\)/\1/p' bfd/configure | head -1) +MULTI_VERSION = $(VERSION)-multiarch +HPPA64_VERSION= $(VERSION)-hppa64 +SPU_VERSION = $(VERSION)-spu + +DISTRIBUTION := $(shell lsb_release -is) +NJOBS = +# Support parallel= in DEB_BUILD_OPTIONS (see #209008) +SPACE = $(EMPTY) $(EMPTY) +COMMA = , +ifneq (,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS)))) + NJOBS := -j $(subst parallel=,,$(filter parallel=%,$(subst $(COMMA), ,$(DEB_BUILD_OPTIONS)))) +endif +ifneq (,$(findstring nogold,$(DEB_BUILD_OPTIONS))) + with_gold = disabled in DEB_BUILD_OPTIONS +endif +ifneq (,$(findstring nostat,$(DEB_BUILD_OPTIONS))) + with_static = disabled in DEB_BUILD_OPTIONS +endif +ifneq (,$(findstring nomult,$(DEB_BUILD_OPTIONS))) + with_multiarch = disabled in DEB_BUILD_OPTIONS +endif + +######################################## + +CONFARGS = \ + --enable-shared \ + --enable-plugins \ + --prefix=/usr \ + --build=$(DEB_BUILD_GNU_TYPE) \ + --host=$(DEB_HOST_GNU_TYPE) \ + --with-pkgversion="GNU Binutils for $(DISTRIBUTION)" + +ifeq ($(DEB_HOST_ARCH),sparc) + CONFARGS += --enable-targets=sparc64-linux-gnu + CONFLICTS = -VextraConflicts="libc6-dev-sparc64 (<< 2.2.5-7)" +endif +ifeq ($(DEB_HOST_ARCH),sparc64) + CONFARGS += --enable-targets=sparc-linux-gnu + CONFLICTS = -VextraConflicts="libc6-dev-sparc64 (<< 2.2.5-7)" +endif +ifeq ($(DEB_HOST_ARCH),powerpc) + CONFARGS += --enable-targets=powerpc64-linux-gnu,spu +endif +ifeq ($(DEB_HOST_ARCH),ppc64) + CONFARGS += --enable-targets=powerpc-linux-gnu,spu +endif +ifeq ($(DEB_HOST_ARCH),s390) + CONFARGS += --enable-targets=s390x-linux-gnu +endif +ifeq ($(DEB_HOST_ARCH),i386) + CONFARGS += --enable-targets=x86_64-linux-gnu +endif +ifeq ($(DEB_HOST_ARCH),kfreebsd-i386) + CONFARGS += --enable-targets=x86_64-kfreebsd-gnu +endif +ifeq ($(DEB_HOST_ARCH),mips) + CONFARGS += --enable-targets=mips64-linux-gnu +endif +ifeq ($(DEB_HOST_ARCH),mipsel) + CONFARGS += --enable-targets=mips64el-linux-gnu +endif +ifeq ($(DEB_HOST_ARCH),ia64) + CONFARGS += --disable-werror +endif + +with_check := yes +ifneq (,$(findstring nocheck,$(DEB_BUILD_OPTIONS))) + with_check := disabled through DEB_BUILD_OPTIONS +endif +ifneq (,$(filter $(DEB_HOST_ARCH),hppa)) + with_check := disabled for architecture $(DEB_HOST_ARCH) +endif +ifneq (,$(filter $(DEB_HOST_ARCH),mips mipsel)) + ignore_regressions := regressions ignored on architecture $(DEB_HOST_ARCH) +endif +with_strip := yes +ifneq (,$(findstring nostrip,$(DEB_BUILD_OPTIONS))) + with_strip := disabled through DEB_BUILD_OPTIONS +endif + +source_files = $(addprefix $(shell basename $(pwd))/, \ + $(filter-out %-stamp CVS debian builddir-% test-summary, $(wildcard *))) + +################################################################################ + +################ +# clean target # +################ + +clean: unpatch + $(checkdir) + -rm -fr builddir-multi builddir-single builddir-hppa64 builddir-spu builddir-gold + -find . -name \*.gmo -o -name \*~ -o -name \*.info ! -name sysroff.info | xargs rm -f + -rm -f $(pwd)/test-summary* + -rm -fr $(d_bin) $(d_dev) $(d_mul) $(d_doc) $(d_hppa64) $(d_src) $(d_spu) $(d_gold) + -rm -fr builddir-static + -rm -fr $(d_static) $(d_udeb) + -rm -rf debian/patched debian/tmp debian/files* debian/substvars + chmod 644 debian/patches/*.dpatch + -rm -f *-stamp + +################################################################################ + +####################### +# single-arch targets # +####################### + +configure-single-stamp: patch-stamp + $(checkdir) + +ifeq ($(with_check),yes) + @if echo "spawn true" | /usr/bin/expect -f - >/dev/null; then \ + : ; \ + else \ + echo "expect is failing on your system with the above error, which means the"; \ + echo "testsuite will fail. Please resolve the above issues and retry the build."; \ + echo "-----------------------------------------------------------------------------"; \ + exit 1; \ + fi +endif + + rm -rf configure-single-stamp \ + builddir-single + mkdir builddir-single + cd builddir-single && env CC="$(CC)" CXX="$(CXX)" CFLAGS="$(CFLAGS)" \ + ../configure $(CONFARGS) + $(MAKE) -C builddir-single configure-host + touch configure-single-stamp + +build-single-stamp: configure-single-stamp + $(checkdir) + $(MAKE) -C builddir-single/bfd headers + $(MAKE) $(NJOBS) -C builddir-single +ifeq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE)) +ifeq ($(with_check),yes) + -$(MAKE) -C builddir-single -k check + cat builddir-single/binutils/binutils.sum \ + builddir-single/gas/testsuite/gas.sum \ + builddir-single/ld/ld.sum >> $(pwd)/test-summary + set -e; \ + if [ -x /usr/bin/python ]; then \ + echo "Test results, compared with installed binutils:"; \ + zcat /usr/share/doc/binutils/test-summary.gz > test-summary-installed; \ + if python debian/test-suite-compare.py test-summary-installed test-summary; then \ + : ; \ + elif [ -n "$(ignore_regressions)" ]; then \ + echo "$(ignore_regressions)"; \ + else \ + false; \ + fi; \ + else \ + echo "python not installed, not comparing test results."; \ + fi +endif +endif + touch build-single-stamp + +################################################################################ + +####################### +# gold-arch targets # +####################### + +GOLD_CONFARGS = --enable-gold +ifneq (,$(filter $(DEB_HOST_ARCH), amd64 i386)) + GOLD_CONFARGS += --enable-targets=i486-linux-gnu,x86_64-linux-gnu +endif +ifeq ($(DEB_HOST_ARCH),powerpc) + GOLD_CONFARGS += --enable-targets=powerpc-linux-gnu +endif + +configure-gold-stamp: patch-stamp + $(checkdir) + rm -rf configure-gold-stamp \ + builddir-gold + mkdir builddir-gold + cd builddir-gold && env CC="$(CC)" CXX="$(CXX)" CFLAGS="$(CFLAGS)" CXXFLAGS="$(CFLAGS) -Wno-error" \ + ../configure $(CONFARGS) $(GOLD_CONFARGS) + $(MAKE) -C builddir-gold configure-host + touch configure-gold-stamp + +build-gold-stamp: configure-gold-stamp + $(checkdir) + $(MAKE) -C builddir-gold/bfd headers + $(MAKE) $(NJOBS) -C builddir-gold +ifeq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE)) +ifeq ($(with_check),yes) + -$(MAKE) $(NJOBS) -C builddir-gold/testsuite \ + && ( \ + $(MAKE) -C builddir-gold/gold -k check \ + && echo "XXX gold subdir check" \ + && $(MAKE) -C builddir-gold/gold/testsuite -k check) +endif +endif + touch build-gold-stamp + +################################################################################ + +##################### +# multiarch targets # +##################### + +multiarch_targets = \ + alpha-linux-gnu \ + arm-linux-gnu \ + armel-linux-gnu \ + hppa-linux-gnu \ + i486-gnu \ + i486-linux-gnu \ + ia64-linux-gnu \ + m68k-linux-gnu \ + m68k-rtems \ + mips-linux-gnu \ + mipsel-linux-gnu \ + mips64-linux-gnu \ + mips64el-linux-gnu \ + powerpc-linux-gnu \ + powerpc64-linux-gnu \ + s390-linux-gnu \ + s390x-linux-gnu \ + sh-linux-gnu \ + sh64-linux-gnu \ + sparc-linux-gnu \ + sparc64-linux-gnu \ + x86_64-linux-gnu \ + m32r-linux-gnu \ + spu + +configure-multi-stamp: patch-stamp + $(checkdir) + rm -rf configure-multi-stamp \ + builddir-multi + mkdir builddir-multi + cd builddir-multi \ + && env CC="$(CC)" CXX="$(CXX)" CFLAGS="$(CFLAGS)" ../configure $(CONFARGS) \ + --enable-targets=$(subst $(SPACE),$(COMMA),$(multiarch_targets)) + $(MAKE) -C builddir-multi configure-host + touch configure-multi-stamp + +build-multi-stamp: configure-multi-stamp + $(checkdir) + $(MAKE) -C builddir-multi/bfd headers + env MAKE="$(MAKE) VERSION=$(MULTI_VERSION)" \ + $(MAKE) $(NJOBS) -C builddir-multi + touch build-multi-stamp + +################################################################################ + +################# +# static target # +################# + +configure-static-stamp: patch-stamp + $(checkdir) + rm -rf configure-static-stamp \ + builddir-static + mkdir builddir-static + cd builddir-static \ + && env CC="$(CC)" CXX="$(CXX)" CFLAGS="-g0 -Os" ../configure \ + --prefix=/usr \ + --build=$(DEB_BUILD_GNU_TYPE) \ + --host=$(DEB_HOST_GNU_TYPE) \ + --with-pkgversion="GNU Binutils for $(DISTRIBUTION)" + $(MAKE) -C builddir-static configure-bfd + $(MAKE) -C builddir-static configure-ld + touch configure-static-stamp + +build-static-stamp: configure-static-stamp + $(checkdir) + $(MAKE) $(NJOBS) -C builddir-static/libiberty CCLD='$(CC) -all-static' + $(MAKE) $(NJOBS) -C builddir-static/bfd CCLD='$(CC) -all-static' + $(MAKE) $(NJOBS) -C builddir-static/ld CCLD='$(CC) -all-static' + touch build-static-stamp + +################################################################################ + +################# +# hppa64 target # +################# + +configure-hppa64-stamp: patch-stamp + $(checkdir) + rm -rf configure-hppa64-stamp \ + builddir-hppa64 + mkdir builddir-hppa64 + cd builddir-hppa64 \ + && env CC="$(CC)" CXX="$(CXX)" CFLAGS="$(CFLAGS)" ../configure \ + --enable-shared \ + --prefix=/usr \ + --build=$(DEB_BUILD_GNU_TYPE) \ + --host=$(DEB_BUILD_GNU_TYPE) \ + --target=hppa64-linux-gnu + $(MAKE) -C builddir-hppa64 configure-host + touch configure-hppa64-stamp + +build-hppa64-stamp: configure-hppa64-stamp + $(checkdir) + $(MAKE) -C builddir-hppa64/bfd headers + env MAKE="$(MAKE) VERSION=$(HPPA64_VERSION)" \ + $(MAKE) $(NJOBS) -C builddir-hppa64 + touch build-hppa64-stamp + +################################################################################ + +############## +# spu target # +############## + +configure-spu-stamp: patch-stamp + $(checkdir) + rm -rf configure-spu-stamp \ + builddir-spu + mkdir builddir-spu + cd builddir-spu \ + && env CC="$(CC)" CFLAGS="$(CFLAGS)" ../configure \ + --enable-shared \ + --prefix=/usr \ + --program-prefix=spu- \ + --build=$(DEB_BUILD_GNU_TYPE) \ + --host=$(DEB_BUILD_GNU_TYPE) \ + --target=spu-elf + $(MAKE) -C builddir-spu configure-host + touch configure-spu-stamp + +build-spu-stamp: configure-spu-stamp + $(checkdir) + $(MAKE) -C builddir-spu/bfd headers + env MAKE="$(MAKE) VERSION=$(SPU_VERSION)" \ + $(MAKE) $(NJOBS) -C builddir-spu + touch build-spu-stamp + +################################################################################ + +pre-build: +#ifneq (,$(filter $(DEB_HOST_ARCH), armel powerpc)) +# @echo Build it ... +#else +# @echo Explicitely fail the build for architecture $(DEB_HOST_ARCH) +# false +#endif + +build_stamps = build-single-stamp +ifeq ($(with_multiarch),yes) + build_stamps += build-multi-stamp +endif +ifeq ($(DEB_HOST_ARCH),hppa) + build_stamps += build-hppa64-stamp +endif +ifneq (,$(filter $(DEB_HOST_ARCH),powerpc ppc64)) + build_stamps += build-spu-stamp +endif +ifeq ($(with_gold),yes) + build_stamps += build-gold-stamp +endif +ifeq ($(with_static),yes) + build_stamps += build-static-stamp +endif +build: pre-build build-stamp +build-stamp: $(build_stamps) + touch build-stamp + +################################################################################ + +################## +# install target # +################## + +install_stamps = install-stamp +ifeq ($(DEB_HOST_ARCH),hppa) + install_stamps += install-hppa64-stamp +endif +ifneq (,$(filter $(DEB_HOST_ARCH),powerpc ppc64)) + install_stamps += install-spu-stamp +endif +ifeq ($(with_gold),yes) + install_stamps += install-gold-stamp +endif +ifeq ($(with_static),yes) + install_stamps += install-static-stamp +endif +install: $(install_stamps) +install-stamp: checkroot build-stamp + $(checkdir) + + rm -fr $(d_bin) $(d_dev) $(d_mul) $(d_doc) $(d_src) + $(install_dir) $(d_bin) $(d_dev) $(d_mul) $(d_doc) $(d_src) + + : # install binutils and -dev stuff + $(MAKE) -C builddir-single \ + CFLAGS="$(CFLAGS)" prefix=$(pwd)/$(d_bin)/usr \ + mandir=$(pwd)/$(d_bin)/usr/share/man \ + infodir=$(pwd)/$(d_doc)/usr/share/info install + +ifeq ($(with_multiarch),yes) + : # now install binutils-multiarch stuff + env MAKE="$(MAKE) VERSION=$(MULTI_VERSION)" \ + $(MAKE) -C builddir-multi \ + CFLAGS="$(CFLAGS)" \ + prefix=$(pwd)/$(d_mul)/usr \ + mandir=$(pwd)/$(d_mul)/usr/share/man \ + infodir=$(pwd)/$(d_doc)/usr/share/info install +endif + + : # copy libiberty.h ... not too keen on this, but it was requested + cp -f include/libiberty.h $(d_bin)/usr/include + + : # copy demangle.h ... not too keen on this, but it was requested + cp -f include/demangle.h $(d_bin)/usr/include + + : # We don't need to distribute everything in binutils and -dev + rm -rf $(d_bin)/usr/include/obstack.h + rm -f $(d_bin)/usr/man/man1/configure.1 + rm -f $(d_doc)/usr/share/info/configure.* $(d_doc)/usr/share/info/standards.* + : # *sigh*, bugs.debian.org/213524 + rm -f $(d_doc)/usr/share/info/dir* + +ifeq ($(with_multiarch),yes) + : # Now get rid of just about everything in binutils-multiarch + rm -rf $(d_mul)/usr/man $(d_mul)/usr/info $(d_mul)/usr/include + rm -rf $(d_mul)/usr/share/man $(d_mul)/usr/share/info $(d_mul)/usr/share/locale + + : # Get rid of ld for the time being since it's suddenly unhappy when + : # linking kernels. Also get rid of the ldscripts for good measure. + rm -f $(d_mul)/usr/bin/as $(d_mul)/usr/bin/gasp $(d_mul)/usr/bin/c++filt \ + $(d_mul)/usr/bin/ld + rm -rf $(d_mul)/usr/lib/ldscripts + ifneq (,$(filter $(DEB_HOST_ARCH),powerpc ppc64)) + rm -f $(d_mul)/usr/bin/embedspu + endif +endif + + $(install_dir) $(d_dev)/usr/include/ $(d_dev)/usr/lib/ + mv $(d_bin)/usr/include/* $(d_dev)/usr/include/ + mv $(d_bin)/usr/lib/*.a $(d_bin)/usr/lib/libbfd.so $(d_bin)/usr/lib/libopcodes.so \ + $(d_dev)/usr/lib/ + +ifeq ($(with_multiarch),yes) + rm -f $(d_mul)/usr/lib/libbfd.so $(d_mul)/usr/lib/libopcodes.so + rm -f $(d_mul)/usr/lib/*.la $(d_mul)/usr/lib/*.a + rm -f $(d_mul)/usr/lib*/libiberty* +endif + + : # Get rid of .la files since libtool obviously has no idea about transient paths + rm -f $(d_bin)/usr/lib/*.la + +ifeq ($(with_strip),yes) + : # Strip shared libraries + pkg_create_dbgsym $(p_bin) $(d_bin) || true + $(STRIP) --strip-unneeded $(d_bin)/usr/lib/libbfd-*so + $(STRIP) --strip-unneeded $(d_bin)/usr/lib/libopcodes-*so + + chmod ugo-x $(d_bin)/usr/lib/*.so + + $(STRIP) $$(file $(d_bin)/usr/bin/* |awk -F: '$$0 !~ /script/ {print $$1}') + + ifeq ($(with_multiarch),yes) + pkg_create_dbgsym $(p_mul) $(d_mul) || true + $(STRIP) --strip-unneeded $(d_mul)/usr/lib/libbfd-*so + $(STRIP) --strip-unneeded $(d_mul)/usr/lib/libopcodes-*so + + chmod ugo-x $(d_mul)/usr/lib/*.so + + $(STRIP) $$(file $(d_mul)/usr/bin/* |awk -F: '$$0 !~ /script/ {print $$1}') + endif +endif + + : # Don't want /usr/-linux to exist in any package + rm -rf $(d_bin)/usr/$(DEB_HOST_GNU_TYPE) + + : # Remove windres manpages + rm -f $(d_bin)/usr/share/man/man1/windres.1 + +ifeq ($(with_multiarch),yes) + rm -rf $(d_mul)/usr/$(DEB_HOST_GNU_TYPE) + rm -f $(d_mul)/usr/share/man/man1/windres.1 +endif + + : # Remove empty directory + rmdir $(d_bin)/usr/include/ + + : # install libiberty PIC library + $(install_file) builddir-single/libiberty/pic/libiberty.a \ + $(d_dev)/usr/lib/libiberty_pic.a + + touch install-stamp + +install-gold-stamp: checkroot build-gold-stamp + $(checkdir) + + rm -fr $(d_gold) + $(install_dir) $(d_gold) + $(install_dir) $(d_gold)/usr/bin + + : # install binutils-gold stuff + $(MAKE) -C builddir-gold/gold \ + CFLAGS="$(CFLAGS)" \ + prefix=$(pwd)/$(d_gold)/usr/ \ + mandir=$(pwd)/$(d_gold)/usr/share/man \ + infodir=$(pwd)/$(d_gold)/usr/share/info install + + : # Don't want /usr/-linux to exist in any package + rm -rf $(d_gold)/usr/$(DEB_HOST_GNU_TYPE) + + : # Now get rid of just about everything in binutils-gold + rm -rf $(d_gold)/usr/man + rm -rf $(d_gold)/usr/info + rm -rf $(d_gold)/usr/include + rm -rf $(d_gold)/usr/share + rm -rf $(d_gold)/usr/hppa-linux-gnu + rm -rf $(d_gold)/usr/lib/libiberty.a + +ifeq ($(with_strip),yes) + pkg_create_dbgsym $(p_gold) $(d_gold) || true + $(STRIP) $$(file $(d_gold)/usr/bin/* | awk -F: '$$0 !~ /script/ {print $$1}') +endif + + touch install-gold-stamp + +install-hppa64-stamp: checkroot build-hppa64-stamp + $(checkdir) + + rm -fr $(d_hppa64) + $(install_dir) $(d_hppa64) + $(install_dir) $(d_hppa64)/usr/lib + + : # install binutils-hppa64 stuff + env MAKE="$(MAKE) VERSION=$(HPPA64_VERSION)" \ + $(MAKE) -C builddir-hppa64 \ + CFLAGS="$(CFLAGS)" \ + prefix=$(pwd)/$(d_hppa64)/usr/ \ + mandir=$(pwd)/$(d_hppa64)/usr/share/man \ + infodir=$(pwd)/$(d_hppa64)/usr/share/info install + + : # move shared libs to the standard path + mv $(d_hppa64)/usr/hppa-linux-gnu/hppa64-linux-gnu/lib/lib*-*.so \ + $(d_hppa64)/usr/lib/. + + : # Now get rid of just about everything in binutils-hppa64 + rm -rf $(d_hppa64)/usr/man + rm -rf $(d_hppa64)/usr/info + rm -rf $(d_hppa64)/usr/include + rm -rf $(d_hppa64)/usr/share + rm -rf $(d_hppa64)/usr/hppa-linux-gnu + rm -rf $(d_hppa64)/usr/lib/libiberty.a + +ifeq ($(with_strip),yes) + : # Strip shared libraries + pkg_create_dbgsym $(p_hppa64) $(d_hppa64) || true + $(STRIP) --strip-unneeded $(d_hppa64)/usr/lib/libbfd-*so + $(STRIP) --strip-unneeded $(d_hppa64)/usr/lib/libopcodes-*so + $(STRIP) $$(file $(d_hppa64)/usr/bin/* | awk -F: '$$0 !~ /script/ {print $$1}') +endif + + chmod ugo-x $(d_hppa64)/usr/lib/*.so + + : # Don't want /usr/-linux to exist in any package + rm -rf $(d_hppa64)/usr/hppa64-linux-gnu + + touch install-hppa64-stamp + +install-static-stamp: checkroot build-static-stamp + $(checkdir) + + rm -fr $(d_static) $(d_udeb) + $(install_dir) $(d_static) $(d_udeb) + + : # Copy static ld-new into /bin for both -static and -static-udeb + $(install_dir) $(d_static)/bin + $(install_binary) builddir-static/ld/ld-new $(d_static)/bin/ld_static + $(install_dir) $(d_udeb)/bin + $(install_binary) builddir-static/ld/ld-new $(d_udeb)/bin/ld_static +ifeq ($(with_strip),yes) + pkg_create_dbgsym $(p_static) $(d_static) || true + $(STRIP) --strip-unneeded $(d_static)/bin/ld_static $(d_udeb)/bin/ld_static +endif + + touch install-static-stamp + +install-spu-stamp: checkroot build-spu-stamp + $(checkdir) + + rm -fr $(d_spu) + $(install_dir) $(d_spu) + $(install_dir) $(d_spu)/usr/lib + + : # install binutils-spu stuff + env MAKE="$(MAKE) VERSION=$(SPU_VERSION)" \ + $(MAKE) -C builddir-spu \ + CFLAGS="$(CFLAGS)" \ + prefix=$(pwd)/$(d_spu)/usr/ \ + mandir=$(pwd)/$(d_spu)/usr/share/man \ + infodir=$(pwd)/$(d_spu)/usr/share/info install + + : # move shared libs to the standard path + mv $(d_spu)/usr/$(DEB_HOST_GNU_TYPE)/spu-elf/lib/lib*-*.so \ + $(d_spu)/usr/lib/. + + : # Now get rid of just about everything in binutils-spu + rm -rf $(d_spu)/usr/man + rm -rf $(d_spu)/usr/info + rm -rf $(d_spu)/usr/include + rm -rf $(d_spu)/usr/share + rm -rf $(d_spu)/usr/$(DEB_HOST_GNU_TYPE) + rm -rf $(d_spu)/usr/lib/libiberty.a + rm -rf $(d_spu)/usr/lib/ldscripts + +ifeq ($(with_strip),yes) + : # Strip shared libraries + pkg_create_dbgsym $(p_spu) $(d_spu) || true + $(STRIP) --strip-unneeded $(d_spu)/usr/lib/libbfd-*so + $(STRIP) --strip-unneeded $(d_spu)/usr/lib/libopcodes-*so + $(STRIP) $$(file $(d_spu)/usr/bin/* | awk -F: '$$0 !~ /script/ {print $$1}') +endif + + chmod ugo-x $(d_spu)/usr/lib/*.so + + : # Don't want /usr/-linux to exist in any package + rm -rf $(d_spu)/usr/spu-elf + + touch install-spu-stamp + +################################################################################ + +####################### +# binary-indep target # +####################### + +binary-indep: checkroot build install + $(checkdir) + + rm -f debian/files debian/substvars + + $(install_dir) $(d_doc)/DEBIAN + + $(install_dir) $(d_doc)/usr/share/doc/$(p_doc)/ + $(install_file) debian/changelog $(d_doc)/usr/share/doc/$(p_doc)/changelog.Debian + $(install_file) debian/copyright $(d_doc)/usr/share/doc/$(p_doc)/ + for i in bfd gas gprof ld; do \ + ln -sf ../$(p_bin)/$$i $(d_doc)/usr/share/doc/$(p_doc)/$$i; \ + done + find $(d_doc)/usr/share/doc/$(p_doc) -maxdepth 1 -type f ! -name copyright | xargs gzip -9 + gzip -9 $(d_doc)/usr/share/info/* + + dpkg-gencontrol -isp -P$(d_doc) -p$(p_doc) + chown -R root:root $(d_doc) + chmod -R go=rX $(d_doc) + dpkg --build $(d_doc) .. + + $(install_dir) $(d_src)/usr/share/doc/$(p_src)/ + $(install_file) debian/changelog $(d_src)/usr/share/doc/$(p_src)/changelog.Debian + $(install_file) debian/copyright $(d_src)/usr/share/doc/$(p_src)/ + find $(d_src)/usr/share/doc/$(p_src) -maxdepth 1 -type f ! -name copyright | xargs gzip -9 + + $(install_dir) $(d_src)/DEBIAN + $(install_dir) $(d_src)/usr/src/binutils/patches + $(install_file) debian/patches/* $(d_src)/usr/src/binutils/patches/ + chmod 755 $(d_src)/usr/src/binutils/patches/*.dpatch + tar -c --bzip2 -C .. --exclude=CVS \ + -f $(pwd)/$(d_src)/usr/src/binutils/binutils-$(VERSION).tar.bz2 \ + $(source_files) + + dpkg-gencontrol -isp -P$(d_src) -p$(p_src) + chown -R root:root $(d_src) + chmod -R go=rX $(d_src) + dpkg --build $(d_src) .. + + +################################################################################ + +####################### +# binary-arch target # +####################### + +binary-arch: checkroot build install + $(checkdir) + + : # make lintian happy + $(install_file) -D debian/$(p_bin).overrides \ + $(d_bin)/usr/share/lintian/overrides/$(p_bin) +ifeq ($(with_multiarch),yes) + $(install_file) -D debian/$(p_mul).overrides \ + $(d_mul)/usr/share/lintian/overrides/$(p_mul) +endif +ifeq ($(DEB_HOST_ARCH),hppa) + $(install_file) -D debian/$(p_hppa64).overrides \ + $(d_hppa64)/usr/share/lintian/overrides/$(p_hppa64) +endif +ifeq ($(with_gold),yes) + $(install_file) -D debian/$(p_gold).overrides \ + $(d_gold)/usr/share/lintian/overrides/$(p_gold) +endif +ifneq (,$(filter $(DEB_HOST_ARCH),powerpc ppc64)) + $(install_file) -D debian/$(p_spu).overrides \ + $(d_spu)/usr/share/lintian/overrides/$(p_spu) +endif + + : # install maintainer scrtips + $(install_dir) $(d_bin)/DEBIAN + $(install_script) debian/binutils.postinst $(d_bin)/DEBIAN/postinst + $(install_script) debian/binutils.postrm $(d_bin)/DEBIAN/postrm + $(install_file) debian/binutils.shlibs $(d_bin)/DEBIAN/shlibs + + $(install_dir) $(d_dev)/DEBIAN + +ifeq ($(with_multiarch),yes) + $(install_dir) $(d_mul)/DEBIAN + $(install_script) debian/binutils-multiarch.postinst $(d_mul)/DEBIAN/postinst + $(install_script) debian/binutils-multiarch.postrm $(d_mul)/DEBIAN/postrm + $(install_script) debian/binutils-multiarch.preinst $(d_mul)/DEBIAN/preinst + $(install_file) debian/binutils-multiarch.shlibs $(d_mul)/DEBIAN/shlibs +endif + +ifeq ($(with_static),yes) + $(install_dir) $(d_static)/DEBIAN + $(install_script) debian/binutils-static.preinst $(d_static)/DEBIAN/preinst + $(install_dir) $(d_udeb)/DEBIAN +endif + +ifeq ($(with_gold),yes) + $(install_dir) $(d_gold)/DEBIAN + $(install_script) debian/binutils-gold.postrm $(d_gold)/DEBIAN/postrm + $(install_script) debian/binutils-gold.preinst $(d_gold)/DEBIAN/preinst +endif + +ifeq ($(DEB_HOST_ARCH),hppa) + $(install_dir) $(d_hppa64)/DEBIAN + $(install_script) debian/binutils-hppa64.postinst $(d_hppa64)/DEBIAN/postinst + $(install_script) debian/binutils-hppa64.postrm $(d_hppa64)/DEBIAN/postrm + $(install_file) debian/binutils-hppa64.shlibs $(d_hppa64)/DEBIAN/shlibs +endif +ifneq (,$(filter $(DEB_HOST_ARCH),powerpc ppc64)) + $(install_dir) $(d_spu)/DEBIAN + $(install_script) debian/binutils-spu.postinst $(d_spu)/DEBIAN/postinst + $(install_script) debian/binutils-spu.postrm $(d_spu)/DEBIAN/postrm + $(install_file) debian/binutils-spu.shlibs $(d_spu)/DEBIAN/shlibs +endif + + : # install docs + $(install_dir) $(d_bin)/usr/share/doc/$(p_bin)/ + $(install_file) debian/changelog $(d_bin)/usr/share/doc/$(p_bin)/changelog.Debian + $(install_file) debian/copyright $(d_bin)/usr/share/doc/$(p_bin)/ + +ifeq ($(with_static),yes) + $(install_dir) $(d_static)/usr/share/doc/$(p_static)/ + $(install_file) debian/changelog $(d_static)/usr/share/doc/$(p_static)/changelog.Debian + $(install_file) debian/copyright $(d_static)/usr/share/doc/$(p_static)/ +endif + + $(install_dir) $(d_dev)/usr/share/doc/ + ln -sf $(p_bin) $(d_dev)/usr/share/doc/$(p_dev) +ifeq ($(with_multiarch),yes) + $(install_dir) $(d_mul)/usr/share/doc/ + ln -sf $(p_bin) $(d_mul)/usr/share/doc/$(p_mul) +endif +ifeq ($(with_gold),yes) + $(install_dir) $(d_gold)/usr/share/doc/ + ln -sf $(p_bin) $(d_gold)/usr/share/doc/$(p_gold) +endif +ifeq ($(DEB_HOST_ARCH),hppa) + $(install_dir) $(d_hppa64)/usr/share/doc/ + ln -sf $(p_bin) $(d_hppa64)/usr/share/doc/$(p_hppa64) +endif +ifneq (,$(filter $(DEB_HOST_ARCH),powerpc ppc64)) + $(install_dir) $(d_spu)/usr/share/doc/ + ln -sf $(p_bin) $(d_spu)/usr/share/doc/$(p_spu) +endif + +ifeq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE)) +ifeq ($(with_check),yes) + $(install_file) $(pwd)/test-summary $(d_bin)/usr/share/doc/$(p_bin)/ +endif +endif + $(install_file) binutils/NEWS debian/README.Debian debian/README.cross \ + $(d_bin)/usr/share/doc/$(p_bin)/ + + $(install_file) binutils/ChangeLog $(d_bin)/usr/share/doc/$(p_bin)/changelog + + for pkg in bfd gas gprof ld; do \ + $(install_dir) $(d_bin)/usr/share/doc/$(p_bin)/$$pkg; \ + done + $(install_file) bfd/ChangeLog bfd/PORTING bfd/TODO \ + $(d_bin)/usr/share/doc/$(p_bin)/bfd/ + $(install_file) gas/ChangeLog gas/NEWS $(d_bin)/usr/share/doc/$(p_bin)/gas/ + $(install_file) gprof/ChangeLog gprof/TODO gprof/TEST \ + $(d_bin)/usr/share/doc/$(p_bin)/gprof/ + $(install_file) ld/ChangeLog ld/TODO ld/NEWS \ + $(d_bin)/usr/share/doc/$(p_bin)/ld/ + + : # These only exist in H. J. Lu releases not GNU ones. + for dir in binutils bfd gas gprof ld; do \ + if [ -f $$dir/ChangeLog.linux ]; then \ + $(install_file) $$dir/ChangeLog.linux $(d_bin)/usr/share/doc/$(p_bin)/$$dir/; \ + fi; \ + done + + : # Copy bbconv.pl to the doc dir for use by interested people + $(install_file) gprof/bbconv.pl $(d_bin)/usr/share/doc/$(p_bin)/gprof/. + + : # Compress stuff that needs it + gzip -9 $(d_bin)/usr/share/man/man1/* + find $(d_bin)/usr/share/doc/$(p_bin)/ -type f ! -name copyright -a ! -name bbconv.pl | xargs gzip -9 +ifeq ($(with_static),yes) + find $(d_static)/usr/share/doc/$(p_static)/ -type f ! -name copyright | xargs gzip -9 +endif + + : # Finish it all up + find $(d_bin) -type f | xargs file | grep ELF | cut -d: -f 1 | xargs dpkg-shlibdeps + dpkg-gencontrol -isp -P$(d_bin) -p$(p_bin) $(CONFLICTS) + + rm -f debian/substvars + dpkg-gencontrol -isp -P$(d_dev) -p$(p_dev) + +ifeq ($(with_multiarch),yes) + rm -f debian/substvars + find $(d_mul) -type f | xargs file | grep ELF | cut -d: -f 1 | xargs dpkg-shlibdeps + dpkg-gencontrol -isp -P$(d_mul) -p$(p_mul) +endif + +ifeq ($(with_static),yes) + dpkg-gencontrol -isp -P$(d_static) -p$(p_static) + dpkg-gencontrol -isp -P$(d_udeb) -p$(p_udeb) -fdebian/files~ + dpkg-distaddfile $(STATIC_UDEB) debian-installer optional +endif + +ifeq ($(with_gold),yes) + rm -f debian/substvars + find $(d_gold) -type f | xargs file | grep ELF | cut -d: -f 1 | xargs dpkg-shlibdeps + dpkg-gencontrol -isp -P$(d_gold) -p$(p_gold) +endif +ifeq ($(DEB_HOST_ARCH),hppa) + rm -f debian/substvars + find $(d_hppa64) -type f | xargs file | grep ELF | cut -d: -f 1 | xargs dpkg-shlibdeps + dpkg-gencontrol -isp -P$(d_hppa64) -p$(p_hppa64) +endif +ifneq (,$(filter $(DEB_HOST_ARCH),powerpc ppc64)) + rm -f debian/substvars + find $(d_spu) -type f | xargs file | grep ELF | cut -d: -f 1 | xargs dpkg-shlibdeps + dpkg-gencontrol -isp -P$(d_spu) -p$(p_spu) +endif + + chown -R root:root $(d_bin) $(d_dev) + chmod -R go=rX $(d_bin) $(d_dev) + dpkg --build $(d_bin) .. + dpkg --build $(d_dev) .. +ifeq ($(with_multiarch),yes) + chown -R root:root $(d_mul) + chmod -R go=rX $(d_mul) + dpkg --build $(d_mul) .. +endif +ifeq ($(with_static),yes) + chown -R root:root $(d_static) $(d_udeb) + chmod -R go=rX $(d_static) $(d_udeb) + dpkg --build $(d_static) .. + dpkg --build $(d_udeb) ../$(STATIC_UDEB) +endif +ifeq ($(with_gold),yes) + chown -R root:root $(d_gold) + chmod -R go=rX $(d_gold) + dpkg --build $(d_gold) .. +endif +ifeq ($(DEB_HOST_ARCH),hppa) + chown -R root:root $(d_hppa64) + chmod -R go=rX $(d_hppa64) + dpkg --build $(d_hppa64) .. +endif +ifneq (,$(filter $(DEB_HOST_ARCH),powerpc ppc64)) + chown -R root:root $(d_spu) + chmod -R go=rX $(d_spu) + dpkg --build $(d_spu) .. +endif + +################################################################################ + +################# +# cross targets # +################# + +# If $(TARGET) is not set, try reading debian/target +ifeq ($(TARGET),) +TARGET := $(shell cat debian/target 2>/dev/null) +endif + +# Process the following only if $(TARGET) is set +ifneq ($(TARGET),) + +# Support TARGET both as Debian architecture specification (e.g. arm), +# and as the target name (e.g. arm-linux-gnu). +try_convert := $(shell dpkg-architecture -f -a$(TARGET) -qDEB_HOST_GNU_TYPE 2>/dev/null) +ifneq ($(try_convert),) +override TARGET := $(try_convert) +endif + +p_cross = $(subst _,-,binutils-$(TARGET)) +d_cross = debian/$(p_cross) + +ifneq ($(filter sparc-linux-gnu powerpc-linux-gnu mips-linux-gnu, $(TARGET)),) +ADDITIONAL_TARGETS = --enable-targets=$(TARGET:%-linux-gnu=%64-linux-gnu) +endif +ifneq ($(filter i386-linux-gnu i486-linux-gnu i586-linux-gnu x86-linux-gnu, $(TARGET)),) +ADDITIONAL_TARGETS = --enable-targets=x86_64-linux-gnu +endif +ifneq ($(filter i386-kfreebsd-gnu i486-kfreebsd-gnu i586-kfreebsd-gnu x86-kfreebsd-gnu, $(TARGET)),) +ADDITIONAL_TARGETS = --enable-targets=x86_64-linux-gnu +endif +ifeq ($(TARGET), x86_64-linux-gnu) +ADDITIONAL_TARGETS = --enable-targets=i486-linux-gnu +endif +ifeq ($(TARGET), x86_64-kfreebsd-gnu) +ADDITIONAL_TARGETS = --enable-targets=i486-kfreebsd-gnu +endif +ifeq ($(TARGET), mipsel-linux-gnu) +ADDITIONAL_TARGETS = --enable-targets=mips64el-linux-gnu +endif +ifeq ($(TARGET), sparc64-linux-gnu) +ADDITIONAL_TARGETS = --enable-targets=sparc-linux-gnu +endif +ifeq ($(TARGET), s390-linux-gnu) +ADDITIONAL_TARGETS = --enable-targets=s390x-linux-gnu +endif +ifeq ($(TARGET), s390x-linux-gnu) +ADDITIONAL_TARGETS = --enable-targets=s390-linux-gnu +endif + +#----------------------------------------------------------------- +# sysroot options +ifdef WITH_SYSROOT + with_sysroot = $(WITH_SYSROOT) +endif +ifdef WITH_BUILD_SYSROOT + with_build_sysroot = $(WITH_BUILD_SYSROOT) +endif + +ifneq ($(with_sysroot),) + CONFARGS += --with-sysroot=$(with_sysroot) +endif +ifneq ($(with_build_sysroot),) + CONFARGS += --with-build-sysroot=$(with_build_sysroot) +endif + +configure-$(TARGET)-stamp: patch-stamp + $(checkdir) + test "" != "$(TARGET)" + rm -rf configure-$(TARGET)-stamp builddir-$(TARGET) + mkdir builddir-$(TARGET) + cd builddir-$(TARGET) \ + && env CC="$(CC)" CXX="$(CXX)" ../configure --host=$(DEB_HOST_GNU_TYPE) \ + --build=$(DEB_BUILD_GNU_TYPE) --target=$(TARGET) --prefix=/usr \ + $(ADDITIONAL_TARGETS) $(CONFARGS) + touch $@ + +build-$(TARGET)-stamp: configure-$(TARGET)-stamp + $(checkdir) + test "" != "$(TARGET)" + $(MAKE) -C builddir-$(TARGET) $(NJOBS) CFLAGS="$(CFLAGS)" + touch $@ + +install-$(TARGET)-stamp: build-$(TARGET)-stamp + $(checkdir) + test "" != "$(TARGET)" + rm -rf $(d_cross) + $(MAKE) -C builddir-$(TARGET) prefix=$(pwd)/$(d_cross)/usr \ + mandir=$(pwd)/$(d_cross)/usr/share/man install + rm -rf $(d_cross)/usr/lib* $(d_cross)/usr/info $(d_cross)/usr/share/locale +ifeq ($(with_strip),yes) + $(STRIP) $$(file $(d_cross)/usr/bin/* | awk -F: '$$0 !~ /script/ {print $$1}') +endif + gzip -9 $(d_cross)/usr/share/man/man1/* + touch $@ + +binary-cross: checkroot install-$(TARGET)-stamp + $(checkdir) + test "" != "$(TARGET)" + + sed "/^$$/ q" < debian/control > debian/control.$(TARGET) + sed -e "s/__TARGET__/$$(echo -n $(TARGET) | sed s/_/-/g)/" \ + < debian/control.cross.in >> debian/control.$(TARGET) + + $(install_dir) $(d_cross)/DEBIAN + + $(install_dir) $(d_cross)/usr/share/doc/$(p_cross)/ + $(install_file) debian/changelog $(d_cross)/usr/share/doc/$(p_cross)/changelog.Debian + $(install_file) debian/copyright debian/README.cross $(d_cross)/usr/share/doc/$(p_cross)/ + gzip -9f $(d_cross)/usr/share/doc/$(p_cross)/changelog.Debian + + for pkg in bfd gas gprof ld; do \ + ln -sf ../binutils/$$pkg $(d_cross)/usr/share/doc/$(p_cross)/$$pkg; \ + done + + rm -f debian/substvars + dpkg-shlibdeps $(d_cross)/usr/bin/* + dpkg-gencontrol -isp -cdebian/control.$(TARGET) -P$(d_cross) -p$(p_cross) + dpkg --build $(d_cross) .. + +clean-cross: unpatch + $(checkdir) + test "" != "$(TARGET)" + rm -rf $(d_cross) debian/control.$(TARGET) debian/files debian/substvars \ + builddir-$(TARGET) {configure,build,install}-$(TARGET)-stamp + +.PHONY: binary-cross clean-cross + +endif + +################################################################################ + +define checkdir + test -f bfd/elf32.c -a -f debian/rules +endef + +# Below here is fairly generic really + +binary: binary-indep binary-arch + +checkroot: + $(checkdir) + test root = "`whoami`" + +.PHONY: binary binary-arch binary-indep clean checkroot --- binutils-2.20.orig/debian/README.Debian +++ binutils-2.20/debian/README.Debian @@ -0,0 +1,26 @@ +Kernel link failure info +------------------------ + +You may experience problems linking older (and some newer) kernels +with this version of binutils. This is not because of a bug in the +linker, but rather a bug in the kernel source. This is being worked +out and fixed by the upstream kernel group in newer kernels, but not +all of the problems may have been fixed at this time. Older kernel +versions will almost always exhibit the problem, however, and no +attempts are being made to fix those that we know of. + +There are a few work-arounds, but the most reliable is to edit the +linker script for your architecture (e.g. arch/i386/vmlinux.lds) and +remove the '*(.text.exit)' entry from the 'DISCARD' line. It will +bloat the kernel somewhat, but it should link properly. + +The ld -oformat option has been replaced +---------------------------------------- + +The ld command-line option '-oformat' has been completely replaced by +'--oformat' in newer binutils. This may cause problems when linking +older kernel versions on i386 which still use the '-oformat' syntax in +arch/boot/Makefile. + +If you encounter problems, edit arch/boot/Makefile in your kernel +source and change '-oformat' to '--oformat'. --- binutils-2.20.orig/debian/binutils.overrides +++ binutils-2.20/debian/binutils.overrides @@ -0,0 +1,2 @@ +# the API of the shared libs is not public, don't care about the name +binutils binary: package-name-doesnt-match-sonames --- binutils-2.20.orig/debian/binutils-multiarch.shlibs +++ binutils-2.20/debian/binutils-multiarch.shlibs @@ -0,0 +1,2 @@ +libbfd 2.20-multiarch binutils-multiarch +libopcodes 2.20-multiarch binutils-multiarch --- binutils-2.20.orig/debian/binutils-static.preinst +++ binutils-2.20/debian/binutils-static.preinst @@ -0,0 +1,10 @@ +#!/bin/sh + +set -e + +if [ -L /usr/share/doc/binutils-static ]; then + # We must be upgrading from a version that depended on binutils + rm -f /usr/share/doc/binutils-static +fi + +exit 0 --- binutils-2.20.orig/debian/binutils-multiarch.postrm +++ binutils-2.20/debian/binutils-multiarch.postrm @@ -0,0 +1,32 @@ +#! /bin/sh + +set -e + +if [ "$1" = "remove" -o "$1" = "abort-install" ]; then + + for f in size objdump ar strings ranlib objcopy addr2line \ + readelf nm strip gprof; do + dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/bin/$f.single /usr/bin/$f + done + + dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/lib/libbfd-single.a /usr/lib/libbfd.a + dpkg-divert --package binutils-multiarch \ + --remove --rename \ + --divert /usr/lib/libopcodes-single.a /usr/lib/libopcodes.a + +fi + +if [ -e /usr/lib/libbfd-*-multiarch.so.0 ]; then + rm -f /usr/lib/libbfd-*-multiarch.so.0; +fi +if [ -e /usr/lib/libopcodes-*-multiarch.so.0 ]; then + rm -f /usr/lib/libopcodes-*-multiarch.so.0; +fi + +if [ "$1" = "remove" ]; then + ldconfig +fi --- binutils-2.20.orig/debian/binutils-multiarch.overrides +++ binutils-2.20/debian/binutils-multiarch.overrides @@ -0,0 +1,10 @@ +# don't warn about missing man pages for diverted binaries +binutils-multiarch binary: binary-without-manpage + +# the API of the shared libs is not public, don't care about the name +binutils-multiarch binary: package-name-doesnt-match-sonames + +# not in binutils-multiarch, just move these away +binutils-multiarch: diversion-for-unknown-file usr/lib/libopcodes.a preinst:19 +binutils-multiarch: diversion-for-unknown-file usr/lib/libbfd.a preinst:16 + --- binutils-2.20.orig/debian/test-suite-compare.py +++ binutils-2.20/debian/test-suite-compare.py @@ -0,0 +1,230 @@ +#!/usr/bin/env python + +# Quick'n'dirty regression check for dejagnu testsuites +# Copyright (C) 2003, 2004, 2005, 2006, 2007 James Troup + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU;5B General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +################################################################################ + +import optparse +import os +import sys + +################################################################################ + +def fubar(msg, exit_code=1): + sys.stderr.write("E: %s\n" % (msg)) + sys.exit(exit_code) + +def warn(msg): + sys.stderr.write("W: %s\n" % (msg)) + +def info(msg): + sys.stderr.write("I: %s\n" % (msg)) + +################################################################################ + +def read_testsummary(filename): + results = {} + file = open(filename) + for line in file.readlines(): + if not line: + continue + if line.startswith("Running"): + s = line.split() + if "/" in s[1]: + x = s[1] + if x.find("/testsuite/") == -1: + fubar("Can't find /testsuite/ in '%s'." % (x)) + # 'Running /home/james/debian/packages/binutils/binutils-2.14.90.0.7/gas/testsuite/gas/hppa/unsorted/unsorted.exp ...' -> 'gas/hppa/unsorted/unsorted.exp' + # ... since using basename() isn't dupe safe. + section = x[x.find("/testsuite/"):].replace("/testsuite/","").split()[0] + + # Tests can be duplicated, e.g. hppa/basic/basic.exp + # is run twice, once for hppa-linux and once for + # hppa64-linux. This is of course a horrible bodge, + # but I can't think of anything trivial and better off + # hand. + + if results.has_key(section): + extra = 1 + too_many = 10 + while results.has_key(section) and extra < too_many: + section = "%s.%s" % (section, extra) + extra += 1 + if extra >= too_many: + fubar("gave up trying to unduplicate %s." % (section)) + + results[section] = {} + continue + + got_state = 0 + for state in [ "PASS", "XPASS", "FAIL", "XFAIL", "UNRESOLVED", + "UNTESTED", "UNSUPPORTED" ]: + if line.startswith(state): + s = line.split(':') + state = s[0] + test = ':'.join(s[1:]).strip() + if results.has_key(test): + warn("%s/%s is duplicated." % (section, test)) + results[section][test] = state + got_state = 1 + break + + if got_state: + continue + + return results + +################################################################################ + +def compare_results(old, new): + total_num = 0 + pass_count = 0 + fail_count = 0 + xfail_count = 0 + untested_count = 0 + regression_count = 0 + progression_count = 0 + change_count = 0 + + for section in new.keys(): + for test in new[section].keys(): + state = new[section][test] + + # Stats pr0n + total_num += 1 + if state == "PASS" or state == "XPASS": + pass_count += 1 + elif state == "FAIL" or state == "UNRESOLVED": + fail_count += 1 + elif state == "XFAIL": + xfail_count += 1 + elif state == "UNTESTED": + untested_count += 1 + + # Compare to old + if not old.has_key(section): + continue + if not old[section].has_key(test): + continue + old_state = old[section][test] + if state == "PASS": + if old_state != "PASS": + progression_count += 1 + info("[%s] progression (%s -> %s): %s" % (section, old_state, state, test)) + elif state == "XPASS": + if old_state != "XPASS" and old_state != "PASS": + progression_count += 1 + warn("[%s] %s: %s" % (section, state, test)) + elif state == "FAIL": + if old_state != "FAIL": + regression_count += 1 + warn("[%s] REGRESSION (%s -> %s): %s" % (section, old_state, state, test)) + elif state == "XFAIL": + if old_state != "XFAIL": + change_count += 1 + info("[%s] change (%s -> %s): %s" % (section, old_state, state, test)) + elif state == "UNRESOLVED": + if old_state != "UNRESOLVED" and old_state != "FAIL": + regression_count += 1 + warn("[%s] REGRESSION (%s -> %s): %s" % (section, old_state, state, test)) + if old_state == "FAIL": + change_count += 1 + info("[%s] change (%s -> %s): %s" % (section, old_state, state, test)) + elif state == "UNTESTED": + if old_state != "UNTESTED": + change_count += 1 + warn("[%s] REGRESSION (%s -> %s): %s" % (section, old_state, state, test)) + + if regression_count: + print "%d REGRESSIONS (%.2f%%)." % (regression_count, (float(regression_count)/total_num)*100) + if progression_count: + print "%d progressions (%.2f%%)." % (progression_count, (float(progression_count)/total_num)*100) + + if change_count: + print "%d changes (%.2f%%)." % (change_count, (float(change_count)/total_num)*100) + + print "%d tests: %d pass (%.2f%%), %d fail (%.2f%%), %d xfail (%.2f%%) %d untested (%.2f%%)." \ + % (total_num, pass_count, (float(pass_count)/total_num)*100, + fail_count, (float(fail_count)/total_num)*100, + xfail_count, (float(xfail_count)/total_num)*100, + untested_count, (float(untested_count)/total_num)*100) + + if regression_count: + sys.exit(1) + +################################################################################ + +def compare_multiple(directory, first_version, second_version): + architectures = [ "alpha", "arm", "hppa", "i386", "ia64", "mips", + "m68k", "mipsel", "powerpc", "s390", "sparc" ] + + for arch in architectures: + print "*********************************** %s ******************************" % (arch) + second_filename = "%s/%s_%s" % (directory, second_version, arch) + if not os.path.exists(second_filename): + print " -- NOT AVAILABLE --" + continue + + new = read_testsummary(second_filename) + first_filename = "%s/%s_%s" % (directory, first_version, arch) + old = read_testsummary(first_filename) + compare_results(old, new) + +################################################################################ + +def init(): + """Initalization, including parsing of options.""" + + usage = """usage: %prog [OPTIONS] +compare (binutils) dejagnu testsuite results. + +Example usage: + + test-suite-compare.py binutils-2.17/test-summary binutils-2.18/test-summary + +Or to compare across all architectures (with test results stored in a +'test-summary' directory): + + test-suite-compare.py -mtest-summary 2.17-3 2.18-1""" + parser = optparse.OptionParser(usage) + parser.add_option("-m", "--multiple", dest="multiple", + nargs=1, type="string", + help="compare multiple architectures") + (options, args) = parser.parse_args() + + if len(args) > 2 or len(args) < 2: + parser.error("takes 2 arguments (old and new)") + (old_version, new_version) = args + + return options, old_version, new_version + +################################################################################ + +def main(): + (options, old_version, new_version) = init() + if options.multiple: + compare_multiple(options.multiple, old_version, new_version) + else: + old = read_testsummary(old_version) + new = read_testsummary(new_version) + compare_results(old, new) + +################################################################################ + +if __name__ == '__main__': + main() --- binutils-2.20.orig/debian/binutils-hppa64.postrm +++ binutils-2.20/debian/binutils-hppa64.postrm @@ -0,0 +1,7 @@ +#! /bin/sh + +set -e + +if [ "$1" = "remove" ]; then + ldconfig +fi --- binutils-2.20.orig/debian/binutils.shlibs +++ binutils-2.20/debian/binutils.shlibs @@ -0,0 +1,2 @@ +libbfd 2.20 binutils +libopcodes 2.20 binutils --- binutils-2.20.orig/debian/control.static +++ binutils-2.20/debian/control.static @@ -0,0 +1,18 @@ + +Package: binutils-static +Architecture: any +Depends: ${shlibs:Depends} +Description: statically linked binutils tools + This package contains statically linked binutils tools used + for linking kernel modules needed to mount /usr or /. At the moment, + it only contains ld. + +Package: binutils-static-udeb +Section: debian-installer +Architecture: any +Depends: ${shlibs:Depends} +Description: statically linked binutils tools for for the Debian installer + This package contains statically linked binutils tools used + for linking kernel modules needed to mount /usr or /. At the moment, + it only contains ld. + --- binutils-2.20.orig/debian/copyright +++ binutils-2.20/debian/copyright @@ -0,0 +1,43 @@ +This is the Debian GNU/Linux prepackaged version of the GNU assembler, +linker, and binary utilities. + +This package was put together by me, James Troup , +from sources, which I obtained from: + + ftp://ftp.gnu.org/pub/gnu/binutils/ + +and: + + cvs://:pserver:anoncvs@sources.redhat.com:/cvs/src + +It was previously maintained by Christopher C. Chimelis + +GNU Binutils is Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, +1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software +Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +On Debian GNU/Linux systems, the complete text of the GNU General +Public License can be found in `/usr/share/common-licenses/GPL' +and `/usr/share/common-licenses/LGPL'. + +The binutils manuals and associated documentation are also Copyright +(C) Free Software Foundation, Inc. They are distributed under the GNU +Free Documentation License Version 1.1 or any later version published +by the Free Software Foundation; with no Invariant Sections, with no +n Debian GNU/Linux systems, the complete text of the GFDL can be found +in `/usr/share/common-licenses/GFDL'. --- binutils-2.20.orig/debian/binutils-spu.overrides +++ binutils-2.20/debian/binutils-spu.overrides @@ -0,0 +1,8 @@ +# don't warn about missing man pages for diverted binaries +binutils-spu binary: binary-without-manpage + +# the API of the shared libs is not public, don't care about the name +binutils-spu binary: package-name-doesnt-match-sonames + +# it's a cross toolchain +binutils-spu binary: binary-or-shlib-defines-rpath --- binutils-2.20.orig/debian/watch +++ binutils-2.20/debian/watch @@ -0,0 +1,2 @@ +version=2 +http://ftp.gnu.org/gnu/binutils/binutils-([\d\.]*).tar.gz --- binutils-2.20.orig/debian/binutils-hppa64.shlibs +++ binutils-2.20/debian/binutils-hppa64.shlibs @@ -0,0 +1,2 @@ +libbfd 2.20-hppa64 binutils-hppa64 +libopcodes 2.20-hppa64 binutils-hppa64 --- binutils-2.20.orig/debian/binutils-spu.postinst +++ binutils-2.20/debian/binutils-spu.postinst @@ -0,0 +1,7 @@ +#! /bin/sh + +set -e + +if [ "$1" = "configure" ]; then + ldconfig +fi --- binutils-2.20.orig/debian/binutils-hppa64.postinst +++ binutils-2.20/debian/binutils-hppa64.postinst @@ -0,0 +1,7 @@ +#! /bin/sh + +set -e + +if [ "$1" = "configure" ]; then + ldconfig +fi --- binutils-2.20.orig/debian/binutils-spu.shlibs +++ binutils-2.20/debian/binutils-spu.shlibs @@ -0,0 +1,2 @@ +libbfd 2.20-spu binutils-spu +libopcodes 2.20-spu binutils-spu --- binutils-2.20.orig/debian/binutils-hppa64.overrides +++ binutils-2.20/debian/binutils-hppa64.overrides @@ -0,0 +1,8 @@ +# don't warn about missing man pages for diverted binaries +binutils-hppa64 binary: binary-without-manpage + +# the API of the shared libs is not public, don't care about the name +binutils-hppa64 binary: package-name-doesnt-match-sonames + +# it's a cross toolchain +binutils-hppa64 binary: binary-or-shlib-defines-rpath --- binutils-2.20.orig/debian/binutils-multiarch.postinst +++ binutils-2.20/debian/binutils-multiarch.postinst @@ -0,0 +1,7 @@ +#! /bin/sh + +set -e + +if [ "$1" = "configure" ]; then + ldconfig +fi --- binutils-2.20.orig/debian/control +++ binutils-2.20/debian/control @@ -0,0 +1,121 @@ +Source: binutils +Section: devel +Priority: optional +Maintainer: Ubuntu Core developers +XSBC-Original-Maintainer: Matthias Klose +Uploaders: James Troup +Standards-Version: 3.8.3 +Build-Depends: dpkg-dev (>= 1.13.9), autoconf (>= 2.64), bison, flex, gettext, texinfo, gcc (>= 4:4.2.2), dejagnu (>= 1.4.2-1.1), dpatch, file, bzip2, lsb-release, zlib1g-dev + +Package: binutils +Architecture: any +Depends: ${shlibs:Depends} +Conflicts: gas, elf-binutils, modutils (<< 2.4.19-1), ${extraConflicts} +Provides: elf-binutils +Suggests: binutils-doc (>= ${source:Version}) +Description: The GNU assembler, linker and binary utilities + The programs in this package are used to assemble, link and manipulate + binary and object files. They may be used in conjunction with a compiler + and various libraries to build programs. + +Package: binutils-dev +Architecture: any +Priority: extra +Depends: binutils (= ${binary:Version}) +Conflicts: libbfd-dev +Provides: libbfd-dev +Replaces: libbfd-dev, libc5-dev +Description: The GNU binary utilities (BFD development files) + This package includes header files and static libraries necessary to build + programs which use the GNU BFD library, which is part of binutils. Note + that building Debian packages which depend on the shared libbfd is Not + Allowed. + +Package: binutils-multiarch +Architecture: any +Priority: extra +Depends: ${shlibs:Depends}, binutils (= ${binary:Version}) +Provides: multiarch-binutils +Description: Binary utilities that support multi-arch targets + The programs in this package are used to manipulate binary and object + files that may have been created on other architectures. This package + is primarily for multi-architecture developers and cross-compilers and + is not needed by normal users or developers. Note that a cross-assembling + version of gas is not included in this package, just the binary utilities. + NORMAL USERS SHOULD NOT INSTALL THIS PACKAGE. It's meant only for those + requiring support for reading info from binaries from other architectures. + +Package: binutils-gold +Architecture: amd64 armel i386 lpia powerpc sparc +Priority: extra +Depends: ${shlibs:Depends}, binutils (= ${binary:Version}) +Conflicts: binutils-multiarch +Description: The (experimental) GNU gold linker utility + Gold is a new linker, still in development, which is faster than the + current linker included in binutils. It currently fails to link some + applications and libraries (i.e. won't link usable kernels). + . + This package diverts the GNU linker (ld) with the experimental gold + linker. + +Package: binutils-static +Architecture: any +Description: statically linked binutils tools + This package contains statically linked binutils tools used + for linking kernel modules needed to mount /usr or /. At the moment, + it only contains ld. + +Package: binutils-static-udeb +Section: debian-installer +Architecture: any +Description: statically linked binutils tools for for the Debian installer + This package contains statically linked binutils tools used + for linking kernel modules needed to mount /usr or /. At the moment, + it only contains ld. + +Package: binutils-hppa64 +Architecture: hppa +Depends: ${shlibs:Depends}, binutils (= ${binary:Version}) +Recommends: libc6-dev +Suggests: binutils-doc (>= ${source:Version}) +Description: The GNU assembler, linker and binary utilities targeted for hppa64-linux + The programs in this package are used to assemble, link and manipulate + binary and object files. They may be used in conjunction with a compiler + and various libraries to build programs. + . + This package is needed to build an 64-bit kernel for 64-bit hppa machines. + +Package: binutils-spu +Architecture: powerpc ppc64 +Depends: ${shlibs:Depends}, binutils (= ${binary:Version}) +Recommends: libc6-dev +Conflicts: spu-binutils +Replaces: spu-binutils +Provides: spu-binutils +Suggests: binutils-doc (>= ${source:Version}) +Description: The GNU assembler, linker and binary utilities targeted for spu-elf + The programs in this package are used to assemble, link and manipulate + binary and object files. They may be used in conjunction with a compiler + and various libraries to build programs. + . + This package is needed to build programs for Cell Broadband Engine SPU + processors. + +Package: binutils-doc +Section: doc +Architecture: all +Priority: optional +Depends: dpkg (>= 1.15.4) | install-info +Conflicts: binutils (<< 2.9.1.0.25-3) +Suggests: binutils (= ${binary:Version}) +Description: Documentation for the GNU assembler, linker and binary utilities + This package consists of the documentation for the GNU assembler, + linker and binary utilities in info format. + +Package: binutils-source +Architecture: all +Priority: optional +Depends: texinfo, zlib1g-dev +Description: The GNU assembler, linker and binary utilities (source) + This package contains the sources and patches which are needed to + build binutils. --- binutils-2.20.orig/debian/patches/127_x86_64_i386_biarch.dpatch +++ binutils-2.20/debian/patches/127_x86_64_i386_biarch.dpatch @@ -0,0 +1,42 @@ +#!/bin/sh -e +## 127_x86_64_i386_biarch.dpatch +## +## DP: Description: Add (/usr)/lib32 to the search paths on x86_64. +## DP: Author: Aurelien Jarno +## DP: Upstream status: Debian specific + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +--- ./ld/emulparams/elf_i386.sh~ 2009-07-29 16:59:23.000000000 +0200 ++++ ./ld/emulparams/elf_i386.sh 2009-08-05 10:38:57.000000000 +0200 +@@ -13,3 +13,13 @@ + NO_SMALL_DATA=yes + SEPARATE_GOTPLT=12 + IREL_IN_PLT= ++ ++# Linux modify the default library search path to first include ++# a 32-bit specific directory. ++case "$target" in ++ x86_64*-linux* | i[3-7]86*-linux* | x86_64*-kfreebsd*-gnu | i[3-7]86*-kfreebsd*-gnu) ++ case "$EMULATION_NAME" in ++ *i386*) LIBPATH_SUFFIX=32 ;; ++ esac ++ ;; ++esac --- binutils-2.20.orig/debian/patches/206-hjl-binutils-shr.dpatch +++ binutils-2.20/debian/patches/206-hjl-binutils-shr.dpatch @@ -0,0 +1,1216 @@ +#!/bin/sh -e +## 206-hjl-binutils-shr.dpatch +## +## DP: Description: implementation of ELF sharable section proposal +## DP: Author: H.J. Lu +## DP: Upstream status: hjl 2.18.50.0.10 +## DP: Original patch: binutils-shr-89.patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +http://groups.google.com/group/generic-abi/browse_thread/thread/f7b3e06417ead85a +http://groups.google.com/group/generic-abi/browse_thread/thread/bca08f6560f61b0d + +bfd/ + +2007-01-23 H.J. Lu + + * elf-bfd.h (_bfd_elf_sharable_com_section): New. + (_bfd_elf_add_sharable_symbol): Likewise. + (_bfd_elf_sharable_section_from_bfd_section): Likewise. + (_bfd_elf_sharable_symbol_processing): Likewise. + (_bfd_elf_sharable_common_definition): Likewise. + (_bfd_elf_sharable_common_section_index): Likewise. + (_bfd_elf_sharable_common_section): Likewise. + (_bfd_elf_sharable_merge_symbol): Likewise. + + * elf.c (special_sections_g): Add ".gnu.linkonce.shrb" and + ".gnu.linkonce.shrd". + (special_sections_s): Add ".sharable_bss" and ".sharable_data". + (get_program_header_size): Handle PT_GNU_SHR segment. + (_bfd_elf_map_sections_to_segments): Likewise. + (assign_file_positions_for_load_sections): Likewise. + + * elf32-i386.c (elf_i386_link_hash_table): Add sdynsharablebss + and srelsharablebss fields. + (elf_i386_link_hash_table_create): Initialize sdynsharablebss + and srelsharablebss. + (elf_i386_create_dynamic_sections): Handle sdynsharablebss and + srelsharablebss. + (elf_i386_adjust_dynamic_symbol): Likewise. + (elf_i386_size_dynamic_sections): Likewise. + (elf_i386_finish_dynamic_symbol): Likewise. + (elf_backend_add_symbol_hook): Defined. + (elf_backend_section_from_bfd_section): Likewise. + (elf_backend_symbol_processing): Likewise. + (elf_backend_common_section_index): Likewise. + (elf_backend_common_section): Likewise. + (elf_backend_common_definition): Likewise. + (elf_backend_merge_symbol): Likewise. + + * elf64-x86-64.c (elf64_x86_64_link_hash_table): Add + sdynsharablebss and srelsharablebss fields. + (elf64_x86_64_link_hash_table_create): Initialize sdynsharablebss + and srelsharablebss. + (elf64_x86_64_create_dynamic_sections): Handle sdynsharablebss + and srelsharablebss. + (elf64_x86_64_adjust_dynamic_symbol): Likewise. + (elf64_x86_64_size_dynamic_sections): Likewise. + (elf64_x86_64_finish_dynamic_symbol): Likewise. + (elf64_x86_64_add_symbol_hook): Handle sharable symbols. + (elf64_x86_64_elf_section_from_bfd_section): Likewise. + (elf64_x86_64_symbol_processing): Likewise. + (elf64_x86_64_merge_symbol): Likewise. + (elf64_x86_64_common_definition): Handle sharable sections. + (elf64_x86_64_common_section_index): Likewise. + (elf64_x86_64_common_section): Likewise. + + * elflink.c (_bfd_elf_create_dynamic_sections): Handle + .dynsharablebss section. + (_bfd_elf_sharable_com_section): New. + (get_sharable_common_section): Likewise. + (_bfd_elf_add_sharable_symbol): Likewise. + (_bfd_elf_sharable_section_from_bfd_section): Likewise. + (_bfd_elf_sharable_symbol_processing): Likewise. + (_bfd_elf_sharable_common_definition): Likewise. + (_bfd_elf_sharable_common_section_index): Likewise. + (_bfd_elf_sharable_common_section): Likewise. + (_bfd_elf_sharable_merge_symbol): Likewise. + + * elfxx-ia64.c (elfNN_ia64_add_symbol_hook): Handle sharable + symbols. + (elf_backend_add_symbol_hook): Defined. + (elf_backend_section_from_bfd_section): Likewise. + (elf_backend_symbol_processing): Likewise. + (elf_backend_common_section_index): Likewise. + (elf_backend_common_section): Likewise. + (elf_backend_common_definition): Likewise. + (elf_backend_merge_symbol): Likewise. + +binutils/ + +2007-01-04 H.J. Lu + + * readelf.c (dump_relocations): Handle sharable sections. + (get_segment_type): Handle sharable segment. + (get_symbol_index_type): Handle sharable sections. + +gas/ + +2007-01-04 H.J. Lu + + * config/obj-elf.c (obj_elf_sharable_common): New. + (elf_pseudo_table): Add "sharable_common". + (obj_elf_change_section): Handle sharable sections. + +include/ + +2007-01-23 H.J. Lu + + * bfdlink.h (bfd_link_info): Add sharable_sections. + +include/elf/ + +2007-01-04 H.J. Lu + + * common.h (PT_GNU_SHR): New. + (SHF_GNU_SHARABLE): Likewise. + (SHN_GNU_SHARABLE_COMMON): Likewise. + +ld/ + +2007-01-04 H.J. Lu + + * emulparams/elf64_ia64.sh (SHARABLE_SECTIONS): Set to yes. + * emulparams/elf_i386.sh (SHARABLE_SECTIONS): Likewise. + * emulparams/elf_x86_64.sh (SHARABLE_SECTIONS): Likewise. + + * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set + link_info.sharable_sections based on $SHARABLE_SECTIONS. + (gld${EMULATION_NAME}_place_orphan): Don't allow orphaned + sharable sections. + + * ldmain.c (main): Initialize link_info.sharable_sections. + * scripttempl/elf.sc: Support sharable sections. + +@DPATCH@ +--- binutils/bfd/elf-bfd.h.shr 2007-06-02 07:39:38.000000000 -0700 ++++ binutils/bfd/elf-bfd.h 2007-06-02 07:39:38.000000000 -0700 +@@ -1856,6 +1856,28 @@ extern bfd_boolean bfd_elf_link_add_symb + (bfd *, struct bfd_link_info *); + extern bfd_boolean _bfd_elf_add_dynamic_entry + (struct bfd_link_info *, bfd_vma, bfd_vma); ++extern asection _bfd_elf_sharable_com_section; ++extern bfd_boolean _bfd_elf_add_sharable_symbol ++ (bfd *, struct bfd_link_info *, Elf_Internal_Sym *, const char **, ++ flagword *, asection **, bfd_vma *); ++extern bfd_boolean _bfd_elf_sharable_section_from_bfd_section ++ (bfd *, asection *, int *); ++extern void _bfd_elf_sharable_symbol_processing ++ (bfd *, asymbol *); ++extern bfd_boolean _bfd_elf_sharable_common_definition ++ (Elf_Internal_Sym *); ++extern unsigned int _bfd_elf_sharable_common_section_index ++ (asection *); ++extern asection *_bfd_elf_sharable_common_section ++ (asection *); ++extern bfd_boolean _bfd_elf_sharable_merge_symbol ++ (struct bfd_link_info *, struct elf_link_hash_entry **, ++ struct elf_link_hash_entry *, Elf_Internal_Sym *, asection **, ++ bfd_vma *, unsigned int *, bfd_boolean *, bfd_boolean *, ++ bfd_boolean *, bfd_boolean *, bfd_boolean *, bfd_boolean *, ++ bfd_boolean *, bfd_boolean *, bfd *, asection **, ++ bfd_boolean *, bfd_boolean *, bfd_boolean *, bfd_boolean *, ++ bfd *, asection **); + + extern bfd_boolean bfd_elf_link_record_dynamic_symbol + (struct bfd_link_info *, struct elf_link_hash_entry *); +--- binutils/bfd/elf.c.shr 2007-06-02 07:39:38.000000000 -0700 ++++ binutils/bfd/elf.c 2007-06-02 07:39:38.000000000 -0700 +@@ -2343,6 +2343,8 @@ static const struct bfd_elf_special_sect + { STRING_COMMA_LEN (".gnu.liblist"), 0, SHT_GNU_LIBLIST, SHF_ALLOC }, + { STRING_COMMA_LEN (".gnu.conflict"), 0, SHT_RELA, SHF_ALLOC }, + { STRING_COMMA_LEN (".gnu.hash"), 0, SHT_GNU_HASH, SHF_ALLOC }, ++ { STRING_COMMA_LEN (".gnu.linkonce.shrb"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_GNU_SHARABLE}, ++ { STRING_COMMA_LEN (".gnu.linkonce.shrd"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_GNU_SHARABLE}, + { NULL, 0, 0, 0, 0 } + }; + +@@ -2397,6 +2399,8 @@ static const struct bfd_elf_special_sect + /* See struct bfd_elf_special_section declaration for the semantics of + this special case where .prefix_length != strlen (.prefix). */ + { ".stabstr", 5, 3, SHT_STRTAB, 0 }, ++ { STRING_COMMA_LEN (".sharable_bss"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_GNU_SHARABLE}, ++ { STRING_COMMA_LEN (".sharable_data"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_GNU_SHARABLE}, + { NULL, 0, 0, 0, 0 } + }; + +@@ -3694,6 +3698,32 @@ get_program_header_size (bfd *abfd, stru + } + } + ++ /* Check to see if we need a PT_GNU_SHR segment for sharable data ++ sections. */ ++ for (s = abfd->sections; s != NULL; s = s->next) ++ { ++ if ((elf_section_flags (s) & SHF_GNU_SHARABLE) != 0 ++ && elf_section_type (s) == SHT_PROGBITS) ++ { ++ /* We need a PT_GNU_SHR segment. */ ++ ++segs; ++ break; ++ } ++ } ++ ++ /* Check to see if we need a PT_GNU_SHR segment for sharable bss ++ sections. */ ++ for (s = abfd->sections; s != NULL; s = s->next) ++ { ++ if ((elf_section_flags (s) & SHF_GNU_SHARABLE) != 0 ++ && elf_section_type (s) == SHT_NOBITS) ++ { ++ /* We need a PT_GNU_SHR segment. */ ++ ++segs; ++ break; ++ } ++ } ++ + /* Let the backend count up any program headers it might need. */ + bed = get_elf_backend_data (abfd); + if (bed->elf_backend_additional_program_headers) +@@ -3834,6 +3864,8 @@ _bfd_elf_map_sections_to_segments (bfd * + bfd_boolean phdr_in_segment = TRUE; + bfd_boolean writable; + int tls_count = 0; ++ int sharable_data_count = 0, sharable_bss_count = 0; ++ asection *first_sharable_data = NULL, *first_sharable_bss = NULL; + asection *first_tls = NULL; + asection *dynsec, *eh_frame_hdr; + bfd_size_type amt; +@@ -4083,6 +4115,22 @@ _bfd_elf_map_sections_to_segments (bfd * + first_tls = s; + tls_count++; + } ++ if (elf_section_flags (s) & SHF_GNU_SHARABLE) ++ { ++ if (elf_section_type (s) == SHT_PROGBITS) ++ { ++ if (! sharable_data_count) ++ first_sharable_data = s; ++ sharable_data_count++; ++ } ++ else ++ { ++ BFD_ASSERT (elf_section_type (s) == SHT_NOBITS); ++ if (! sharable_bss_count) ++ first_sharable_bss = s; ++ sharable_bss_count++; ++ } ++ } + } + + /* If there are any SHF_TLS output sections, add PT_TLS segment. */ +@@ -4112,6 +4160,60 @@ _bfd_elf_map_sections_to_segments (bfd * + pm = &m->next; + } + ++ /* If there are any output SHF_GNU_SHARABLE data sections, add a ++ PT_GNU_SHR segment. */ ++ if (sharable_data_count > 0) ++ { ++ int i; ++ ++ amt = sizeof (struct elf_segment_map); ++ amt += (sharable_data_count - 1) * sizeof (asection *); ++ m = bfd_zalloc (abfd, amt); ++ if (m == NULL) ++ goto error_return; ++ m->next = NULL; ++ m->p_type = PT_GNU_SHR; ++ m->count = sharable_data_count; ++ /* Mandated PF_R. */ ++ m->p_flags = PF_R; ++ m->p_flags_valid = 1; ++ for (i = 0; i < sharable_data_count; ++i) ++ { ++ m->sections[i] = first_sharable_data; ++ first_sharable_data = first_sharable_data->next; ++ } ++ ++ *pm = m; ++ pm = &m->next; ++ } ++ ++ /* If there are any output SHF_GNU_SHARABLE bss sections, add a ++ PT_GNU_SHR segment. */ ++ if (sharable_bss_count > 0) ++ { ++ int i; ++ ++ amt = sizeof (struct elf_segment_map); ++ amt += (sharable_bss_count - 1) * sizeof (asection *); ++ m = bfd_zalloc (abfd, amt); ++ if (m == NULL) ++ goto error_return; ++ m->next = NULL; ++ m->p_type = PT_GNU_SHR; ++ m->count = sharable_bss_count; ++ /* Mandated PF_R. */ ++ m->p_flags = PF_R; ++ m->p_flags_valid = 1; ++ for (i = 0; i < sharable_bss_count; ++i) ++ { ++ m->sections[i] = first_sharable_bss; ++ first_sharable_bss = first_sharable_bss->next; ++ } ++ ++ *pm = m; ++ pm = &m->next; ++ } ++ + /* If there is a .eh_frame_hdr section, throw in a PT_GNU_EH_FRAME + segment. */ + eh_frame_hdr = elf_tdata (abfd)->eh_frame_hdr; +@@ -4531,6 +4633,7 @@ assign_file_positions_for_load_sections + align = (bfd_size_type) 1 << bfd_get_section_alignment (abfd, sec); + + if (p->p_type == PT_LOAD ++ || p->p_type == PT_GNU_SHR + || p->p_type == PT_TLS) + { + bfd_signed_vma adjust = sec->lma - (p->p_paddr + p->p_memsz); +--- binutils/bfd/elf32-i386.c.shr 2007-05-15 07:35:03.000000000 -0700 ++++ binutils/bfd/elf32-i386.c 2007-06-02 07:39:38.000000000 -0700 +@@ -660,6 +660,8 @@ struct elf_i386_link_hash_table + asection *srelplt; + asection *sdynbss; + asection *srelbss; ++ asection *sdynsharablebss; ++ asection *srelsharablebss; + + /* The (unloaded but important) .rel.plt.unloaded section on VxWorks. */ + asection *srelplt2; +@@ -752,6 +754,8 @@ elf_i386_link_hash_table_create (bfd *ab + ret->srelplt = NULL; + ret->sdynbss = NULL; + ret->srelbss = NULL; ++ ret->sdynsharablebss = NULL; ++ ret->srelsharablebss = NULL; + ret->tls_ldm_got.refcount = 0; + ret->next_tls_desc_index = 0; + ret->sgotplt_jump_table_size = 0; +@@ -812,10 +816,19 @@ elf_i386_create_dynamic_sections (bfd *d + htab->srelplt = bfd_get_section_by_name (dynobj, ".rel.plt"); + htab->sdynbss = bfd_get_section_by_name (dynobj, ".dynbss"); + if (!info->shared) +- htab->srelbss = bfd_get_section_by_name (dynobj, ".rel.bss"); ++ { ++ htab->srelbss = bfd_get_section_by_name (dynobj, ".rel.bss"); ++ htab->sdynsharablebss ++ = bfd_get_section_by_name (dynobj, ".dynsharablebss"); ++ htab->srelsharablebss ++ = bfd_get_section_by_name (dynobj, ".rel.sharable_bss"); ++ } + + if (!htab->splt || !htab->srelplt || !htab->sdynbss +- || (!info->shared && !htab->srelbss)) ++ || (!info->shared ++ && (!htab->srelbss ++ || !htab->sdynsharablebss ++ || !htab->srelsharablebss))) + abort (); + + if (htab->is_vxworks +@@ -1529,17 +1542,23 @@ elf_i386_adjust_dynamic_symbol (struct b + both the dynamic object and the regular object will refer to the + same memory location for the variable. */ + ++ s = htab->sdynbss; ++ + /* We must generate a R_386_COPY reloc to tell the dynamic linker to + copy the initial value out of the dynamic object and into the + runtime process image. */ + if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) + { +- htab->srelbss->size += sizeof (Elf32_External_Rel); ++ if (elf_section_flags (h->root.u.def.section) & SHF_GNU_SHARABLE) ++ { ++ htab->srelsharablebss->size += sizeof (Elf32_External_Rel); ++ s = htab->sdynsharablebss; ++ } ++ else ++ htab->srelbss->size += sizeof (Elf32_External_Rel); + h->needs_copy = 1; + } + +- s = htab->sdynbss; +- + return _bfd_elf_adjust_dynamic_copy (h, s); + } + +@@ -1993,7 +2012,8 @@ elf_i386_size_dynamic_sections (bfd *out + if (s == htab->splt + || s == htab->sgot + || s == htab->sgotplt +- || s == htab->sdynbss) ++ || s == htab->sdynbss ++ || s == htab->sdynsharablebss) + { + /* Strip this section if we don't need it; see the + comment below. */ +@@ -3531,21 +3551,27 @@ elf_i386_finish_dynamic_symbol (bfd *out + { + Elf_Internal_Rela rel; + bfd_byte *loc; ++ asection *s; ++ ++ if (h->root.u.def.section == htab->sdynsharablebss) ++ s = htab->srelsharablebss; ++ else ++ s = htab->srelbss; + + /* This symbol needs a copy reloc. Set it up. */ + + if (h->dynindx == -1 + || (h->root.type != bfd_link_hash_defined + && h->root.type != bfd_link_hash_defweak) +- || htab->srelbss == NULL) ++ || s == NULL) + abort (); + + rel.r_offset = (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + rel.r_info = ELF32_R_INFO (h->dynindx, R_386_COPY); +- loc = htab->srelbss->contents; +- loc += htab->srelbss->reloc_count++ * sizeof (Elf32_External_Rel); ++ loc = s->contents; ++ loc += s->reloc_count++ * sizeof (Elf32_External_Rel); + bfd_elf32_swap_reloc_out (output_bfd, &rel, loc); + } + +@@ -3833,6 +3859,21 @@ elf_i386_hash_symbol (struct elf_link_ha + #define elf_backend_plt_sym_val elf_i386_plt_sym_val + #define elf_backend_hash_symbol elf_i386_hash_symbol + ++#define elf_backend_add_symbol_hook \ ++ _bfd_elf_add_sharable_symbol ++#define elf_backend_section_from_bfd_section \ ++ _bfd_elf_sharable_section_from_bfd_section ++#define elf_backend_symbol_processing \ ++ _bfd_elf_sharable_symbol_processing ++#define elf_backend_common_section_index \ ++ _bfd_elf_sharable_common_section_index ++#define elf_backend_common_section \ ++ _bfd_elf_sharable_common_section ++#define elf_backend_common_definition \ ++ _bfd_elf_sharable_common_definition ++#define elf_backend_merge_symbol \ ++ _bfd_elf_sharable_merge_symbol ++ + #include "elf32-target.h" + + /* FreeBSD support. */ +--- binutils/bfd/elf64-x86-64.c.shr 2007-05-15 07:35:03.000000000 -0700 ++++ binutils/bfd/elf64-x86-64.c 2007-06-02 07:39:38.000000000 -0700 +@@ -469,6 +469,8 @@ struct elf64_x86_64_link_hash_table + asection *srelplt; + asection *sdynbss; + asection *srelbss; ++ asection *sdynsharablebss; ++ asection *srelsharablebss; + + /* The offset into splt of the PLT entry for the TLS descriptor + resolver. Special values are 0, if not necessary (or not found +@@ -556,6 +558,8 @@ elf64_x86_64_link_hash_table_create (bfd + ret->srelplt = NULL; + ret->sdynbss = NULL; + ret->srelbss = NULL; ++ ret->sdynsharablebss = NULL; ++ ret->srelsharablebss = NULL; + ret->sym_sec.abfd = NULL; + ret->tlsdesc_plt = 0; + ret->tlsdesc_got = 0; +@@ -614,10 +618,19 @@ elf64_x86_64_create_dynamic_sections (bf + htab->srelplt = bfd_get_section_by_name (dynobj, ".rela.plt"); + htab->sdynbss = bfd_get_section_by_name (dynobj, ".dynbss"); + if (!info->shared) +- htab->srelbss = bfd_get_section_by_name (dynobj, ".rela.bss"); ++ { ++ htab->srelbss = bfd_get_section_by_name (dynobj, ".rela.bss"); ++ htab->sdynsharablebss ++ = bfd_get_section_by_name (dynobj, ".dynsharablebss"); ++ htab->srelsharablebss ++ = bfd_get_section_by_name (dynobj, ".rela.sharable_bss"); ++ } + + if (!htab->splt || !htab->srelplt || !htab->sdynbss +- || (!info->shared && !htab->srelbss)) ++ || (!info->shared ++ && (!htab->srelbss ++ || !htab->sdynsharablebss ++ || !htab->srelsharablebss))) + abort (); + + return TRUE; +@@ -1395,17 +1408,23 @@ elf64_x86_64_adjust_dynamic_symbol (stru + + htab = elf64_x86_64_hash_table (info); + ++ s = htab->sdynbss; ++ + /* We must generate a R_X86_64_COPY reloc to tell the dynamic linker + to copy the initial value out of the dynamic object and into the + runtime process image. */ + if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) + { +- htab->srelbss->size += sizeof (Elf64_External_Rela); ++ if (elf_section_flags (h->root.u.def.section) & SHF_GNU_SHARABLE) ++ { ++ htab->srelsharablebss->size += sizeof (Elf64_External_Rela); ++ s = htab->sdynsharablebss; ++ } ++ else ++ htab->srelbss->size += sizeof (Elf64_External_Rela); + h->needs_copy = 1; + } + +- s = htab->sdynbss; +- + return _bfd_elf_adjust_dynamic_copy (h, s); + } + +@@ -1853,7 +1872,8 @@ elf64_x86_64_size_dynamic_sections (bfd + if (s == htab->splt + || s == htab->sgot + || s == htab->sgotplt +- || s == htab->sdynbss) ++ || s == htab->sdynbss ++ || s == htab->sdynsharablebss) + { + /* Strip this section if we don't need it; see the + comment below. */ +@@ -3192,13 +3212,19 @@ elf64_x86_64_finish_dynamic_symbol (bfd + { + Elf_Internal_Rela rela; + bfd_byte *loc; ++ asection *s; ++ ++ if (h->root.u.def.section == htab->sdynsharablebss) ++ s = htab->srelsharablebss; ++ else ++ s = htab->srelbss; + + /* This symbol needs a copy reloc. Set it up. */ + + if (h->dynindx == -1 + || (h->root.type != bfd_link_hash_defined + && h->root.type != bfd_link_hash_defweak) +- || htab->srelbss == NULL) ++ || s == NULL) + abort (); + + rela.r_offset = (h->root.u.def.value +@@ -3206,8 +3232,8 @@ elf64_x86_64_finish_dynamic_symbol (bfd + + h->root.u.def.section->output_offset); + rela.r_info = ELF64_R_INFO (h->dynindx, R_X86_64_COPY); + rela.r_addend = 0; +- loc = htab->srelbss->contents; +- loc += htab->srelbss->reloc_count++ * sizeof (Elf64_External_Rela); ++ loc = s->contents; ++ loc += s->reloc_count++ * sizeof (Elf64_External_Rela); + bfd_elf64_swap_reloca_out (output_bfd, &rela, loc); + } + +@@ -3471,9 +3497,12 @@ elf64_x86_64_add_symbol_hook (bfd *abfd, + } + *secp = lcomm; + *valp = sym->st_size; ++ return TRUE; + break; + } +- return TRUE; ++ ++ return _bfd_elf_add_sharable_symbol (abfd, info, sym, namep, flagsp, ++ secp, valp); + } + + +@@ -3489,7 +3518,7 @@ elf64_x86_64_elf_section_from_bfd_sectio + *index = SHN_X86_64_LCOMMON; + return TRUE; + } +- return FALSE; ++ return _bfd_elf_sharable_section_from_bfd_section (abfd, sec, index); + } + + /* Process a symbol. */ +@@ -3507,22 +3536,26 @@ elf64_x86_64_symbol_processing (bfd *abf + asym->value = elfsym->internal_elf_sym.st_size; + /* Common symbol doesn't set BSF_GLOBAL. */ + asym->flags &= ~BSF_GLOBAL; ++ return; + break; + } ++ ++ _bfd_elf_sharable_symbol_processing (abfd, asym); + } + + static bfd_boolean + elf64_x86_64_common_definition (Elf_Internal_Sym *sym) + { + return (sym->st_shndx == SHN_COMMON +- || sym->st_shndx == SHN_X86_64_LCOMMON); ++ || sym->st_shndx == SHN_X86_64_LCOMMON ++ || _bfd_elf_sharable_common_definition (sym)); + } + + static unsigned int + elf64_x86_64_common_section_index (asection *sec) + { + if ((elf_section_flags (sec) & SHF_X86_64_LARGE) == 0) +- return SHN_COMMON; ++ return _bfd_elf_sharable_common_section_index (sec); + else + return SHN_X86_64_LCOMMON; + } +@@ -3531,7 +3564,7 @@ static asection * + elf64_x86_64_common_section (asection *sec) + { + if ((elf_section_flags (sec) & SHF_X86_64_LARGE) == 0) +- return bfd_com_section_ptr; ++ return _bfd_elf_sharable_common_section (sec); + else + return &_bfd_elf_large_com_section; + } +@@ -3568,7 +3601,8 @@ elf64_x86_64_merge_symbol (struct bfd_li + && h->root.type == bfd_link_hash_common + && !*newdyn + && bfd_is_com_section (*sec) +- && *oldsec != *sec) ++ && *oldsec != *sec ++ && _bfd_elf_sharable_common_section_index (*oldsec) == SHN_COMMON) + { + if (sym->st_shndx == SHN_COMMON + && (elf_section_flags (*oldsec) & SHF_X86_64_LARGE) != 0) +@@ -3576,13 +3610,26 @@ elf64_x86_64_merge_symbol (struct bfd_li + h->root.u.c.p->section + = bfd_make_section_old_way (oldbfd, "COMMON"); + h->root.u.c.p->section->flags = SEC_ALLOC; ++ return TRUE; + } + else if (sym->st_shndx == SHN_X86_64_LCOMMON + && (elf_section_flags (*oldsec) & SHF_X86_64_LARGE) == 0) +- *psec = *sec = bfd_com_section_ptr; ++ { ++ *psec = *sec = bfd_com_section_ptr; ++ return TRUE; ++ } + } + +- return TRUE; ++ return _bfd_elf_sharable_merge_symbol (info, sym_hash, h, sym, ++ psec, pvalue, pold_alignment, ++ skip, override, ++ type_change_ok, size_change_ok, ++ newdyn, newdef, ++ newdyncommon, newweak, ++ abfd, sec, ++ olddyn, olddef, ++ olddyncommon, oldweak, ++ oldbfd, oldsec); + } + + static int +--- binutils/bfd/elflink.c.shr 2007-06-02 07:39:38.000000000 -0700 ++++ binutils/bfd/elflink.c 2007-06-02 07:39:38.000000000 -0700 +@@ -352,6 +352,27 @@ _bfd_elf_create_dynamic_sections (bfd *a + if (s == NULL + || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align)) + return FALSE; ++ ++ if (info->sharable_sections) ++ { ++ s = bfd_make_section (abfd, ".dynsharablebss"); ++ if (s == NULL ++ || ! bfd_set_section_flags (abfd, s, ++ (SEC_ALLOC ++ | SEC_LINKER_CREATED))) ++ return FALSE; ++ ++ s = bfd_make_section (abfd, ++ (bed->default_use_rela_p ++ ? ".rela.sharable_bss" ++ : ".rel.sharable_bss")); ++ if (s == NULL ++ || ! bfd_set_section_flags (abfd, s, ++ flags | SEC_READONLY) ++ || ! bfd_set_section_alignment (abfd, s, ++ bed->s->log_file_align)) ++ return FALSE; ++ } + } + } + +@@ -11533,3 +11554,219 @@ _bfd_elf_common_section (asection *sec A + { + return bfd_com_section_ptr; + } ++ ++asection _bfd_elf_sharable_com_section ++ = BFD_FAKE_SECTION (_bfd_elf_sharable_com_section, SEC_IS_COMMON, ++ NULL, "SHARABLE_COMMON", 0); ++ ++static asection * ++get_sharable_common_section (bfd *abfd) ++{ ++ asection *scomm = bfd_get_section_by_name (abfd, "SHARABLE_COMMON"); ++ ++ if (scomm == NULL) ++ { ++ scomm = bfd_make_section_with_flags (abfd, ++ "SHARABLE_COMMON", ++ (SEC_ALLOC ++ | SEC_IS_COMMON ++ | SEC_LINKER_CREATED)); ++ if (scomm == NULL) ++ return scomm; ++ elf_section_flags (scomm) |= SHF_GNU_SHARABLE; ++ } ++ ++ return scomm; ++} ++ ++bfd_boolean ++_bfd_elf_add_sharable_symbol (bfd *abfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info ATTRIBUTE_UNUSED, ++ Elf_Internal_Sym *sym, ++ const char **namep ATTRIBUTE_UNUSED, ++ flagword *flagsp ATTRIBUTE_UNUSED, ++ asection **secp, ++ bfd_vma *valp) ++{ ++ asection *scomm; ++ ++ switch (sym->st_shndx) ++ { ++ case SHN_GNU_SHARABLE_COMMON: ++ scomm = get_sharable_common_section (abfd); ++ if (scomm == NULL) ++ return FALSE; ++ *secp = scomm; ++ *valp = sym->st_size; ++ break; ++ } ++ return TRUE; ++} ++ ++bfd_boolean ++_bfd_elf_sharable_section_from_bfd_section ++ (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, int *index) ++{ ++ if (sec == &_bfd_elf_sharable_com_section) ++ { ++ *index = SHN_GNU_SHARABLE_COMMON; ++ return TRUE; ++ } ++ return FALSE; ++} ++ ++void ++_bfd_elf_sharable_symbol_processing (bfd *abfd ATTRIBUTE_UNUSED, ++ asymbol *asym) ++{ ++ elf_symbol_type *elfsym = (elf_symbol_type *) asym; ++ ++ switch (elfsym->internal_elf_sym.st_shndx) ++ { ++ case SHN_GNU_SHARABLE_COMMON: ++ asym->section = &_bfd_elf_sharable_com_section; ++ asym->value = elfsym->internal_elf_sym.st_size; ++ asym->flags &= ~BSF_GLOBAL; ++ break; ++ } ++} ++ ++bfd_boolean ++_bfd_elf_sharable_common_definition (Elf_Internal_Sym *sym) ++{ ++ return (sym->st_shndx == SHN_COMMON ++ || sym->st_shndx == SHN_GNU_SHARABLE_COMMON); ++} ++ ++unsigned int ++_bfd_elf_sharable_common_section_index (asection *sec) ++{ ++ if ((elf_section_flags (sec) & SHF_GNU_SHARABLE) == 0) ++ return SHN_COMMON; ++ else ++ return SHN_GNU_SHARABLE_COMMON; ++} ++ ++asection * ++_bfd_elf_sharable_common_section (asection *sec) ++{ ++ if ((elf_section_flags (sec) & SHF_GNU_SHARABLE) == 0) ++ return bfd_com_section_ptr; ++ else ++ return &_bfd_elf_sharable_com_section; ++} ++ ++bfd_boolean ++_bfd_elf_sharable_merge_symbol ++ (struct bfd_link_info *info ATTRIBUTE_UNUSED, ++ struct elf_link_hash_entry **sym_hash ATTRIBUTE_UNUSED, ++ struct elf_link_hash_entry *h, ++ Elf_Internal_Sym *sym ATTRIBUTE_UNUSED, ++ asection **psec, ++ bfd_vma *pvalue ATTRIBUTE_UNUSED, ++ unsigned int *pold_alignment ATTRIBUTE_UNUSED, ++ bfd_boolean *skip ATTRIBUTE_UNUSED, ++ bfd_boolean *override ATTRIBUTE_UNUSED, ++ bfd_boolean *type_change_ok ATTRIBUTE_UNUSED, ++ bfd_boolean *size_change_ok ATTRIBUTE_UNUSED, ++ bfd_boolean *newdef ATTRIBUTE_UNUSED, ++ bfd_boolean *newdyn, ++ bfd_boolean *newdyncommon ATTRIBUTE_UNUSED, ++ bfd_boolean *newweak ATTRIBUTE_UNUSED, ++ bfd *abfd, ++ asection **sec, ++ bfd_boolean *olddef ATTRIBUTE_UNUSED, ++ bfd_boolean *olddyn, ++ bfd_boolean *olddyncommon ATTRIBUTE_UNUSED, ++ bfd_boolean *oldweak ATTRIBUTE_UNUSED, ++ bfd *oldbfd, ++ asection **oldsec) ++{ ++ /* Check sharable symbol. If one is undefined, it is OK. */ ++ if (*oldsec && !bfd_is_und_section (*sec)) ++ { ++ bfd_boolean sharable, oldsharable; ++ ++ sharable = (elf_section_data (*sec) ++ && (elf_section_flags (*sec) & SHF_GNU_SHARABLE)); ++ oldsharable = (elf_section_data (*oldsec) ++ && (elf_section_flags (*oldsec) ++ & SHF_GNU_SHARABLE)); ++ ++ if (sharable != oldsharable) ++ { ++ bfd *nsbfd, *sbfd; ++ asection *nssec, *ssec; ++ bfd_boolean nsdyn, sdyn, nsdef, sdef; ++ ++ if (oldsharable) ++ { ++ sbfd = oldbfd; ++ nsbfd = abfd; ++ ssec = *oldsec; ++ nssec = *sec; ++ sdyn = *olddyn; ++ nsdyn = *newdyn; ++ sdef = *olddef; ++ nsdef = *newdef; ++ } ++ else ++ { ++ sbfd = abfd; ++ nsbfd = oldbfd; ++ ssec = *sec; ++ nssec = *oldsec; ++ sdyn = *newdyn; ++ nsdyn = *olddyn; ++ sdef = *newdef; ++ nsdef = *olddef; ++ } ++ ++ if (sdef && !sdyn) ++ { ++ /* If the sharable definition comes from a relocatable ++ file, it will override the non-sharable one in DSO. */ ++ return TRUE; ++ } ++ else if (!nsdef ++ && !nsdyn ++ && (h->root.type == bfd_link_hash_common ++ || bfd_is_com_section (nssec))) ++ { ++ asection *scomm; ++ ++ /* When the non-sharable common symbol in a relocatable ++ file, we can turn it into sharable. If the sharable ++ symbol isn't common, the non-sharable common symbol ++ will be overidden. We only need to handle the ++ sharable common symbol and the non-sharable common ++ symbol. We just turn the non-sharable common symbol ++ into the sharable one. */ ++ if (sym->st_shndx == SHN_GNU_SHARABLE_COMMON) ++ { ++ scomm = get_sharable_common_section (oldbfd); ++ if (scomm == NULL) ++ return FALSE; ++ h->root.u.c.p->section = scomm; ++ } ++ else ++ { ++ scomm = get_sharable_common_section (abfd); ++ if (scomm == NULL) ++ return FALSE; ++ *psec = *sec = scomm; ++ } ++ ++ return TRUE; ++ } ++ ++ (*_bfd_error_handler) ++ (_("%s: sharable symbol in %B section %A mismatches non-shrable symbol in %B section %A"), ++ sbfd, ssec, nsbfd, nssec, h->root.root.string); ++ bfd_set_error (bfd_error_bad_value); ++ return FALSE; ++ } ++ } ++ ++ return TRUE; ++} +--- binutils/bfd/elfxx-ia64.c.shr 2007-04-27 05:25:13.000000000 -0700 ++++ binutils/bfd/elfxx-ia64.c 2007-06-02 07:39:38.000000000 -0700 +@@ -1636,7 +1636,8 @@ elfNN_ia64_add_symbol_hook (abfd, info, + *valp = sym->st_size; + } + +- return TRUE; ++ return _bfd_elf_add_sharable_symbol (abfd, info, sym, namep, flagsp, ++ secp, valp); + } + + /* Return the number of additional phdrs we will need. */ +@@ -5822,6 +5823,19 @@ elfNN_hpux_backend_symbol_processing (bf + #define elf_backend_special_sections elfNN_ia64_special_sections + #define elf_backend_default_execstack 0 + ++#define elf_backend_section_from_bfd_section \ ++ _bfd_elf_sharable_section_from_bfd_section ++#define elf_backend_symbol_processing \ ++ _bfd_elf_sharable_symbol_processing ++#define elf_backend_common_section_index \ ++ _bfd_elf_sharable_common_section_index ++#define elf_backend_common_section \ ++ _bfd_elf_sharable_common_section ++#define elf_backend_common_definition \ ++ _bfd_elf_sharable_common_definition ++#define elf_backend_merge_symbol \ ++ _bfd_elf_sharable_merge_symbol ++ + /* FIXME: PR 290: The Intel C compiler generates SHT_IA_64_UNWIND with + SHF_LINK_ORDER. But it doesn't set the sh_link or sh_info fields. + We don't want to flood users with so many error messages. We turn +--- binutils/binutils/readelf.c.shr 2007-06-02 07:38:12.000000000 -0700 ++++ binutils/binutils/readelf.c 2007-06-02 07:39:38.000000000 -0700 +@@ -1262,6 +1262,8 @@ dump_relocations (FILE *file, + sec_name = "ABS"; + else if (psym->st_shndx == SHN_COMMON) + sec_name = "COMMON"; ++ else if (psym->st_shndx == SHN_GNU_SHARABLE_COMMON) ++ sec_name = "GNU_SHARABLE_COMMON"; + else if (elf_header.e_machine == EM_MIPS + && psym->st_shndx == SHN_MIPS_SCOMMON) + sec_name = "SCOMMON"; +@@ -2459,6 +2461,7 @@ get_segment_type (unsigned long p_type) + case PT_SHLIB: return "SHLIB"; + case PT_PHDR: return "PHDR"; + case PT_TLS: return "TLS"; ++ case PT_GNU_SHR: return "GNU_SHR"; + + case PT_GNU_EH_FRAME: + return "GNU_EH_FRAME"; +@@ -6966,6 +6969,8 @@ get_symbol_index_type (unsigned int type + case SHN_UNDEF: return "UND"; + case SHN_ABS: return "ABS"; + case SHN_COMMON: return "COM"; ++ case SHN_GNU_SHARABLE_COMMON: ++ return "GNU_SHARABLE_COM"; + default: + if (type == SHN_IA_64_ANSI_COMMON + && elf_header.e_machine == EM_IA_64 +--- binutils/gas/config/obj-elf.c.shr 2007-03-01 15:11:20.000000000 -0800 ++++ binutils/gas/config/obj-elf.c 2007-06-02 07:39:38.000000000 -0700 +@@ -72,6 +72,7 @@ static void obj_elf_symver (int); + static void obj_elf_subsection (int); + static void obj_elf_popsection (int); + static void obj_elf_tls_common (int); ++static void obj_elf_sharable_common (int); + static void obj_elf_lcomm (int); + static void obj_elf_struct (int); + +@@ -129,6 +130,8 @@ static const pseudo_typeS elf_pseudo_tab + + {"tls_common", obj_elf_tls_common, 0}, + ++ {"sharable_common", obj_elf_sharable_common, 0}, ++ + /* End sentinel. */ + {NULL, NULL, 0}, + }; +@@ -373,6 +376,39 @@ obj_elf_tls_common (int ignore ATTRIBUTE + } + + static void ++obj_elf_sharable_common (int ignore ATTRIBUTE_UNUSED) ++{ ++ static segT sharable_bss_section; ++ asection *saved_com_section_ptr = elf_com_section_ptr; ++ asection *saved_bss_section = bss_section; ++ ++ if (sharable_bss_section == NULL) ++ { ++ flagword applicable; ++ segT seg = now_seg; ++ subsegT subseg = now_subseg; ++ ++ /* The .sharable_bss section is for local .sharable_common ++ symbols. */ ++ sharable_bss_section = subseg_new (".sharable_bss", 0); ++ applicable = bfd_applicable_section_flags (stdoutput); ++ bfd_set_section_flags (stdoutput, sharable_bss_section, ++ applicable & SEC_ALLOC); ++ seg_info (sharable_bss_section)->bss = 1; ++ ++ subseg_set (seg, subseg); ++ } ++ ++ elf_com_section_ptr = &_bfd_elf_sharable_com_section; ++ bss_section = sharable_bss_section; ++ ++ s_comm_internal (0, elf_common_parse); ++ ++ elf_com_section_ptr = saved_com_section_ptr; ++ bss_section = saved_bss_section; ++} ++ ++static void + obj_elf_lcomm (int ignore ATTRIBUTE_UNUSED) + { + symbolS *symbolP = s_comm_internal (0, s_lcomm_internal); +@@ -586,11 +622,17 @@ obj_elf_change_section (const char *name + + .section .lbss,"aw",@progbits + ++ "@progbits" is incorrect. Also for sharable bss ++ sections, gcc, as of 2005-07-06, will emit ++ ++ .section .sharable_bss,"aw",@progbits ++ + "@progbits" is incorrect. */ + #ifdef TC_I386 + && (bed->s->arch_size != 64 + || !(ssect->attr & SHF_X86_64_LARGE)) + #endif ++ && !(ssect->attr & SHF_GNU_SHARABLE) + && ssect->type != SHT_INIT_ARRAY + && ssect->type != SHT_FINI_ARRAY + && ssect->type != SHT_PREINIT_ARRAY) +--- binutils/include/bfdlink.h.shr 2007-06-02 07:38:14.000000000 -0700 ++++ binutils/include/bfdlink.h 2007-06-02 07:39:38.000000000 -0700 +@@ -347,6 +347,9 @@ struct bfd_link_info + --dynamic-list command line options. */ + unsigned int dynamic: 1; + ++ /* TRUE if sharables sections may be created. */ ++ unsigned int sharable_sections: 1; ++ + /* What to do with unresolved symbols in an object file. + When producing executables the default is GENERATE_ERROR. + When producing shared libraries the default is IGNORE. The +--- binutils/include/elf/common.h.shr 2007-04-27 05:25:14.000000000 -0700 ++++ binutils/include/elf/common.h 2007-06-02 07:39:38.000000000 -0700 +@@ -308,6 +308,7 @@ + #define PT_SUNW_EH_FRAME PT_GNU_EH_FRAME /* Solaris uses the same value */ + #define PT_GNU_STACK (PT_LOOS + 0x474e551) /* Stack flags */ + #define PT_GNU_RELRO (PT_LOOS + 0x474e552) /* Read-only after relocation */ ++#define PT_GNU_SHR (PT_LOOS + 0x474e554) /* Sharable segment */ + + /* Program segment permissions, in program header p_flags field. */ + +@@ -379,6 +380,8 @@ + #define SHF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ + #define SHF_MASKPROC 0xF0000000 /* Processor-specific semantics */ + ++#define SHF_GNU_SHARABLE 0x01000000 /* sharable section */ ++ + /* Values of note segment descriptor types for core files. */ + + #define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ +@@ -499,6 +502,9 @@ + #define SHN_HIRESERVE 0xFFFF /* End range of reserved indices */ + #define SHN_BAD ((unsigned) -1) /* Used internally by bfd */ + ++/* Associated symbol is in common sharable */ ++#define SHN_GNU_SHARABLE_COMMON (SHN_LOOS + 10) ++ + /* The following constants control how a symbol may be accessed once it has + become part of an executable or shared library. */ + +--- binutils/ld/emulparams/elf64_ia64.sh.shr 2006-09-18 10:08:08.000000000 -0700 ++++ binutils/ld/emulparams/elf64_ia64.sh 2007-06-02 07:39:38.000000000 -0700 +@@ -37,3 +37,4 @@ OTHER_READONLY_SECTIONS="${OTHER_READONL + # .dtors. They have to be next to .sbss/.sbss2/.sdata/.sdata2. + SMALL_DATA_CTOR=" " + SMALL_DATA_DTOR=" " ++SHARABLE_SECTIONS=yes +--- binutils/ld/emulparams/elf_i386.sh.shr 2006-09-18 10:08:08.000000000 -0700 ++++ binutils/ld/emulparams/elf_i386.sh 2007-06-02 07:39:38.000000000 -0700 +@@ -12,3 +12,4 @@ GENERATE_SHLIB_SCRIPT=yes + GENERATE_PIE_SCRIPT=yes + NO_SMALL_DATA=yes + SEPARATE_GOTPLT=12 ++SHARABLE_SECTIONS=yes +--- binutils/ld/emulparams/elf_x86_64.sh.shr 2006-10-18 20:47:43.000000000 -0700 ++++ binutils/ld/emulparams/elf_x86_64.sh 2007-06-02 07:39:38.000000000 -0700 +@@ -14,6 +14,7 @@ GENERATE_PIE_SCRIPT=yes + NO_SMALL_DATA=yes + LARGE_SECTIONS=yes + SEPARATE_GOTPLT=24 ++SHARABLE_SECTIONS=yes + + if [ "x${host}" = "x${target}" ]; then + case " $EMULATION_LIBPATH " in +--- binutils/ld/emultempl/elf32.em.shr 2007-04-27 05:25:14.000000000 -0700 ++++ binutils/ld/emultempl/elf32.em 2007-06-02 07:39:38.000000000 -0700 +@@ -97,6 +97,7 @@ gld${EMULATION_NAME}_before_parse (void) + ldfile_set_output_arch ("${OUTPUT_ARCH}", bfd_arch_`echo ${ARCH} | sed -e 's/:.*//'`); + config.dynamic_link = ${DYNAMIC_LINK-TRUE}; + config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`; ++ link_info.sharable_sections = `if test "$SHARABLE_SECTIONS" = "yes" ; then echo TRUE ; else echo FALSE ; fi`; + } + + EOF +@@ -1456,6 +1457,12 @@ gld${EMULATION_NAME}_place_orphan (asect + + secname = bfd_get_section_name (s->owner, s); + ++ /* Orphaned sharable sections won't have correct page ++ requirements. */ ++ if (elf_section_flags (s) & SHF_GNU_SHARABLE) ++ einfo ("%F%P: unable to place orphaned sharable section %A (%B)\n", ++ s, s->owner); ++ + if (! link_info.relocatable + && link_info.combreloc + && (s->flags & SEC_ALLOC)) +--- binutils/ld/ldmain.c.shr 2007-06-02 07:38:14.000000000 -0700 ++++ binutils/ld/ldmain.c 2007-06-02 07:40:46.000000000 -0700 +@@ -275,6 +275,7 @@ main (int argc, char **argv) + link_info.relax_pass = 1; + link_info.pei386_auto_import = -1; + link_info.spare_dynamic_tags = 5; ++ link_info.sharable_sections = FALSE; + + ldfile_add_arch (""); + emulation = get_emulation (argc, argv); +--- binutils/ld/scripttempl/elf.sc.shr 2007-05-03 20:14:32.000000000 -0700 ++++ binutils/ld/scripttempl/elf.sc 2007-06-02 07:39:38.000000000 -0700 +@@ -236,6 +236,40 @@ STACK=" .stack ${RELOCATING-0}${ + ${RELOCATING+_stack = .;} + *(.stack) + }" ++test "${SHARABLE_SECTIONS}" = "yes" && OTHER_READWRITE_SECTIONS=" ++ ${OTHER_READWRITE_SECTIONS} ++ /* Sharable data sections. */ ++ .sharable_data ${RELOCATING-0} : ${RELOCATING+ALIGN(${MAXPAGESIZE})} ++ { ++ ${RELOCATING+PROVIDE_HIDDEN (__sharable_data_start = .);} ++ *(.sharable_data${RELOCATING+ .sharable_data.* .gnu.linkonce.shrd.*}) ++ /* Align here to ensure that the sharable data section ends at the ++ page boundary. */ ++ ${RELOCATING+. = ALIGN(. != 0 ? ${MAXPAGESIZE} : 1);} ++ ${RELOCATING+PROVIDE_HIDDEN (__sharable_data_end = .);} ++ } ++" ++test "${SHARABLE_SECTIONS}" = "yes" && OTHER_BSS_SECTIONS=" ++ ${OTHER_BSS_SECTIONS} ++ /* Sharable bss sections */ ++ .sharable_bss ${RELOCATING-0} : ${RELOCATING+ALIGN(${MAXPAGESIZE})} ++ { ++ ${RELOCATING+PROVIDE_HIDDEN (__sharable_bss_start = .);} ++ *(.dynsharablebss) ++ *(.sharable_bss${RELOCATING+ .sharable_bss.* .gnu.linkonce.shrb.*}) ++ *(SHARABLE_COMMON) ++ /* Align here to ensure that the sharable bss section ends at the ++ page boundary. */ ++ ${RELOCATING+. = ALIGN(. != 0 ? ${MAXPAGESIZE} : 1);} ++ ${RELOCATING+PROVIDE_HIDDEN (__sharable_bss_end = .);} ++ } ++" ++test "${SHARABLE_SECTIONS}" = "yes" && REL_SHARABLE=" ++ .rel.sharable_data ${RELOCATING-0} : { *(.rel.sharable_data${RELOCATING+ .rel.sharable_data.* .rel.gnu.linkonce.shrd.*}) } ++ .rela.sharable_data ${RELOCATING-0} : { *(.rela.sharable_data${RELOCATING+ .rela.sharable_data.* .rela.gnu.linkonce.shrd.*}) } ++ .rel.sharable_bss ${RELOCATING-0} : { *(.rel.sharable_bss${RELOCATING+ .rel.sharable_bss.* .rel.gnu.linkonce.shrb.*}) } ++ .rela.sharable_bss ${RELOCATING-0} : { *(.rela.sharable_bss${RELOCATING+ .rela.sharable_bss.* .rela.gnu.linkonce.shrb.*}) } ++" + + # if this is for an embedded system, don't add SIZEOF_HEADERS. + if [ -z "$EMBEDDED" ]; then +@@ -305,6 +339,7 @@ eval $COMBRELOCCAT < +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: Explicitely use bash for the ld testsuite. + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +--- ./ld/testsuite/config/default.exp.orig 2009-04-19 21:52:33.000000000 +0200 ++++ ./ld/testsuite/config/default.exp 2009-04-19 21:54:01.000000000 +0200 +@@ -119,10 +119,10 @@ + #makefile rules, with embedded shell variable expansions. + #make wants $$shell_var, we want $shell_var ... + set cmd "host='$target_triplet' && . $srcdir/../configure.host && sed -e 's,\\\$\\\$,\$,g' <&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +--- ./include/plugin-api.h 15 Jan 2009 01:28:14 -0000 1.5 ++++ ./include/plugin-api.h 16 Oct 2009 14:08:17 -0000 +@@ -1,6 +1,6 @@ + /* plugin-api.h -- External linker plugin API. */ + +-/* Copyright 2008 Free Software Foundation, Inc. ++/* Copyright 2009 Free Software Foundation, Inc. + Written by Cary Coutant . + + This file is part of binutils. +@@ -111,13 +111,34 @@ enum ld_plugin_symbol_visibility + enum ld_plugin_symbol_resolution + { + LDPR_UNKNOWN = 0, ++ ++ /* Symbol is still undefined at this point. */ + LDPR_UNDEF, ++ ++ /* This is the prevailing definition of the symbol, with references from ++ regular object code. */ + LDPR_PREVAILING_DEF, ++ ++ /* This is the prevailing definition of the symbol, with no ++ references from regular objects. It is only referenced from IR ++ code. */ + LDPR_PREVAILING_DEF_IRONLY, ++ ++ /* This definition was pre-empted by a definition in a regular ++ object file. */ + LDPR_PREEMPTED_REG, ++ ++ /* This definition was pre-empted by a definition in another IR file. */ + LDPR_PREEMPTED_IR, ++ ++ /* This symbol was resolved by a definition in another IR file. */ + LDPR_RESOLVED_IR, ++ ++ /* This symbol was resolved by a definition in a regular object ++ linked into the main executable. */ + LDPR_RESOLVED_EXEC, ++ ++ /* This symbol was resolved by a definition in a shared object. */ + LDPR_RESOLVED_DYN + }; + +@@ -193,6 +214,12 @@ typedef + enum ld_plugin_status + (*ld_plugin_add_input_file) (char *pathname); + ++/* The linker's interface for adding a library that should be searched. */ ++ ++typedef ++enum ld_plugin_status ++(*ld_plugin_add_input_library) (char *libname); ++ + /* The linker's interface for issuing a warning or error message. */ + + typedef +@@ -224,7 +251,8 @@ enum ld_plugin_tag + LDPT_ADD_INPUT_FILE, + LDPT_MESSAGE, + LDPT_GET_INPUT_FILE, +- LDPT_RELEASE_INPUT_FILE ++ LDPT_RELEASE_INPUT_FILE, ++ LDPT_ADD_INPUT_LIBRARY + }; + + /* The plugin transfer vector. */ +@@ -245,6 +273,7 @@ struct ld_plugin_tv + ld_plugin_message tv_message; + ld_plugin_get_input_file tv_get_input_file; + ld_plugin_release_input_file tv_release_input_file; ++ ld_plugin_add_input_library tv_add_input_library; + } tv_u; + }; + --- binutils-2.20.orig/debian/patches/001_ld_makefile_patch.dpatch +++ binutils-2.20/debian/patches/001_ld_makefile_patch.dpatch @@ -0,0 +1,52 @@ +#!/bin/sh -e +## 001_ld_makefile_patch.dpatch +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: Description: correct where ld scripts are installed +## DP: Author: Chris Chimelis +## DP: Upstream status: N/A +## DP: Date: ?? + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +diff -urNad --exclude=CVS --exclude=.svn ./ld/Makefile.am /tmp/dpep-work.eKU2vW/binutils-2.16.1cvs20050902/ld/Makefile.am +--- ./ld/Makefile.am 2005-08-31 03:27:36.000000000 +0000 ++++ /tmp/dpep-work.eKU2vW/binutils-2.16.1cvs20050902/ld/Makefile.am 2005-09-02 21:42:18.000000000 +0000 +@@ -20,7 +20,7 @@ + # We put the scripts in the directory $(scriptdir)/ldscripts. + # We can't put the scripts in $(datadir) because the SEARCH_DIR + # directives need to be different for native and cross linkers. +-scriptdir = $(tooldir)/lib ++scriptdir = $(libdir) + + EMUL = @EMUL@ + EMULATION_OFILES = @EMULATION_OFILES@ +diff -urNad --exclude=CVS --exclude=.svn ./ld/Makefile.in /tmp/dpep-work.eKU2vW/binutils-2.16.1cvs20050902/ld/Makefile.in +--- ./ld/Makefile.in 2005-08-31 03:27:36.000000000 +0000 ++++ /tmp/dpep-work.eKU2vW/binutils-2.16.1cvs20050902/ld/Makefile.in 2005-09-02 21:43:37.259127535 +0000 +@@ -268,7 +268,7 @@ + # We put the scripts in the directory $(scriptdir)/ldscripts. + # We can't put the scripts in $(datadir) because the SEARCH_DIR + # directives need to be different for native and cross linkers. +-scriptdir = $(tooldir)/lib ++scriptdir = $(libdir) + BASEDIR = $(srcdir)/.. + BFDDIR = $(BASEDIR)/bfd + INCDIR = $(BASEDIR)/include --- binutils-2.20.orig/debian/patches/012_check_ldrunpath_length.dpatch +++ binutils-2.20/debian/patches/012_check_ldrunpath_length.dpatch @@ -0,0 +1,47 @@ +#!/bin/sh -e +## 012_check_ldrunpath_length.dpatch by Chris Chimelis +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: Only generate an RPATH entry if LD_RUN_PATH is not empty, for +## DP: cases where -rpath isn't specified. (#151024) + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +diff -urNad binutils-2.16/ld/emultempl/elf32.em /tmp/dpep.u3SQkH/binutils-2.16/ld/emultempl/elf32.em +--- binutils-2.16/ld/emultempl/elf32.em 2005-04-13 19:59:07.000000000 +0200 ++++ /tmp/dpep.u3SQkH/binutils-2.16/ld/emultempl/elf32.em 2005-05-06 19:18:08.236669718 +0200 +@@ -885,6 +885,8 @@ + && command_line.rpath == NULL) + { + lib_path = (const char *) getenv ("LD_RUN_PATH"); ++ if ((lib_path) && (strlen (lib_path) == 0)) ++ lib_path = NULL; + if (gld${EMULATION_NAME}_search_needed (lib_path, &n, + force)) + break; +@@ -1059,6 +1061,8 @@ + rpath = command_line.rpath; + if (rpath == NULL) + rpath = (const char *) getenv ("LD_RUN_PATH"); ++ if ((rpath) && (strlen (rpath) == 0)) ++ rpath = NULL; + if (! (bfd_elf_size_dynamic_sections + (output_bfd, command_line.soname, rpath, + command_line.filter_shlib, --- binutils-2.20.orig/debian/patches/200-hjl-ld-env.dpatch +++ binutils-2.20/debian/patches/200-hjl-ld-env.dpatch @@ -0,0 +1,88 @@ +#!/bin/sh -e +## 200-hjl-ld-env.dpatch +## +## DP: Description: Handle LD_SYMBOLIC and LD_SYMBOLIC_FUNCTIONS env vars +## DP: Author: H.J. Lu +## DP: Upstream status: hjl 2.19.51.0.3 +## DP: Original patch: ld-env-11.patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p0 < $0;; + -unpatch) patch $patch_opts -p0 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +2007-01-24 H.J. Lu + + * NEWS: Mention LD_SYMBOLIC and LD_SYMBOLIC_FUNCTIONS. + + * ld.texinfo: Document LD_SYMBOLIC and LD_SYMBOLIC_FUNCTIONS. + + * ldmain.c (main): Handle LD_SYMBOLIC and + LD_SYMBOLIC_FUNCTIONS. + +@DPATCH@ + +--- ld/NEWS.env 2008-09-08 09:34:53.000000000 -0700 ++++ ld/NEWS 2008-09-08 09:36:43.000000000 -0700 +@@ -1,5 +1,8 @@ + -*- text -*- + ++* ELF: Support environment variables, LD_SYMBOLIC for -Bsymbolic and ++ LD_SYMBOLIC_FUNCTIONS for -Bsymbolic-functions. ++ + Changes in 2.19: + + * Linker scripts support a new INSERT command that makes it easier to +--- ld/ld.texinfo.env 2008-07-22 07:19:39.000000000 -0700 ++++ ld/ld.texinfo 2008-09-08 09:35:29.000000000 -0700 +@@ -1147,14 +1147,21 @@ When creating a shared library, bind ref + definition within the shared library, if any. Normally, it is possible + for a program linked against a shared library to override the definition + within the shared library. This option is only meaningful on ELF +-platforms which support shared libraries. ++platforms which support shared libraries. If @option{-Bsymbolic} is not ++used when linking a shared library, the linker will also turn on this ++option if the environment variable @code{LD_SYMBOLIC} is set. + + @kindex -Bsymbolic-functions + @item -Bsymbolic-functions + When creating a shared library, bind references to global function + symbols to the definition within the shared library, if any. + This option is only meaningful on ELF platforms which support shared +-libraries. ++libraries. If @option{-Bsymbolic-functions} is not used when linking a ++shared library, the linker will also turn on this option if the ++environment variable @code{LD_SYMBOLIC_FUNCTIONS} is set. When ++both environment variables @code{LD_SYMBOLIC} and ++@code{LD_SYMBOLIC_FUNCTIONS} are set, @code{LD_SYMBOLIC} will take ++precedent. + + @kindex --dynamic-list=@var{dynamic-list-file} + @item --dynamic-list=@var{dynamic-list-file} +--- ld/ldmain.c.env 2008-09-08 09:35:29.000000000 -0700 ++++ ld/ldmain.c 2008-09-08 09:35:29.000000000 -0700 +@@ -253,6 +253,11 @@ main (int argc, char **argv) + command_line.warn_search_mismatch = TRUE; + command_line.check_section_addresses = TRUE; + ++ if (getenv ("LD_SYMBOLIC") != NULL) ++ command_line.symbolic = symbolic; ++ else if (getenv ("LD_SYMBOLIC_FUNCTIONS") != NULL) ++ command_line.symbolic = symbolic_functions; ++ + /* We initialize DEMANGLING based on the environment variable + COLLECT_NO_DEMANGLE. The gcc collect2 program will demangle the + output of the linker, unless COLLECT_NO_DEMANGLE is set in the --- binutils-2.20.orig/debian/patches/131_ld_bootstrap_testsuite.dpatch +++ binutils-2.20/debian/patches/131_ld_bootstrap_testsuite.dpatch @@ -0,0 +1,72 @@ +#!/bin/sh -e +## 131_ld_bootstrap_testsuite.dpatch +## +## DP: Description: Fix ld-bootstrap testsuite when configured with --enable-plugins +## DP: Author: Rafael Espindola +## DP: Upstream status: proposed patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +Index: ld/testsuite/ld-bootstrap/bootstrap.exp +=================================================================== +RCS file: /cvs/src/src/ld/testsuite/ld-bootstrap/bootstrap.exp,v +retrieving revision 1.18 +diff -u -r1.18 bootstrap.exp +--- ./ld/testsuite/ld-bootstrap/bootstrap.exp 2 Sep 2009 07:25:38 -0000 1.18 ++++ ./ld/testsuite/ld-bootstrap/bootstrap.exp 9 Oct 2009 15:38:50 -0000 +@@ -30,6 +30,15 @@ + return + } + ++remote_exec host "$nm --help" "" "/dev/null" "plugin-support" ++set tmp [file_contents "plugin-support"] ++regexp ".*\(--plugin\).*\n" $tmp foo plugins ++if [info exists plugins] then { ++ set plugins "yes" ++} else { ++ set plugins "no" ++} ++ + # Bootstrap ld. First link the object files together using -r, in + # order to test -r. Then link the result into an executable, ld1, to + # really test -r. Use ld1 to link a fresh ld, ld2. Use ld2 to link a +@@ -61,6 +70,11 @@ + continue + } + ++ if { $flags == "--static" && $plugins == "yes" } then { ++ untested $testname ++ continue ++ } ++ + # If we only have a shared libbfd, we probably can't run the + # --static test. + if { $flags == "--static" && ! [string match "*libbfd.a*" $BFDLIB] } then { +@@ -91,6 +105,10 @@ + } + } + ++ if { $plugins == "yes" } { ++ set extralibs "$extralibs -ldl" ++ } ++ + # On Irix 5, linking with --static only works if all the files are + # compiled using -non_shared. + if {"$flags" == "--static"} { --- binutils-2.20.orig/debian/patches/203-hjl-binutils-indirect.dpatch +++ binutils-2.20/debian/patches/203-hjl-binutils-indirect.dpatch @@ -0,0 +1,559 @@ +#!/bin/sh -e +## 203-hjl-binutils-indirect.dpatch +## +## DP: Description: PR ld/3351; avoid linker crash on ia64 +## DP: Author: H.J. Lu +## DP: Upstream status: hjl 2.19.50.0.10 +## DP: Original patch: binutils-indirect-2.patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +bfd/ + +2006-10-17 H.J. Lu + + PR ld/3351 + * elflink.c (_bfd_elf_update_dynamic_flags): New. + (_bfd_elf_merge_symbol): Update both real and indirect symbol + dynamic flags. + (_bfd_elf_add_default_symbol): Make the real symbol dynamic if + the indirect symbol is defined in a shared library. + (elf_link_add_object_symbols): Likewise. If the indirect + symbol has been forced local, don't make the real symbol + dynamic. + (elf_link_check_versioned_symbol): Check indirect symbol. + (elf_link_output_extsym): Use real symbol definition when + reporting indirect symbol error. Check version info for + dynamic versioned symbol. + +ld/testsuite/ + +2006-10-17 H.J. Lu + + PR ld/3351 + * ld-elf/indirect.exp: New file. + * ld-elf/indirect1a.c: Likewise. + * ld-elf/indirect1b.c: Likewise. + * ld-elf/indirect1c.c: Likewise. + * ld-elf/indirect2.c: Likewise. + * ld-elf/indirect3.out: Likewise. + * ld-elf/indirect3a.c: Likewise. + * ld-elf/indirect3b.c: Likewise. + * ld-elf/indirect3c.c: Likewise. + * ld-elf/indirect4.out: Likewise. + * ld-elf/indirect4a.c: Likewise. + * ld-elf/indirect4b.c: Likewise. + * ld-elf/indirect4c.c: Likewise. + +@DPATCH@ +--- binutils/bfd/elflink.c.indirect 2009-01-02 08:48:16.000000000 -0800 ++++ binutils/bfd/elflink.c 2009-01-02 09:07:14.000000000 -0800 +@@ -822,6 +822,33 @@ _bfd_elf_link_renumber_dynsyms (bfd *out + return dynsymcount; + } + ++/* Mark if a symbol has a definition in a dynamic object or is ++ weak in all dynamic objects. */ ++ ++static void ++_bfd_elf_mark_dynamic_def_weak (struct elf_link_hash_entry *h, ++ asection *sec, int bind) ++{ ++ if (!h->dynamic_def) ++ { ++ if (!bfd_is_und_section (sec)) ++ h->dynamic_def = 1; ++ else ++ { ++ /* Check if this symbol is weak in all dynamic objects. If it ++ is the first time we see it in a dynamic object, we mark ++ if it is weak. Otherwise, we clear it. */ ++ if (!h->ref_dynamic) ++ { ++ if (bind == STB_WEAK) ++ h->dynamic_weak = 1; ++ } ++ else if (bind != STB_WEAK) ++ h->dynamic_weak = 0; ++ } ++ } ++} ++ + /* This function is called when we want to define a new symbol. It + handles the various cases which arise when we find a definition in + a dynamic object, or when there is already a definition in a +@@ -850,6 +877,7 @@ _bfd_elf_merge_symbol (bfd *abfd, + { + asection *sec, *oldsec; + struct elf_link_hash_entry *h; ++ struct elf_link_hash_entry *hi; + struct elf_link_hash_entry *flip; + int bind; + bfd *oldbfd; +@@ -888,8 +916,9 @@ _bfd_elf_merge_symbol (bfd *abfd, + if (!(*bed->relocs_compatible) (abfd->xvec, info->output_bfd->xvec)) + return TRUE; + +- /* For merging, we only care about real symbols. */ +- ++ /* For merging, we only care about real symbols. But we need to make ++ sure that indirect symbol dynamic flags are updated. */ ++ hi = h; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; +@@ -1055,23 +1084,11 @@ _bfd_elf_merge_symbol (bfd *abfd, + /* We need to remember if a symbol has a definition in a dynamic + object or is weak in all dynamic objects. Internal and hidden + visibility will make it unavailable to dynamic objects. */ +- if (newdyn && !h->dynamic_def) ++ if (newdyn) + { +- if (!bfd_is_und_section (sec)) +- h->dynamic_def = 1; +- else +- { +- /* Check if this symbol is weak in all dynamic objects. If it +- is the first time we see it in a dynamic object, we mark +- if it is weak. Otherwise, we clear it. */ +- if (!h->ref_dynamic) +- { +- if (bind == STB_WEAK) +- h->dynamic_weak = 1; +- } +- else if (bind != STB_WEAK) +- h->dynamic_weak = 0; +- } ++ _bfd_elf_mark_dynamic_def_weak (h, sec, bind); ++ if (h != hi) ++ _bfd_elf_mark_dynamic_def_weak (hi, sec, bind); + } + + /* If the old symbol has non-default visibility, we ignore the new +@@ -1083,6 +1100,7 @@ _bfd_elf_merge_symbol (bfd *abfd, + *skip = TRUE; + /* Make sure this symbol is dynamic. */ + h->ref_dynamic = 1; ++ hi->ref_dynamic = 1; + /* A protected symbol has external availability. Make sure it is + recorded as dynamic. + +@@ -1624,6 +1642,7 @@ _bfd_elf_add_default_symbol (bfd *abfd, + if (! dynamic) + { + if (info->shared ++ || hi->def_dynamic + || hi->ref_dynamic) + *dynsym = TRUE; + } +@@ -3807,6 +3826,7 @@ elf_link_add_object_symbols (bfd *abfd, + flagword flags; + const char *name; + struct elf_link_hash_entry *h; ++ struct elf_link_hash_entry *hi; + bfd_boolean definition; + bfd_boolean size_change_ok; + bfd_boolean type_change_ok; +@@ -4091,6 +4111,9 @@ elf_link_add_object_symbols (bfd *abfd, + goto error_free_vers; + + h = *sym_hash; ++ /* We need to make sure that indirect symbol dynamic flags are ++ updated. */ ++ hi = h; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; +@@ -4305,22 +4328,36 @@ elf_link_add_object_symbols (bfd *abfd, + h->dynamic_def = 1; + } + } +- if (! info->executable +- || h->def_dynamic +- || h->ref_dynamic) ++ ++ /* If the indirect symbol has been forced local, don't ++ make the real symbol dynamic. */ ++ if ((h == hi || !hi->forced_local) ++ && (! info->executable ++ || h->def_dynamic ++ || h->ref_dynamic)) + dynsym = TRUE; + } + else + { + if (! definition) +- h->ref_dynamic = 1; ++ { ++ h->ref_dynamic = 1; ++ hi->ref_dynamic = 1; ++ } + else +- h->def_dynamic = 1; +- if (h->def_regular +- || h->ref_regular +- || (h->u.weakdef != NULL +- && ! new_weakdef +- && h->u.weakdef->dynindx != -1)) ++ { ++ h->def_dynamic = 1; ++ hi->def_dynamic = 1; ++ } ++ ++ /* If the indirect symbol has been forced local, don't ++ make the real symbol dynamic. */ ++ if ((h == hi || !hi->forced_local) ++ && (h->def_regular ++ || h->ref_regular ++ || (h->u.weakdef != NULL ++ && ! new_weakdef ++ && h->u.weakdef->dynindx != -1))) + dynsym = TRUE; + } + +@@ -8280,6 +8317,10 @@ elf_link_check_versioned_symbol (struct + if (!is_elf_hash_table (info->hash)) + return FALSE; + ++ /* Check indirect symbol. */ ++ while (h->root.type == bfd_link_hash_indirect) ++ h = (struct elf_link_hash_entry *) h->root.u.i.link; ++ + switch (h->root.type) + { + default: +@@ -8488,11 +8529,17 @@ elf_link_output_extsym (struct elf_link_ + && !h->dynamic_weak + && ! elf_link_check_versioned_symbol (finfo->info, bed, h)) + { ++ struct elf_link_hash_entry *hi = h; ++ ++ /* Check indirect symbol. */ ++ while (hi->root.type == bfd_link_hash_indirect) ++ hi = (struct elf_link_hash_entry *) hi->root.u.i.link; ++ + (*_bfd_error_handler) + (_("%B: %s symbol `%s' in %B is referenced by DSO"), + finfo->output_bfd, +- h->root.u.def.section == bfd_abs_section_ptr +- ? finfo->output_bfd : h->root.u.def.section->owner, ++ hi->root.u.def.section == bfd_abs_section_ptr ++ ? finfo->output_bfd : hi->root.u.def.section->owner, + ELF_ST_VISIBILITY (h->other) == STV_INTERNAL + ? "internal" + : ELF_ST_VISIBILITY (h->other) == STV_HIDDEN +@@ -8702,6 +8749,23 @@ elf_link_output_extsym (struct elf_link_ + { + bfd_byte *esym; + ++ /* Since there is no version information in the dynamic string, ++ if there is no version info in symbol version section, we will ++ have a run-time problem. */ ++ if (h->verinfo.verdef == NULL) ++ { ++ char *p = strrchr (h->root.root.string, ELF_VER_CHR); ++ ++ if (p && p [1] != '\0') ++ { ++ (*_bfd_error_handler) ++ (_("%B: No symbol version section for versioned symbol `%s'"), ++ finfo->output_bfd, h->root.root.string); ++ eoinfo->failed = TRUE; ++ return FALSE; ++ } ++ } ++ + sym.st_name = h->dynstr_index; + esym = finfo->dynsym_sec->contents + h->dynindx * bed->s->sizeof_sym; + if (! check_dynsym (finfo->output_bfd, &sym)) +--- binutils/ld/testsuite/ld-elf/indirect.exp.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect.exp 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,126 @@ ++# Expect script for various indirect symbol tests. ++# Copyright 2006 Free Software Foundation, Inc. ++# ++# This file is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 2 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. ++# ++ ++# ++# Written by H.J. Lu (hongjiu.lu@intel.com) ++# ++ ++# Exclude non-ELF targets. ++ ++if ![is_elf_format] { ++ return ++} ++ ++# Check if compiler works ++if { [which $CC] == 0 } { ++ return ++} ++ ++proc check_link_message { cmd string testname } { ++ send_log "$cmd\n" ++ verbose "$cmd" ++ catch "exec $cmd" exec_output ++ send_log "$exec_output\n" ++ verbose "$exec_output" ++ ++ foreach str $string { ++ if [string match "*$str*" $exec_output] { ++ pass "$testname: $str" ++ } else { ++ fail "$testname: $str" ++ } ++ } ++} ++ ++if { ![ld_compile $CC $srcdir/$subdir/indirect1a.c tmpdir/indirect1a.o] ++ || ![ld_compile $CC $srcdir/$subdir/indirect1b.c tmpdir/indirect1b.o] ++ || ![ld_compile "$CC -fPIC" $srcdir/$subdir/indirect2.c tmpdir/indirect2.o] ++ || ![ld_compile $CC $srcdir/$subdir/indirect3a.c tmpdir/indirect3a.o] ++ || ![ld_compile $CC $srcdir/$subdir/indirect3b.c tmpdir/indirect3b.o] ++ || ![ld_compile $CC $srcdir/$subdir/indirect4a.c tmpdir/indirect4a.o] ++ || ![ld_compile $CC $srcdir/$subdir/indirect4b.c tmpdir/indirect4b.o] } { ++ unresolved "Indirect symbol tests" ++ return ++} ++ ++set build_tests { ++ {"Build libindirect1c.so" ++ "-shared" "-fPIC" ++ {indirect1c.c} {} "libindirect1c.so"} ++ {"Build libindirect3c.so" ++ "-shared" "-fPIC" ++ {indirect3c.c} {} "libindirect3c.so"} ++ {"Build libindirect4c.so" ++ "-shared" "-fPIC" ++ {indirect4c.c} {} "libindirect4c.so"} ++} ++ ++run_cc_link_tests $build_tests ++ ++global ld ++ ++set string ": final link failed: Nonrepresentable section on output" ++ ++set string1 ": local symbol \`foo\' in tmpdir/indirect1b.o is referenced by DSO" ++ ++set testname "Indirect symbol 1a" ++set cmd "$ld -e start -o tmpdir/indirect1 tmpdir/indirect1a.o tmpdir/indirect1b.o tmpdir/libindirect1c.so" ++check_link_message "$cmd" [list $string1 $string] "$testname" ++ ++set testname "Indirect symbol 1b" ++set cmd "$ld -e start -o tmpdir/indirect1 tmpdir/indirect1a.o tmpdir/libindirect1c.so tmpdir/indirect1b.o" ++check_link_message "$cmd" [list $string1 $string] "$testname" ++ ++set string2 ": No symbol version section for versioned symbol \`foo@FOO\'" ++set testname "Indirect symbol 2" ++set cmd "$ld -shared -o tmpdir/indirect2.so tmpdir/indirect2.o" ++check_link_message "$cmd" [list $string2 $string] "$testname" ++ ++# The following tests require running the executable generated by ld. ++if ![isnative] { ++ return ++} ++ ++set run_tests { ++ {"Run with libindirect3c.so 1" ++ "tmpdir/indirect3a.o tmpdir/indirect3b.o tmpdir/libindirect3c.so" "" ++ {dummy.c} "indirect3a" "indirect3.out"} ++ {"Run with libindirect3c.so 2" ++ "tmpdir/indirect3a.o tmpdir/libindirect3c.so tmpdir/indirect3b.o" "" ++ {dummy.c} "indirect3b" "indirect3.out"} ++ {"Run with libindirect3c.so 3" ++ "tmpdir/indirect3b.o tmpdir/libindirect3c.so tmpdir/indirect3a.o" "" ++ {dummy.c} "indirect3c" "indirect3.out"} ++ {"Run with libindirect3c.so 4" ++ "tmpdir/libindirect3c.so tmpdir/indirect3b.o tmpdir/indirect3a.o" "" ++ {dummy.c} "indirect3d" "indirect3.out"} ++ {"Run with libindirect4c.so 1" ++ "tmpdir/indirect4a.o tmpdir/indirect4b.o tmpdir/libindirect4c.so" "" ++ {dummy.c} "indirect4a" "indirect4.out"} ++ {"Run with libindirect4c.so 2" ++ "tmpdir/indirect4a.o tmpdir/libindirect4c.so tmpdir/indirect4b.o" "" ++ {dummy.c} "indirect4b" "indirect4.out"} ++ {"Run with libindirect4c.so 3" ++ "tmpdir/indirect4b.o tmpdir/libindirect4c.so tmpdir/indirect4a.o" "" ++ {dummy.c} "indirect4c" "indirect4.out"} ++ {"Run with libindirect4c.so 4" ++ "tmpdir/libindirect4c.so tmpdir/indirect4b.o tmpdir/indirect4a.o" "" ++ {dummy.c} "indirect4d" "indirect4.out"} ++} ++ ++run_ld_link_exec_tests [] $run_tests +--- binutils/ld/testsuite/ld-elf/indirect1a.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect1a.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,8 @@ ++extern void bar (void); ++ ++int ++start (void) ++{ ++ bar (); ++ return 0; ++} +--- binutils/ld/testsuite/ld-elf/indirect1b.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect1b.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,6 @@ ++void ++foo (void) ++{ ++} ++ ++asm (".symver foo,foo@FOO"); +--- binutils/ld/testsuite/ld-elf/indirect1c.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect1c.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,7 @@ ++extern void foo (void); ++ ++void ++bar (void) ++{ ++ foo (); ++} +--- binutils/ld/testsuite/ld-elf/indirect2.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect2.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,9 @@ ++extern void foo (void); ++ ++asm (".symver foo,foo@@@FOO"); ++ ++void ++bar (void) ++{ ++ foo (); ++} +--- binutils/ld/testsuite/ld-elf/indirect3.out.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect3.out 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,2 @@ ++MAIN ++DSO +--- binutils/ld/testsuite/ld-elf/indirect3a.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect3a.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,10 @@ ++extern void bar (void); ++extern void foo (void); ++ ++int ++main (void) ++{ ++ foo (); ++ bar (); ++ return 0; ++} +--- binutils/ld/testsuite/ld-elf/indirect3b.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect3b.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,9 @@ ++#include ++ ++void ++foo (void) ++{ ++ printf ("MAIN\n"); ++} ++ ++asm (".symver foo,foo@FOO"); +--- binutils/ld/testsuite/ld-elf/indirect3c.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect3c.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,15 @@ ++#include ++ ++extern void foo (void); ++ ++void ++foo (void) ++{ ++ printf ("DSO\n"); ++} ++ ++void ++bar (void) ++{ ++ foo (); ++} +--- binutils/ld/testsuite/ld-elf/indirect4.out.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect4.out 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,2 @@ ++MAIN2 ++MAIN2 +--- binutils/ld/testsuite/ld-elf/indirect4a.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect4a.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,10 @@ ++extern void bar (void); ++extern void foo (void); ++ ++int ++main (void) ++{ ++ foo (); ++ bar (); ++ return 0; ++} +--- binutils/ld/testsuite/ld-elf/indirect4b.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect4b.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,17 @@ ++#include ++ ++void ++foo2 (void) ++{ ++ printf ("MAIN2\n"); ++} ++ ++asm (".symver foo2,foo@@FOO2"); ++ ++void ++foo1 (void) ++{ ++ printf ("MAIN1\n"); ++} ++ ++asm (".symver foo1,foo@FOO1"); +--- binutils/ld/testsuite/ld-elf/indirect4c.c.indirect 2009-01-02 09:06:01.000000000 -0800 ++++ binutils/ld/testsuite/ld-elf/indirect4c.c 2009-01-02 09:06:01.000000000 -0800 +@@ -0,0 +1,15 @@ ++#include ++ ++extern void foo (void); ++ ++void ++foo (void) ++{ ++ printf ("DSO\n"); ++} ++ ++void ++bar (void) ++{ ++ foo (); ++} --- binutils-2.20.orig/debian/patches/003_gprof_see_also_monitor.dpatch +++ binutils-2.20/debian/patches/003_gprof_see_also_monitor.dpatch @@ -0,0 +1,37 @@ +#!/bin/sh -e +## 014_gprof_manpage_fix.dpatch by Chris Chimelis +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: Don't mention monitor(3) which doesn't exist in Debian. (#160654) + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +diff -urNad /home/james/debian/packages/binutils/binutils-2.14.90.0.6/gprof/gprof.texi binutils-2.14.90.0.6/gprof/gprof.texi +--- /home/james/debian/packages/binutils/binutils-2.14.90.0.6/gprof/gprof.texi 2002-08-02 01:49:32.000000000 +0100 ++++ binutils-2.14.90.0.6/gprof/gprof.texi 2003-09-10 22:42:37.000000000 +0100 +@@ -181,7 +181,7 @@ + @c man end + + @c man begin SEEALSO +-monitor(3), profil(2), cc(1), prof(1), and the Info entry for @file{gprof}. ++cc(1), prof(1), and the Info entry for @file{gprof}. + + ``An Execution Profiler for Modular Programs'', + by S. Graham, P. Kessler, M. McKusick; --- binutils-2.20.orig/debian/patches/212-hjl-bfd-64k.dpatch +++ binutils-2.20/debian/patches/212-hjl-bfd-64k.dpatch @@ -0,0 +1,70 @@ +#!/bin/sh -e +## 212-hjl-bfd-64k.dpatch +## +## DP: Description: elf.c (assign_section_numbers): Check if number of sections +## DP: Description: >= SHN_LORESERVE. +## DP: Description: elfcode.h (elf_object_p): Likewise. +## DP: Author: H.J. Lu +## DP: Upstream status: hjl 2.18.50.0.5 +## DP: Original patch: bfd-64k-2.patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p0 < $0;; + -unpatch) patch $patch_opts -p0 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +2008-03-12 H.J. Lu + + * elf.c (assign_section_numbers): Check if number of sections + >= SHN_LORESERVE. + * elfcode.h (elf_object_p): Likewise. + +@DPATCH@ +--- bfd/elf.c.64k 2008-03-12 12:32:53.000000000 -0700 ++++ bfd/elf.c 2008-03-12 14:06:17.000000000 -0700 +@@ -2831,6 +2831,13 @@ assign_section_numbers (bfd *abfd, struc + _bfd_elf_strtab_addref (elf_shstrtab (abfd), t->strtab_hdr.sh_name); + } + ++ if (section_number >= SHN_LORESERVE) ++ { ++ _bfd_error_handler (_("%B: too many sections: %u"), ++ abfd, section_number); ++ return FALSE; ++ } ++ + _bfd_elf_strtab_finalize (elf_shstrtab (abfd)); + t->shstrtab_hdr.sh_size = _bfd_elf_strtab_size (elf_shstrtab (abfd)); + +--- bfd/elfcode.h.64k 2008-03-12 12:32:05.000000000 -0700 ++++ bfd/elfcode.h 2008-03-12 15:30:51.000000000 -0700 +@@ -684,8 +684,14 @@ elf_object_p (bfd *abfd) + if (i_ehdrp->e_shnum == SHN_UNDEF) + { + i_ehdrp->e_shnum = i_shdr.sh_size; +- if (i_ehdrp->e_shnum != i_shdr.sh_size +- || i_ehdrp->e_shnum == 0) ++ if (i_ehdrp->e_shnum >= SHN_LORESERVE) ++ { ++ _bfd_error_handler (_("%B: too many sections: %u"), ++ abfd, i_ehdrp->e_shnum); ++ abort (); ++ } ++ else if (i_ehdrp->e_shnum != i_shdr.sh_size ++ || i_ehdrp->e_shnum == 0) + goto got_wrong_format_error; + } + --- binutils-2.20.orig/debian/patches/211-hjl-binutils-weakdef.dpatch +++ binutils-2.20/debian/patches/211-hjl-binutils-weakdef.dpatch @@ -0,0 +1,127 @@ +#!/bin/sh -e +## 211-hjl-binutils-weakdef.dpatch +## +## DP: Description: elflink.c (elf_link_add_object_symbols): Check symbol type +## DP: Description: for symbol alias in a dynamic object. +## DP: Author: H.J. Lu +## DP: Upstream status: hjl 2.19.51.0.3 +## DP: Original patch: binutils-weakdef-2.patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +bfd/ + +2007-07-19 H.J. Lu + + * elflink.c (elf_link_add_object_symbols): Check symbol type + for symbol alias in a dynamic object. + +ld/testsuite/ + +2007-07-19 H.J. Lu + + * ld-elf/data2.c: New. + * ld-elf/weakdef1.c: Likewise. + + * ld-elf/shared.exp: Add tests for libdata2 and weakdef1. + +@DPATCH@ +--- binutils/bfd/elflink.c.weakdef 2008-09-16 07:11:39.000000000 -0700 ++++ binutils/bfd/elflink.c 2008-09-16 07:11:41.000000000 -0700 +@@ -4641,6 +4641,7 @@ elf_link_add_object_symbols (bfd *abfd, + asection *slook; + bfd_vma vlook; + long ilook; ++ int tlook; + size_t i, j, idx; + + hlook = weaks; +@@ -4653,6 +4654,7 @@ elf_link_add_object_symbols (bfd *abfd, + || hlook->root.type == bfd_link_hash_indirect); + slook = hlook->root.u.def.section; + vlook = hlook->root.u.def.value; ++ tlook = hlook->type; + + ilook = -1; + i = 0; +@@ -4690,9 +4692,10 @@ elf_link_add_object_symbols (bfd *abfd, + { + h = sorted_sym_hash [i]; + +- /* Stop if value or section doesn't match. */ ++ /* Stop if value, section or type doesn't match. */ + if (h->root.u.def.value != vlook +- || h->root.u.def.section != slook) ++ || h->root.u.def.section != slook ++ || h->type != tlook) + break; + else if (h != hlook) + { +--- binutils/ld/testsuite/ld-elf/data2.c.weakdef 2008-09-16 07:11:41.000000000 -0700 ++++ binutils/ld/testsuite/ld-elf/data2.c 2008-09-16 07:11:41.000000000 -0700 +@@ -0,0 +1,9 @@ ++int foo = 0; ++extern int foo_alias __attribute__ ((weak, alias ("foo"))); ++ ++void ++bar (void) ++{ ++ foo = -1; ++} ++ +--- binutils/ld/testsuite/ld-elf/shared.exp.weakdef 2008-09-16 07:10:01.000000000 -0700 ++++ binutils/ld/testsuite/ld-elf/shared.exp 2008-09-16 07:12:43.000000000 -0700 +@@ -123,6 +123,9 @@ set build_tests { + {"Build libdata1.so" + "-shared" "-fPIC" + {data1.c} {} "libdata1.so"} ++ {"Build libdata2.so" ++ "-shared" "-fPIC" ++ {data2.c} {} "libdata2.so"} + {"Build libcomm1.o" + "-r -nostdlib" "" + {comm1.c} {} "libcomm1.o"} +@@ -241,6 +244,9 @@ set run_tests { + {"Run with libdata1.so" + "tmpdir/libdata1.so" "" + {dynbss1.c} "dynbss1" "pass.out"} ++ {"Run with libdata2.so" ++ "tmpdir/libdata2.so" "" ++ {weakdef1.c} "weakdef1" "pass.out"} + {"Run with libfunc1.so comm1.o" + "tmpdir/libfunc1.so tmpdir/comm1.o" "" + {dummy.c} "comm1" "pass.out"} +--- binutils/ld/testsuite/ld-elf/weakdef1.c.weakdef 2008-09-16 07:11:41.000000000 -0700 ++++ binutils/ld/testsuite/ld-elf/weakdef1.c 2008-09-16 07:11:41.000000000 -0700 +@@ -0,0 +1,15 @@ ++#include ++#include ++ ++extern int foo_alias; ++extern void bar (void); ++ ++int ++main (void) ++{ ++ bar (); ++ if (foo_alias != -1) ++ abort (); ++ printf ("PASS\n"); ++ return 0; ++} --- binutils-2.20.orig/debian/patches/210-hjl-binutils-signed.dpatch +++ binutils-2.20/debian/patches/210-hjl-binutils-signed.dpatch @@ -0,0 +1,704 @@ +#!/bin/sh -e +## 210-hjl-binutils-signed.dpatch +## +## DP: Description: objdump.c (disassemble_bytes,dump_reloc_set): Print addend as signed. +## DP: Author: H.J. Lu +## DP: Upstream status: hjl 2.18.50.0.5 +## DP: Original patch: binutils-signed-3.patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +binutils/ + +2007-06-22 H.J. Lu + + * objdump.c (disassemble_bytes): Print addend as signed. + (dump_reloc_set): Likewise. + +gas/testsuite/ + +2007-06-22 H.J. Lu + + * gas/alpha/elf-reloc-1.d: Expect addend as signed. + * gas/i386/mixed-mode-reloc64.d: Likewise. + * gas/i386/reloc64.d: Likewise. + * gas/ia64/pcrel.d: Likewise. + * gas/mips/branch-misc-2-64.d: Likewise. + * gas/mips/branch-misc-2pic-64.d: Likewise. + * gas/mips/ldstla-n64-sym32.d: Likewise. + * gas/mips/mips16-hilo-n32.d: Likewise. + * gas/ppc/astest.d: Likewise. + * gas/ppc/astest2.d: Likewise. + * gas/ppc/astest2_64.d: Likewise. + * gas/ppc/astest64.d: Likewise. + * gas/ppc/test1elf32.d: Likewise. + * gas/ppc/test1elf64.d: Likewise. + * gas/sparc/reloc64.d: Likewise. + +@DPATCH@ +--- binutils/binutils/objdump.c.signed 2007-07-24 15:03:40.000000000 -0700 ++++ binutils/binutils/objdump.c 2007-09-26 09:51:38.000000000 -0700 +@@ -1650,8 +1650,15 @@ disassemble_bytes (struct disassemble_in + + if (q->addend) + { +- printf ("+0x"); +- objdump_print_value (q->addend, info, TRUE); ++ bfd_signed_vma addend = q->addend; ++ if (addend < 0) ++ { ++ printf ("-0x"); ++ addend = -addend; ++ } ++ else ++ printf ("+0x"); ++ objdump_print_value (addend, info, TRUE); + } + + printf ("\n"); +@@ -2710,8 +2717,15 @@ dump_reloc_set (bfd *abfd, asection *sec + + if (q->addend) + { +- printf ("+0x"); +- bfd_printf_vma (abfd, q->addend); ++ bfd_signed_vma addend = q->addend; ++ if (addend < 0) ++ { ++ printf ("-0x"); ++ addend = -addend; ++ } ++ else ++ printf ("+0x"); ++ bfd_printf_vma (abfd, addend); + } + + printf ("\n"); +--- binutils/gas/testsuite/gas/alpha/elf-reloc-1.d.signed 2003-06-17 04:16:16.000000000 -0700 ++++ binutils/gas/testsuite/gas/alpha/elf-reloc-1.d 2007-09-26 09:51:38.000000000 -0700 +@@ -16,6 +16,6 @@ OFFSET TYPE VALUE + 0*000001c GPRELHIGH d + 0*0000020 GPRELLOW e + 0*0000024 GPDISP \.text\+0x0*0000008 +-0*0000030 GPDISP \.text\+0xf*ffffff8 ++0*0000030 GPDISP \.text-0x0*0000008 + + +--- binutils/gas/testsuite/gas/i386/mixed-mode-reloc64.d.signed 2005-09-28 08:31:21.000000000 -0700 ++++ binutils/gas/testsuite/gas/i386/mixed-mode-reloc64.d 2007-09-26 09:51:38.000000000 -0700 +@@ -7,8 +7,8 @@ + RELOCATION RECORDS FOR \[.text\]: + OFFSET[ ]+TYPE[ ]+VALUE[ ]* + [0-9a-f]+[ ]+R_X86_64_GOT32[ ]+xtrn[ ]* +-[0-9a-f]+[ ]+R_X86_64_PLT32[ ]+xtrn\+0xf+c[ ]* ++[0-9a-f]+[ ]+R_X86_64_PLT32[ ]+xtrn-0x0*4[ ]* + [0-9a-f]+[ ]+R_X86_64_GOT32[ ]+xtrn[ ]* +-[0-9a-f]+[ ]+R_X86_64_PLT32[ ]+xtrn\+0xf+c[ ]* ++[0-9a-f]+[ ]+R_X86_64_PLT32[ ]+xtrn-0x0*4[ ]* + [0-9a-f]+[ ]+R_X86_64_GOT32[ ]+xtrn[ ]* +-[0-9a-f]+[ ]+R_X86_64_PLT32[ ]+xtrn\+0xf+c[ ]* ++[0-9a-f]+[ ]+R_X86_64_PLT32[ ]+xtrn-0x0*4[ ]* +--- binutils/gas/testsuite/gas/i386/reloc64.d.signed 2007-09-26 09:51:26.000000000 -0700 ++++ binutils/gas/testsuite/gas/i386/reloc64.d 2007-09-26 09:59:15.000000000 -0700 +@@ -16,33 +16,33 @@ Disassembly of section \.text: + .*[ ]+R_X86_64_PC32[ ]+xtrn\+0x0*2 + .*[ ]+R_X86_64_PC16[ ]+xtrn\+0x0*2 + .*[ ]+R_X86_64_PC8[ ]+xtrn\+0x0*1 +-.*[ ]+R_X86_64_PC32[ ]+xtrn\+0xf+c +-.*[ ]+R_X86_64_PC32[ ]+xtrn\+0xf+c +-.*[ ]+R_X86_64_PC32[ ]+xtrn\+0xf+c +-.*[ ]+R_X86_64_PC8[ ]+xtrn\+0xf+f ++.*[ ]+R_X86_64_PC32[ ]+xtrn-0x0*4 ++.*[ ]+R_X86_64_PC32[ ]+xtrn-0x0*4 ++.*[ ]+R_X86_64_PC32[ ]+xtrn-0x0*4 ++.*[ ]+R_X86_64_PC8[ ]+xtrn-0x0*1 + .*[ ]+R_X86_64_GOT64[ ]+xtrn + .*[ ]+R_X86_64_GOT32[ ]+xtrn + .*[ ]+R_X86_64_GOT32[ ]+xtrn + .*[ ]+R_X86_64_GOTOFF64[ ]+xtrn + .*[ ]+R_X86_64_GOTPCREL[ ]+xtrn + .*[ ]+R_X86_64_GOTPCREL[ ]+xtrn +-.*[ ]+R_X86_64_GOTPCREL[ ]+xtrn\+0xf+c ++.*[ ]+R_X86_64_GOTPCREL[ ]+xtrn-0x0*4 + .*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_\+0x0*2 +-.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_\+0xf+c +-.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_\+0xf+c ++.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_-0x0*4 ++.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_-0x0*4 + .*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_\+0x0*2 + .*[ ]+R_X86_64_PLT32[ ]+xtrn + .*[ ]+R_X86_64_PLT32[ ]+xtrn +-.*[ ]+R_X86_64_PLT32[ ]+xtrn\+0xf+c ++.*[ ]+R_X86_64_PLT32[ ]+xtrn-0x0*4 + .*[ ]+R_X86_64_TLSGD[ ]+xtrn + .*[ ]+R_X86_64_TLSGD[ ]+xtrn +-.*[ ]+R_X86_64_TLSGD[ ]+xtrn\+0xf+c ++.*[ ]+R_X86_64_TLSGD[ ]+xtrn-0x0*4 + .*[ ]+R_X86_64_GOTTPOFF[ ]+xtrn + .*[ ]+R_X86_64_GOTTPOFF[ ]+xtrn +-.*[ ]+R_X86_64_GOTTPOFF[ ]+xtrn\+0xf+c ++.*[ ]+R_X86_64_GOTTPOFF[ ]+xtrn-0x0*4 + .*[ ]+R_X86_64_TLSLD[ ]+xtrn + .*[ ]+R_X86_64_TLSLD[ ]+xtrn +-.*[ ]+R_X86_64_TLSLD[ ]+xtrn\+0xf+c ++.*[ ]+R_X86_64_TLSLD[ ]+xtrn-0x0*4 + .*[ ]+R_X86_64_DTPOFF64[ ]+xtrn + .*[ ]+R_X86_64_DTPOFF32[ ]+xtrn + .*[ ]+R_X86_64_DTPOFF32[ ]+xtrn +--- binutils/gas/testsuite/gas/ia64/pcrel.d.signed 2005-03-28 14:34:20.000000000 -0800 ++++ binutils/gas/testsuite/gas/ia64/pcrel.d 2007-09-26 09:51:38.000000000 -0700 +@@ -9,28 +9,28 @@ OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[ + 0+10[[:space:]]+PCREL22[[:space:]]+esym + 0+20[[:space:]]+PCREL22[[:space:]]+esym\+0x0+20 + 0+30[[:space:]]+PCREL22[[:space:]]+esym +-0+40[[:space:]]+PCREL22[[:space:]]+esym\+0xf+e0 ++0+40[[:space:]]+PCREL22[[:space:]]+esym-0x0+20 + + RELOCATION RECORDS FOR \[\.movl\]: + OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* + 0+12[[:space:]]+PCREL64I[[:space:]]+esym + 0+22[[:space:]]+PCREL64I[[:space:]]+esym\+0x0+20 + 0+32[[:space:]]+PCREL64I[[:space:]]+esym +-0+42[[:space:]]+PCREL64I[[:space:]]+esym\+0xf+e0 ++0+42[[:space:]]+PCREL64I[[:space:]]+esym-0x0+20 + + RELOCATION RECORDS FOR \[\.data8\]: + OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* + 0+10[[:space:]]+PCREL64[LM]SB[[:space:]]+esym + 0+20[[:space:]]+PCREL64[LM]SB[[:space:]]+esym\+0x0+20 + 0+30[[:space:]]+PCREL64[LM]SB[[:space:]]+esym +-0+40[[:space:]]+PCREL64[LM]SB[[:space:]]+esym\+0xf+e0 ++0+40[[:space:]]+PCREL64[LM]SB[[:space:]]+esym-0x0+20 + + RELOCATION RECORDS FOR \[\.data4\]: + OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* + 0+10[[:space:]]+PCREL32[LM]SB[[:space:]]+esym + 0+20[[:space:]]+PCREL32[LM]SB[[:space:]]+esym\+0x0+20 + 0+30[[:space:]]+PCREL32[LM]SB[[:space:]]+esym +-0+40[[:space:]]+PCREL32[LM]SB[[:space:]]+esym\+0xf+e0 ++0+40[[:space:]]+PCREL32[LM]SB[[:space:]]+esym-0x0+20 + + + Contents of section \.mov: +--- binutils/gas/testsuite/gas/mips/branch-misc-2-64.d.signed 2005-11-23 06:04:18.000000000 -0800 ++++ binutils/gas/testsuite/gas/mips/branch-misc-2-64.d 2007-09-26 09:51:38.000000000 -0700 +@@ -12,51 +12,51 @@ Disassembly of section .text: + \.\.\. + \.\.\. + 0+003c <[^>]*> 04110000 bal 0000000000000040 +-[ ]*3c: R_MIPS_PC16 g1\+0xfffffffffffffffc +-[ ]*3c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*3c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*3c: R_MIPS_PC16 g1-0x4 ++[ ]*3c: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*3c: R_MIPS_NONE \*ABS\*-0x4 + 0+0040 <[^>]*> 00000000 nop + 0+0044 <[^>]*> 04110000 bal 0000000000000048 +-[ ]*44: R_MIPS_PC16 g2\+0xfffffffffffffffc +-[ ]*44: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*44: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*44: R_MIPS_PC16 g2-0x4 ++[ ]*44: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*44: R_MIPS_NONE \*ABS\*-0x4 + 0+0048 <[^>]*> 00000000 nop + 0+004c <[^>]*> 04110000 bal 0000000000000050 +-[ ]*4c: R_MIPS_PC16 g3\+0xfffffffffffffffc +-[ ]*4c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*4c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*4c: R_MIPS_PC16 g3-0x4 ++[ ]*4c: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*4c: R_MIPS_NONE \*ABS\*-0x4 + 0+0050 <[^>]*> 00000000 nop + 0+0054 <[^>]*> 04110000 bal 0000000000000058 +-[ ]*54: R_MIPS_PC16 g4\+0xfffffffffffffffc +-[ ]*54: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*54: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*54: R_MIPS_PC16 g4-0x4 ++[ ]*54: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*54: R_MIPS_NONE \*ABS\*-0x4 + 0+0058 <[^>]*> 00000000 nop + 0+005c <[^>]*> 04110000 bal 0000000000000060 +-[ ]*5c: R_MIPS_PC16 g5\+0xfffffffffffffffc +-[ ]*5c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*5c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*5c: R_MIPS_PC16 g5-0x4 ++[ ]*5c: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*5c: R_MIPS_NONE \*ABS\*-0x4 + 0+0060 <[^>]*> 00000000 nop + 0+0064 <[^>]*> 04110000 bal 0000000000000068 +-[ ]*64: R_MIPS_PC16 g6\+0xfffffffffffffffc +-[ ]*64: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*64: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*64: R_MIPS_PC16 g6-0x4 ++[ ]*64: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*64: R_MIPS_NONE \*ABS\*-0x4 + 0+0068 <[^>]*> 00000000 nop + \.\.\. + \.\.\. + \.\.\. + 0+00a8 <[^>]*> 10000000 b 00000000000000ac +-[ ]*a8: R_MIPS_PC16 x1\+0xfffffffffffffffc +-[ ]*a8: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*a8: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*a8: R_MIPS_PC16 x1-0x4 ++[ ]*a8: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*a8: R_MIPS_NONE \*ABS\*-0x4 + 0+00ac <[^>]*> 00000000 nop + 0+00b0 <[^>]*> 10000000 b 00000000000000b4 +-[ ]*b0: R_MIPS_PC16 x2\+0xfffffffffffffffc +-[ ]*b0: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*b0: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*b0: R_MIPS_PC16 x2-0x4 ++[ ]*b0: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*b0: R_MIPS_NONE \*ABS\*-0x4 + 0+00b4 <[^>]*> 00000000 nop + 0+00b8 <[^>]*> 10000000 b 00000000000000bc +-[ ]*b8: R_MIPS_PC16 \.data\+0xfffffffffffffffc +-[ ]*b8: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*b8: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*b8: R_MIPS_PC16 \.data-0x4 ++[ ]*b8: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*b8: R_MIPS_NONE \*ABS\*-0x4 + 0+00bc <[^>]*> 00000000 nop + \.\.\. +--- binutils/gas/testsuite/gas/mips/branch-misc-2pic-64.d.signed 2005-11-23 06:04:18.000000000 -0800 ++++ binutils/gas/testsuite/gas/mips/branch-misc-2pic-64.d 2007-09-26 09:51:38.000000000 -0700 +@@ -12,51 +12,51 @@ Disassembly of section .text: + \.\.\. + \.\.\. + 0+003c <[^>]*> 04110000 bal 0000000000000040 +-[ ]*3c: R_MIPS_PC16 g1\+0xfffffffffffffffc +-[ ]*3c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*3c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*3c: R_MIPS_PC16 g1-0x4 ++[ ]*3c: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*3c: R_MIPS_NONE \*ABS\*-0x4 + 0+0040 <[^>]*> 00000000 nop + 0+0044 <[^>]*> 04110000 bal 0000000000000048 +-[ ]*44: R_MIPS_PC16 g2\+0xfffffffffffffffc +-[ ]*44: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*44: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*44: R_MIPS_PC16 g2-0x4 ++[ ]*44: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*44: R_MIPS_NONE \*ABS\*-0x4 + 0+0048 <[^>]*> 00000000 nop + 0+004c <[^>]*> 04110000 bal 0000000000000050 +-[ ]*4c: R_MIPS_PC16 g3\+0xfffffffffffffffc +-[ ]*4c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*4c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*4c: R_MIPS_PC16 g3-0x4 ++[ ]*4c: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*4c: R_MIPS_NONE \*ABS\*-0x4 + 0+0050 <[^>]*> 00000000 nop + 0+0054 <[^>]*> 04110000 bal 0000000000000058 +-[ ]*54: R_MIPS_PC16 g4\+0xfffffffffffffffc +-[ ]*54: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*54: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*54: R_MIPS_PC16 g4-0x4 ++[ ]*54: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*54: R_MIPS_NONE \*ABS\*-0x4 + 0+0058 <[^>]*> 00000000 nop + 0+005c <[^>]*> 04110000 bal 0000000000000060 +-[ ]*5c: R_MIPS_PC16 g5\+0xfffffffffffffffc +-[ ]*5c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*5c: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*5c: R_MIPS_PC16 g5-0x4 ++[ ]*5c: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*5c: R_MIPS_NONE \*ABS\*-0x4 + 0+0060 <[^>]*> 00000000 nop + 0+0064 <[^>]*> 04110000 bal 0000000000000068 +-[ ]*64: R_MIPS_PC16 g6\+0xfffffffffffffffc +-[ ]*64: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*64: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*64: R_MIPS_PC16 g6-0x4 ++[ ]*64: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*64: R_MIPS_NONE \*ABS\*-0x4 + 0+0068 <[^>]*> 00000000 nop + \.\.\. + \.\.\. + \.\.\. + 0+00a8 <[^>]*> 10000000 b 00000000000000ac +-[ ]*a8: R_MIPS_PC16 x1\+0xfffffffffffffffc +-[ ]*a8: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*a8: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*a8: R_MIPS_PC16 x1-0x4 ++[ ]*a8: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*a8: R_MIPS_NONE \*ABS\*-0x4 + 0+00ac <[^>]*> 00000000 nop + 0+00b0 <[^>]*> 10000000 b 00000000000000b4 +-[ ]*b0: R_MIPS_PC16 x2\+0xfffffffffffffffc +-[ ]*b0: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*b0: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*b0: R_MIPS_PC16 x2-0x4 ++[ ]*b0: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*b0: R_MIPS_NONE \*ABS\*-0x4 + 0+00b4 <[^>]*> 00000000 nop + 0+00b8 <[^>]*> 10000000 b 00000000000000bc +-[ ]*b8: R_MIPS_PC16 \.data\+0xfffffffffffffffc +-[ ]*b8: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc +-[ ]*b8: R_MIPS_NONE \*ABS\*\+0xfffffffffffffffc ++[ ]*b8: R_MIPS_PC16 \.data-0x4 ++[ ]*b8: R_MIPS_NONE \*ABS\*-0x4 ++[ ]*b8: R_MIPS_NONE \*ABS\*-0x4 + 0+00bc <[^>]*> 00000000 nop + \.\.\. +--- binutils/gas/testsuite/gas/mips/ldstla-n64-sym32.d.signed 2005-03-04 01:51:11.000000000 -0800 ++++ binutils/gas/testsuite/gas/mips/ldstla-n64-sym32.d 2007-09-26 09:51:38.000000000 -0700 +@@ -196,19 +196,19 @@ Disassembly .*: + .*: R_MIPS_NONE .* + .* daddu a0,a0,v1 + .* lui a0,0x0 +-.*: R_MIPS_HI16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_HI16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* d?addiu a0,a0,0 +-.*: R_MIPS_LO16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_LO16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* lui a0,0x0 +-.*: R_MIPS_HI16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_HI16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* d?addiu a0,a0,0 +-.*: R_MIPS_LO16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_LO16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* daddu a0,a0,v1 +@@ -406,20 +406,20 @@ Disassembly .*: + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* lui a0,0x0 +-.*: R_MIPS_HI16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_HI16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* lw a0,0\(a0\) +-.*: R_MIPS_LO16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_LO16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* lui a0,0x0 +-.*: R_MIPS_HI16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_HI16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* daddu a0,a0,v1 + .* lw a0,0\(a0\) +-.*: R_MIPS_LO16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_LO16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + # +@@ -616,20 +616,20 @@ Disassembly .*: + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* lui at,0x0 +-.*: R_MIPS_HI16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_HI16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* sw a0,0\(at\) +-.*: R_MIPS_LO16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_LO16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* lui at,0x0 +-.*: R_MIPS_HI16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_HI16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* daddu at,at,v1 + .* sw a0,0\(at\) +-.*: R_MIPS_LO16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_LO16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + # +@@ -880,21 +880,21 @@ Disassembly .*: + .* swl a0,0\(at\) + .* swr a0,3\(at\) + .* lui at,0x0 +-.*: R_MIPS_HI16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_HI16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* d?addiu at,at,0 +-.*: R_MIPS_LO16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_LO16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* swl a0,0\(at\) + .* swr a0,3\(at\) + .* lui at,0x0 +-.*: R_MIPS_HI16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_HI16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* d?addiu at,at,0 +-.*: R_MIPS_LO16 extern\+0xfffffffffffcc000 ++.*: R_MIPS_LO16 extern-0x34000 + .*: R_MIPS_NONE .* + .*: R_MIPS_NONE .* + .* daddu at,at,v1 +--- binutils/gas/testsuite/gas/mips/mips16-hilo-n32.d.signed 2005-02-15 11:57:53.000000000 -0800 ++++ binutils/gas/testsuite/gas/mips/mips16-hilo-n32.d 2007-09-26 09:51:38.000000000 -0700 +@@ -141,45 +141,45 @@ Disassembly of section \.text: + 13c: f400 3480 sll a0,16 + 140: f010 4c00 addiu a0,-32768 + 144: f000 6c00 li a0,0 +- 144: R_MIPS16_HI16 \.data\+0xffff8000 ++ 144: R_MIPS16_HI16 \.data-0x8000 + 148: f400 3480 sll a0,16 + 14c: f000 4c00 addiu a0,0 +- 14c: R_MIPS16_LO16 \.data\+0xffff8000 ++ 14c: R_MIPS16_LO16 \.data-0x8000 + 150: f000 6c00 li a0,0 +- 150: R_MIPS16_HI16 \.data\+0xffff8004 ++ 150: R_MIPS16_HI16 \.data-0x7ffc + 154: f400 3480 sll a0,16 + 158: f000 4c00 addiu a0,0 +- 158: R_MIPS16_LO16 \.data\+0xffff8004 ++ 158: R_MIPS16_LO16 \.data-0x7ffc + 15c: f000 6c00 li a0,0 +- 15c: R_MIPS16_HI16 big_external_data_label\+0xffff8000 ++ 15c: R_MIPS16_HI16 big_external_data_label-0x8000 + 160: f400 3480 sll a0,16 + 164: f000 4c00 addiu a0,0 +- 164: R_MIPS16_LO16 big_external_data_label\+0xffff8000 ++ 164: R_MIPS16_LO16 big_external_data_label-0x8000 + 168: f000 6c00 li a0,0 +- 168: R_MIPS16_HI16 small_external_data_label\+0xffff8000 ++ 168: R_MIPS16_HI16 small_external_data_label-0x8000 + 16c: f400 3480 sll a0,16 + 170: f000 4c00 addiu a0,0 +- 170: R_MIPS16_LO16 small_external_data_label\+0xffff8000 ++ 170: R_MIPS16_LO16 small_external_data_label-0x8000 + 174: f000 6c00 li a0,0 +- 174: R_MIPS16_HI16 big_external_common\+0xffff8000 ++ 174: R_MIPS16_HI16 big_external_common-0x8000 + 178: f400 3480 sll a0,16 + 17c: f000 4c00 addiu a0,0 +- 17c: R_MIPS16_LO16 big_external_common\+0xffff8000 ++ 17c: R_MIPS16_LO16 big_external_common-0x8000 + 180: f000 6c00 li a0,0 +- 180: R_MIPS16_HI16 small_external_common\+0xffff8000 ++ 180: R_MIPS16_HI16 small_external_common-0x8000 + 184: f400 3480 sll a0,16 + 188: f000 4c00 addiu a0,0 +- 188: R_MIPS16_LO16 small_external_common\+0xffff8000 ++ 188: R_MIPS16_LO16 small_external_common-0x8000 + 18c: f000 6c00 li a0,0 +- 18c: R_MIPS16_HI16 \.bss\+0xffff8000 ++ 18c: R_MIPS16_HI16 \.bss-0x8000 + 190: f400 3480 sll a0,16 + 194: f000 4c00 addiu a0,0 +- 194: R_MIPS16_LO16 \.bss\+0xffff8000 ++ 194: R_MIPS16_LO16 \.bss-0x8000 + 198: f000 6c00 li a0,0 +- 198: R_MIPS16_HI16 \.sbss\+0xffff8000 ++ 198: R_MIPS16_HI16 \.sbss-0x8000 + 19c: f400 3480 sll a0,16 + 1a0: f000 4c00 addiu a0,0 +- 1a0: R_MIPS16_LO16 \.sbss\+0xffff8000 ++ 1a0: R_MIPS16_LO16 \.sbss-0x8000 + 1a4: 6c01 li a0,1 + 1a6: f400 3480 sll a0,16 + 1aa: 4c00 addiu a0,0 +@@ -399,45 +399,45 @@ Disassembly of section \.text: + 3b4: f400 35a0 sll a1,16 + 3b8: f010 9d80 lw a0,-32768\(a1\) + 3bc: f000 6d00 li a1,0 +- 3bc: R_MIPS16_HI16 \.data\+0xffff8000 ++ 3bc: R_MIPS16_HI16 \.data-0x8000 + 3c0: f400 35a0 sll a1,16 + 3c4: f000 9d80 lw a0,0\(a1\) +- 3c4: R_MIPS16_LO16 \.data\+0xffff8000 ++ 3c4: R_MIPS16_LO16 \.data-0x8000 + 3c8: f000 6d00 li a1,0 +- 3c8: R_MIPS16_HI16 \.data\+0xffff8004 ++ 3c8: R_MIPS16_HI16 \.data-0x7ffc + 3cc: f400 35a0 sll a1,16 + 3d0: f000 9d80 lw a0,0\(a1\) +- 3d0: R_MIPS16_LO16 \.data\+0xffff8004 ++ 3d0: R_MIPS16_LO16 \.data-0x7ffc + 3d4: f000 6d00 li a1,0 +- 3d4: R_MIPS16_HI16 big_external_data_label\+0xffff8000 ++ 3d4: R_MIPS16_HI16 big_external_data_label-0x8000 + 3d8: f400 35a0 sll a1,16 + 3dc: f000 9d80 lw a0,0\(a1\) +- 3dc: R_MIPS16_LO16 big_external_data_label\+0xffff8000 ++ 3dc: R_MIPS16_LO16 big_external_data_label-0x8000 + 3e0: f000 6d00 li a1,0 +- 3e0: R_MIPS16_HI16 small_external_data_label\+0xffff8000 ++ 3e0: R_MIPS16_HI16 small_external_data_label-0x8000 + 3e4: f400 35a0 sll a1,16 + 3e8: f000 9d80 lw a0,0\(a1\) +- 3e8: R_MIPS16_LO16 small_external_data_label\+0xffff8000 ++ 3e8: R_MIPS16_LO16 small_external_data_label-0x8000 + 3ec: f000 6d00 li a1,0 +- 3ec: R_MIPS16_HI16 big_external_common\+0xffff8000 ++ 3ec: R_MIPS16_HI16 big_external_common-0x8000 + 3f0: f400 35a0 sll a1,16 + 3f4: f000 9d80 lw a0,0\(a1\) +- 3f4: R_MIPS16_LO16 big_external_common\+0xffff8000 ++ 3f4: R_MIPS16_LO16 big_external_common-0x8000 + 3f8: f000 6d00 li a1,0 +- 3f8: R_MIPS16_HI16 small_external_common\+0xffff8000 ++ 3f8: R_MIPS16_HI16 small_external_common-0x8000 + 3fc: f400 35a0 sll a1,16 + 400: f000 9d80 lw a0,0\(a1\) +- 400: R_MIPS16_LO16 small_external_common\+0xffff8000 ++ 400: R_MIPS16_LO16 small_external_common-0x8000 + 404: f000 6d00 li a1,0 +- 404: R_MIPS16_HI16 \.bss\+0xffff8000 ++ 404: R_MIPS16_HI16 \.bss-0x8000 + 408: f400 35a0 sll a1,16 + 40c: f000 9d80 lw a0,0\(a1\) +- 40c: R_MIPS16_LO16 \.bss\+0xffff8000 ++ 40c: R_MIPS16_LO16 \.bss-0x8000 + 410: f000 6d00 li a1,0 +- 410: R_MIPS16_HI16 \.sbss\+0xffff8000 ++ 410: R_MIPS16_HI16 \.sbss-0x8000 + 414: f400 35a0 sll a1,16 + 418: f000 9d80 lw a0,0\(a1\) +- 418: R_MIPS16_LO16 \.sbss\+0xffff8000 ++ 418: R_MIPS16_LO16 \.sbss-0x8000 + 41c: 6d01 li a1,1 + 41e: f400 35a0 sll a1,16 + 422: 9d80 lw a0,0\(a1\) +--- binutils/gas/testsuite/gas/ppc/astest.d.signed 2005-03-02 05:25:01.000000000 -0800 ++++ binutils/gas/testsuite/gas/ppc/astest.d 2007-09-26 09:51:38.000000000 -0700 +@@ -52,11 +52,11 @@ Disassembly of section \.text: + 60: 00 00 00 00 \.long 0x0 + 60: R_PPC_ADDR32 z + 64: ff ff ff fc fnmsub f31,f31,f31,f31 +- 64: R_PPC_ADDR32 x\+0xf+ffffffc ++ 64: R_PPC_ADDR32 x-0x4 + 68: 00 00 00 00 \.long 0x0 + 68: R_PPC_ADDR32 \.data + 6c: ff ff ff fc fnmsub f31,f31,f31,f31 +- 6c: R_PPC_ADDR32 z\+0xf+ffffffc ++ 6c: R_PPC_ADDR32 z-0x4 + 70: ff ff ff 9c \.long 0xffffff9c + 74: ff ff ff 9c \.long 0xffffff9c + 78: 00 00 00 00 \.long 0x0 +--- binutils/gas/testsuite/gas/ppc/astest2.d.signed 2005-03-02 05:25:01.000000000 -0800 ++++ binutils/gas/testsuite/gas/ppc/astest2.d 2007-09-26 09:51:38.000000000 -0700 +@@ -48,11 +48,11 @@ Disassembly of section \.text: + 60: 00 00 00 00 \.long 0x0 + 60: R_PPC_ADDR32 z + 64: ff ff ff fc fnmsub f31,f31,f31,f31 +- 64: R_PPC_ADDR32 x\+0xf+ffffffc ++ 64: R_PPC_ADDR32 x-0x4 + 68: 00 00 00 00 \.long 0x0 + 68: R_PPC_ADDR32 \.data + 6c: ff ff ff fc fnmsub f31,f31,f31,f31 +- 6c: R_PPC_ADDR32 z\+0xf+ffffffc ++ 6c: R_PPC_ADDR32 z-0x4 + 70: 00 00 00 08 \.long 0x8 + 74: 00 00 00 08 \.long 0x8 + +--- binutils/gas/testsuite/gas/ppc/astest2_64.d.signed 2005-03-02 05:25:01.000000000 -0800 ++++ binutils/gas/testsuite/gas/ppc/astest2_64.d 2007-09-26 09:51:38.000000000 -0700 +@@ -45,11 +45,11 @@ Disassembly of section \.text: + 58: 00 00 00 00 \.long 0x0 + 58: R_PPC64_ADDR32 z + 5c: ff ff ff fc fnmsub f31,f31,f31,f31 +- 5c: R_PPC64_ADDR32 x\+0xfffffffffffffffc ++ 5c: R_PPC64_ADDR32 x-0x4 + 60: 00 00 00 00 \.long 0x0 + 60: R_PPC64_ADDR32 \.data + 64: ff ff ff fc fnmsub f31,f31,f31,f31 +- 64: R_PPC64_ADDR32 z\+0xfffffffffffffffc ++ 64: R_PPC64_ADDR32 z-0x4 + 68: 00 00 00 08 \.long 0x8 + 6c: 00 00 00 08 \.long 0x8 + +--- binutils/gas/testsuite/gas/ppc/astest64.d.signed 2005-03-02 05:25:01.000000000 -0800 ++++ binutils/gas/testsuite/gas/ppc/astest64.d 2007-09-26 09:51:38.000000000 -0700 +@@ -49,11 +49,11 @@ Disassembly of section \.text: + 58: 00 00 00 00 \.long 0x0 + 58: R_PPC64_ADDR32 z + 5c: ff ff ff fc fnmsub f31,f31,f31,f31 +- 5c: R_PPC64_ADDR32 x\+0xfffffffffffffffc ++ 5c: R_PPC64_ADDR32 x-0x4 + 60: 00 00 00 00 \.long 0x0 + 60: R_PPC64_ADDR32 \.data + 64: ff ff ff fc fnmsub f31,f31,f31,f31 +- 64: R_PPC64_ADDR32 z\+0xfffffffffffffffc ++ 64: R_PPC64_ADDR32 z-0x4 + 68: ff ff ff a4 \.long 0xffffffa4 + 6c: ff ff ff a4 \.long 0xffffffa4 + 70: 00 00 00 00 \.long 0x0 +--- binutils/gas/testsuite/gas/ppc/test1elf32.d.signed 2005-03-02 05:25:01.000000000 -0800 ++++ binutils/gas/testsuite/gas/ppc/test1elf32.d 2007-09-26 09:51:38.000000000 -0700 +@@ -79,7 +79,7 @@ Disassembly of section \.data: + + 0+000c : + c: ff ff ff fc fnmsub f31,f31,f31,f31 +- c: R_PPC_REL32 jk\+0xf+fffc ++ c: R_PPC_REL32 jk-0x4 + + 0+0010 : + 10: 00 00 00 00 \.long 0x0 +--- binutils/gas/testsuite/gas/ppc/test1elf64.d.signed 2005-03-02 05:25:01.000000000 -0800 ++++ binutils/gas/testsuite/gas/ppc/test1elf64.d 2007-09-26 09:51:38.000000000 -0700 +@@ -114,7 +114,7 @@ Disassembly of section \.data: + + 0000000000000014 : + 14: ff ff ff fc fnmsub f31,f31,f31,f31 +- 14: R_PPC64_REL32 jk\+0xfffffffffffffffc ++ 14: R_PPC64_REL32 jk-0x4 + + 0000000000000018 : + 18: 00 00 00 00 \.long 0x0 +--- binutils/gas/testsuite/gas/sparc/reloc64.d.signed 1999-06-10 14:08:04.000000000 -0700 ++++ binutils/gas/testsuite/gas/sparc/reloc64.d 2007-09-26 09:51:38.000000000 -0700 +@@ -35,13 +35,13 @@ Disassembly of section .text: + 44: R_SPARC_LO10 .text + 48: 01 00 00 00 nop + 4c: 03 00 00 00 sethi %hi\((0x|)0\), %g1 +- 4c: R_SPARC_HH22 .text\+0xfedcba9876543210 ++ 4c: R_SPARC_HH22 .text\-0x123456789abcdf0 + 50: 82 10 60 00 mov %g1, %g1 ! 0 +- 50: R_SPARC_HM10 .text\+0xfedcba9876543210 ++ 50: R_SPARC_HM10 .text\-0x123456789abcdf0 + 54: 05 00 00 00 sethi %hi\((0x|)0\), %g2 +- 54: R_SPARC_LM22 .text\+0xfedcba9876543210 ++ 54: R_SPARC_LM22 .text\-0x123456789abcdf0 + 58: 84 10 60 00 mov %g1, %g2 +- 58: R_SPARC_LO10 .text\+0xfedcba9876543210 ++ 58: R_SPARC_LO10 .text\-0x123456789abcdf0 + 5c: 01 00 00 00 nop + 60: 03 2a 61 d9 sethi %hi\(0xa9876400\), %g1 + 64: 82 10 61 43 or %g1, 0x143, %g1.* +@@ -70,7 +70,7 @@ Disassembly of section .text: + a0: R_SPARC_LOX10 .text + a4: 01 00 00 00 nop + a8: 03 00 00 00 sethi %hi\((0x|)0\), %g1 +- a8: R_SPARC_HIX22 .text\+0xffffffff76543210 ++ a8: R_SPARC_HIX22 .text-0x89abcdf0 + ac: 82 18 60 00 xor %g1, 0, %g1 +- ac: R_SPARC_LOX10 .text\+0xffffffff76543210 ++ ac: R_SPARC_LOX10 .text-0x89abcdf0 + b0: 01 00 00 00 nop --- binutils-2.20.orig/debian/patches/128_build_id.dpatch +++ binutils-2.20/debian/patches/128_build_id.dpatch @@ -0,0 +1,64 @@ +#!/bin/sh -e +## 128_build_id.dpatch +## +## DP: Description: Fix ld corrupt build ID generation +## DP: Author: Nick Clifton +## DP: Upstream status: Taken from Fedora (BZ 501582) + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +--- ./bfd/section.c.orig 2009-09-09 23:40:20.000000000 +0200 ++++ ./bfd/section.c 2009-09-10 17:09:57.000000000 +0200 +@@ -1496,7 +1496,7 @@ + return TRUE; + + p = (bfd_byte *) +- bfd_malloc (sec->rawsize > sec->size ? sec->rawsize : sec->size); ++ bfd_zmalloc (sec->rawsize > sec->size ? sec->rawsize : sec->size); + if (p == NULL) + return FALSE; + *buf = p; +--- ./bfd/elfcode.h.orig 2009-09-09 23:40:19.000000000 +0200 ++++ ./bfd/elfcode.h 2009-09-10 17:08:49.000000000 +0200 +@@ -1139,6 +1139,24 @@ + + if (i_shdr.contents) + (*process) (i_shdr.contents, i_shdr.sh_size, arg); ++ else ++ { ++ asection *sec; ++ ++ sec = bfd_section_from_elf_index (abfd, count); ++ if (sec != NULL) ++ { ++ if (sec->contents == NULL) ++ { ++ /* Force rereading from file. */ ++ sec->flags &= ~SEC_IN_MEMORY; ++ if (! bfd_malloc_and_get_section (abfd, sec, & sec->contents)) ++ continue; ++ } ++ if (sec->contents != NULL) ++ (*process) (sec->contents, i_shdr.sh_size, arg); ++ } ++ } + } + + return TRUE; --- binutils-2.20.orig/debian/patches/006_better_file_error.dpatch +++ binutils-2.20/debian/patches/006_better_file_error.dpatch @@ -0,0 +1,43 @@ +#!/bin/sh -e +## 006_better_file_error.dpatch by David Kimdon +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: Specify which filename is causing an error if the filename is a +## DP: directory. (#45832) + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +diff -urNad /home/james/debian/packages/binutils/binutils-2.14.90.0.6/bfd/opncls.c binutils-2.14.90.0.6/bfd/opncls.c +--- /home/james/debian/packages/binutils/binutils-2.14.90.0.6/bfd/opncls.c 2003-07-23 16:08:09.000000000 +0100 ++++ binutils-2.14.90.0.6/bfd/opncls.c 2003-09-10 22:35:00.000000000 +0100 +@@ -150,6 +150,13 @@ + { + bfd *nbfd; + const bfd_target *target_vec; ++ struct stat s; ++ ++ if (stat (filename, &s) == 0) ++ if (S_ISDIR(s.st_mode)) { ++ bfd_set_error (bfd_error_file_not_recognized); ++ return NULL; ++ } + + nbfd = _bfd_new_bfd (); + if (nbfd == NULL) --- binutils-2.20.orig/debian/patches/213-hjl-binutils-sec64k.dpatch +++ binutils-2.20/debian/patches/213-hjl-binutils-sec64k.dpatch @@ -0,0 +1,523 @@ +#!/bin/sh -e +## 213-hjl-binutils-sec64k.dpatch +## +## DP: Description: Proposed patch for PR binutils/6412 +## DP: Author: H.J. Lu +## DP: Upstream status: hjl 2.20.51.0.1 +## DP: Original patch: binutils-sec64k-6.patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +bfd/ + +2008-04-21 H.J. Lu + + PR binutils/6412 + * bfd.c (bfd): Add has_gap_in_elf_shndx. + * bfd-in2.h: Regenerated. + + * bfd-in.h (bfd_has_gap_in_elf_shndx): New. + + * elf.c (setup_group): Handle gap in section indices. + * elfcode.h (elf_swap_symbol_in): Likewise. + (elf_object_p): Likewise. Use %B where reporting corrupt + string table index. + +include/elf/ + +2008-04-21 H.J. Lu + + PR binutils/6412 + * internal.h (ELF_SECTION_HEADER_INDEX_GAP): New. + +2008-04-21 H.J. Lu + + PR binutils/6412 + * readelf.c (hole_in_shndx): New. + (original_shndx_info): Likewise. + (original_shndx): Likewise. + (process_file_header): Move ELF magic bytes check to ... + (get_file_header): Here. + (get_32bit_section_headers): Set hole_in_shndx if sh_link + >= number of sections. + (get_64bit_section_headers): Likewise. + (get_32bit_elf_symbols): Adjust st_shndx if hole_in_shndx + isn't 0. + (get_64bit_elf_symbols): Likewise. + (process_section_headers): Adjust elf_header.e_shstrndx, + sh_link and sh_info, save original sh_link and sh_info, + display adjustment for sh_link and sh_info if hole_in_shndx + isn't 0. + (process_section_groups): Adjust member section index if + hole_in_shndx isn't 0. + (process_object): Free original_shndx if needed. + +@DPATCH@ +--- binutils/bfd/bfd-in.h.sec64k 2009-09-04 17:51:38.000000000 -0700 ++++ binutils/bfd/bfd-in.h 2009-09-10 09:47:27.000000000 -0700 +@@ -497,6 +497,7 @@ extern void warn_deprecated (const char + #define bfd_my_archive(abfd) ((abfd)->my_archive) + #define bfd_has_map(abfd) ((abfd)->has_armap) + #define bfd_is_thin_archive(abfd) ((abfd)->is_thin_archive) ++#define bfd_has_gap_in_elf_shndx(abfd) ((abfd)->has_gap_in_elf_shndx) + + #define bfd_valid_reloc_types(abfd) ((abfd)->xvec->valid_reloc_types) + #define bfd_usrdata(abfd) ((abfd)->usrdata) +--- binutils/bfd/bfd-in2.h.sec64k 2009-09-10 09:29:36.000000000 -0700 ++++ binutils/bfd/bfd-in2.h 2009-09-10 09:47:27.000000000 -0700 +@@ -504,6 +504,7 @@ extern void warn_deprecated (const char + #define bfd_my_archive(abfd) ((abfd)->my_archive) + #define bfd_has_map(abfd) ((abfd)->has_armap) + #define bfd_is_thin_archive(abfd) ((abfd)->is_thin_archive) ++#define bfd_has_gap_in_elf_shndx(abfd) ((abfd)->has_gap_in_elf_shndx) + + #define bfd_valid_reloc_types(abfd) ((abfd)->xvec->valid_reloc_types) + #define bfd_usrdata(abfd) ((abfd)->usrdata) +@@ -5034,6 +5035,9 @@ struct bfd + + /* Set if this is a thin archive. */ + unsigned int is_thin_archive : 1; ++ ++ /* Set if there is a gap in ELF section index. */ ++ unsigned int has_gap_in_elf_shndx : 1; + }; + + typedef enum bfd_error +--- binutils/bfd/bfd.c.sec64k 2009-09-10 09:29:40.000000000 -0700 ++++ binutils/bfd/bfd.c 2009-09-10 09:47:27.000000000 -0700 +@@ -286,6 +286,9 @@ CODE_FRAGMENT + . + . {* Set if this is a thin archive. *} + . unsigned int is_thin_archive : 1; ++. ++. {* Set if there is a gap in ELF section index. *} ++. unsigned int has_gap_in_elf_shndx : 1; + .}; + . + */ +--- binutils/bfd/elf.c.sec64k 2009-09-10 09:47:27.000000000 -0700 ++++ binutils/bfd/elf.c 2009-09-10 09:47:27.000000000 -0700 +@@ -627,6 +627,12 @@ setup_group (bfd *abfd, Elf_Internal_Shd + |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD; + break; + } ++ ++ /* Handle gap in section indices. */ ++ if (bfd_has_gap_in_elf_shndx (abfd) ++ && idx > (SHN_HIRESERVE & 0xffff)) ++ idx -= ELF_SECTION_HEADER_INDEX_GAP; ++ + if (idx >= shnum) + { + ((*_bfd_error_handler) +--- binutils/bfd/elfcode.h.sec64k 2009-09-10 09:47:27.000000000 -0700 ++++ binutils/bfd/elfcode.h 2009-09-10 09:47:27.000000000 -0700 +@@ -194,6 +194,10 @@ elf_swap_symbol_in (bfd *abfd, + if (shndx == NULL) + return FALSE; + dst->st_shndx = H_GET_32 (abfd, shndx->est_shndx); ++ /* Handle gap in section indices. */ ++ if (bfd_has_gap_in_elf_shndx (abfd) ++ && dst->st_shndx > (SHN_HIRESERVE & 0xffff)) ++ dst->st_shndx -= ELF_SECTION_HEADER_INDEX_GAP; + } + else if (dst->st_shndx >= (SHN_LORESERVE & 0xffff)) + dst->st_shndx += SHN_LORESERVE - (SHN_LORESERVE & 0xffff); +@@ -800,6 +804,28 @@ elf_object_p (bfd *abfd) + != 0)) + abfd->flags &= ~D_PAGED; + } ++ ++ /* To support files generated by the older linker, we adjust ++ section indices if there is a gap. */ ++ if (bfd_has_gap_in_elf_shndx (abfd)) ++ { ++ BFD_ASSERT (i_ehdrp->e_shstrndx == i_shdrp->sh_link); ++ ++ for (; num_sec > 0; num_sec--, i_shdrp++) ++ { ++ if (i_shdrp->sh_link > (SHN_HIRESERVE & 0xffff)) ++ i_shdrp->sh_link -= ELF_SECTION_HEADER_INDEX_GAP; ++ ++ if (i_shdrp->sh_info > (SHN_HIRESERVE & 0xffff) ++ && ((i_shdrp->sh_flags & SHF_INFO_LINK) ++ || i_shdrp->sh_type == SHT_RELA ++ || i_shdrp->sh_type == SHT_REL)) ++ i_shdrp->sh_info -= ELF_SECTION_HEADER_INDEX_GAP; ++ } ++ ++ if (i_ehdrp->e_shstrndx > (SHN_HIRESERVE & 0xffff)) ++ i_ehdrp->e_shstrndx -= ELF_SECTION_HEADER_INDEX_GAP; ++ } + } + + /* A further sanity check. */ +@@ -814,7 +840,8 @@ elf_object_p (bfd *abfd) + So we are kind, and reset the string index value to 0 + so that at least some processing can be done. */ + i_ehdrp->e_shstrndx = SHN_UNDEF; +- _bfd_error_handler (_("warning: %s has a corrupt string table index - ignoring"), abfd->filename); ++ _bfd_error_handler (_("warning: %B has a corrupt string table index - ignoring"), ++ abfd); + } + } + else if (i_ehdrp->e_shstrndx != SHN_UNDEF) +--- binutils/binutils/readelf.c.sec64k 2009-09-10 09:47:25.000000000 -0700 ++++ binutils/binutils/readelf.c 2009-09-10 10:05:27.000000000 -0700 +@@ -193,6 +193,15 @@ static int do_notes; + static int do_archive_index; + static int is_32bit_elf; + ++struct original_shndx_info ++{ ++ unsigned int sh_link; ++ unsigned int sh_info; ++}; ++static struct original_shndx_info *original_shndx; ++/* The largest section index in sh_link if it isn't 0. */ ++static unsigned int hole_in_shndx; ++ + struct group_list + { + struct group_list * next; +@@ -3198,16 +3207,6 @@ get_data_encoding (unsigned int encoding + static int + process_file_header (void) + { +- if ( elf_header.e_ident[EI_MAG0] != ELFMAG0 +- || elf_header.e_ident[EI_MAG1] != ELFMAG1 +- || elf_header.e_ident[EI_MAG2] != ELFMAG2 +- || elf_header.e_ident[EI_MAG3] != ELFMAG3) +- { +- error +- (_("Not an ELF file - it has the wrong magic bytes at the start\n")); +- return 0; +- } +- + init_dwarf_regnames (elf_header.e_machine); + + if (do_header) +@@ -3694,6 +3693,10 @@ get_32bit_section_headers (FILE * file, + internal->sh_info = BYTE_GET (shdrs[i].sh_info); + internal->sh_addralign = BYTE_GET (shdrs[i].sh_addralign); + internal->sh_entsize = BYTE_GET (shdrs[i].sh_entsize); ++ /* The older linker generates section header indices with ++ hole. */ ++ if (i > 0 && internal->sh_link >= elf_header.e_shnum) ++ hole_in_shndx = internal->sh_link; + } + + free (shdrs); +@@ -3737,6 +3740,10 @@ get_64bit_section_headers (FILE * file, + internal->sh_info = BYTE_GET (shdrs[i].sh_info); + internal->sh_offset = BYTE_GET (shdrs[i].sh_offset); + internal->sh_addralign = BYTE_GET (shdrs[i].sh_addralign); ++ /* The older linker generates section header indices with ++ hole. */ ++ if (i > 0 && internal->sh_link >= elf_header.e_shnum) ++ hole_in_shndx = internal->sh_link; + } + + free (shdrs); +@@ -3796,8 +3803,12 @@ get_32bit_elf_symbols (FILE * file, Elf_ + psym->st_size = BYTE_GET (esyms[j].st_size); + psym->st_shndx = BYTE_GET (esyms[j].st_shndx); + if (psym->st_shndx == (SHN_XINDEX & 0xffff) && shndx != NULL) +- psym->st_shndx +- = byte_get ((unsigned char *) &shndx[j], sizeof (shndx[j])); ++ { ++ psym->st_shndx ++ = byte_get ((unsigned char *) &shndx[j], sizeof (shndx[j])); ++ if (hole_in_shndx && psym->st_shndx > (SHN_HIRESERVE & 0xffff)) ++ psym->st_shndx -= ELF_SECTION_HEADER_INDEX_GAP; ++ } + else if (psym->st_shndx >= (SHN_LORESERVE & 0xffff)) + psym->st_shndx += SHN_LORESERVE - (SHN_LORESERVE & 0xffff); + psym->st_info = BYTE_GET (esyms[j].st_info); +@@ -3863,8 +3874,12 @@ get_64bit_elf_symbols (FILE * file, Elf_ + psym->st_other = BYTE_GET (esyms[j].st_other); + psym->st_shndx = BYTE_GET (esyms[j].st_shndx); + if (psym->st_shndx == (SHN_XINDEX & 0xffff) && shndx != NULL) +- psym->st_shndx +- = byte_get ((unsigned char *) &shndx[j], sizeof (shndx[j])); ++ { ++ psym->st_shndx ++ = byte_get ((unsigned char *) &shndx[j], sizeof (shndx[j])); ++ if (hole_in_shndx && psym->st_shndx > (SHN_HIRESERVE & 0xffff)) ++ psym->st_shndx -= ELF_SECTION_HEADER_INDEX_GAP; ++ } + else if (psym->st_shndx >= (SHN_LORESERVE & 0xffff)) + psym->st_shndx += SHN_LORESERVE - (SHN_LORESERVE & 0xffff); + psym->st_value = BYTE_GET (esyms[j].st_value); +@@ -4106,6 +4121,7 @@ process_section_headers (FILE * file) + unsigned int i; + + section_headers = NULL; ++ original_shndx = NULL; + + if (elf_header.e_shnum == 0) + { +@@ -4127,6 +4143,44 @@ process_section_headers (FILE * file) + else if (! get_64bit_section_headers (file, elf_header.e_shnum)) + return 0; + ++ if (hole_in_shndx ++ && ((hole_in_shndx - ELF_SECTION_HEADER_INDEX_GAP) ++ < elf_header.e_shnum)) ++ { ++ Elf_Internal_Shdr *internal; ++ struct original_shndx_info *p; ++ ++ if (elf_header.e_shstrndx > (SHN_HIRESERVE & 0xffff)) ++ elf_header.e_shstrndx -= ELF_SECTION_HEADER_INDEX_GAP; ++ ++ original_shndx = cmalloc (elf_header.e_shnum, ++ sizeof (*original_shndx)); ++ if (original_shndx == NULL) ++ { ++ error (_("Out of memory\n")); ++ return 0; ++ } ++ ++ internal = section_headers; ++ p = original_shndx; ++ for (i = elf_header.e_shnum; ++ i > 0; ++ i--, internal++, p++) ++ { ++ p->sh_link = internal->sh_link; ++ p->sh_info = internal->sh_info; ++ ++ if (internal->sh_link > (SHN_HIRESERVE & 0xffff)) ++ internal->sh_link -= ELF_SECTION_HEADER_INDEX_GAP; ++ ++ if (internal->sh_info > (SHN_HIRESERVE & 0xffff) ++ && (internal->sh_flags & SHF_INFO_LINK ++ || internal->sh_type == SHT_REL ++ || internal->sh_type == SHT_RELA)) ++ internal->sh_info -= ELF_SECTION_HEADER_INDEX_GAP; ++ } ++ } ++ + /* Read in the string table, so that we have names to display. */ + if (elf_header.e_shstrndx != SHN_UNDEF + && elf_header.e_shstrndx < elf_header.e_shnum) +@@ -4402,7 +4456,23 @@ process_section_headers (FILE * file) + } + } + +- if (do_section_details) ++ if (hole_in_shndx && original_shndx) ++ { ++ if (original_shndx[i].sh_link != section->sh_link) ++ printf ("%2u/-%3u ", ++ original_shndx[i].sh_link, ++ ELF_SECTION_HEADER_INDEX_GAP); ++ else ++ printf ("%2u ", section->sh_link); ++ if (original_shndx[i].sh_info != section->sh_info) ++ printf ("%3u/-%3u ", ++ original_shndx[i].sh_info, ++ ELF_SECTION_HEADER_INDEX_GAP); ++ else ++ printf ("%3u ", section->sh_info); ++ printf ("%2lu\n", (unsigned long) section->sh_addralign); ++ } ++ else if (do_section_details) + { + if (link_too_big != NULL && * link_too_big) + printf ("<%s> ", link_too_big); +@@ -4454,7 +4524,23 @@ process_section_headers (FILE * file) + else + printf (" %3s ", get_elf_section_flags (section->sh_flags)); + +- printf ("%2u %3u ", section->sh_link, section->sh_info); ++ if (hole_in_shndx) ++ { ++ if (original_shndx[i].sh_link != section->sh_link) ++ printf ("%2u/-%3u ", ++ original_shndx[i].sh_link, ++ ELF_SECTION_HEADER_INDEX_GAP); ++ else ++ printf ("%2u ", section->sh_link); ++ if (original_shndx[i].sh_info != section->sh_info) ++ printf ("%3u/-%3u ", ++ original_shndx[i].sh_info, ++ ELF_SECTION_HEADER_INDEX_GAP); ++ else ++ printf ("%3u ", section->sh_info); ++ } ++ else ++ printf ("%2u %3u ", section->sh_link, section->sh_info); + + if ((unsigned long) section->sh_addralign == section->sh_addralign) + printf ("%2lu\n", (unsigned long) section->sh_addralign); +@@ -4476,14 +4562,35 @@ process_section_headers (FILE * file) + printf (" "); + print_vma (section->sh_offset, LONG_HEX); + } +- printf (" %u\n ", section->sh_link); ++ if (hole_in_shndx) ++ { ++ if (original_shndx[i].sh_link != section->sh_link) ++ printf (" %u/-%3u\n ", ++ original_shndx[i].sh_link, ++ ELF_SECTION_HEADER_INDEX_GAP); ++ else ++ printf (" %u\n ", section->sh_link); ++ } ++ else ++ printf (" %u\n ", section->sh_link); + print_vma (section->sh_size, LONG_HEX); + putchar (' '); + print_vma (section->sh_entsize, LONG_HEX); + +- printf (" %-16u %lu\n", +- section->sh_info, +- (unsigned long) section->sh_addralign); ++ if (hole_in_shndx) ++ { ++ if (original_shndx[i].sh_info != section->sh_info) ++ printf (" %-11u/-%3u", ++ original_shndx[i].sh_info, ++ ELF_SECTION_HEADER_INDEX_GAP); ++ else ++ printf (" %-16u", section->sh_info); ++ printf (" %lu\n", (unsigned long) section->sh_addralign); ++ } ++ else ++ printf (" %-16u %lu\n", ++ section->sh_info, ++ (unsigned long) section->sh_addralign); + } + else + { +@@ -4503,10 +4610,28 @@ process_section_headers (FILE * file) + + printf (" %3s ", get_elf_section_flags (section->sh_flags)); + +- printf (" %2u %3u %lu\n", +- section->sh_link, +- section->sh_info, +- (unsigned long) section->sh_addralign); ++ if (hole_in_shndx) ++ { ++ if (original_shndx[i].sh_link != section->sh_link) ++ printf (" %2u/-%3u", ++ original_shndx[i].sh_link, ++ ELF_SECTION_HEADER_INDEX_GAP); ++ else ++ printf (" %2u", section->sh_link); ++ if (original_shndx[i].sh_info != section->sh_info) ++ printf (" %3u/-%3u", ++ original_shndx[i].sh_info, ++ ELF_SECTION_HEADER_INDEX_GAP); ++ else ++ printf (" %3u", section->sh_info); ++ printf (" %lu\n", ++ (unsigned long) section->sh_addralign); ++ } ++ else ++ printf (" %2u %3u %lu\n", ++ section->sh_link, ++ section->sh_info, ++ (unsigned long) section->sh_addralign); + } + + if (do_section_details) +@@ -4703,10 +4828,15 @@ process_section_groups (FILE * file) + for (j = 0; j < size; j++) + { + struct group_list * g; ++ unsigned int orig; + + entry = byte_get (indices, 4); + indices += 4; + ++ orig = entry; ++ if (hole_in_shndx && entry > (SHN_HIRESERVE & 0xffff)) ++ entry -= ELF_SECTION_HEADER_INDEX_GAP; ++ + if (entry >= elf_header.e_shnum) + { + error (_("section [%5u] in group section [%5u] > maximum section [%5u]\n"), +@@ -4743,7 +4873,13 @@ process_section_groups (FILE * file) + if (do_section_groups) + { + sec = section_headers + entry; +- printf (" [%5u] %s\n", entry, SECTION_NAME (sec)); ++ if (orig != entry) ++ printf (" [%5u/-%3u] %s\n", ++ orig, ELF_SECTION_HEADER_INDEX_GAP, ++ SECTION_NAME (sec)); ++ else ++ printf (" [%5u] %s\n", ++ entry, SECTION_NAME (sec)); + } + + g = (struct group_list *) xmalloc (sizeof (struct group_list)); +@@ -10622,6 +10758,15 @@ get_file_header (FILE * file) + if (fread (elf_header.e_ident, EI_NIDENT, 1, file) != 1) + return 0; + ++ if (elf_header.e_ident[EI_MAG0] != ELFMAG0 ++ || elf_header.e_ident[EI_MAG1] != ELFMAG1 ++ || elf_header.e_ident[EI_MAG2] != ELFMAG2 ++ || elf_header.e_ident[EI_MAG3] != ELFMAG3) ++ { ++ error (_("Not an ELF file - it has the wrong magic bytes at the start\n")); ++ return 0; ++ } ++ + /* Determine how to read the rest of the header. */ + switch (elf_header.e_ident[EI_DATA]) + { +@@ -10717,6 +10862,8 @@ process_object (char * file_name, FILE * + { + unsigned int i; + ++ hole_in_shndx = 0; ++ + if (! get_file_header (file)) + { + error (_("%s: Failed to read file header\n"), file_name); +@@ -10804,6 +10951,12 @@ process_object (char * file_name, FILE * + section_headers = NULL; + } + ++ if (original_shndx) ++ { ++ free (original_shndx); ++ original_shndx = NULL; ++ } ++ + if (string_table) + { + free (string_table); +--- binutils/include/elf/internal.h.sec64k 2009-05-05 10:56:16.000000000 -0700 ++++ binutils/include/elf/internal.h 2009-09-10 09:47:27.000000000 -0700 +@@ -330,4 +330,8 @@ struct elf_segment_map + (ELF_SECTION_SIZE(sec_hdr, segment) > 0 \ + && ELF_IS_SECTION_IN_SEGMENT (sec_hdr, segment)) + ++/* The gap in section indices created by the older linker before ++ bug fix for PR ld/5900. */ ++#define ELF_SECTION_HEADER_INDEX_GAP (SHN_HIRESERVE + 1 - SHN_LORESERVE) ++ + #endif /* _ELF_INTERNAL_H */ --- binutils-2.20.orig/debian/patches/002_gprof_profile_arcs.dpatch +++ binutils-2.20/debian/patches/002_gprof_profile_arcs.dpatch @@ -0,0 +1,51 @@ +#!/bin/sh -e +## 003_gmon_manpage_fix.dpatch by Chris Chimelis +## +## All lines beginning with `## DP:' are a description of the patch. +## DP: Add more documentation about profiling and -fprofile-arcs. + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +diff -urNad binutils-2.16/gprof/gprof.texi /tmp/dpep.NHuhql/binutils-2.16/gprof/gprof.texi +--- binutils-2.16/gprof/gprof.texi 2005-03-03 13:05:12.000000000 +0100 ++++ /tmp/dpep.NHuhql/binutils-2.16/gprof/gprof.texi 2005-05-06 19:14:10.038173569 +0200 +@@ -138,6 +138,10 @@ + If more than one profile file is specified, the @code{gprof} + output shows the sum of the profile information in the given profile files. + ++If you use gcc 2.95.x or 3.0 to compile your binaries, you may need ++to add the @samp{-fprofile-arcs} to the compile command line in order ++for the call graphs to be properly stored in gmon.out. ++ + @code{Gprof} calculates the amount of time spent in each routine. + Next, these times are propagated along the edges of the call graph. + Cycles are discovered, and calls into a cycle are made to share the time +@@ -268,6 +272,11 @@ + options. The same option, @samp{-pg}, alters either compilation or linking + to do what is necessary for profiling. Here are examples: + ++If you use gcc 2.95.x or 3.0.x, you may need to add the ++@samp{-fprofile-arcs} option to the compile line along with @samp{-pg} ++in order to allow the call-graphs to be properly included in the gmon.out ++file. ++ + @example + cc -g -c myprog.c utils.c -pg + cc -o myprog myprog.o utils.o -pg --- binutils-2.20.orig/debian/patches/129_dir_section.dpatch +++ binutils-2.20/debian/patches/129_dir_section.dpatch @@ -0,0 +1,154 @@ +#!/bin/sh -e +## 129_dir_section.dpatch +## +## DP: Description: Add directory section for info documents. +## DP: Author: Matthias Klose +## DP: Upstream status: submitted upstream + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +bfd/ +2009-08-27 Matthias Klose + + * bfd.texinfo: Add directory section for info document. + +gas/ +2009-08-27 Matthias Klose + + * doc/as.texinfo: Add directory section for info document. + +gprof/ +2009-08-27 Matthias Klose + + * gprof.texi: Add directory section for info document. + +ld/ +2009-08-27 Matthias Klose + + * ld.texinfo, ldint.texinfo: Add directory section for info document. + +@DPATCH@ +--- ./bfd/doc/bfd.texinfo~ 2008-11-19 17:22:46.000000000 +0100 ++++ ./bfd/doc/bfd.texinfo 2009-08-27 15:59:58.000000000 +0200 +@@ -6,13 +6,12 @@ + @c + @synindex fn cp + +-@ifinfo +-@format +-START-INFO-DIR-ENTRY ++@ifnottex ++@dircategory Software development ++@direntry + * Bfd: (bfd). The Binary File Descriptor library. +-END-INFO-DIR-ENTRY +-@end format +-@end ifinfo ++@end direntry ++@end ifnottex + + @copying + This file documents the BFD library. +--- ./gas/doc/as.texinfo~ 2009-08-06 19:38:02.000000000 +0200 ++++ ./gas/doc/as.texinfo 2009-08-27 15:59:27.000000000 +0200 +@@ -84,14 +84,13 @@ + @c might as well show 'em anyways. + @end ifinfo + +-@ifinfo +-@format +-START-INFO-DIR-ENTRY ++@ifnottex ++@dircategory Software development ++@direntry + * As: (as). The GNU assembler. + * Gas: (as). The GNU assembler. +-END-INFO-DIR-ENTRY +-@end format +-@end ifinfo ++@end direntry ++@end ifnottex + + @finalout + @syncodeindex ky cp +--- ./gprof/gprof.texi~ 2009-08-27 15:26:11.000000000 +0200 ++++ ./gprof/gprof.texi 2009-08-27 16:00:58.000000000 +0200 +@@ -10,15 +10,14 @@ + @include bfdver.texi + @c man end + +-@ifinfo ++@ifnottex + @c This is a dir.info fragment to support semi-automated addition of + @c manuals to an info tree. zoo@cygnus.com is developing this facility. +-@format +-START-INFO-DIR-ENTRY ++@dircategory Software development ++@direntry + * gprof: (gprof). Profiling your program's execution +-END-INFO-DIR-ENTRY +-@end format +-@end ifinfo ++@end direntry ++@end ifnottex + + @copying + This file documents the gprof profiler of the GNU system. +--- ./ld/ld.texinfo~ 2009-07-06 15:48:51.000000000 +0200 ++++ ./ld/ld.texinfo 2009-08-27 15:57:09.000000000 +0200 +@@ -39,13 +39,12 @@ + @end ifset + @c man end + +-@ifinfo +-@format +-START-INFO-DIR-ENTRY ++@ifnottex ++@dircategory Software development ++@direntry + * Ld: (ld). The GNU linker. +-END-INFO-DIR-ENTRY +-@end format +-@end ifinfo ++@end direntry ++@end ifnottex + + @copying + This file documents the @sc{gnu} linker LD +--- ./ld/ldint.texinfo~ 2007-10-01 11:54:57.000000000 +0200 ++++ ./ld/ldint.texinfo 2009-08-27 15:58:50.000000000 +0200 +@@ -4,13 +4,12 @@ + @c 2003, 2007 + @c Free Software Foundation, Inc. + +-@ifinfo +-@format +-START-INFO-DIR-ENTRY ++@ifnottex ++@dircategory Software development ++@direntry + * Ld-Internals: (ldint). The GNU linker internals. +-END-INFO-DIR-ENTRY +-@end format +-@end ifinfo ++@end direntry ++@end ifnottex + + @copying + This file documents the internals of the GNU linker ld. --- binutils-2.20.orig/debian/patches/133_gas_release_build.dpatch +++ binutils-2.20/debian/patches/133_gas_release_build.dpatch @@ -0,0 +1,39 @@ +#!/bin/sh -e +## 133_gas_release_build.dpatch +## +## DP: Description: Fix release build on arm +## DP: Author: Matthias Klose +## DP: Upstream status: submitted + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +--- ./gas/config/tc-arm.c.orig 2009-08-30 00:10:59.000000000 +0200 ++++ ./gas/config/tc-arm.c 2009-10-16 19:47:39.000000000 +0200 +@@ -2486,7 +2486,9 @@ + frag->tc_frag_data.first_map = symbolP; + } + if (frag->tc_frag_data.last_map != NULL) +- know (S_GET_VALUE (frag->tc_frag_data.last_map) < S_GET_VALUE (symbolP)); ++ { ++ know (S_GET_VALUE (frag->tc_frag_data.last_map) < S_GET_VALUE (symbolP)); ++ } + frag->tc_frag_data.last_map = symbolP; + } + --- binutils-2.20.orig/debian/patches/00list +++ binutils-2.20/debian/patches/00list @@ -0,0 +1,28 @@ +001_ld_makefile_patch +002_gprof_profile_arcs +003_gprof_see_also_monitor +006_better_file_error +012_check_ldrunpath_length +013_bash_in_ld_testsuite + +127_x86_64_i386_biarch +128_build_id +129_dir_section +130_gold_disable_testsuite_build +131_ld_bootstrap_testsuite +132_gold_plugin_api_build +133_gas_release_build + +# not applied for Ubuntu: +#200-hjl-ld-env + +203-hjl-binutils-indirect + +# not applied for Ubuntu: +#206-hjl-binutils-shr + +209-hjl-binutils-error +210-hjl-binutils-signed +211-hjl-binutils-weakdef +212-hjl-bfd-64k +213-hjl-binutils-sec64k --- binutils-2.20.orig/debian/patches/209-hjl-binutils-error.dpatch +++ binutils-2.20/debian/patches/209-hjl-binutils-error.dpatch @@ -0,0 +1,1001 @@ +#!/bin/sh -e +## 209-hjl-binutils-error.dpatch +## +## DP: Description: Avoid unnecessary linker messages when running "make check" +## DP: Author: H.J. Lu +## DP: Upstream status: hjl 2.18.51.0.3 +## DP: Original patch: binutils-error-7.patch + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +bfd/ + +2007-07-03 H.J. Lu + + PR ld/4409 + * elf-bfd.h (RELOC_FOR_GLOBAL_SYMBOL): Add an argument for + error ignored. + * elf-m10200.c (mn10200_elf_relocate_section): Updated. + * elf-m10300.c (mn10300_elf_relocate_section): Likewise. + * elf32-arm.c (elf32_arm_relocate_section): Likewise. + * elf32-avr.c (elf32_avr_relocate_section): Likewise. + * elf32-bfin.c (bfinfdpic_relocate_section): Likewise. + (bfin_relocate_section): Likewise. + * elf32-cr16.c (elf32_cr16_relocate_section): Likewise. + * elf32-cr16c.c (elf32_cr16c_relocate_section): Likewise. + * elf32-cris.c (cris_elf_relocate_section): Likewise. + * elf32-crx.c (elf32_crx_relocate_section): Likewise. + * elf32-d10v.c (elf32_d10v_relocate_section): Likewise. + * elf32-fr30.c (fr30_elf_relocate_section): Likewise. + * elf32-frv.c (elf32_frv_relocate_section): Likewise. + * elf32-h8300.c (elf32_h8_relocate_section): Likewise. + * elf32-hppa.c (elf32_hppa_relocate_section): Likewise. + * elf32-i386.c (elf_i386_relocate_section): Likewise. + * elf32-i860.c (elf32_i860_relocate_section): Likewise. + * elf32-ip2k.c (ip2k_elf_relocate_section): Likewise. + * elf32-iq2000.c (iq2000_elf_relocate_section): Likewise. + * elf32-m68hc1x.c (elf32_m68hc11_relocate_section): Likewise. + * elf32-m68k.c (elf_m68k_relocate_section): Likewise. + * elf32-mcore.c (mcore_elf_relocate_section): Likewise. + * elf32-mep.c (mep_elf_relocate_section): Likewise. + * elf32-msp430.c (elf32_msp430_relocate_section): Likewise. + * elf32-mt.c (mt_elf_relocate_section): Likewise. + * elf32-openrisc.c (openrisc_elf_relocate_section): Likewise. + * elf32-ppc.c (ppc_elf_relocate_section): Likewise. + * elf32-s390.c (elf_s390_relocate_section): Likewise. + * elf32-v850.c (v850_elf_relocate_section): Likewise. + * elf32-vax.c (elf_vax_relocate_section): Likewise. + * elf32-xc16x.c (elf32_xc16x_relocate_section): Likewise. + * elf32-xstormy16.c (xstormy16_elf_relocate_section): Likewise. + * elf32-xtensa.c (elf_xtensa_relocate_section): Likewise. + * elf64-alpha.c (elf64_alpha_relocate_section): Likewise. + * elf64-mmix.c (mmix_elf_relocate_section): Likewise. + * elf64-ppc.c (ppc64_elf_relocate_section): Likewise. + * elf64-s390.c (elf_s390_relocate_section): Likewise. + * elf64-x86-64.c (elf64_x86_64_relocate_section): Likewise. + * elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Likewise. + + * elfxx-ia64.c (elfNN_ia64_relocate_section): Skip if error + from RELOC_FOR_GLOBAL_SYMBOL in executable is ignored. + +ld/ + +2007-07-03 H.J. Lu + + PR ld/4409 + * ldmain.c (how_to_report_unresolved_symbols): New. + (main): Set link_info.unresolved_syms_in_objects and + link_info.unresolved_syms_in_shared_libs if they aren't set + yet. + + * ldmain.h (how_to_report_unresolved_symbols): New. + + * lexsup.c (how_to_report_unresolved_symbols): Removed. + (parse_args): Set link_info.pie to FALSE for -shared. Don't + set default values for link_info.unresolved_syms_in_objects nor + link_info.unresolved_syms_in_shared_libs. + +ld/testsuite/ + +2007-07-03 H.J. Lu + + PR ld/4409 + * ld-ia64/error1.d: New file. + * ld-ia64/error1.s: Likewise. + * ld-ia64/error2.d: Likewise. + * ld-ia64/error3.d: Likewise. + * ld-ia64/error4.d: Likewise. + +@DPATCH@ +--- binutils/bfd/elf-bfd.h.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/bfd/elf-bfd.h 2009-03-05 05:57:51.000000000 -0800 +@@ -2174,7 +2174,7 @@ extern asection _bfd_elf_large_com_secti + #define RELOC_FOR_GLOBAL_SYMBOL(info, input_bfd, input_section, rel, \ + r_symndx, symtab_hdr, sym_hashes, \ + h, sec, relocation, \ +- unresolved_reloc, warned) \ ++ unresolved_reloc, warned, ignored) \ + do \ + { \ + /* It seems this can happen with erroneous or unsupported \ +@@ -2189,6 +2189,7 @@ extern asection _bfd_elf_large_com_secti + h = (struct elf_link_hash_entry *) h->root.u.i.link; \ + \ + warned = FALSE; \ ++ ignored = FALSE; \ + unresolved_reloc = FALSE; \ + relocation = 0; \ + if (h->root.type == bfd_link_hash_defined \ +@@ -2211,7 +2212,7 @@ extern asection _bfd_elf_large_com_secti + ; \ + else if (info->unresolved_syms_in_objects == RM_IGNORE \ + && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT) \ +- ; \ ++ ignored = TRUE; \ + else if (!info->relocatable) \ + { \ + bfd_boolean err; \ +--- binutils/bfd/elf-m10200.c.error 2007-10-30 11:48:32.000000000 -0700 ++++ binutils/bfd/elf-m10200.c 2009-03-05 05:57:51.000000000 -0800 +@@ -392,12 +392,12 @@ mn10200_elf_relocate_section (output_bfd + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf-m10300.c.error 2008-11-29 12:07:44.000000000 -0800 ++++ binutils/bfd/elf-m10300.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1465,13 +1465,13 @@ mn10300_elf_relocate_section (bfd *outpu + else + { + bfd_boolean unresolved_reloc; +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + struct elf_link_hash_entry *hh; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + hh, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + h = (struct elf32_mn10300_link_hash_entry *) hh; + +--- binutils/bfd/elf32-arm.c.error 2009-02-27 12:06:08.000000000 -0800 ++++ binutils/bfd/elf32-arm.c 2009-03-05 05:57:51.000000000 -0800 +@@ -8000,12 +8000,12 @@ elf32_arm_relocate_section (bfd * + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + sym_type = h->type; + } +--- binutils/bfd/elf32-avr.c.error 2009-02-20 09:01:14.000000000 -0800 ++++ binutils/bfd/elf32-avr.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1202,12 +1202,12 @@ elf32_avr_relocate_section (bfd *output_ + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + name = h->root.root.string; + } +--- binutils/bfd/elf32-bfin.c.error 2008-11-29 12:07:45.000000000 -0800 ++++ binutils/bfd/elf32-bfin.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1419,12 +1419,12 @@ bfin_relocate_section (bfd * output_bfd, + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +@@ -2630,13 +2630,13 @@ bfinfdpic_relocate_section (bfd * output + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + bfd_boolean unresolved_reloc; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + osec = sec; + } + +--- binutils/bfd/elf32-cr16.c.error 2008-11-29 12:07:45.000000000 -0800 ++++ binutils/bfd/elf32-cr16.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1450,12 +1450,12 @@ elf32_cr16_relocate_section (bfd *output + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + r = cr16_elf_final_link_relocate (howto, input_bfd, output_bfd, +--- binutils/bfd/elf32-cr16c.c.error 2007-10-30 11:48:32.000000000 -0700 ++++ binutils/bfd/elf32-cr16c.c 2009-03-05 05:57:51.000000000 -0800 +@@ -718,12 +718,12 @@ elf32_cr16c_relocate_section (bfd *outpu + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-cris.c.error 2009-02-03 11:30:04.000000000 -0800 ++++ binutils/bfd/elf32-cris.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1103,13 +1103,13 @@ cris_elf_relocate_section (output_bfd, i + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + bfd_boolean unresolved_reloc; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + symname = h->root.root.string; + +--- binutils/bfd/elf32-crx.c.error 2007-10-30 11:48:32.000000000 -0700 ++++ binutils/bfd/elf32-crx.c 2009-03-05 05:57:51.000000000 -0800 +@@ -869,12 +869,12 @@ elf32_crx_relocate_section (bfd *output_ + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-d10v.c.error 2007-10-30 11:48:32.000000000 -0700 ++++ binutils/bfd/elf32-d10v.c 2009-03-05 05:57:51.000000000 -0800 +@@ -455,12 +455,12 @@ elf32_d10v_relocate_section (bfd *output + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-fr30.c.error 2008-01-09 06:17:24.000000000 -0800 ++++ binutils/bfd/elf32-fr30.c 2009-03-05 05:57:51.000000000 -0800 +@@ -567,12 +567,12 @@ fr30_elf_relocate_section (output_bfd, i + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + name = h->root.root.string; + } +--- binutils/bfd/elf32-frv.c.error 2008-08-12 07:24:02.000000000 -0700 ++++ binutils/bfd/elf32-frv.c 2009-03-05 05:57:51.000000000 -0800 +@@ -2798,13 +2798,13 @@ elf32_frv_relocate_section (output_bfd, + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + bfd_boolean unresolved_reloc; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + osec = sec; + } + +--- binutils/bfd/elf32-h8300.c.error 2007-10-30 11:48:32.000000000 -0700 ++++ binutils/bfd/elf32-h8300.c 2009-03-05 05:57:51.000000000 -0800 +@@ -452,12 +452,12 @@ elf32_h8_relocate_section (bfd *output_b + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-hppa.c.error 2009-03-05 05:49:31.000000000 -0800 ++++ binutils/bfd/elf32-hppa.c 2009-03-05 05:57:51.000000000 -0800 +@@ -3674,13 +3674,14 @@ elf32_hppa_relocate_section (bfd *output + else + { + struct elf_link_hash_entry *eh; +- bfd_boolean unresolved_reloc; ++ bfd_boolean unresolved_reloc, ignored; + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rela, + r_symndx, symtab_hdr, sym_hashes, + eh, sym_sec, relocation, +- unresolved_reloc, warned_undef); ++ unresolved_reloc, warned_undef, ++ ignored); + + if (!info->relocatable + && relocation == 0 +--- binutils/bfd/elf32-i386.c.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/bfd/elf32-i386.c 2009-03-05 05:57:51.000000000 -0800 +@@ -2679,12 +2679,12 @@ elf_i386_relocate_section (bfd *output_b + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-i860.c.error 2007-10-30 11:48:33.000000000 -0700 ++++ binutils/bfd/elf32-i860.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1120,12 +1120,12 @@ elf32_i860_relocate_section (bfd *output + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-ip2k.c.error 2007-10-30 11:48:33.000000000 -0700 ++++ binutils/bfd/elf32-ip2k.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1449,13 +1449,13 @@ ip2k_elf_relocate_section (bfd *output_b + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + bfd_boolean unresolved_reloc; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + name = h->root.root.string; + } +--- binutils/bfd/elf32-iq2000.c.error 2008-08-12 07:24:02.000000000 -0700 ++++ binutils/bfd/elf32-iq2000.c 2009-03-05 05:57:51.000000000 -0800 +@@ -623,12 +623,12 @@ iq2000_elf_relocate_section (bfd * + else + { + bfd_boolean unresolved_reloc; +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + name = h->root.root.string; + } +--- binutils/bfd/elf32-lm32.c.error 2008-12-23 11:10:18.000000000 -0800 ++++ binutils/bfd/elf32-lm32.c 2009-03-05 06:05:24.000000000 -0800 +@@ -887,12 +887,12 @@ lm32_elf_relocate_section (bfd *output_b + { + /* It's a global symbol. */ + bfd_boolean unresolved_reloc; +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + osec = sec; + name = h->root.root.string; + } +--- binutils/bfd/elf32-m68hc1x.c.error 2008-03-12 12:32:03.000000000 -0700 ++++ binutils/bfd/elf32-m68hc1x.c 2009-03-05 05:57:51.000000000 -0800 +@@ -947,12 +947,12 @@ elf32_m68hc11_relocate_section (bfd *out + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, unresolved_reloc, +- warned); ++ warned, ignored); + + is_far = (h && (h->other & STO_M68HC12_FAR)); + stub_name = h->root.root.string; +--- binutils/bfd/elf32-m68k.c.error 2009-02-03 11:30:04.000000000 -0800 ++++ binutils/bfd/elf32-m68k.c 2009-03-05 05:57:51.000000000 -0800 +@@ -3518,12 +3518,12 @@ elf_m68k_relocate_section (output_bfd, i + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-mcore.c.error 2007-10-30 11:48:33.000000000 -0700 ++++ binutils/bfd/elf32-mcore.c 2009-03-05 05:57:51.000000000 -0800 +@@ -458,12 +458,12 @@ mcore_elf_relocate_section (bfd * output + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-mep.c.error 2009-02-03 11:30:04.000000000 -0800 ++++ binutils/bfd/elf32-mep.c 2009-03-05 05:57:51.000000000 -0800 +@@ -489,12 +489,12 @@ mep_elf_relocate_section + } + else + { +- bfd_boolean warned, unresolved_reloc; ++ bfd_boolean warned, unresolved_reloc, ignored; + + RELOC_FOR_GLOBAL_SYMBOL(info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + name = h->root.root.string; + } +--- binutils/bfd/elf32-msp430.c.error 2007-10-30 11:48:33.000000000 -0700 ++++ binutils/bfd/elf32-msp430.c 2009-03-05 05:57:51.000000000 -0800 +@@ -446,12 +446,12 @@ elf32_msp430_relocate_section (bfd * out + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-mt.c.error 2008-08-12 07:24:02.000000000 -0700 ++++ binutils/bfd/elf32-mt.c 2009-03-05 05:57:51.000000000 -0800 +@@ -344,12 +344,12 @@ mt_elf_relocate_section + else + { + bfd_boolean unresolved_reloc; +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + name = h->root.root.string; + } +--- binutils/bfd/elf32-openrisc.c.error 2007-10-30 11:48:33.000000000 -0700 ++++ binutils/bfd/elf32-openrisc.c 2009-03-05 05:57:51.000000000 -0800 +@@ -365,12 +365,12 @@ openrisc_elf_relocate_section (bfd *outp + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-ppc.c.error 2009-03-05 05:49:31.000000000 -0800 ++++ binutils/bfd/elf32-ppc.c 2009-03-05 05:57:51.000000000 -0800 +@@ -6262,10 +6262,12 @@ ppc_elf_relocate_section (bfd *output_bf + } + else + { ++ bfd_boolean ignored; ++ + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + sym_name = h->root.root.string; + } +--- binutils/bfd/elf32-s390.c.error 2008-11-29 12:07:45.000000000 -0800 ++++ binutils/bfd/elf32-s390.c 2009-03-05 05:57:51.000000000 -0800 +@@ -2289,11 +2289,12 @@ elf_s390_relocate_section (output_bfd, i + else + { + bfd_boolean warned ATTRIBUTE_UNUSED; ++ bfd_boolean ignored ATTRIBUTE_UNUSED; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-v850.c.error 2008-11-29 12:07:45.000000000 -0800 ++++ binutils/bfd/elf32-v850.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1624,7 +1624,7 @@ v850_elf_relocate_section (bfd *output_b + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + /* Note - this check is delayed until now as it is possible and + valid to have a file without any symbols but with relocs that +@@ -1641,7 +1641,7 @@ v850_elf_relocate_section (bfd *output_b + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-vax.c.error 2008-11-29 12:07:45.000000000 -0800 ++++ binutils/bfd/elf32-vax.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1398,12 +1398,12 @@ elf_vax_relocate_section (bfd *output_bf + else + { + bfd_boolean unresolved_reloc; +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + if ((h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) +--- binutils/bfd/elf32-xc16x.c.error 2007-10-30 11:48:33.000000000 -0700 ++++ binutils/bfd/elf32-xc16x.c 2009-03-05 05:57:51.000000000 -0800 +@@ -374,12 +374,12 @@ elf32_xc16x_relocate_section (bfd *outpu + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-xstormy16.c.error 2007-10-30 11:48:33.000000000 -0700 ++++ binutils/bfd/elf32-xstormy16.c 2009-03-05 05:57:51.000000000 -0800 +@@ -823,12 +823,12 @@ xstormy16_elf_relocate_section (bfd * + } + else + { +- bfd_boolean unresolved_reloc, warned; ++ bfd_boolean unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf32-xtensa.c.error 2009-02-25 10:36:15.000000000 -0800 ++++ binutils/bfd/elf32-xtensa.c 2009-03-05 05:57:51.000000000 -0800 +@@ -2625,10 +2625,12 @@ elf_xtensa_relocate_section (bfd *output + } + else + { ++ bfd_boolean ignored; ++ + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + if (relocation == 0 + && !unresolved_reloc +--- binutils/bfd/elf64-alpha.c.error 2008-11-29 12:07:45.000000000 -0800 ++++ binutils/bfd/elf64-alpha.c 2009-03-05 05:57:51.000000000 -0800 +@@ -4168,7 +4168,7 @@ elf64_alpha_relocate_section (bfd *outpu + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + bfd_boolean unresolved_reloc; + struct elf_link_hash_entry *hh; + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); +@@ -4176,7 +4176,7 @@ elf64_alpha_relocate_section (bfd *outpu + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + hh, sec, value, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + if (warned) + continue; +--- binutils/bfd/elf64-mmix.c.error 2007-10-30 11:48:33.000000000 -0700 ++++ binutils/bfd/elf64-mmix.c 2009-03-05 05:57:51.000000000 -0800 +@@ -1402,12 +1402,13 @@ mmix_elf_relocate_section (output_bfd, i + } + else + { +- bfd_boolean unresolved_reloc; ++ bfd_boolean unresolved_reloc, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, undefined_signalled); ++ unresolved_reloc, undefined_signalled, ++ ignored); + name = h->root.root.string; + } + +--- binutils/bfd/elf64-ppc.c.error 2009-03-05 05:49:31.000000000 -0800 ++++ binutils/bfd/elf64-ppc.c 2009-03-05 05:57:51.000000000 -0800 +@@ -10327,10 +10327,12 @@ ppc64_elf_relocate_section (bfd *output_ + } + else + { ++ bfd_boolean ignored; ++ + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h_elf, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + sym_name = h_elf->root.root.string; + sym_type = h_elf->type; + } +--- binutils/bfd/elf64-s390.c.error 2008-12-04 06:17:01.000000000 -0800 ++++ binutils/bfd/elf64-s390.c 2009-03-05 05:57:51.000000000 -0800 +@@ -2263,11 +2263,12 @@ elf_s390_relocate_section (output_bfd, i + else + { + bfd_boolean warned ATTRIBUTE_UNUSED; ++ bfd_boolean ignored ATTRIBUTE_UNUSED; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elf64-x86-64.c.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/bfd/elf64-x86-64.c 2009-03-05 05:57:51.000000000 -0800 +@@ -2382,12 +2382,12 @@ elf64_x86_64_relocate_section (bfd *outp + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + } + + if (sec != NULL && elf_discarded_section (sec)) +--- binutils/bfd/elfxx-ia64.c.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/bfd/elfxx-ia64.c 2009-03-05 05:57:51.000000000 -0800 +@@ -4544,17 +4544,17 @@ elfNN_ia64_relocate_section (bfd *output + else + { + bfd_boolean unresolved_reloc; +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sym_sec, value, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + + if (h->root.type == bfd_link_hash_undefweak) + undef_weak_ref = TRUE; +- else if (warned) ++ else if (warned || (ignored && info->executable)) + continue; + } + +--- binutils/bfd/elfxx-sparc.c.error 2008-11-29 12:07:46.000000000 -0800 ++++ binutils/bfd/elfxx-sparc.c 2009-03-05 05:57:51.000000000 -0800 +@@ -2569,12 +2569,12 @@ _bfd_sparc_elf_relocate_section (bfd *ou + } + else + { +- bfd_boolean warned; ++ bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, +- unresolved_reloc, warned); ++ unresolved_reloc, warned, ignored); + if (warned) + { + /* To avoid generating warning messages about truncated +--- binutils/ld/ldmain.c.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/ld/ldmain.c 2009-03-05 05:57:51.000000000 -0800 +@@ -104,6 +104,9 @@ bfd_boolean add_needed = TRUE; + /* TRUE if we should demangle symbol names. */ + bfd_boolean demangling; + ++/* How to report unresolved symbols. */ ++enum report_method how_to_report_unresolved_symbols = RM_GENERATE_ERROR; ++ + args_type command_line; + + ld_config_type config; +@@ -388,6 +391,27 @@ main (int argc, char **argv) + if (! link_info.shared || link_info.pie) + link_info.executable = TRUE; + ++ /* When creating a shared library, the default behaviour is to ++ ignore any unresolved references. */ ++ ++ if (link_info.unresolved_syms_in_objects == RM_NOT_YET_SET) ++ { ++ if (link_info.shared && !link_info.pie) ++ link_info.unresolved_syms_in_objects = RM_IGNORE; ++ else ++ link_info.unresolved_syms_in_objects ++ = how_to_report_unresolved_symbols; ++ } ++ ++ if (link_info.unresolved_syms_in_shared_libs == RM_NOT_YET_SET) ++ { ++ if (link_info.shared && !link_info.pie) ++ link_info.unresolved_syms_in_shared_libs = RM_IGNORE; ++ else ++ link_info.unresolved_syms_in_shared_libs ++ = how_to_report_unresolved_symbols; ++ } ++ + /* Treat ld -r -s as ld -r -S -x (i.e., strip all local symbols). I + don't see how else this can be handled, since in this case we + must preserve all externally visible symbols. */ +--- binutils/ld/ldmain.h.error 2008-02-15 09:03:46.000000000 -0800 ++++ binutils/ld/ldmain.h 2009-03-05 05:57:51.000000000 -0800 +@@ -37,6 +37,7 @@ extern bfd_boolean whole_archive; + extern bfd_boolean as_needed; + extern bfd_boolean add_needed; + extern bfd_boolean demangling; ++extern enum report_method how_to_report_unresolved_symbols; + extern int g_switch_value; + extern const char *output_filename; + extern struct bfd_link_info link_info; +--- binutils/ld/lexsup.c.error 2009-02-03 11:30:15.000000000 -0800 ++++ binutils/ld/lexsup.c 2009-03-05 05:57:51.000000000 -0800 +@@ -581,7 +581,6 @@ parse_args (unsigned argc, char **argv) + struct option *longopts; + struct option *really_longopts; + int last_optind; +- enum report_method how_to_report_unresolved_symbols = RM_GENERATE_ERROR; + + shortopts = xmalloc (OPTION_COUNT * 3 + 2); + longopts = xmalloc (sizeof (*longopts) * (OPTION_COUNT + 1)); +@@ -1127,12 +1126,7 @@ parse_args (unsigned argc, char **argv) + if (config.has_shared) + { + link_info.shared = TRUE; +- /* When creating a shared library, the default +- behaviour is to ignore any unresolved references. */ +- if (link_info.unresolved_syms_in_objects == RM_NOT_YET_SET) +- link_info.unresolved_syms_in_objects = RM_IGNORE; +- if (link_info.unresolved_syms_in_shared_libs == RM_NOT_YET_SET) +- link_info.unresolved_syms_in_shared_libs = RM_IGNORE; ++ link_info.pie = FALSE; + } + else + einfo (_("%P%F: -shared not supported\n")); +@@ -1473,14 +1467,6 @@ parse_args (unsigned argc, char **argv) + set_default_dirlist (default_dirlist); + free (default_dirlist); + } +- +- if (link_info.unresolved_syms_in_objects == RM_NOT_YET_SET) +- /* FIXME: Should we allow emulations a chance to set this ? */ +- link_info.unresolved_syms_in_objects = how_to_report_unresolved_symbols; +- +- if (link_info.unresolved_syms_in_shared_libs == RM_NOT_YET_SET) +- /* FIXME: Should we allow emulations a chance to set this ? */ +- link_info.unresolved_syms_in_shared_libs = how_to_report_unresolved_symbols; + } + + /* Add the (colon-separated) elements of DIRLIST_PTR to the +--- binutils/ld/testsuite/ld-ia64/error1.d.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/ld/testsuite/ld-ia64/error1.d 2009-03-05 05:57:51.000000000 -0800 +@@ -0,0 +1,7 @@ ++#source: error1.s ++#ld: -unresolved-symbols=ignore-all ++#readelf: -s ++ ++#... ++[ ]+[0-9]+:[ ]+[0]+[ ]+0[ ]+NOTYPE[ ]+GLOBAL DEFAULT[ ]+UND[ ]+foo ++#pass +--- binutils/ld/testsuite/ld-ia64/error1.s.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/ld/testsuite/ld-ia64/error1.s 2009-03-05 05:57:51.000000000 -0800 +@@ -0,0 +1,30 @@ ++ .explicit ++ .pred.safe_across_calls p1-p5,p16-p63 ++ .text ++ .align 16 ++ .global _start# ++ .proc _start# ++_start: ++ .prologue 12, 32 ++ .mii ++ .save ar.pfs, r33 ++ alloc r33 = ar.pfs, 0, 3, 0, 0 ++ .save rp, r32 ++ mov r32 = b0 ++ mov r34 = r1 ++ .body ++ ;; ++ .bbb ++ nop 0 ++ nop 0 ++ br.call.sptk.many b0 = foo# ++ ;; ++ .mmi ++ nop 0 ++ mov r1 = r34 ++ mov b0 = r32 ++ .mib ++ nop 0 ++ mov ar.pfs = r33 ++ br.ret.sptk.many b0 ++ .endp _start# +--- binutils/ld/testsuite/ld-ia64/error2.d.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/ld/testsuite/ld-ia64/error2.d 2009-03-05 05:57:51.000000000 -0800 +@@ -0,0 +1,7 @@ ++#source: error1.s ++#ld: -pie -unresolved-symbols=ignore-all ++#readelf: -s ++ ++#... ++[ ]+[0-9]+:[ ]+[0]+[ ]+0[ ]+NOTYPE[ ]+GLOBAL DEFAULT[ ]+UND[ ]+foo ++#pass +--- binutils/ld/testsuite/ld-ia64/error3.d.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/ld/testsuite/ld-ia64/error3.d 2009-03-05 05:57:51.000000000 -0800 +@@ -0,0 +1,7 @@ ++#source: error1.s ++#ld: -pie -shared ++#readelf: -s ++ ++#... ++[ ]+[0-9]+:[ ]+[0]+[ ]+0[ ]+NOTYPE[ ]+GLOBAL DEFAULT[ ]+UND[ ]+foo ++#pass +--- binutils/ld/testsuite/ld-ia64/error4.d.error 2009-03-05 05:57:51.000000000 -0800 ++++ binutils/ld/testsuite/ld-ia64/error4.d 2009-03-05 05:57:51.000000000 -0800 +@@ -0,0 +1,3 @@ ++#source: error1.s ++#ld: -shared -pie ++#error: .*undefined reference to `foo' --- binutils-2.20.orig/debian/patches/130_gold_disable_testsuite_build.dpatch +++ binutils-2.20/debian/patches/130_gold_disable_testsuite_build.dpatch @@ -0,0 +1,48 @@ +#!/bin/sh -e +## 130_gold_disable_testsuite_build.dpatch +## +## DP: Description: Disable build of gold/testsuite +## DP: Author: Matthias Klose +## DP: Upstream status: local + +if [ $# -ne 1 ]; then + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1 +fi + +[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts +patch_opts="${patch_opts:--f --no-backup-if-mismatch}" + +case "$1" in + -patch) patch $patch_opts -p1 < $0;; + -unpatch) patch $patch_opts -p1 -R < $0;; + *) + echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" + exit 1;; +esac + +exit 0 + +@DPATCH@ +--- ./gold/Makefile.am~ 2009-10-06 14:35:04.000000000 +0000 ++++ ./gold/Makefile.am 2009-08-24 05:55:55.000000000 +0000 +@@ -2,7 +2,7 @@ + + AUTOMAKE_OPTIONS = foreign + +-SUBDIRS = po testsuite ++SUBDIRS = po + + tooldir = $(exec_prefix)/$(target_alias) + +--- ./gold/Makefile.in~ 2009-10-06 14:35:19.000000000 +0000 ++++ ./gold/Makefile.in 2009-08-24 05:55:55.000000000 +0000 +@@ -327,7 +327,7 @@ + top_builddir = @top_builddir@ + top_srcdir = @top_srcdir@ + AUTOMAKE_OPTIONS = foreign +-SUBDIRS = po testsuite ++SUBDIRS = po + tooldir = $(exec_prefix)/$(target_alias) + ACLOCAL_AMFLAGS = -I ../bfd -I ../config + AM_CFLAGS = $(WARN_CFLAGS) $(LFS_CFLAGS) $(RANDOM_SEED_CFLAGS) --- binutils-2.20.orig/gas/config/tc-arm.c.orig +++ binutils-2.20/gas/config/tc-arm.c.orig @@ -0,0 +1,22739 @@ +/* tc-arm.c -- Assemble for the ARM + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006, 2007, 2008, 2009 + Free Software Foundation, Inc. + Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) + Modified by David Taylor (dtaylor@armltd.co.uk) + Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) + Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) + Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "as.h" +#include +#include +#define NO_RELOC 0 +#include "safe-ctype.h" +#include "subsegs.h" +#include "obstack.h" + +#include "opcode/arm.h" + +#ifdef OBJ_ELF +#include "elf/arm.h" +#include "dw2gencfi.h" +#endif + +#include "dwarf2dbg.h" + +#ifdef OBJ_ELF +/* Must be at least the size of the largest unwind opcode (currently two). */ +#define ARM_OPCODE_CHUNK_SIZE 8 + +/* This structure holds the unwinding state. */ + +static struct +{ + symbolS * proc_start; + symbolS * table_entry; + symbolS * personality_routine; + int personality_index; + /* The segment containing the function. */ + segT saved_seg; + subsegT saved_subseg; + /* Opcodes generated from this function. */ + unsigned char * opcodes; + int opcode_count; + int opcode_alloc; + /* The number of bytes pushed to the stack. */ + offsetT frame_size; + /* We don't add stack adjustment opcodes immediately so that we can merge + multiple adjustments. We can also omit the final adjustment + when using a frame pointer. */ + offsetT pending_offset; + /* These two fields are set by both unwind_movsp and unwind_setfp. They + hold the reg+offset to use when restoring sp from a frame pointer. */ + offsetT fp_offset; + int fp_reg; + /* Nonzero if an unwind_setfp directive has been seen. */ + unsigned fp_used:1; + /* Nonzero if the last opcode restores sp from fp_reg. */ + unsigned sp_restored:1; +} unwind; + +#endif /* OBJ_ELF */ + +/* Results from operand parsing worker functions. */ + +typedef enum +{ + PARSE_OPERAND_SUCCESS, + PARSE_OPERAND_FAIL, + PARSE_OPERAND_FAIL_NO_BACKTRACK +} parse_operand_result; + +enum arm_float_abi +{ + ARM_FLOAT_ABI_HARD, + ARM_FLOAT_ABI_SOFTFP, + ARM_FLOAT_ABI_SOFT +}; + +/* Types of processor to assemble for. */ +#ifndef CPU_DEFAULT +#if defined __XSCALE__ +#define CPU_DEFAULT ARM_ARCH_XSCALE +#else +#if defined __thumb__ +#define CPU_DEFAULT ARM_ARCH_V5T +#endif +#endif +#endif + +#ifndef FPU_DEFAULT +# ifdef TE_LINUX +# define FPU_DEFAULT FPU_ARCH_FPA +# elif defined (TE_NetBSD) +# ifdef OBJ_ELF +# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ +# else + /* Legacy a.out format. */ +# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ +# endif +# elif defined (TE_VXWORKS) +# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ +# else + /* For backwards compatibility, default to FPA. */ +# define FPU_DEFAULT FPU_ARCH_FPA +# endif +#endif /* ifndef FPU_DEFAULT */ + +#define streq(a, b) (strcmp (a, b) == 0) + +static arm_feature_set cpu_variant; +static arm_feature_set arm_arch_used; +static arm_feature_set thumb_arch_used; + +/* Flags stored in private area of BFD structure. */ +static int uses_apcs_26 = FALSE; +static int atpcs = FALSE; +static int support_interwork = FALSE; +static int uses_apcs_float = FALSE; +static int pic_code = FALSE; +static int fix_v4bx = FALSE; +/* Warn on using deprecated features. */ +static int warn_on_deprecated = TRUE; + + +/* Variables that we set while parsing command-line options. Once all + options have been read we re-process these values to set the real + assembly flags. */ +static const arm_feature_set *legacy_cpu = NULL; +static const arm_feature_set *legacy_fpu = NULL; + +static const arm_feature_set *mcpu_cpu_opt = NULL; +static const arm_feature_set *mcpu_fpu_opt = NULL; +static const arm_feature_set *march_cpu_opt = NULL; +static const arm_feature_set *march_fpu_opt = NULL; +static const arm_feature_set *mfpu_opt = NULL; +static const arm_feature_set *object_arch = NULL; + +/* Constants for known architecture features. */ +static const arm_feature_set fpu_default = FPU_DEFAULT; +static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; +static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; +static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; +static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; +static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; +static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; +static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; +static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; + +#ifdef CPU_DEFAULT +static const arm_feature_set cpu_default = CPU_DEFAULT; +#endif + +static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); +static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); +static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); +static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); +static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); +static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); +static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); +static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); +static const arm_feature_set arm_ext_v4t_5 = + ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); +static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); +static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); +static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); +static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); +static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); +static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); +static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); +static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); +static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); +static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); +static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); +static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); +static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); +static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); +static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); +static const arm_feature_set arm_ext_m = + ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0); + +static const arm_feature_set arm_arch_any = ARM_ANY; +static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); +static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; +static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; + +static const arm_feature_set arm_cext_iwmmxt2 = + ARM_FEATURE (0, ARM_CEXT_IWMMXT2); +static const arm_feature_set arm_cext_iwmmxt = + ARM_FEATURE (0, ARM_CEXT_IWMMXT); +static const arm_feature_set arm_cext_xscale = + ARM_FEATURE (0, ARM_CEXT_XSCALE); +static const arm_feature_set arm_cext_maverick = + ARM_FEATURE (0, ARM_CEXT_MAVERICK); +static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); +static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); +static const arm_feature_set fpu_vfp_ext_v1xd = + ARM_FEATURE (0, FPU_VFP_EXT_V1xD); +static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); +static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); +static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); +static const arm_feature_set fpu_vfp_ext_d32 = + ARM_FEATURE (0, FPU_VFP_EXT_D32); +static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); +static const arm_feature_set fpu_vfp_v3_or_neon_ext = + ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); +static const arm_feature_set fpu_neon_fp16 = ARM_FEATURE (0, FPU_NEON_FP16); + +static int mfloat_abi_opt = -1; +/* Record user cpu selection for object attributes. */ +static arm_feature_set selected_cpu = ARM_ARCH_NONE; +/* Must be long enough to hold any of the names in arm_cpus. */ +static char selected_cpu_name[16]; +#ifdef OBJ_ELF +# ifdef EABI_DEFAULT +static int meabi_flags = EABI_DEFAULT; +# else +static int meabi_flags = EF_ARM_EABI_UNKNOWN; +# endif + +static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; + +bfd_boolean +arm_is_eabi (void) +{ + return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); +} +#endif + +#ifdef OBJ_ELF +/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ +symbolS * GOT_symbol; +#endif + +/* 0: assemble for ARM, + 1: assemble for Thumb, + 2: assemble for Thumb even though target CPU does not support thumb + instructions. */ +static int thumb_mode = 0; +/* A value distinct from the possible values for thumb_mode that we + can use to record whether thumb_mode has been copied into the + tc_frag_data field of a frag. */ +#define MODE_RECORDED (1 << 4) + +/* Specifies the intrinsic IT insn behavior mode. */ +enum implicit_it_mode +{ + IMPLICIT_IT_MODE_NEVER = 0x00, + IMPLICIT_IT_MODE_ARM = 0x01, + IMPLICIT_IT_MODE_THUMB = 0x02, + IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) +}; +static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; + +/* If unified_syntax is true, we are processing the new unified + ARM/Thumb syntax. Important differences from the old ARM mode: + + - Immediate operands do not require a # prefix. + - Conditional affixes always appear at the end of the + instruction. (For backward compatibility, those instructions + that formerly had them in the middle, continue to accept them + there.) + - The IT instruction may appear, and if it does is validated + against subsequent conditional affixes. It does not generate + machine code. + + Important differences from the old Thumb mode: + + - Immediate operands do not require a # prefix. + - Most of the V6T2 instructions are only available in unified mode. + - The .N and .W suffixes are recognized and honored (it is an error + if they cannot be honored). + - All instructions set the flags if and only if they have an 's' affix. + - Conditional affixes may be used. They are validated against + preceding IT instructions. Unlike ARM mode, you cannot use a + conditional affix except in the scope of an IT instruction. */ + +static bfd_boolean unified_syntax = FALSE; + +enum neon_el_type +{ + NT_invtype, + NT_untyped, + NT_integer, + NT_float, + NT_poly, + NT_signed, + NT_unsigned +}; + +struct neon_type_el +{ + enum neon_el_type type; + unsigned size; +}; + +#define NEON_MAX_TYPE_ELS 4 + +struct neon_type +{ + struct neon_type_el el[NEON_MAX_TYPE_ELS]; + unsigned elems; +}; + +enum it_instruction_type +{ + OUTSIDE_IT_INSN, + INSIDE_IT_INSN, + INSIDE_IT_LAST_INSN, + IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; + if inside, should be the last one. */ + NEUTRAL_IT_INSN, /* This could be either inside or outside, + i.e. BKPT and NOP. */ + IT_INSN /* The IT insn has been parsed. */ +}; + +struct arm_it +{ + const char * error; + unsigned long instruction; + int size; + int size_req; + int cond; + /* "uncond_value" is set to the value in place of the conditional field in + unconditional versions of the instruction, or -1 if nothing is + appropriate. */ + int uncond_value; + struct neon_type vectype; + /* Set to the opcode if the instruction needs relaxation. + Zero if the instruction is not relaxed. */ + unsigned long relax; + struct + { + bfd_reloc_code_real_type type; + expressionS exp; + int pc_rel; + } reloc; + + enum it_instruction_type it_insn_type; + + struct + { + unsigned reg; + signed int imm; + struct neon_type_el vectype; + unsigned present : 1; /* Operand present. */ + unsigned isreg : 1; /* Operand was a register. */ + unsigned immisreg : 1; /* .imm field is a second register. */ + unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ + unsigned immisalign : 1; /* Immediate is an alignment specifier. */ + unsigned immisfloat : 1; /* Immediate was parsed as a float. */ + /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV + instructions. This allows us to disambiguate ARM <-> vector insns. */ + unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ + unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ + unsigned isquad : 1; /* Operand is Neon quad-precision register. */ + unsigned issingle : 1; /* Operand is VFP single-precision register. */ + unsigned hasreloc : 1; /* Operand has relocation suffix. */ + unsigned writeback : 1; /* Operand has trailing ! */ + unsigned preind : 1; /* Preindexed address. */ + unsigned postind : 1; /* Postindexed address. */ + unsigned negative : 1; /* Index register was negated. */ + unsigned shifted : 1; /* Shift applied to operation. */ + unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ + } operands[6]; +}; + +static struct arm_it inst; + +#define NUM_FLOAT_VALS 8 + +const char * fp_const[] = +{ + "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 +}; + +/* Number of littlenums required to hold an extended precision number. */ +#define MAX_LITTLENUMS 6 + +LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; + +#define FAIL (-1) +#define SUCCESS (0) + +#define SUFF_S 1 +#define SUFF_D 2 +#define SUFF_E 3 +#define SUFF_P 4 + +#define CP_T_X 0x00008000 +#define CP_T_Y 0x00400000 + +#define CONDS_BIT 0x00100000 +#define LOAD_BIT 0x00100000 + +#define DOUBLE_LOAD_FLAG 0x00000001 + +struct asm_cond +{ + const char * template_name; + unsigned long value; +}; + +#define COND_ALWAYS 0xE + +struct asm_psr +{ + const char * template_name; + unsigned long field; +}; + +struct asm_barrier_opt +{ + const char * template_name; + unsigned long value; +}; + +/* The bit that distinguishes CPSR and SPSR. */ +#define SPSR_BIT (1 << 22) + +/* The individual PSR flag bits. */ +#define PSR_c (1 << 16) +#define PSR_x (1 << 17) +#define PSR_s (1 << 18) +#define PSR_f (1 << 19) + +struct reloc_entry +{ + char * name; + bfd_reloc_code_real_type reloc; +}; + +enum vfp_reg_pos +{ + VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, + VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn +}; + +enum vfp_ldstm_type +{ + VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX +}; + +/* Bits for DEFINED field in neon_typed_alias. */ +#define NTA_HASTYPE 1 +#define NTA_HASINDEX 2 + +struct neon_typed_alias +{ + unsigned char defined; + unsigned char index; + struct neon_type_el eltype; +}; + +/* ARM register categories. This includes coprocessor numbers and various + architecture extensions' registers. */ +enum arm_reg_type +{ + REG_TYPE_RN, + REG_TYPE_CP, + REG_TYPE_CN, + REG_TYPE_FN, + REG_TYPE_VFS, + REG_TYPE_VFD, + REG_TYPE_NQ, + REG_TYPE_VFSD, + REG_TYPE_NDQ, + REG_TYPE_NSDQ, + REG_TYPE_VFC, + REG_TYPE_MVF, + REG_TYPE_MVD, + REG_TYPE_MVFX, + REG_TYPE_MVDX, + REG_TYPE_MVAX, + REG_TYPE_DSPSC, + REG_TYPE_MMXWR, + REG_TYPE_MMXWC, + REG_TYPE_MMXWCG, + REG_TYPE_XSCALE, +}; + +/* Structure for a hash table entry for a register. + If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra + information which states whether a vector type or index is specified (for a + register alias created with .dn or .qn). Otherwise NEON should be NULL. */ +struct reg_entry +{ + const char * name; + unsigned char number; + unsigned char type; + unsigned char builtin; + struct neon_typed_alias * neon; +}; + +/* Diagnostics used when we don't get a register of the expected type. */ +const char * const reg_expected_msgs[] = +{ + N_("ARM register expected"), + N_("bad or missing co-processor number"), + N_("co-processor register expected"), + N_("FPA register expected"), + N_("VFP single precision register expected"), + N_("VFP/Neon double precision register expected"), + N_("Neon quad precision register expected"), + N_("VFP single or double precision register expected"), + N_("Neon double or quad precision register expected"), + N_("VFP single, double or Neon quad precision register expected"), + N_("VFP system register expected"), + N_("Maverick MVF register expected"), + N_("Maverick MVD register expected"), + N_("Maverick MVFX register expected"), + N_("Maverick MVDX register expected"), + N_("Maverick MVAX register expected"), + N_("Maverick DSPSC register expected"), + N_("iWMMXt data register expected"), + N_("iWMMXt control register expected"), + N_("iWMMXt scalar register expected"), + N_("XScale accumulator register expected"), +}; + +/* Some well known registers that we refer to directly elsewhere. */ +#define REG_SP 13 +#define REG_LR 14 +#define REG_PC 15 + +/* ARM instructions take 4bytes in the object file, Thumb instructions + take 2: */ +#define INSN_SIZE 4 + +struct asm_opcode +{ + /* Basic string to match. */ + const char * template_name; + + /* Parameters to instruction. */ + unsigned char operands[8]; + + /* Conditional tag - see opcode_lookup. */ + unsigned int tag : 4; + + /* Basic instruction code. */ + unsigned int avalue : 28; + + /* Thumb-format instruction code. */ + unsigned int tvalue; + + /* Which architecture variant provides this instruction. */ + const arm_feature_set * avariant; + const arm_feature_set * tvariant; + + /* Function to call to encode instruction in ARM format. */ + void (* aencode) (void); + + /* Function to call to encode instruction in Thumb format. */ + void (* tencode) (void); +}; + +/* Defines for various bits that we will want to toggle. */ +#define INST_IMMEDIATE 0x02000000 +#define OFFSET_REG 0x02000000 +#define HWOFFSET_IMM 0x00400000 +#define SHIFT_BY_REG 0x00000010 +#define PRE_INDEX 0x01000000 +#define INDEX_UP 0x00800000 +#define WRITE_BACK 0x00200000 +#define LDM_TYPE_2_OR_3 0x00400000 +#define CPSI_MMOD 0x00020000 + +#define LITERAL_MASK 0xf000f000 +#define OPCODE_MASK 0xfe1fffff +#define V4_STR_BIT 0x00000020 + +#define T2_SUBS_PC_LR 0xf3de8f00 + +#define DATA_OP_SHIFT 21 + +#define T2_OPCODE_MASK 0xfe1fffff +#define T2_DATA_OP_SHIFT 21 + +/* Codes to distinguish the arithmetic instructions. */ +#define OPCODE_AND 0 +#define OPCODE_EOR 1 +#define OPCODE_SUB 2 +#define OPCODE_RSB 3 +#define OPCODE_ADD 4 +#define OPCODE_ADC 5 +#define OPCODE_SBC 6 +#define OPCODE_RSC 7 +#define OPCODE_TST 8 +#define OPCODE_TEQ 9 +#define OPCODE_CMP 10 +#define OPCODE_CMN 11 +#define OPCODE_ORR 12 +#define OPCODE_MOV 13 +#define OPCODE_BIC 14 +#define OPCODE_MVN 15 + +#define T2_OPCODE_AND 0 +#define T2_OPCODE_BIC 1 +#define T2_OPCODE_ORR 2 +#define T2_OPCODE_ORN 3 +#define T2_OPCODE_EOR 4 +#define T2_OPCODE_ADD 8 +#define T2_OPCODE_ADC 10 +#define T2_OPCODE_SBC 11 +#define T2_OPCODE_SUB 13 +#define T2_OPCODE_RSB 14 + +#define T_OPCODE_MUL 0x4340 +#define T_OPCODE_TST 0x4200 +#define T_OPCODE_CMN 0x42c0 +#define T_OPCODE_NEG 0x4240 +#define T_OPCODE_MVN 0x43c0 + +#define T_OPCODE_ADD_R3 0x1800 +#define T_OPCODE_SUB_R3 0x1a00 +#define T_OPCODE_ADD_HI 0x4400 +#define T_OPCODE_ADD_ST 0xb000 +#define T_OPCODE_SUB_ST 0xb080 +#define T_OPCODE_ADD_SP 0xa800 +#define T_OPCODE_ADD_PC 0xa000 +#define T_OPCODE_ADD_I8 0x3000 +#define T_OPCODE_SUB_I8 0x3800 +#define T_OPCODE_ADD_I3 0x1c00 +#define T_OPCODE_SUB_I3 0x1e00 + +#define T_OPCODE_ASR_R 0x4100 +#define T_OPCODE_LSL_R 0x4080 +#define T_OPCODE_LSR_R 0x40c0 +#define T_OPCODE_ROR_R 0x41c0 +#define T_OPCODE_ASR_I 0x1000 +#define T_OPCODE_LSL_I 0x0000 +#define T_OPCODE_LSR_I 0x0800 + +#define T_OPCODE_MOV_I8 0x2000 +#define T_OPCODE_CMP_I8 0x2800 +#define T_OPCODE_CMP_LR 0x4280 +#define T_OPCODE_MOV_HR 0x4600 +#define T_OPCODE_CMP_HR 0x4500 + +#define T_OPCODE_LDR_PC 0x4800 +#define T_OPCODE_LDR_SP 0x9800 +#define T_OPCODE_STR_SP 0x9000 +#define T_OPCODE_LDR_IW 0x6800 +#define T_OPCODE_STR_IW 0x6000 +#define T_OPCODE_LDR_IH 0x8800 +#define T_OPCODE_STR_IH 0x8000 +#define T_OPCODE_LDR_IB 0x7800 +#define T_OPCODE_STR_IB 0x7000 +#define T_OPCODE_LDR_RW 0x5800 +#define T_OPCODE_STR_RW 0x5000 +#define T_OPCODE_LDR_RH 0x5a00 +#define T_OPCODE_STR_RH 0x5200 +#define T_OPCODE_LDR_RB 0x5c00 +#define T_OPCODE_STR_RB 0x5400 + +#define T_OPCODE_PUSH 0xb400 +#define T_OPCODE_POP 0xbc00 + +#define T_OPCODE_BRANCH 0xe000 + +#define THUMB_SIZE 2 /* Size of thumb instruction. */ +#define THUMB_PP_PC_LR 0x0100 +#define THUMB_LOAD_BIT 0x0800 +#define THUMB2_LOAD_BIT 0x00100000 + +#define BAD_ARGS _("bad arguments to instruction") +#define BAD_SP _("r13 not allowed here") +#define BAD_PC _("r15 not allowed here") +#define BAD_COND _("instruction cannot be conditional") +#define BAD_OVERLAP _("registers may not be the same") +#define BAD_HIREG _("lo register required") +#define BAD_THUMB32 _("instruction not supported in Thumb16 mode") +#define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); +#define BAD_BRANCH _("branch must be last instruction in IT block") +#define BAD_NOT_IT _("instruction not allowed in IT block") +#define BAD_FPU _("selected FPU does not support instruction") +#define BAD_OUT_IT _("thumb conditional instruction should be in IT block") +#define BAD_IT_COND _("incorrect condition in IT block") +#define BAD_IT_IT _("IT falling in the range of a previous IT block") +#define MISSING_FNSTART _("missing .fnstart before unwinding directive") + +static struct hash_control * arm_ops_hsh; +static struct hash_control * arm_cond_hsh; +static struct hash_control * arm_shift_hsh; +static struct hash_control * arm_psr_hsh; +static struct hash_control * arm_v7m_psr_hsh; +static struct hash_control * arm_reg_hsh; +static struct hash_control * arm_reloc_hsh; +static struct hash_control * arm_barrier_opt_hsh; + +/* Stuff needed to resolve the label ambiguity + As: + ... + label: + may differ from: + ... + label: + */ + +symbolS * last_label_seen; +static int label_is_thumb_function_name = FALSE; + +/* Literal pool structure. Held on a per-section + and per-sub-section basis. */ + +#define MAX_LITERAL_POOL_SIZE 1024 +typedef struct literal_pool +{ + expressionS literals [MAX_LITERAL_POOL_SIZE]; + unsigned int next_free_entry; + unsigned int id; + symbolS * symbol; + segT section; + subsegT sub_section; + struct literal_pool * next; +} literal_pool; + +/* Pointer to a linked list of literal pools. */ +literal_pool * list_of_pools = NULL; + +#ifdef OBJ_ELF +# define now_it seg_info (now_seg)->tc_segment_info_data.current_it +#else +static struct current_it now_it; +#endif + +static inline int +now_it_compatible (int cond) +{ + return (cond & ~1) == (now_it.cc & ~1); +} + +static inline int +conditional_insn (void) +{ + return inst.cond != COND_ALWAYS; +} + +static int in_it_block (void); + +static int handle_it_state (void); + +static void force_automatic_it_block_close (void); + +static void it_fsm_post_encode (void); + +#define set_it_insn_type(type) \ + do \ + { \ + inst.it_insn_type = type; \ + if (handle_it_state () == FAIL) \ + return; \ + } \ + while (0) + +#define set_it_insn_type_nonvoid(type, failret) \ + do \ + { \ + inst.it_insn_type = type; \ + if (handle_it_state () == FAIL) \ + return failret; \ + } \ + while(0) + +#define set_it_insn_type_last() \ + do \ + { \ + if (inst.cond == COND_ALWAYS) \ + set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ + else \ + set_it_insn_type (INSIDE_IT_LAST_INSN); \ + } \ + while (0) + +/* Pure syntax. */ + +/* This array holds the chars that always start a comment. If the + pre-processor is disabled, these aren't very useful. */ +const char comment_chars[] = "@"; + +/* This array holds the chars that only start a comment at the beginning of + a line. If the line seems to have the form '# 123 filename' + .line and .file directives will appear in the pre-processed output. */ +/* Note that input_file.c hand checks for '#' at the beginning of the + first line of the input file. This is because the compiler outputs + #NO_APP at the beginning of its output. */ +/* Also note that comments like this one will always work. */ +const char line_comment_chars[] = "#"; + +const char line_separator_chars[] = ";"; + +/* Chars that can be used to separate mant + from exp in floating point numbers. */ +const char EXP_CHARS[] = "eE"; + +/* Chars that mean this number is a floating point constant. */ +/* As in 0f12.456 */ +/* or 0d1.2345e12 */ + +const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; + +/* Prefix characters that indicate the start of an immediate + value. */ +#define is_immediate_prefix(C) ((C) == '#' || (C) == '$') + +/* Separator character handling. */ + +#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) + +static inline int +skip_past_char (char ** str, char c) +{ + if (**str == c) + { + (*str)++; + return SUCCESS; + } + else + return FAIL; +} + +#define skip_past_comma(str) skip_past_char (str, ',') + +/* Arithmetic expressions (possibly involving symbols). */ + +/* Return TRUE if anything in the expression is a bignum. */ + +static int +walk_no_bignums (symbolS * sp) +{ + if (symbol_get_value_expression (sp)->X_op == O_big) + return 1; + + if (symbol_get_value_expression (sp)->X_add_symbol) + { + return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) + || (symbol_get_value_expression (sp)->X_op_symbol + && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); + } + + return 0; +} + +static int in_my_get_expression = 0; + +/* Third argument to my_get_expression. */ +#define GE_NO_PREFIX 0 +#define GE_IMM_PREFIX 1 +#define GE_OPT_PREFIX 2 +/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) + immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ +#define GE_OPT_PREFIX_BIG 3 + +static int +my_get_expression (expressionS * ep, char ** str, int prefix_mode) +{ + char * save_in; + segT seg; + + /* In unified syntax, all prefixes are optional. */ + if (unified_syntax) + prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode + : GE_OPT_PREFIX; + + switch (prefix_mode) + { + case GE_NO_PREFIX: break; + case GE_IMM_PREFIX: + if (!is_immediate_prefix (**str)) + { + inst.error = _("immediate expression requires a # prefix"); + return FAIL; + } + (*str)++; + break; + case GE_OPT_PREFIX: + case GE_OPT_PREFIX_BIG: + if (is_immediate_prefix (**str)) + (*str)++; + break; + default: abort (); + } + + memset (ep, 0, sizeof (expressionS)); + + save_in = input_line_pointer; + input_line_pointer = *str; + in_my_get_expression = 1; + seg = expression (ep); + in_my_get_expression = 0; + + if (ep->X_op == O_illegal || ep->X_op == O_absent) + { + /* We found a bad or missing expression in md_operand(). */ + *str = input_line_pointer; + input_line_pointer = save_in; + if (inst.error == NULL) + inst.error = (ep->X_op == O_absent + ? _("missing expression") :_("bad expression")); + return 1; + } + +#ifdef OBJ_AOUT + if (seg != absolute_section + && seg != text_section + && seg != data_section + && seg != bss_section + && seg != undefined_section) + { + inst.error = _("bad segment"); + *str = input_line_pointer; + input_line_pointer = save_in; + return 1; + } +#endif + + /* Get rid of any bignums now, so that we don't generate an error for which + we can't establish a line number later on. Big numbers are never valid + in instructions, which is where this routine is always called. */ + if (prefix_mode != GE_OPT_PREFIX_BIG + && (ep->X_op == O_big + || (ep->X_add_symbol + && (walk_no_bignums (ep->X_add_symbol) + || (ep->X_op_symbol + && walk_no_bignums (ep->X_op_symbol)))))) + { + inst.error = _("invalid constant"); + *str = input_line_pointer; + input_line_pointer = save_in; + return 1; + } + + *str = input_line_pointer; + input_line_pointer = save_in; + return 0; +} + +/* Turn a string in input_line_pointer into a floating point constant + of type TYPE, and store the appropriate bytes in *LITP. The number + of LITTLENUMS emitted is stored in *SIZEP. An error message is + returned, or NULL on OK. + + Note that fp constants aren't represent in the normal way on the ARM. + In big endian mode, things are as expected. However, in little endian + mode fp constants are big-endian word-wise, and little-endian byte-wise + within the words. For example, (double) 1.1 in big endian mode is + the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is + the byte sequence 99 99 f1 3f 9a 99 99 99. + + ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ + +char * +md_atof (int type, char * litP, int * sizeP) +{ + int prec; + LITTLENUM_TYPE words[MAX_LITTLENUMS]; + char *t; + int i; + + switch (type) + { + case 'f': + case 'F': + case 's': + case 'S': + prec = 2; + break; + + case 'd': + case 'D': + case 'r': + case 'R': + prec = 4; + break; + + case 'x': + case 'X': + prec = 5; + break; + + case 'p': + case 'P': + prec = 5; + break; + + default: + *sizeP = 0; + return _("Unrecognized or unsupported floating point constant"); + } + + t = atof_ieee (input_line_pointer, type, words); + if (t) + input_line_pointer = t; + *sizeP = prec * sizeof (LITTLENUM_TYPE); + + if (target_big_endian) + { + for (i = 0; i < prec; i++) + { + md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + } + else + { + if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) + for (i = prec - 1; i >= 0; i--) + { + md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + else + /* For a 4 byte float the order of elements in `words' is 1 0. + For an 8 byte float the order is 1 0 3 2. */ + for (i = 0; i < prec; i += 2) + { + md_number_to_chars (litP, (valueT) words[i + 1], + sizeof (LITTLENUM_TYPE)); + md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), + (valueT) words[i], sizeof (LITTLENUM_TYPE)); + litP += 2 * sizeof (LITTLENUM_TYPE); + } + } + + return NULL; +} + +/* We handle all bad expressions here, so that we can report the faulty + instruction in the error message. */ +void +md_operand (expressionS * expr) +{ + if (in_my_get_expression) + expr->X_op = O_illegal; +} + +/* Immediate values. */ + +/* Generic immediate-value read function for use in directives. + Accepts anything that 'expression' can fold to a constant. + *val receives the number. */ +#ifdef OBJ_ELF +static int +immediate_for_directive (int *val) +{ + expressionS exp; + exp.X_op = O_illegal; + + if (is_immediate_prefix (*input_line_pointer)) + { + input_line_pointer++; + expression (&exp); + } + + if (exp.X_op != O_constant) + { + as_bad (_("expected #constant")); + ignore_rest_of_line (); + return FAIL; + } + *val = exp.X_add_number; + return SUCCESS; +} +#endif + +/* Register parsing. */ + +/* Generic register parser. CCP points to what should be the + beginning of a register name. If it is indeed a valid register + name, advance CCP over it and return the reg_entry structure; + otherwise return NULL. Does not issue diagnostics. */ + +static struct reg_entry * +arm_reg_parse_multi (char **ccp) +{ + char *start = *ccp; + char *p; + struct reg_entry *reg; + +#ifdef REGISTER_PREFIX + if (*start != REGISTER_PREFIX) + return NULL; + start++; +#endif +#ifdef OPTIONAL_REGISTER_PREFIX + if (*start == OPTIONAL_REGISTER_PREFIX) + start++; +#endif + + p = start; + if (!ISALPHA (*p) || !is_name_beginner (*p)) + return NULL; + + do + p++; + while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); + + reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); + + if (!reg) + return NULL; + + *ccp = p; + return reg; +} + +static int +arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, + enum arm_reg_type type) +{ + /* Alternative syntaxes are accepted for a few register classes. */ + switch (type) + { + case REG_TYPE_MVF: + case REG_TYPE_MVD: + case REG_TYPE_MVFX: + case REG_TYPE_MVDX: + /* Generic coprocessor register names are allowed for these. */ + if (reg && reg->type == REG_TYPE_CN) + return reg->number; + break; + + case REG_TYPE_CP: + /* For backward compatibility, a bare number is valid here. */ + { + unsigned long processor = strtoul (start, ccp, 10); + if (*ccp != start && processor <= 15) + return processor; + } + + case REG_TYPE_MMXWC: + /* WC includes WCG. ??? I'm not sure this is true for all + instructions that take WC registers. */ + if (reg && reg->type == REG_TYPE_MMXWCG) + return reg->number; + break; + + default: + break; + } + + return FAIL; +} + +/* As arm_reg_parse_multi, but the register must be of type TYPE, and the + return value is the register number or FAIL. */ + +static int +arm_reg_parse (char **ccp, enum arm_reg_type type) +{ + char *start = *ccp; + struct reg_entry *reg = arm_reg_parse_multi (ccp); + int ret; + + /* Do not allow a scalar (reg+index) to parse as a register. */ + if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) + return FAIL; + + if (reg && reg->type == type) + return reg->number; + + if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) + return ret; + + *ccp = start; + return FAIL; +} + +/* Parse a Neon type specifier. *STR should point at the leading '.' + character. Does no verification at this stage that the type fits the opcode + properly. E.g., + + .i32.i32.s16 + .s32.f32 + .u16 + + Can all be legally parsed by this function. + + Fills in neon_type struct pointer with parsed information, and updates STR + to point after the parsed type specifier. Returns SUCCESS if this was a legal + type, FAIL if not. */ + +static int +parse_neon_type (struct neon_type *type, char **str) +{ + char *ptr = *str; + + if (type) + type->elems = 0; + + while (type->elems < NEON_MAX_TYPE_ELS) + { + enum neon_el_type thistype = NT_untyped; + unsigned thissize = -1u; + + if (*ptr != '.') + break; + + ptr++; + + /* Just a size without an explicit type. */ + if (ISDIGIT (*ptr)) + goto parsesize; + + switch (TOLOWER (*ptr)) + { + case 'i': thistype = NT_integer; break; + case 'f': thistype = NT_float; break; + case 'p': thistype = NT_poly; break; + case 's': thistype = NT_signed; break; + case 'u': thistype = NT_unsigned; break; + case 'd': + thistype = NT_float; + thissize = 64; + ptr++; + goto done; + default: + as_bad (_("unexpected character `%c' in type specifier"), *ptr); + return FAIL; + } + + ptr++; + + /* .f is an abbreviation for .f32. */ + if (thistype == NT_float && !ISDIGIT (*ptr)) + thissize = 32; + else + { + parsesize: + thissize = strtoul (ptr, &ptr, 10); + + if (thissize != 8 && thissize != 16 && thissize != 32 + && thissize != 64) + { + as_bad (_("bad size %d in type specifier"), thissize); + return FAIL; + } + } + + done: + if (type) + { + type->el[type->elems].type = thistype; + type->el[type->elems].size = thissize; + type->elems++; + } + } + + /* Empty/missing type is not a successful parse. */ + if (type->elems == 0) + return FAIL; + + *str = ptr; + + return SUCCESS; +} + +/* Errors may be set multiple times during parsing or bit encoding + (particularly in the Neon bits), but usually the earliest error which is set + will be the most meaningful. Avoid overwriting it with later (cascading) + errors by calling this function. */ + +static void +first_error (const char *err) +{ + if (!inst.error) + inst.error = err; +} + +/* Parse a single type, e.g. ".s32", leading period included. */ +static int +parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) +{ + char *str = *ccp; + struct neon_type optype; + + if (*str == '.') + { + if (parse_neon_type (&optype, &str) == SUCCESS) + { + if (optype.elems == 1) + *vectype = optype.el[0]; + else + { + first_error (_("only one type should be specified for operand")); + return FAIL; + } + } + else + { + first_error (_("vector type expected")); + return FAIL; + } + } + else + return FAIL; + + *ccp = str; + + return SUCCESS; +} + +/* Special meanings for indices (which have a range of 0-7), which will fit into + a 4-bit integer. */ + +#define NEON_ALL_LANES 15 +#define NEON_INTERLEAVE_LANES 14 + +/* Parse either a register or a scalar, with an optional type. Return the + register number, and optionally fill in the actual type of the register + when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and + type/index information in *TYPEINFO. */ + +static int +parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, + enum arm_reg_type *rtype, + struct neon_typed_alias *typeinfo) +{ + char *str = *ccp; + struct reg_entry *reg = arm_reg_parse_multi (&str); + struct neon_typed_alias atype; + struct neon_type_el parsetype; + + atype.defined = 0; + atype.index = -1; + atype.eltype.type = NT_invtype; + atype.eltype.size = -1; + + /* Try alternate syntax for some types of register. Note these are mutually + exclusive with the Neon syntax extensions. */ + if (reg == NULL) + { + int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); + if (altreg != FAIL) + *ccp = str; + if (typeinfo) + *typeinfo = atype; + return altreg; + } + + /* Undo polymorphism when a set of register types may be accepted. */ + if ((type == REG_TYPE_NDQ + && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) + || (type == REG_TYPE_VFSD + && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) + || (type == REG_TYPE_NSDQ + && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD + || reg->type == REG_TYPE_NQ)) + || (type == REG_TYPE_MMXWC + && (reg->type == REG_TYPE_MMXWCG))) + type = reg->type; + + if (type != reg->type) + return FAIL; + + if (reg->neon) + atype = *reg->neon; + + if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) + { + if ((atype.defined & NTA_HASTYPE) != 0) + { + first_error (_("can't redefine type for operand")); + return FAIL; + } + atype.defined |= NTA_HASTYPE; + atype.eltype = parsetype; + } + + if (skip_past_char (&str, '[') == SUCCESS) + { + if (type != REG_TYPE_VFD) + { + first_error (_("only D registers may be indexed")); + return FAIL; + } + + if ((atype.defined & NTA_HASINDEX) != 0) + { + first_error (_("can't change index for operand")); + return FAIL; + } + + atype.defined |= NTA_HASINDEX; + + if (skip_past_char (&str, ']') == SUCCESS) + atype.index = NEON_ALL_LANES; + else + { + expressionS exp; + + my_get_expression (&exp, &str, GE_NO_PREFIX); + + if (exp.X_op != O_constant) + { + first_error (_("constant expression required")); + return FAIL; + } + + if (skip_past_char (&str, ']') == FAIL) + return FAIL; + + atype.index = exp.X_add_number; + } + } + + if (typeinfo) + *typeinfo = atype; + + if (rtype) + *rtype = type; + + *ccp = str; + + return reg->number; +} + +/* Like arm_reg_parse, but allow allow the following extra features: + - If RTYPE is non-zero, return the (possibly restricted) type of the + register (e.g. Neon double or quad reg when either has been requested). + - If this is a Neon vector type with additional type information, fill + in the struct pointed to by VECTYPE (if non-NULL). + This function will fault on encountering a scalar. */ + +static int +arm_typed_reg_parse (char **ccp, enum arm_reg_type type, + enum arm_reg_type *rtype, struct neon_type_el *vectype) +{ + struct neon_typed_alias atype; + char *str = *ccp; + int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); + + if (reg == FAIL) + return FAIL; + + /* Do not allow a scalar (reg+index) to parse as a register. */ + if ((atype.defined & NTA_HASINDEX) != 0) + { + first_error (_("register operand expected, but got scalar")); + return FAIL; + } + + if (vectype) + *vectype = atype.eltype; + + *ccp = str; + + return reg; +} + +#define NEON_SCALAR_REG(X) ((X) >> 4) +#define NEON_SCALAR_INDEX(X) ((X) & 15) + +/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't + have enough information to be able to do a good job bounds-checking. So, we + just do easy checks here, and do further checks later. */ + +static int +parse_scalar (char **ccp, int elsize, struct neon_type_el *type) +{ + int reg; + char *str = *ccp; + struct neon_typed_alias atype; + + reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); + + if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) + return FAIL; + + if (atype.index == NEON_ALL_LANES) + { + first_error (_("scalar must have an index")); + return FAIL; + } + else if (atype.index >= 64 / elsize) + { + first_error (_("scalar index out of range")); + return FAIL; + } + + if (type) + *type = atype.eltype; + + *ccp = str; + + return reg * 16 + atype.index; +} + +/* Parse an ARM register list. Returns the bitmask, or FAIL. */ + +static long +parse_reg_list (char ** strp) +{ + char * str = * strp; + long range = 0; + int another_range; + + /* We come back here if we get ranges concatenated by '+' or '|'. */ + do + { + another_range = 0; + + if (*str == '{') + { + int in_range = 0; + int cur_reg = -1; + + str++; + do + { + int reg; + + if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) + { + first_error (_(reg_expected_msgs[REG_TYPE_RN])); + return FAIL; + } + + if (in_range) + { + int i; + + if (reg <= cur_reg) + { + first_error (_("bad range in register list")); + return FAIL; + } + + for (i = cur_reg + 1; i < reg; i++) + { + if (range & (1 << i)) + as_tsktsk + (_("Warning: duplicated register (r%d) in register list"), + i); + else + range |= 1 << i; + } + in_range = 0; + } + + if (range & (1 << reg)) + as_tsktsk (_("Warning: duplicated register (r%d) in register list"), + reg); + else if (reg <= cur_reg) + as_tsktsk (_("Warning: register range not in ascending order")); + + range |= 1 << reg; + cur_reg = reg; + } + while (skip_past_comma (&str) != FAIL + || (in_range = 1, *str++ == '-')); + str--; + + if (*str++ != '}') + { + first_error (_("missing `}'")); + return FAIL; + } + } + else + { + expressionS expr; + + if (my_get_expression (&expr, &str, GE_NO_PREFIX)) + return FAIL; + + if (expr.X_op == O_constant) + { + if (expr.X_add_number + != (expr.X_add_number & 0x0000ffff)) + { + inst.error = _("invalid register mask"); + return FAIL; + } + + if ((range & expr.X_add_number) != 0) + { + int regno = range & expr.X_add_number; + + regno &= -regno; + regno = (1 << regno) - 1; + as_tsktsk + (_("Warning: duplicated register (r%d) in register list"), + regno); + } + + range |= expr.X_add_number; + } + else + { + if (inst.reloc.type != 0) + { + inst.error = _("expression too complex"); + return FAIL; + } + + memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); + inst.reloc.type = BFD_RELOC_ARM_MULTI; + inst.reloc.pc_rel = 0; + } + } + + if (*str == '|' || *str == '+') + { + str++; + another_range = 1; + } + } + while (another_range); + + *strp = str; + return range; +} + +/* Types of registers in a list. */ + +enum reg_list_els +{ + REGLIST_VFP_S, + REGLIST_VFP_D, + REGLIST_NEON_D +}; + +/* Parse a VFP register list. If the string is invalid return FAIL. + Otherwise return the number of registers, and set PBASE to the first + register. Parses registers of type ETYPE. + If REGLIST_NEON_D is used, several syntax enhancements are enabled: + - Q registers can be used to specify pairs of D registers + - { } can be omitted from around a singleton register list + FIXME: This is not implemented, as it would require backtracking in + some cases, e.g.: + vtbl.8 d3,d4,d5 + This could be done (the meaning isn't really ambiguous), but doesn't + fit in well with the current parsing framework. + - 32 D registers may be used (also true for VFPv3). + FIXME: Types are ignored in these register lists, which is probably a + bug. */ + +static int +parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) +{ + char *str = *ccp; + int base_reg; + int new_base; + enum arm_reg_type regtype = 0; + int max_regs = 0; + int count = 0; + int warned = 0; + unsigned long mask = 0; + int i; + + if (*str != '{') + { + inst.error = _("expecting {"); + return FAIL; + } + + str++; + + switch (etype) + { + case REGLIST_VFP_S: + regtype = REG_TYPE_VFS; + max_regs = 32; + break; + + case REGLIST_VFP_D: + regtype = REG_TYPE_VFD; + break; + + case REGLIST_NEON_D: + regtype = REG_TYPE_NDQ; + break; + } + + if (etype != REGLIST_VFP_S) + { + /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ + if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) + { + max_regs = 32; + if (thumb_mode) + ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, + fpu_vfp_ext_d32); + else + ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, + fpu_vfp_ext_d32); + } + else + max_regs = 16; + } + + base_reg = max_regs; + + do + { + int setmask = 1, addregs = 1; + + new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); + + if (new_base == FAIL) + { + first_error (_(reg_expected_msgs[regtype])); + return FAIL; + } + + if (new_base >= max_regs) + { + first_error (_("register out of range in list")); + return FAIL; + } + + /* Note: a value of 2 * n is returned for the register Q. */ + if (regtype == REG_TYPE_NQ) + { + setmask = 3; + addregs = 2; + } + + if (new_base < base_reg) + base_reg = new_base; + + if (mask & (setmask << new_base)) + { + first_error (_("invalid register list")); + return FAIL; + } + + if ((mask >> new_base) != 0 && ! warned) + { + as_tsktsk (_("register list not in ascending order")); + warned = 1; + } + + mask |= setmask << new_base; + count += addregs; + + if (*str == '-') /* We have the start of a range expression */ + { + int high_range; + + str++; + + if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) + == FAIL) + { + inst.error = gettext (reg_expected_msgs[regtype]); + return FAIL; + } + + if (high_range >= max_regs) + { + first_error (_("register out of range in list")); + return FAIL; + } + + if (regtype == REG_TYPE_NQ) + high_range = high_range + 1; + + if (high_range <= new_base) + { + inst.error = _("register range not in ascending order"); + return FAIL; + } + + for (new_base += addregs; new_base <= high_range; new_base += addregs) + { + if (mask & (setmask << new_base)) + { + inst.error = _("invalid register list"); + return FAIL; + } + + mask |= setmask << new_base; + count += addregs; + } + } + } + while (skip_past_comma (&str) != FAIL); + + str++; + + /* Sanity check -- should have raised a parse error above. */ + if (count == 0 || count > max_regs) + abort (); + + *pbase = base_reg; + + /* Final test -- the registers must be consecutive. */ + mask >>= base_reg; + for (i = 0; i < count; i++) + { + if ((mask & (1u << i)) == 0) + { + inst.error = _("non-contiguous register range"); + return FAIL; + } + } + + *ccp = str; + + return count; +} + +/* True if two alias types are the same. */ + +static bfd_boolean +neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) +{ + if (!a && !b) + return TRUE; + + if (!a || !b) + return FALSE; + + if (a->defined != b->defined) + return FALSE; + + if ((a->defined & NTA_HASTYPE) != 0 + && (a->eltype.type != b->eltype.type + || a->eltype.size != b->eltype.size)) + return FALSE; + + if ((a->defined & NTA_HASINDEX) != 0 + && (a->index != b->index)) + return FALSE; + + return TRUE; +} + +/* Parse element/structure lists for Neon VLD and VST instructions. + The base register is put in *PBASE. + The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of + the return value. + The register stride (minus one) is put in bit 4 of the return value. + Bits [6:5] encode the list length (minus one). + The type of the list elements is put in *ELTYPE, if non-NULL. */ + +#define NEON_LANE(X) ((X) & 0xf) +#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) +#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) + +static int +parse_neon_el_struct_list (char **str, unsigned *pbase, + struct neon_type_el *eltype) +{ + char *ptr = *str; + int base_reg = -1; + int reg_incr = -1; + int count = 0; + int lane = -1; + int leading_brace = 0; + enum arm_reg_type rtype = REG_TYPE_NDQ; + int addregs = 1; + const char *const incr_error = _("register stride must be 1 or 2"); + const char *const type_error = _("mismatched element/structure types in list"); + struct neon_typed_alias firsttype; + + if (skip_past_char (&ptr, '{') == SUCCESS) + leading_brace = 1; + + do + { + struct neon_typed_alias atype; + int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); + + if (getreg == FAIL) + { + first_error (_(reg_expected_msgs[rtype])); + return FAIL; + } + + if (base_reg == -1) + { + base_reg = getreg; + if (rtype == REG_TYPE_NQ) + { + reg_incr = 1; + addregs = 2; + } + firsttype = atype; + } + else if (reg_incr == -1) + { + reg_incr = getreg - base_reg; + if (reg_incr < 1 || reg_incr > 2) + { + first_error (_(incr_error)); + return FAIL; + } + } + else if (getreg != base_reg + reg_incr * count) + { + first_error (_(incr_error)); + return FAIL; + } + + if (! neon_alias_types_same (&atype, &firsttype)) + { + first_error (_(type_error)); + return FAIL; + } + + /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list + modes. */ + if (ptr[0] == '-') + { + struct neon_typed_alias htype; + int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; + if (lane == -1) + lane = NEON_INTERLEAVE_LANES; + else if (lane != NEON_INTERLEAVE_LANES) + { + first_error (_(type_error)); + return FAIL; + } + if (reg_incr == -1) + reg_incr = 1; + else if (reg_incr != 1) + { + first_error (_("don't use Rn-Rm syntax with non-unit stride")); + return FAIL; + } + ptr++; + hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); + if (hireg == FAIL) + { + first_error (_(reg_expected_msgs[rtype])); + return FAIL; + } + if (! neon_alias_types_same (&htype, &firsttype)) + { + first_error (_(type_error)); + return FAIL; + } + count += hireg + dregs - getreg; + continue; + } + + /* If we're using Q registers, we can't use [] or [n] syntax. */ + if (rtype == REG_TYPE_NQ) + { + count += 2; + continue; + } + + if ((atype.defined & NTA_HASINDEX) != 0) + { + if (lane == -1) + lane = atype.index; + else if (lane != atype.index) + { + first_error (_(type_error)); + return FAIL; + } + } + else if (lane == -1) + lane = NEON_INTERLEAVE_LANES; + else if (lane != NEON_INTERLEAVE_LANES) + { + first_error (_(type_error)); + return FAIL; + } + count++; + } + while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); + + /* No lane set by [x]. We must be interleaving structures. */ + if (lane == -1) + lane = NEON_INTERLEAVE_LANES; + + /* Sanity check. */ + if (lane == -1 || base_reg == -1 || count < 1 || count > 4 + || (count > 1 && reg_incr == -1)) + { + first_error (_("error parsing element/structure list")); + return FAIL; + } + + if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) + { + first_error (_("expected }")); + return FAIL; + } + + if (reg_incr == -1) + reg_incr = 1; + + if (eltype) + *eltype = firsttype.eltype; + + *pbase = base_reg; + *str = ptr; + + return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); +} + +/* Parse an explicit relocation suffix on an expression. This is + either nothing, or a word in parentheses. Note that if !OBJ_ELF, + arm_reloc_hsh contains no entries, so this function can only + succeed if there is no () after the word. Returns -1 on error, + BFD_RELOC_UNUSED if there wasn't any suffix. */ +static int +parse_reloc (char **str) +{ + struct reloc_entry *r; + char *p, *q; + + if (**str != '(') + return BFD_RELOC_UNUSED; + + p = *str + 1; + q = p; + + while (*q && *q != ')' && *q != ',') + q++; + if (*q != ')') + return -1; + + if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) + return -1; + + *str = q + 1; + return r->reloc; +} + +/* Directives: register aliases. */ + +static struct reg_entry * +insert_reg_alias (char *str, int number, int type) +{ + struct reg_entry *new_reg; + const char *name; + + if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) + { + if (new_reg->builtin) + as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); + + /* Only warn about a redefinition if it's not defined as the + same register. */ + else if (new_reg->number != number || new_reg->type != type) + as_warn (_("ignoring redefinition of register alias '%s'"), str); + + return NULL; + } + + name = xstrdup (str); + new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); + + new_reg->name = name; + new_reg->number = number; + new_reg->type = type; + new_reg->builtin = FALSE; + new_reg->neon = NULL; + + if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) + abort (); + + return new_reg; +} + +static void +insert_neon_reg_alias (char *str, int number, int type, + struct neon_typed_alias *atype) +{ + struct reg_entry *reg = insert_reg_alias (str, number, type); + + if (!reg) + { + first_error (_("attempt to redefine typed alias")); + return; + } + + if (atype) + { + reg->neon = xmalloc (sizeof (struct neon_typed_alias)); + *reg->neon = *atype; + } +} + +/* Look for the .req directive. This is of the form: + + new_register_name .req existing_register_name + + If we find one, or if it looks sufficiently like one that we want to + handle any error here, return TRUE. Otherwise return FALSE. */ + +static bfd_boolean +create_register_alias (char * newname, char *p) +{ + struct reg_entry *old; + char *oldname, *nbuf; + size_t nlen; + + /* The input scrubber ensures that whitespace after the mnemonic is + collapsed to single spaces. */ + oldname = p; + if (strncmp (oldname, " .req ", 6) != 0) + return FALSE; + + oldname += 6; + if (*oldname == '\0') + return FALSE; + + old = hash_find (arm_reg_hsh, oldname); + if (!old) + { + as_warn (_("unknown register '%s' -- .req ignored"), oldname); + return TRUE; + } + + /* If TC_CASE_SENSITIVE is defined, then newname already points to + the desired alias name, and p points to its end. If not, then + the desired alias name is in the global original_case_string. */ +#ifdef TC_CASE_SENSITIVE + nlen = p - newname; +#else + newname = original_case_string; + nlen = strlen (newname); +#endif + + nbuf = alloca (nlen + 1); + memcpy (nbuf, newname, nlen); + nbuf[nlen] = '\0'; + + /* Create aliases under the new name as stated; an all-lowercase + version of the new name; and an all-uppercase version of the new + name. */ + if (insert_reg_alias (nbuf, old->number, old->type) != NULL) + { + for (p = nbuf; *p; p++) + *p = TOUPPER (*p); + + if (strncmp (nbuf, newname, nlen)) + { + /* If this attempt to create an additional alias fails, do not bother + trying to create the all-lower case alias. We will fail and issue + a second, duplicate error message. This situation arises when the + programmer does something like: + foo .req r0 + Foo .req r1 + The second .req creates the "Foo" alias but then fails to create + the artificial FOO alias because it has already been created by the + first .req. */ + if (insert_reg_alias (nbuf, old->number, old->type) == NULL) + return TRUE; + } + + for (p = nbuf; *p; p++) + *p = TOLOWER (*p); + + if (strncmp (nbuf, newname, nlen)) + insert_reg_alias (nbuf, old->number, old->type); + } + + return TRUE; +} + +/* Create a Neon typed/indexed register alias using directives, e.g.: + X .dn d5.s32[1] + Y .qn 6.s16 + Z .dn d7 + T .dn Z[0] + These typed registers can be used instead of the types specified after the + Neon mnemonic, so long as all operands given have types. Types can also be + specified directly, e.g.: + vadd d0.s32, d1.s32, d2.s32 */ + +static bfd_boolean +create_neon_reg_alias (char *newname, char *p) +{ + enum arm_reg_type basetype; + struct reg_entry *basereg; + struct reg_entry mybasereg; + struct neon_type ntype; + struct neon_typed_alias typeinfo; + char *namebuf, *nameend; + int namelen; + + typeinfo.defined = 0; + typeinfo.eltype.type = NT_invtype; + typeinfo.eltype.size = -1; + typeinfo.index = -1; + + nameend = p; + + if (strncmp (p, " .dn ", 5) == 0) + basetype = REG_TYPE_VFD; + else if (strncmp (p, " .qn ", 5) == 0) + basetype = REG_TYPE_NQ; + else + return FALSE; + + p += 5; + + if (*p == '\0') + return FALSE; + + basereg = arm_reg_parse_multi (&p); + + if (basereg && basereg->type != basetype) + { + as_bad (_("bad type for register")); + return FALSE; + } + + if (basereg == NULL) + { + expressionS exp; + /* Try parsing as an integer. */ + my_get_expression (&exp, &p, GE_NO_PREFIX); + if (exp.X_op != O_constant) + { + as_bad (_("expression must be constant")); + return FALSE; + } + basereg = &mybasereg; + basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 + : exp.X_add_number; + basereg->neon = 0; + } + + if (basereg->neon) + typeinfo = *basereg->neon; + + if (parse_neon_type (&ntype, &p) == SUCCESS) + { + /* We got a type. */ + if (typeinfo.defined & NTA_HASTYPE) + { + as_bad (_("can't redefine the type of a register alias")); + return FALSE; + } + + typeinfo.defined |= NTA_HASTYPE; + if (ntype.elems != 1) + { + as_bad (_("you must specify a single type only")); + return FALSE; + } + typeinfo.eltype = ntype.el[0]; + } + + if (skip_past_char (&p, '[') == SUCCESS) + { + expressionS exp; + /* We got a scalar index. */ + + if (typeinfo.defined & NTA_HASINDEX) + { + as_bad (_("can't redefine the index of a scalar alias")); + return FALSE; + } + + my_get_expression (&exp, &p, GE_NO_PREFIX); + + if (exp.X_op != O_constant) + { + as_bad (_("scalar index must be constant")); + return FALSE; + } + + typeinfo.defined |= NTA_HASINDEX; + typeinfo.index = exp.X_add_number; + + if (skip_past_char (&p, ']') == FAIL) + { + as_bad (_("expecting ]")); + return FALSE; + } + } + + namelen = nameend - newname; + namebuf = alloca (namelen + 1); + strncpy (namebuf, newname, namelen); + namebuf[namelen] = '\0'; + + insert_neon_reg_alias (namebuf, basereg->number, basetype, + typeinfo.defined != 0 ? &typeinfo : NULL); + + /* Insert name in all uppercase. */ + for (p = namebuf; *p; p++) + *p = TOUPPER (*p); + + if (strncmp (namebuf, newname, namelen)) + insert_neon_reg_alias (namebuf, basereg->number, basetype, + typeinfo.defined != 0 ? &typeinfo : NULL); + + /* Insert name in all lowercase. */ + for (p = namebuf; *p; p++) + *p = TOLOWER (*p); + + if (strncmp (namebuf, newname, namelen)) + insert_neon_reg_alias (namebuf, basereg->number, basetype, + typeinfo.defined != 0 ? &typeinfo : NULL); + + return TRUE; +} + +/* Should never be called, as .req goes between the alias and the + register name, not at the beginning of the line. */ + +static void +s_req (int a ATTRIBUTE_UNUSED) +{ + as_bad (_("invalid syntax for .req directive")); +} + +static void +s_dn (int a ATTRIBUTE_UNUSED) +{ + as_bad (_("invalid syntax for .dn directive")); +} + +static void +s_qn (int a ATTRIBUTE_UNUSED) +{ + as_bad (_("invalid syntax for .qn directive")); +} + +/* The .unreq directive deletes an alias which was previously defined + by .req. For example: + + my_alias .req r11 + .unreq my_alias */ + +static void +s_unreq (int a ATTRIBUTE_UNUSED) +{ + char * name; + char saved_char; + + name = input_line_pointer; + + while (*input_line_pointer != 0 + && *input_line_pointer != ' ' + && *input_line_pointer != '\n') + ++input_line_pointer; + + saved_char = *input_line_pointer; + *input_line_pointer = 0; + + if (!*name) + as_bad (_("invalid syntax for .unreq directive")); + else + { + struct reg_entry *reg = hash_find (arm_reg_hsh, name); + + if (!reg) + as_bad (_("unknown register alias '%s'"), name); + else if (reg->builtin) + as_warn (_("ignoring attempt to undefine built-in register '%s'"), + name); + else + { + char * p; + char * nbuf; + + hash_delete (arm_reg_hsh, name, FALSE); + free ((char *) reg->name); + if (reg->neon) + free (reg->neon); + free (reg); + + /* Also locate the all upper case and all lower case versions. + Do not complain if we cannot find one or the other as it + was probably deleted above. */ + + nbuf = strdup (name); + for (p = nbuf; *p; p++) + *p = TOUPPER (*p); + reg = hash_find (arm_reg_hsh, nbuf); + if (reg) + { + hash_delete (arm_reg_hsh, nbuf, FALSE); + free ((char *) reg->name); + if (reg->neon) + free (reg->neon); + free (reg); + } + + for (p = nbuf; *p; p++) + *p = TOLOWER (*p); + reg = hash_find (arm_reg_hsh, nbuf); + if (reg) + { + hash_delete (arm_reg_hsh, nbuf, FALSE); + free ((char *) reg->name); + if (reg->neon) + free (reg->neon); + free (reg); + } + + free (nbuf); + } + } + + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); +} + +/* Directives: Instruction set selection. */ + +#ifdef OBJ_ELF +/* This code is to handle mapping symbols as defined in the ARM ELF spec. + (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). + Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), + and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ + +/* Create a new mapping symbol for the transition to STATE. */ + +static void +make_mapping_symbol (enum mstate state, valueT value, fragS *frag) +{ + symbolS * symbolP; + const char * symname; + int type; + + switch (state) + { + case MAP_DATA: + symname = "$d"; + type = BSF_NO_FLAGS; + break; + case MAP_ARM: + symname = "$a"; + type = BSF_NO_FLAGS; + break; + case MAP_THUMB: + symname = "$t"; + type = BSF_NO_FLAGS; + break; + default: + abort (); + } + + symbolP = symbol_new (symname, now_seg, value, frag); + symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; + + switch (state) + { + case MAP_ARM: + THUMB_SET_FUNC (symbolP, 0); + ARM_SET_THUMB (symbolP, 0); + ARM_SET_INTERWORK (symbolP, support_interwork); + break; + + case MAP_THUMB: + THUMB_SET_FUNC (symbolP, 1); + ARM_SET_THUMB (symbolP, 1); + ARM_SET_INTERWORK (symbolP, support_interwork); + break; + + case MAP_DATA: + default: + break; + } + + /* Save the mapping symbols for future reference. Also check that + we do not place two mapping symbols at the same offset within a + frag. We'll handle overlap between frags in + check_mapping_symbols. */ + if (value == 0) + { + know (frag->tc_frag_data.first_map == NULL); + frag->tc_frag_data.first_map = symbolP; + } + if (frag->tc_frag_data.last_map != NULL) + know (S_GET_VALUE (frag->tc_frag_data.last_map) < S_GET_VALUE (symbolP)); + frag->tc_frag_data.last_map = symbolP; +} + +/* We must sometimes convert a region marked as code to data during + code alignment, if an odd number of bytes have to be padded. The + code mapping symbol is pushed to an aligned address. */ + +static void +insert_data_mapping_symbol (enum mstate state, + valueT value, fragS *frag, offsetT bytes) +{ + /* If there was already a mapping symbol, remove it. */ + if (frag->tc_frag_data.last_map != NULL + && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) + { + symbolS *symp = frag->tc_frag_data.last_map; + + if (value == 0) + { + know (frag->tc_frag_data.first_map == symp); + frag->tc_frag_data.first_map = NULL; + } + frag->tc_frag_data.last_map = NULL; + symbol_remove (symp, &symbol_rootP, &symbol_lastP); + } + + make_mapping_symbol (MAP_DATA, value, frag); + make_mapping_symbol (state, value + bytes, frag); +} + +static void mapping_state_2 (enum mstate state, int max_chars); + +/* Set the mapping state to STATE. Only call this when about to + emit some STATE bytes to the file. */ + +void +mapping_state (enum mstate state) +{ + enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; + +#define TRANSITION(from, to) (mapstate == (from) && state == (to)) + + if (mapstate == state) + /* The mapping symbol has already been emitted. + There is nothing else to do. */ + return; + else if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) + /* This case will be evaluated later in the next else. */ + return; + else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) + || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) + { + /* Only add the symbol if the offset is > 0: + if we're at the first frag, check it's size > 0; + if we're not at the first frag, then for sure + the offset is > 0. */ + struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; + const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); + + if (add_symbol) + make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); + } + + mapping_state_2 (state, 0); +#undef TRANSITION +} + +/* Same as mapping_state, but MAX_CHARS bytes have already been + allocated. Put the mapping symbol that far back. */ + +static void +mapping_state_2 (enum mstate state, int max_chars) +{ + enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; + + if (!SEG_NORMAL (now_seg)) + return; + + if (mapstate == state) + /* The mapping symbol has already been emitted. + There is nothing else to do. */ + return; + + seg_info (now_seg)->tc_segment_info_data.mapstate = state; + make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); +} +#else +#define mapping_state(x) /* nothing */ +#define mapping_state_2(x, y) /* nothing */ +#endif + +/* Find the real, Thumb encoded start of a Thumb function. */ + +#ifdef OBJ_COFF +static symbolS * +find_real_start (symbolS * symbolP) +{ + char * real_start; + const char * name = S_GET_NAME (symbolP); + symbolS * new_target; + + /* This definition must agree with the one in gcc/config/arm/thumb.c. */ +#define STUB_NAME ".real_start_of" + + if (name == NULL) + abort (); + + /* The compiler may generate BL instructions to local labels because + it needs to perform a branch to a far away location. These labels + do not have a corresponding ".real_start_of" label. We check + both for S_IS_LOCAL and for a leading dot, to give a way to bypass + the ".real_start_of" convention for nonlocal branches. */ + if (S_IS_LOCAL (symbolP) || name[0] == '.') + return symbolP; + + real_start = ACONCAT ((STUB_NAME, name, NULL)); + new_target = symbol_find (real_start); + + if (new_target == NULL) + { + as_warn (_("Failed to find real start of function: %s\n"), name); + new_target = symbolP; + } + + return new_target; +} +#endif + +static void +opcode_select (int width) +{ + switch (width) + { + case 16: + if (! thumb_mode) + { + if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) + as_bad (_("selected processor does not support THUMB opcodes")); + + thumb_mode = 1; + /* No need to force the alignment, since we will have been + coming from ARM mode, which is word-aligned. */ + record_alignment (now_seg, 1); + } + break; + + case 32: + if (thumb_mode) + { + if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) + as_bad (_("selected processor does not support ARM opcodes")); + + thumb_mode = 0; + + if (!need_pass_2) + frag_align (2, 0, 0); + + record_alignment (now_seg, 1); + } + break; + + default: + as_bad (_("invalid instruction size selected (%d)"), width); + } +} + +static void +s_arm (int ignore ATTRIBUTE_UNUSED) +{ + opcode_select (32); + demand_empty_rest_of_line (); +} + +static void +s_thumb (int ignore ATTRIBUTE_UNUSED) +{ + opcode_select (16); + demand_empty_rest_of_line (); +} + +static void +s_code (int unused ATTRIBUTE_UNUSED) +{ + int temp; + + temp = get_absolute_expression (); + switch (temp) + { + case 16: + case 32: + opcode_select (temp); + break; + + default: + as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); + } +} + +static void +s_force_thumb (int ignore ATTRIBUTE_UNUSED) +{ + /* If we are not already in thumb mode go into it, EVEN if + the target processor does not support thumb instructions. + This is used by gcc/config/arm/lib1funcs.asm for example + to compile interworking support functions even if the + target processor should not support interworking. */ + if (! thumb_mode) + { + thumb_mode = 2; + record_alignment (now_seg, 1); + } + + demand_empty_rest_of_line (); +} + +static void +s_thumb_func (int ignore ATTRIBUTE_UNUSED) +{ + s_thumb (0); + + /* The following label is the name/address of the start of a Thumb function. + We need to know this for the interworking support. */ + label_is_thumb_function_name = TRUE; +} + +/* Perform a .set directive, but also mark the alias as + being a thumb function. */ + +static void +s_thumb_set (int equiv) +{ + /* XXX the following is a duplicate of the code for s_set() in read.c + We cannot just call that code as we need to get at the symbol that + is created. */ + char * name; + char delim; + char * end_name; + symbolS * symbolP; + + /* Especial apologies for the random logic: + This just grew, and could be parsed much more simply! + Dean - in haste. */ + name = input_line_pointer; + delim = get_symbol_end (); + end_name = input_line_pointer; + *end_name = delim; + + if (*input_line_pointer != ',') + { + *end_name = 0; + as_bad (_("expected comma after name \"%s\""), name); + *end_name = delim; + ignore_rest_of_line (); + return; + } + + input_line_pointer++; + *end_name = 0; + + if (name[0] == '.' && name[1] == '\0') + { + /* XXX - this should not happen to .thumb_set. */ + abort (); + } + + if ((symbolP = symbol_find (name)) == NULL + && (symbolP = md_undefined_symbol (name)) == NULL) + { +#ifndef NO_LISTING + /* When doing symbol listings, play games with dummy fragments living + outside the normal fragment chain to record the file and line info + for this symbol. */ + if (listing & LISTING_SYMBOLS) + { + extern struct list_info_struct * listing_tail; + fragS * dummy_frag = xmalloc (sizeof (fragS)); + + memset (dummy_frag, 0, sizeof (fragS)); + dummy_frag->fr_type = rs_fill; + dummy_frag->line = listing_tail; + symbolP = symbol_new (name, undefined_section, 0, dummy_frag); + dummy_frag->fr_symbol = symbolP; + } + else +#endif + symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); + +#ifdef OBJ_COFF + /* "set" symbols are local unless otherwise specified. */ + SF_SET_LOCAL (symbolP); +#endif /* OBJ_COFF */ + } /* Make a new symbol. */ + + symbol_table_insert (symbolP); + + * end_name = delim; + + if (equiv + && S_IS_DEFINED (symbolP) + && S_GET_SEGMENT (symbolP) != reg_section) + as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); + + pseudo_set (symbolP); + + demand_empty_rest_of_line (); + + /* XXX Now we come to the Thumb specific bit of code. */ + + THUMB_SET_FUNC (symbolP, 1); + ARM_SET_THUMB (symbolP, 1); +#if defined OBJ_ELF || defined OBJ_COFF + ARM_SET_INTERWORK (symbolP, support_interwork); +#endif +} + +/* Directives: Mode selection. */ + +/* .syntax [unified|divided] - choose the new unified syntax + (same for Arm and Thumb encoding, modulo slight differences in what + can be represented) or the old divergent syntax for each mode. */ +static void +s_syntax (int unused ATTRIBUTE_UNUSED) +{ + char *name, delim; + + name = input_line_pointer; + delim = get_symbol_end (); + + if (!strcasecmp (name, "unified")) + unified_syntax = TRUE; + else if (!strcasecmp (name, "divided")) + unified_syntax = FALSE; + else + { + as_bad (_("unrecognized syntax mode \"%s\""), name); + return; + } + *input_line_pointer = delim; + demand_empty_rest_of_line (); +} + +/* Directives: sectioning and alignment. */ + +/* Same as s_align_ptwo but align 0 => align 2. */ + +static void +s_align (int unused ATTRIBUTE_UNUSED) +{ + int temp; + bfd_boolean fill_p; + long temp_fill; + long max_alignment = 15; + + temp = get_absolute_expression (); + if (temp > max_alignment) + as_bad (_("alignment too large: %d assumed"), temp = max_alignment); + else if (temp < 0) + { + as_bad (_("alignment negative. 0 assumed.")); + temp = 0; + } + + if (*input_line_pointer == ',') + { + input_line_pointer++; + temp_fill = get_absolute_expression (); + fill_p = TRUE; + } + else + { + fill_p = FALSE; + temp_fill = 0; + } + + if (!temp) + temp = 2; + + /* Only make a frag if we HAVE to. */ + if (temp && !need_pass_2) + { + if (!fill_p && subseg_text_p (now_seg)) + frag_align_code (temp, 0); + else + frag_align (temp, (int) temp_fill, 0); + } + demand_empty_rest_of_line (); + + record_alignment (now_seg, temp); +} + +static void +s_bss (int ignore ATTRIBUTE_UNUSED) +{ + /* We don't support putting frags in the BSS segment, we fake it by + marking in_bss, then looking at s_skip for clues. */ + subseg_set (bss_section, 0); + demand_empty_rest_of_line (); + +#ifdef md_elf_section_change_hook + md_elf_section_change_hook (); +#endif +} + +static void +s_even (int ignore ATTRIBUTE_UNUSED) +{ + /* Never make frag if expect extra pass. */ + if (!need_pass_2) + frag_align (1, 0, 0); + + record_alignment (now_seg, 1); + + demand_empty_rest_of_line (); +} + +/* Directives: Literal pools. */ + +static literal_pool * +find_literal_pool (void) +{ + literal_pool * pool; + + for (pool = list_of_pools; pool != NULL; pool = pool->next) + { + if (pool->section == now_seg + && pool->sub_section == now_subseg) + break; + } + + return pool; +} + +static literal_pool * +find_or_make_literal_pool (void) +{ + /* Next literal pool ID number. */ + static unsigned int latest_pool_num = 1; + literal_pool * pool; + + pool = find_literal_pool (); + + if (pool == NULL) + { + /* Create a new pool. */ + pool = xmalloc (sizeof (* pool)); + if (! pool) + return NULL; + + pool->next_free_entry = 0; + pool->section = now_seg; + pool->sub_section = now_subseg; + pool->next = list_of_pools; + pool->symbol = NULL; + + /* Add it to the list. */ + list_of_pools = pool; + } + + /* New pools, and emptied pools, will have a NULL symbol. */ + if (pool->symbol == NULL) + { + pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, + (valueT) 0, &zero_address_frag); + pool->id = latest_pool_num ++; + } + + /* Done. */ + return pool; +} + +/* Add the literal in the global 'inst' + structure to the relevant literal pool. */ + +static int +add_to_lit_pool (void) +{ + literal_pool * pool; + unsigned int entry; + + pool = find_or_make_literal_pool (); + + /* Check if this literal value is already in the pool. */ + for (entry = 0; entry < pool->next_free_entry; entry ++) + { + if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) + && (inst.reloc.exp.X_op == O_constant) + && (pool->literals[entry].X_add_number + == inst.reloc.exp.X_add_number) + && (pool->literals[entry].X_unsigned + == inst.reloc.exp.X_unsigned)) + break; + + if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) + && (inst.reloc.exp.X_op == O_symbol) + && (pool->literals[entry].X_add_number + == inst.reloc.exp.X_add_number) + && (pool->literals[entry].X_add_symbol + == inst.reloc.exp.X_add_symbol) + && (pool->literals[entry].X_op_symbol + == inst.reloc.exp.X_op_symbol)) + break; + } + + /* Do we need to create a new entry? */ + if (entry == pool->next_free_entry) + { + if (entry >= MAX_LITERAL_POOL_SIZE) + { + inst.error = _("literal pool overflow"); + return FAIL; + } + + pool->literals[entry] = inst.reloc.exp; + pool->next_free_entry += 1; + } + + inst.reloc.exp.X_op = O_symbol; + inst.reloc.exp.X_add_number = ((int) entry) * 4; + inst.reloc.exp.X_add_symbol = pool->symbol; + + return SUCCESS; +} + +/* Can't use symbol_new here, so have to create a symbol and then at + a later date assign it a value. Thats what these functions do. */ + +static void +symbol_locate (symbolS * symbolP, + const char * name, /* It is copied, the caller can modify. */ + segT segment, /* Segment identifier (SEG_). */ + valueT valu, /* Symbol value. */ + fragS * frag) /* Associated fragment. */ +{ + unsigned int name_length; + char * preserved_copy_of_name; + + name_length = strlen (name) + 1; /* +1 for \0. */ + obstack_grow (¬es, name, name_length); + preserved_copy_of_name = obstack_finish (¬es); + +#ifdef tc_canonicalize_symbol_name + preserved_copy_of_name = + tc_canonicalize_symbol_name (preserved_copy_of_name); +#endif + + S_SET_NAME (symbolP, preserved_copy_of_name); + + S_SET_SEGMENT (symbolP, segment); + S_SET_VALUE (symbolP, valu); + symbol_clear_list_pointers (symbolP); + + symbol_set_frag (symbolP, frag); + + /* Link to end of symbol chain. */ + { + extern int symbol_table_frozen; + + if (symbol_table_frozen) + abort (); + } + + symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); + + obj_symbol_new_hook (symbolP); + +#ifdef tc_symbol_new_hook + tc_symbol_new_hook (symbolP); +#endif + +#ifdef DEBUG_SYMS + verify_symbol_chain (symbol_rootP, symbol_lastP); +#endif /* DEBUG_SYMS */ +} + + +static void +s_ltorg (int ignored ATTRIBUTE_UNUSED) +{ + unsigned int entry; + literal_pool * pool; + char sym_name[20]; + + pool = find_literal_pool (); + if (pool == NULL + || pool->symbol == NULL + || pool->next_free_entry == 0) + return; + + mapping_state (MAP_DATA); + + /* Align pool as you have word accesses. + Only make a frag if we have to. */ + if (!need_pass_2) + frag_align (2, 0, 0); + + record_alignment (now_seg, 2); + + sprintf (sym_name, "$$lit_\002%x", pool->id); + + symbol_locate (pool->symbol, sym_name, now_seg, + (valueT) frag_now_fix (), frag_now); + symbol_table_insert (pool->symbol); + + ARM_SET_THUMB (pool->symbol, thumb_mode); + +#if defined OBJ_COFF || defined OBJ_ELF + ARM_SET_INTERWORK (pool->symbol, support_interwork); +#endif + + for (entry = 0; entry < pool->next_free_entry; entry ++) + /* First output the expression in the instruction to the pool. */ + emit_expr (&(pool->literals[entry]), 4); /* .word */ + + /* Mark the pool as empty. */ + pool->next_free_entry = 0; + pool->symbol = NULL; +} + +#ifdef OBJ_ELF +/* Forward declarations for functions below, in the MD interface + section. */ +static void fix_new_arm (fragS *, int, short, expressionS *, int, int); +static valueT create_unwind_entry (int); +static void start_unwind_section (const segT, int); +static void add_unwind_opcode (valueT, int); +static void flush_pending_unwind (void); + +/* Directives: Data. */ + +static void +s_arm_elf_cons (int nbytes) +{ + expressionS exp; + +#ifdef md_flush_pending_output + md_flush_pending_output (); +#endif + + if (is_it_end_of_statement ()) + { + demand_empty_rest_of_line (); + return; + } + +#ifdef md_cons_align + md_cons_align (nbytes); +#endif + + mapping_state (MAP_DATA); + do + { + int reloc; + char *base = input_line_pointer; + + expression (& exp); + + if (exp.X_op != O_symbol) + emit_expr (&exp, (unsigned int) nbytes); + else + { + char *before_reloc = input_line_pointer; + reloc = parse_reloc (&input_line_pointer); + if (reloc == -1) + { + as_bad (_("unrecognized relocation suffix")); + ignore_rest_of_line (); + return; + } + else if (reloc == BFD_RELOC_UNUSED) + emit_expr (&exp, (unsigned int) nbytes); + else + { + reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); + int size = bfd_get_reloc_size (howto); + + if (reloc == BFD_RELOC_ARM_PLT32) + { + as_bad (_("(plt) is only valid on branch targets")); + reloc = BFD_RELOC_UNUSED; + size = 0; + } + + if (size > nbytes) + as_bad (_("%s relocations do not fit in %d bytes"), + howto->name, nbytes); + else + { + /* We've parsed an expression stopping at O_symbol. + But there may be more expression left now that we + have parsed the relocation marker. Parse it again. + XXX Surely there is a cleaner way to do this. */ + char *p = input_line_pointer; + int offset; + char *save_buf = alloca (input_line_pointer - base); + memcpy (save_buf, base, input_line_pointer - base); + memmove (base + (input_line_pointer - before_reloc), + base, before_reloc - base); + + input_line_pointer = base + (input_line_pointer-before_reloc); + expression (&exp); + memcpy (base, save_buf, p - base); + + offset = nbytes - size; + p = frag_more ((int) nbytes); + fix_new_exp (frag_now, p - frag_now->fr_literal + offset, + size, &exp, 0, reloc); + } + } + } + } + while (*input_line_pointer++ == ','); + + /* Put terminator back into stream. */ + input_line_pointer --; + demand_empty_rest_of_line (); +} + +/* Emit an expression containing a 32-bit thumb instruction. + Implementation based on put_thumb32_insn. */ + +static void +emit_thumb32_expr (expressionS * exp) +{ + expressionS exp_high = *exp; + + exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; + emit_expr (& exp_high, (unsigned int) THUMB_SIZE); + exp->X_add_number &= 0xffff; + emit_expr (exp, (unsigned int) THUMB_SIZE); +} + +/* Guess the instruction size based on the opcode. */ + +static int +thumb_insn_size (int opcode) +{ + if ((unsigned int) opcode < 0xe800u) + return 2; + else if ((unsigned int) opcode >= 0xe8000000u) + return 4; + else + return 0; +} + +static bfd_boolean +emit_insn (expressionS *exp, int nbytes) +{ + int size = 0; + + if (exp->X_op == O_constant) + { + size = nbytes; + + if (size == 0) + size = thumb_insn_size (exp->X_add_number); + + if (size != 0) + { + if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) + { + as_bad (_(".inst.n operand too big. "\ + "Use .inst.w instead")); + size = 0; + } + else + { + if (now_it.state == AUTOMATIC_IT_BLOCK) + set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); + else + set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); + + if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) + emit_thumb32_expr (exp); + else + emit_expr (exp, (unsigned int) size); + + it_fsm_post_encode (); + } + } + else + as_bad (_("cannot determine Thumb instruction size. " \ + "Use .inst.n/.inst.w instead")); + } + else + as_bad (_("constant expression required")); + + return (size != 0); +} + +/* Like s_arm_elf_cons but do not use md_cons_align and + set the mapping state to MAP_ARM/MAP_THUMB. */ + +static void +s_arm_elf_inst (int nbytes) +{ + if (is_it_end_of_statement ()) + { + demand_empty_rest_of_line (); + return; + } + + /* Calling mapping_state () here will not change ARM/THUMB, + but will ensure not to be in DATA state. */ + + if (thumb_mode) + mapping_state (MAP_THUMB); + else + { + if (nbytes != 0) + { + as_bad (_("width suffixes are invalid in ARM mode")); + ignore_rest_of_line (); + return; + } + + nbytes = 4; + + mapping_state (MAP_ARM); + } + + do + { + expressionS exp; + + expression (& exp); + + if (! emit_insn (& exp, nbytes)) + { + ignore_rest_of_line (); + return; + } + } + while (*input_line_pointer++ == ','); + + /* Put terminator back into stream. */ + input_line_pointer --; + demand_empty_rest_of_line (); +} + +/* Parse a .rel31 directive. */ + +static void +s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) +{ + expressionS exp; + char *p; + valueT highbit; + + highbit = 0; + if (*input_line_pointer == '1') + highbit = 0x80000000; + else if (*input_line_pointer != '0') + as_bad (_("expected 0 or 1")); + + input_line_pointer++; + if (*input_line_pointer != ',') + as_bad (_("missing comma")); + input_line_pointer++; + +#ifdef md_flush_pending_output + md_flush_pending_output (); +#endif + +#ifdef md_cons_align + md_cons_align (4); +#endif + + mapping_state (MAP_DATA); + + expression (&exp); + + p = frag_more (4); + md_number_to_chars (p, highbit, 4); + fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, + BFD_RELOC_ARM_PREL31); + + demand_empty_rest_of_line (); +} + +/* Directives: AEABI stack-unwind tables. */ + +/* Parse an unwind_fnstart directive. Simply records the current location. */ + +static void +s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) +{ + demand_empty_rest_of_line (); + if (unwind.proc_start) + { + as_bad (_("duplicate .fnstart directive")); + return; + } + + /* Mark the start of the function. */ + unwind.proc_start = expr_build_dot (); + + /* Reset the rest of the unwind info. */ + unwind.opcode_count = 0; + unwind.table_entry = NULL; + unwind.personality_routine = NULL; + unwind.personality_index = -1; + unwind.frame_size = 0; + unwind.fp_offset = 0; + unwind.fp_reg = REG_SP; + unwind.fp_used = 0; + unwind.sp_restored = 0; +} + + +/* Parse a handlerdata directive. Creates the exception handling table entry + for the function. */ + +static void +s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) +{ + demand_empty_rest_of_line (); + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + if (unwind.table_entry) + as_bad (_("duplicate .handlerdata directive")); + + create_unwind_entry (1); +} + +/* Parse an unwind_fnend directive. Generates the index table entry. */ + +static void +s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) +{ + long where; + char *ptr; + valueT val; + unsigned int marked_pr_dependency; + + demand_empty_rest_of_line (); + + if (!unwind.proc_start) + { + as_bad (_(".fnend directive without .fnstart")); + return; + } + + /* Add eh table entry. */ + if (unwind.table_entry == NULL) + val = create_unwind_entry (0); + else + val = 0; + + /* Add index table entry. This is two words. */ + start_unwind_section (unwind.saved_seg, 1); + frag_align (2, 0, 0); + record_alignment (now_seg, 2); + + ptr = frag_more (8); + where = frag_now_fix () - 8; + + /* Self relative offset of the function start. */ + fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, + BFD_RELOC_ARM_PREL31); + + /* Indicate dependency on EHABI-defined personality routines to the + linker, if it hasn't been done already. */ + marked_pr_dependency + = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; + if (unwind.personality_index >= 0 && unwind.personality_index < 3 + && !(marked_pr_dependency & (1 << unwind.personality_index))) + { + static const char *const name[] = + { + "__aeabi_unwind_cpp_pr0", + "__aeabi_unwind_cpp_pr1", + "__aeabi_unwind_cpp_pr2" + }; + symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); + fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); + seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency + |= 1 << unwind.personality_index; + } + + if (val) + /* Inline exception table entry. */ + md_number_to_chars (ptr + 4, val, 4); + else + /* Self relative offset of the table entry. */ + fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, + BFD_RELOC_ARM_PREL31); + + /* Restore the original section. */ + subseg_set (unwind.saved_seg, unwind.saved_subseg); + + unwind.proc_start = NULL; +} + + +/* Parse an unwind_cantunwind directive. */ + +static void +s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) +{ + demand_empty_rest_of_line (); + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + if (unwind.personality_routine || unwind.personality_index != -1) + as_bad (_("personality routine specified for cantunwind frame")); + + unwind.personality_index = -2; +} + + +/* Parse a personalityindex directive. */ + +static void +s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) +{ + expressionS exp; + + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + if (unwind.personality_routine || unwind.personality_index != -1) + as_bad (_("duplicate .personalityindex directive")); + + expression (&exp); + + if (exp.X_op != O_constant + || exp.X_add_number < 0 || exp.X_add_number > 15) + { + as_bad (_("bad personality routine number")); + ignore_rest_of_line (); + return; + } + + unwind.personality_index = exp.X_add_number; + + demand_empty_rest_of_line (); +} + + +/* Parse a personality directive. */ + +static void +s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) +{ + char *name, *p, c; + + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + if (unwind.personality_routine || unwind.personality_index != -1) + as_bad (_("duplicate .personality directive")); + + name = input_line_pointer; + c = get_symbol_end (); + p = input_line_pointer; + unwind.personality_routine = symbol_find_or_make (name); + *p = c; + demand_empty_rest_of_line (); +} + + +/* Parse a directive saving core registers. */ + +static void +s_arm_unwind_save_core (void) +{ + valueT op; + long range; + int n; + + range = parse_reg_list (&input_line_pointer); + if (range == FAIL) + { + as_bad (_("expected register list")); + ignore_rest_of_line (); + return; + } + + demand_empty_rest_of_line (); + + /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} + into .unwind_save {..., sp...}. We aren't bothered about the value of + ip because it is clobbered by calls. */ + if (unwind.sp_restored && unwind.fp_reg == 12 + && (range & 0x3000) == 0x1000) + { + unwind.opcode_count--; + unwind.sp_restored = 0; + range = (range | 0x2000) & ~0x1000; + unwind.pending_offset = 0; + } + + /* Pop r4-r15. */ + if (range & 0xfff0) + { + /* See if we can use the short opcodes. These pop a block of up to 8 + registers starting with r4, plus maybe r14. */ + for (n = 0; n < 8; n++) + { + /* Break at the first non-saved register. */ + if ((range & (1 << (n + 4))) == 0) + break; + } + /* See if there are any other bits set. */ + if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) + { + /* Use the long form. */ + op = 0x8000 | ((range >> 4) & 0xfff); + add_unwind_opcode (op, 2); + } + else + { + /* Use the short form. */ + if (range & 0x4000) + op = 0xa8; /* Pop r14. */ + else + op = 0xa0; /* Do not pop r14. */ + op |= (n - 1); + add_unwind_opcode (op, 1); + } + } + + /* Pop r0-r3. */ + if (range & 0xf) + { + op = 0xb100 | (range & 0xf); + add_unwind_opcode (op, 2); + } + + /* Record the number of bytes pushed. */ + for (n = 0; n < 16; n++) + { + if (range & (1 << n)) + unwind.frame_size += 4; + } +} + + +/* Parse a directive saving FPA registers. */ + +static void +s_arm_unwind_save_fpa (int reg) +{ + expressionS exp; + int num_regs; + valueT op; + + /* Get Number of registers to transfer. */ + if (skip_past_comma (&input_line_pointer) != FAIL) + expression (&exp); + else + exp.X_op = O_illegal; + + if (exp.X_op != O_constant) + { + as_bad (_("expected , ")); + ignore_rest_of_line (); + return; + } + + num_regs = exp.X_add_number; + + if (num_regs < 1 || num_regs > 4) + { + as_bad (_("number of registers must be in the range [1:4]")); + ignore_rest_of_line (); + return; + } + + demand_empty_rest_of_line (); + + if (reg == 4) + { + /* Short form. */ + op = 0xb4 | (num_regs - 1); + add_unwind_opcode (op, 1); + } + else + { + /* Long form. */ + op = 0xc800 | (reg << 4) | (num_regs - 1); + add_unwind_opcode (op, 2); + } + unwind.frame_size += num_regs * 12; +} + + +/* Parse a directive saving VFP registers for ARMv6 and above. */ + +static void +s_arm_unwind_save_vfp_armv6 (void) +{ + int count; + unsigned int start; + valueT op; + int num_vfpv3_regs = 0; + int num_regs_below_16; + + count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); + if (count == FAIL) + { + as_bad (_("expected register list")); + ignore_rest_of_line (); + return; + } + + demand_empty_rest_of_line (); + + /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather + than FSTMX/FLDMX-style ones). */ + + /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ + if (start >= 16) + num_vfpv3_regs = count; + else if (start + count > 16) + num_vfpv3_regs = start + count - 16; + + if (num_vfpv3_regs > 0) + { + int start_offset = start > 16 ? start - 16 : 0; + op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); + add_unwind_opcode (op, 2); + } + + /* Generate opcode for registers numbered in the range 0 .. 15. */ + num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; + gas_assert (num_regs_below_16 + num_vfpv3_regs == count); + if (num_regs_below_16 > 0) + { + op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); + add_unwind_opcode (op, 2); + } + + unwind.frame_size += count * 8; +} + + +/* Parse a directive saving VFP registers for pre-ARMv6. */ + +static void +s_arm_unwind_save_vfp (void) +{ + int count; + unsigned int reg; + valueT op; + + count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); + if (count == FAIL) + { + as_bad (_("expected register list")); + ignore_rest_of_line (); + return; + } + + demand_empty_rest_of_line (); + + if (reg == 8) + { + /* Short form. */ + op = 0xb8 | (count - 1); + add_unwind_opcode (op, 1); + } + else + { + /* Long form. */ + op = 0xb300 | (reg << 4) | (count - 1); + add_unwind_opcode (op, 2); + } + unwind.frame_size += count * 8 + 4; +} + + +/* Parse a directive saving iWMMXt data registers. */ + +static void +s_arm_unwind_save_mmxwr (void) +{ + int reg; + int hi_reg; + int i; + unsigned mask = 0; + valueT op; + + if (*input_line_pointer == '{') + input_line_pointer++; + + do + { + reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); + + if (reg == FAIL) + { + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); + goto error; + } + + if (mask >> reg) + as_tsktsk (_("register list not in ascending order")); + mask |= 1 << reg; + + if (*input_line_pointer == '-') + { + input_line_pointer++; + hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); + if (hi_reg == FAIL) + { + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); + goto error; + } + else if (reg >= hi_reg) + { + as_bad (_("bad register range")); + goto error; + } + for (; reg < hi_reg; reg++) + mask |= 1 << reg; + } + } + while (skip_past_comma (&input_line_pointer) != FAIL); + + if (*input_line_pointer == '}') + input_line_pointer++; + + demand_empty_rest_of_line (); + + /* Generate any deferred opcodes because we're going to be looking at + the list. */ + flush_pending_unwind (); + + for (i = 0; i < 16; i++) + { + if (mask & (1 << i)) + unwind.frame_size += 8; + } + + /* Attempt to combine with a previous opcode. We do this because gcc + likes to output separate unwind directives for a single block of + registers. */ + if (unwind.opcode_count > 0) + { + i = unwind.opcodes[unwind.opcode_count - 1]; + if ((i & 0xf8) == 0xc0) + { + i &= 7; + /* Only merge if the blocks are contiguous. */ + if (i < 6) + { + if ((mask & 0xfe00) == (1 << 9)) + { + mask |= ((1 << (i + 11)) - 1) & 0xfc00; + unwind.opcode_count--; + } + } + else if (i == 6 && unwind.opcode_count >= 2) + { + i = unwind.opcodes[unwind.opcode_count - 2]; + reg = i >> 4; + i &= 0xf; + + op = 0xffff << (reg - 1); + if (reg > 0 + && ((mask & op) == (1u << (reg - 1)))) + { + op = (1 << (reg + i + 1)) - 1; + op &= ~((1 << reg) - 1); + mask |= op; + unwind.opcode_count -= 2; + } + } + } + } + + hi_reg = 15; + /* We want to generate opcodes in the order the registers have been + saved, ie. descending order. */ + for (reg = 15; reg >= -1; reg--) + { + /* Save registers in blocks. */ + if (reg < 0 + || !(mask & (1 << reg))) + { + /* We found an unsaved reg. Generate opcodes to save the + preceding block. */ + if (reg != hi_reg) + { + if (reg == 9) + { + /* Short form. */ + op = 0xc0 | (hi_reg - 10); + add_unwind_opcode (op, 1); + } + else + { + /* Long form. */ + op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); + add_unwind_opcode (op, 2); + } + } + hi_reg = reg - 1; + } + } + + return; +error: + ignore_rest_of_line (); +} + +static void +s_arm_unwind_save_mmxwcg (void) +{ + int reg; + int hi_reg; + unsigned mask = 0; + valueT op; + + if (*input_line_pointer == '{') + input_line_pointer++; + + do + { + reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); + + if (reg == FAIL) + { + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); + goto error; + } + + reg -= 8; + if (mask >> reg) + as_tsktsk (_("register list not in ascending order")); + mask |= 1 << reg; + + if (*input_line_pointer == '-') + { + input_line_pointer++; + hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); + if (hi_reg == FAIL) + { + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); + goto error; + } + else if (reg >= hi_reg) + { + as_bad (_("bad register range")); + goto error; + } + for (; reg < hi_reg; reg++) + mask |= 1 << reg; + } + } + while (skip_past_comma (&input_line_pointer) != FAIL); + + if (*input_line_pointer == '}') + input_line_pointer++; + + demand_empty_rest_of_line (); + + /* Generate any deferred opcodes because we're going to be looking at + the list. */ + flush_pending_unwind (); + + for (reg = 0; reg < 16; reg++) + { + if (mask & (1 << reg)) + unwind.frame_size += 4; + } + op = 0xc700 | mask; + add_unwind_opcode (op, 2); + return; +error: + ignore_rest_of_line (); +} + + +/* Parse an unwind_save directive. + If the argument is non-zero, this is a .vsave directive. */ + +static void +s_arm_unwind_save (int arch_v6) +{ + char *peek; + struct reg_entry *reg; + bfd_boolean had_brace = FALSE; + + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + /* Figure out what sort of save we have. */ + peek = input_line_pointer; + + if (*peek == '{') + { + had_brace = TRUE; + peek++; + } + + reg = arm_reg_parse_multi (&peek); + + if (!reg) + { + as_bad (_("register expected")); + ignore_rest_of_line (); + return; + } + + switch (reg->type) + { + case REG_TYPE_FN: + if (had_brace) + { + as_bad (_("FPA .unwind_save does not take a register list")); + ignore_rest_of_line (); + return; + } + input_line_pointer = peek; + s_arm_unwind_save_fpa (reg->number); + return; + + case REG_TYPE_RN: s_arm_unwind_save_core (); return; + case REG_TYPE_VFD: + if (arch_v6) + s_arm_unwind_save_vfp_armv6 (); + else + s_arm_unwind_save_vfp (); + return; + case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; + case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; + + default: + as_bad (_(".unwind_save does not support this kind of register")); + ignore_rest_of_line (); + } +} + + +/* Parse an unwind_movsp directive. */ + +static void +s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) +{ + int reg; + valueT op; + int offset; + + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); + if (reg == FAIL) + { + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); + ignore_rest_of_line (); + return; + } + + /* Optional constant. */ + if (skip_past_comma (&input_line_pointer) != FAIL) + { + if (immediate_for_directive (&offset) == FAIL) + return; + } + else + offset = 0; + + demand_empty_rest_of_line (); + + if (reg == REG_SP || reg == REG_PC) + { + as_bad (_("SP and PC not permitted in .unwind_movsp directive")); + return; + } + + if (unwind.fp_reg != REG_SP) + as_bad (_("unexpected .unwind_movsp directive")); + + /* Generate opcode to restore the value. */ + op = 0x90 | reg; + add_unwind_opcode (op, 1); + + /* Record the information for later. */ + unwind.fp_reg = reg; + unwind.fp_offset = unwind.frame_size - offset; + unwind.sp_restored = 1; +} + +/* Parse an unwind_pad directive. */ + +static void +s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) +{ + int offset; + + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + if (immediate_for_directive (&offset) == FAIL) + return; + + if (offset & 3) + { + as_bad (_("stack increment must be multiple of 4")); + ignore_rest_of_line (); + return; + } + + /* Don't generate any opcodes, just record the details for later. */ + unwind.frame_size += offset; + unwind.pending_offset += offset; + + demand_empty_rest_of_line (); +} + +/* Parse an unwind_setfp directive. */ + +static void +s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) +{ + int sp_reg; + int fp_reg; + int offset; + + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); + if (skip_past_comma (&input_line_pointer) == FAIL) + sp_reg = FAIL; + else + sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); + + if (fp_reg == FAIL || sp_reg == FAIL) + { + as_bad (_("expected , ")); + ignore_rest_of_line (); + return; + } + + /* Optional constant. */ + if (skip_past_comma (&input_line_pointer) != FAIL) + { + if (immediate_for_directive (&offset) == FAIL) + return; + } + else + offset = 0; + + demand_empty_rest_of_line (); + + if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) + { + as_bad (_("register must be either sp or set by a previous" + "unwind_movsp directive")); + return; + } + + /* Don't generate any opcodes, just record the information for later. */ + unwind.fp_reg = fp_reg; + unwind.fp_used = 1; + if (sp_reg == REG_SP) + unwind.fp_offset = unwind.frame_size - offset; + else + unwind.fp_offset -= offset; +} + +/* Parse an unwind_raw directive. */ + +static void +s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) +{ + expressionS exp; + /* This is an arbitrary limit. */ + unsigned char op[16]; + int count; + + if (!unwind.proc_start) + as_bad (MISSING_FNSTART); + + expression (&exp); + if (exp.X_op == O_constant + && skip_past_comma (&input_line_pointer) != FAIL) + { + unwind.frame_size += exp.X_add_number; + expression (&exp); + } + else + exp.X_op = O_illegal; + + if (exp.X_op != O_constant) + { + as_bad (_("expected , ")); + ignore_rest_of_line (); + return; + } + + count = 0; + + /* Parse the opcode. */ + for (;;) + { + if (count >= 16) + { + as_bad (_("unwind opcode too long")); + ignore_rest_of_line (); + } + if (exp.X_op != O_constant || exp.X_add_number & ~0xff) + { + as_bad (_("invalid unwind opcode")); + ignore_rest_of_line (); + return; + } + op[count++] = exp.X_add_number; + + /* Parse the next byte. */ + if (skip_past_comma (&input_line_pointer) == FAIL) + break; + + expression (&exp); + } + + /* Add the opcode bytes in reverse order. */ + while (count--) + add_unwind_opcode (op[count], 1); + + demand_empty_rest_of_line (); +} + + +/* Parse a .eabi_attribute directive. */ + +static void +s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) +{ + int tag = s_vendor_attribute (OBJ_ATTR_PROC); + + if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) + attributes_set_explicitly[tag] = 1; +} +#endif /* OBJ_ELF */ + +static void s_arm_arch (int); +static void s_arm_object_arch (int); +static void s_arm_cpu (int); +static void s_arm_fpu (int); + +#ifdef TE_PE + +static void +pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) +{ + expressionS exp; + + do + { + expression (&exp); + if (exp.X_op == O_symbol) + exp.X_op = O_secrel; + + emit_expr (&exp, 4); + } + while (*input_line_pointer++ == ','); + + input_line_pointer--; + demand_empty_rest_of_line (); +} +#endif /* TE_PE */ + +/* This table describes all the machine specific pseudo-ops the assembler + has to support. The fields are: + pseudo-op name without dot + function to call to execute this pseudo-op + Integer arg to pass to the function. */ + +const pseudo_typeS md_pseudo_table[] = +{ + /* Never called because '.req' does not start a line. */ + { "req", s_req, 0 }, + /* Following two are likewise never called. */ + { "dn", s_dn, 0 }, + { "qn", s_qn, 0 }, + { "unreq", s_unreq, 0 }, + { "bss", s_bss, 0 }, + { "align", s_align, 0 }, + { "arm", s_arm, 0 }, + { "thumb", s_thumb, 0 }, + { "code", s_code, 0 }, + { "force_thumb", s_force_thumb, 0 }, + { "thumb_func", s_thumb_func, 0 }, + { "thumb_set", s_thumb_set, 0 }, + { "even", s_even, 0 }, + { "ltorg", s_ltorg, 0 }, + { "pool", s_ltorg, 0 }, + { "syntax", s_syntax, 0 }, + { "cpu", s_arm_cpu, 0 }, + { "arch", s_arm_arch, 0 }, + { "object_arch", s_arm_object_arch, 0 }, + { "fpu", s_arm_fpu, 0 }, +#ifdef OBJ_ELF + { "word", s_arm_elf_cons, 4 }, + { "long", s_arm_elf_cons, 4 }, + { "inst.n", s_arm_elf_inst, 2 }, + { "inst.w", s_arm_elf_inst, 4 }, + { "inst", s_arm_elf_inst, 0 }, + { "rel31", s_arm_rel31, 0 }, + { "fnstart", s_arm_unwind_fnstart, 0 }, + { "fnend", s_arm_unwind_fnend, 0 }, + { "cantunwind", s_arm_unwind_cantunwind, 0 }, + { "personality", s_arm_unwind_personality, 0 }, + { "personalityindex", s_arm_unwind_personalityindex, 0 }, + { "handlerdata", s_arm_unwind_handlerdata, 0 }, + { "save", s_arm_unwind_save, 0 }, + { "vsave", s_arm_unwind_save, 1 }, + { "movsp", s_arm_unwind_movsp, 0 }, + { "pad", s_arm_unwind_pad, 0 }, + { "setfp", s_arm_unwind_setfp, 0 }, + { "unwind_raw", s_arm_unwind_raw, 0 }, + { "eabi_attribute", s_arm_eabi_attribute, 0 }, +#else + { "word", cons, 4}, + + /* These are used for dwarf. */ + {"2byte", cons, 2}, + {"4byte", cons, 4}, + {"8byte", cons, 8}, + /* These are used for dwarf2. */ + { "file", (void (*) (int)) dwarf2_directive_file, 0 }, + { "loc", dwarf2_directive_loc, 0 }, + { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, +#endif + { "extend", float_cons, 'x' }, + { "ldouble", float_cons, 'x' }, + { "packed", float_cons, 'p' }, +#ifdef TE_PE + {"secrel32", pe_directive_secrel, 0}, +#endif + { 0, 0, 0 } +}; + +/* Parser functions used exclusively in instruction operands. */ + +/* Generic immediate-value read function for use in insn parsing. + STR points to the beginning of the immediate (the leading #); + VAL receives the value; if the value is outside [MIN, MAX] + issue an error. PREFIX_OPT is true if the immediate prefix is + optional. */ + +static int +parse_immediate (char **str, int *val, int min, int max, + bfd_boolean prefix_opt) +{ + expressionS exp; + my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); + if (exp.X_op != O_constant) + { + inst.error = _("constant expression required"); + return FAIL; + } + + if (exp.X_add_number < min || exp.X_add_number > max) + { + inst.error = _("immediate value out of range"); + return FAIL; + } + + *val = exp.X_add_number; + return SUCCESS; +} + +/* Less-generic immediate-value read function with the possibility of loading a + big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate + instructions. Puts the result directly in inst.operands[i]. */ + +static int +parse_big_immediate (char **str, int i) +{ + expressionS exp; + char *ptr = *str; + + my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); + + if (exp.X_op == O_constant) + { + inst.operands[i].imm = exp.X_add_number & 0xffffffff; + /* If we're on a 64-bit host, then a 64-bit number can be returned using + O_constant. We have to be careful not to break compilation for + 32-bit X_add_number, though. */ + if ((exp.X_add_number & ~0xffffffffl) != 0) + { + /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ + inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; + inst.operands[i].regisimm = 1; + } + } + else if (exp.X_op == O_big + && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 + && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) + { + unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; + /* Bignums have their least significant bits in + generic_bignum[0]. Make sure we put 32 bits in imm and + 32 bits in reg, in a (hopefully) portable way. */ + gas_assert (parts != 0); + inst.operands[i].imm = 0; + for (j = 0; j < parts; j++, idx++) + inst.operands[i].imm |= generic_bignum[idx] + << (LITTLENUM_NUMBER_OF_BITS * j); + inst.operands[i].reg = 0; + for (j = 0; j < parts; j++, idx++) + inst.operands[i].reg |= generic_bignum[idx] + << (LITTLENUM_NUMBER_OF_BITS * j); + inst.operands[i].regisimm = 1; + } + else + return FAIL; + + *str = ptr; + + return SUCCESS; +} + +/* Returns the pseudo-register number of an FPA immediate constant, + or FAIL if there isn't a valid constant here. */ + +static int +parse_fpa_immediate (char ** str) +{ + LITTLENUM_TYPE words[MAX_LITTLENUMS]; + char * save_in; + expressionS exp; + int i; + int j; + + /* First try and match exact strings, this is to guarantee + that some formats will work even for cross assembly. */ + + for (i = 0; fp_const[i]; i++) + { + if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) + { + char *start = *str; + + *str += strlen (fp_const[i]); + if (is_end_of_line[(unsigned char) **str]) + return i + 8; + *str = start; + } + } + + /* Just because we didn't get a match doesn't mean that the constant + isn't valid, just that it is in a format that we don't + automatically recognize. Try parsing it with the standard + expression routines. */ + + memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); + + /* Look for a raw floating point number. */ + if ((save_in = atof_ieee (*str, 'x', words)) != NULL + && is_end_of_line[(unsigned char) *save_in]) + { + for (i = 0; i < NUM_FLOAT_VALS; i++) + { + for (j = 0; j < MAX_LITTLENUMS; j++) + { + if (words[j] != fp_values[i][j]) + break; + } + + if (j == MAX_LITTLENUMS) + { + *str = save_in; + return i + 8; + } + } + } + + /* Try and parse a more complex expression, this will probably fail + unless the code uses a floating point prefix (eg "0f"). */ + save_in = input_line_pointer; + input_line_pointer = *str; + if (expression (&exp) == absolute_section + && exp.X_op == O_big + && exp.X_add_number < 0) + { + /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. + Ditto for 15. */ + if (gen_to_words (words, 5, (long) 15) == 0) + { + for (i = 0; i < NUM_FLOAT_VALS; i++) + { + for (j = 0; j < MAX_LITTLENUMS; j++) + { + if (words[j] != fp_values[i][j]) + break; + } + + if (j == MAX_LITTLENUMS) + { + *str = input_line_pointer; + input_line_pointer = save_in; + return i + 8; + } + } + } + } + + *str = input_line_pointer; + input_line_pointer = save_in; + inst.error = _("invalid FPA immediate expression"); + return FAIL; +} + +/* Returns 1 if a number has "quarter-precision" float format + 0baBbbbbbc defgh000 00000000 00000000. */ + +static int +is_quarter_float (unsigned imm) +{ + int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; + return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; +} + +/* Parse an 8-bit "quarter-precision" floating point number of the form: + 0baBbbbbbc defgh000 00000000 00000000. + The zero and minus-zero cases need special handling, since they can't be + encoded in the "quarter-precision" float format, but can nonetheless be + loaded as integer constants. */ + +static unsigned +parse_qfloat_immediate (char **ccp, int *immed) +{ + char *str = *ccp; + char *fpnum; + LITTLENUM_TYPE words[MAX_LITTLENUMS]; + int found_fpchar = 0; + + skip_past_char (&str, '#'); + + /* We must not accidentally parse an integer as a floating-point number. Make + sure that the value we parse is not an integer by checking for special + characters '.' or 'e'. + FIXME: This is a horrible hack, but doing better is tricky because type + information isn't in a very usable state at parse time. */ + fpnum = str; + skip_whitespace (fpnum); + + if (strncmp (fpnum, "0x", 2) == 0) + return FAIL; + else + { + for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) + if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') + { + found_fpchar = 1; + break; + } + + if (!found_fpchar) + return FAIL; + } + + if ((str = atof_ieee (str, 's', words)) != NULL) + { + unsigned fpword = 0; + int i; + + /* Our FP word must be 32 bits (single-precision FP). */ + for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) + { + fpword <<= LITTLENUM_NUMBER_OF_BITS; + fpword |= words[i]; + } + + if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) + *immed = fpword; + else + return FAIL; + + *ccp = str; + + return SUCCESS; + } + + return FAIL; +} + +/* Shift operands. */ +enum shift_kind +{ + SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX +}; + +struct asm_shift_name +{ + const char *name; + enum shift_kind kind; +}; + +/* Third argument to parse_shift. */ +enum parse_shift_mode +{ + NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ + SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ + SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ + SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ + SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ +}; + +/* Parse a specifier on an ARM data processing instruction. + This has three forms: + + (LSL|LSR|ASL|ASR|ROR) Rs + (LSL|LSR|ASL|ASR|ROR) #imm + RRX + + Note that ASL is assimilated to LSL in the instruction encoding, and + RRX to ROR #0 (which cannot be written as such). */ + +static int +parse_shift (char **str, int i, enum parse_shift_mode mode) +{ + const struct asm_shift_name *shift_name; + enum shift_kind shift; + char *s = *str; + char *p = s; + int reg; + + for (p = *str; ISALPHA (*p); p++) + ; + + if (p == *str) + { + inst.error = _("shift expression expected"); + return FAIL; + } + + shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); + + if (shift_name == NULL) + { + inst.error = _("shift expression expected"); + return FAIL; + } + + shift = shift_name->kind; + + switch (mode) + { + case NO_SHIFT_RESTRICT: + case SHIFT_IMMEDIATE: break; + + case SHIFT_LSL_OR_ASR_IMMEDIATE: + if (shift != SHIFT_LSL && shift != SHIFT_ASR) + { + inst.error = _("'LSL' or 'ASR' required"); + return FAIL; + } + break; + + case SHIFT_LSL_IMMEDIATE: + if (shift != SHIFT_LSL) + { + inst.error = _("'LSL' required"); + return FAIL; + } + break; + + case SHIFT_ASR_IMMEDIATE: + if (shift != SHIFT_ASR) + { + inst.error = _("'ASR' required"); + return FAIL; + } + break; + + default: abort (); + } + + if (shift != SHIFT_RRX) + { + /* Whitespace can appear here if the next thing is a bare digit. */ + skip_whitespace (p); + + if (mode == NO_SHIFT_RESTRICT + && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) + { + inst.operands[i].imm = reg; + inst.operands[i].immisreg = 1; + } + else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) + return FAIL; + } + inst.operands[i].shift_kind = shift; + inst.operands[i].shifted = 1; + *str = p; + return SUCCESS; +} + +/* Parse a for an ARM data processing instruction: + + # + #, + + , + + where is defined by parse_shift above, and is a + multiple of 2 between 0 and 30. Validation of immediate operands + is deferred to md_apply_fix. */ + +static int +parse_shifter_operand (char **str, int i) +{ + int value; + expressionS expr; + + if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) + { + inst.operands[i].reg = value; + inst.operands[i].isreg = 1; + + /* parse_shift will override this if appropriate */ + inst.reloc.exp.X_op = O_constant; + inst.reloc.exp.X_add_number = 0; + + if (skip_past_comma (str) == FAIL) + return SUCCESS; + + /* Shift operation on register. */ + return parse_shift (str, i, NO_SHIFT_RESTRICT); + } + + if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) + return FAIL; + + if (skip_past_comma (str) == SUCCESS) + { + /* #x, y -- ie explicit rotation by Y. */ + if (my_get_expression (&expr, str, GE_NO_PREFIX)) + return FAIL; + + if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) + { + inst.error = _("constant expression expected"); + return FAIL; + } + + value = expr.X_add_number; + if (value < 0 || value > 30 || value % 2 != 0) + { + inst.error = _("invalid rotation"); + return FAIL; + } + if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) + { + inst.error = _("invalid constant"); + return FAIL; + } + + /* Convert to decoded value. md_apply_fix will put it back. */ + inst.reloc.exp.X_add_number + = (((inst.reloc.exp.X_add_number << (32 - value)) + | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); + } + + inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; + inst.reloc.pc_rel = 0; + return SUCCESS; +} + +/* Group relocation information. Each entry in the table contains the + textual name of the relocation as may appear in assembler source + and must end with a colon. + Along with this textual name are the relocation codes to be used if + the corresponding instruction is an ALU instruction (ADD or SUB only), + an LDR, an LDRS, or an LDC. */ + +struct group_reloc_table_entry +{ + const char *name; + int alu_code; + int ldr_code; + int ldrs_code; + int ldc_code; +}; + +typedef enum +{ + /* Varieties of non-ALU group relocation. */ + + GROUP_LDR, + GROUP_LDRS, + GROUP_LDC +} group_reloc_type; + +static struct group_reloc_table_entry group_reloc_table[] = + { /* Program counter relative: */ + { "pc_g0_nc", + BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ + 0, /* LDR */ + 0, /* LDRS */ + 0 }, /* LDC */ + { "pc_g0", + BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ + BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ + BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ + BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ + { "pc_g1_nc", + BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ + 0, /* LDR */ + 0, /* LDRS */ + 0 }, /* LDC */ + { "pc_g1", + BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ + BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ + BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ + BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ + { "pc_g2", + BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ + BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ + BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ + BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ + /* Section base relative */ + { "sb_g0_nc", + BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ + 0, /* LDR */ + 0, /* LDRS */ + 0 }, /* LDC */ + { "sb_g0", + BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ + BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ + BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ + BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ + { "sb_g1_nc", + BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ + 0, /* LDR */ + 0, /* LDRS */ + 0 }, /* LDC */ + { "sb_g1", + BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ + BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ + BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ + BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ + { "sb_g2", + BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ + BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ + BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ + BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ + +/* Given the address of a pointer pointing to the textual name of a group + relocation as may appear in assembler source, attempt to find its details + in group_reloc_table. The pointer will be updated to the character after + the trailing colon. On failure, FAIL will be returned; SUCCESS + otherwise. On success, *entry will be updated to point at the relevant + group_reloc_table entry. */ + +static int +find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) +{ + unsigned int i; + for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) + { + int length = strlen (group_reloc_table[i].name); + + if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 + && (*str)[length] == ':') + { + *out = &group_reloc_table[i]; + *str += (length + 1); + return SUCCESS; + } + } + + return FAIL; +} + +/* Parse a for an ARM data processing instruction + (as for parse_shifter_operand) where group relocations are allowed: + + # + #, + #:: + + , + + where is one of the strings defined in group_reloc_table. + The hashes are optional. + + Everything else is as for parse_shifter_operand. */ + +static parse_operand_result +parse_shifter_operand_group_reloc (char **str, int i) +{ + /* Determine if we have the sequence of characters #: or just : + coming next. If we do, then we check for a group relocation. + If we don't, punt the whole lot to parse_shifter_operand. */ + + if (((*str)[0] == '#' && (*str)[1] == ':') + || (*str)[0] == ':') + { + struct group_reloc_table_entry *entry; + + if ((*str)[0] == '#') + (*str) += 2; + else + (*str)++; + + /* Try to parse a group relocation. Anything else is an error. */ + if (find_group_reloc_table_entry (str, &entry) == FAIL) + { + inst.error = _("unknown group relocation"); + return PARSE_OPERAND_FAIL_NO_BACKTRACK; + } + + /* We now have the group relocation table entry corresponding to + the name in the assembler source. Next, we parse the expression. */ + if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) + return PARSE_OPERAND_FAIL_NO_BACKTRACK; + + /* Record the relocation type (always the ALU variant here). */ + inst.reloc.type = entry->alu_code; + gas_assert (inst.reloc.type != 0); + + return PARSE_OPERAND_SUCCESS; + } + else + return parse_shifter_operand (str, i) == SUCCESS + ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; + + /* Never reached. */ +} + +/* Parse all forms of an ARM address expression. Information is written + to inst.operands[i] and/or inst.reloc. + + Preindexed addressing (.preind=1): + + [Rn, #offset] .reg=Rn .reloc.exp=offset + [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 + [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 + .shift_kind=shift .reloc.exp=shift_imm + + These three may have a trailing ! which causes .writeback to be set also. + + Postindexed addressing (.postind=1, .writeback=1): + + [Rn], #offset .reg=Rn .reloc.exp=offset + [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 + [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 + .shift_kind=shift .reloc.exp=shift_imm + + Unindexed addressing (.preind=0, .postind=0): + + [Rn], {option} .reg=Rn .imm=option .immisreg=0 + + Other: + + [Rn]{!} shorthand for [Rn,#0]{!} + =immediate .isreg=0 .reloc.exp=immediate + label .reg=PC .reloc.pc_rel=1 .reloc.exp=label + + It is the caller's responsibility to check for addressing modes not + supported by the instruction, and to set inst.reloc.type. */ + +static parse_operand_result +parse_address_main (char **str, int i, int group_relocations, + group_reloc_type group_type) +{ + char *p = *str; + int reg; + + if (skip_past_char (&p, '[') == FAIL) + { + if (skip_past_char (&p, '=') == FAIL) + { + /* bare address - translate to PC-relative offset */ + inst.reloc.pc_rel = 1; + inst.operands[i].reg = REG_PC; + inst.operands[i].isreg = 1; + inst.operands[i].preind = 1; + } + /* else a load-constant pseudo op, no special treatment needed here */ + + if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) + return PARSE_OPERAND_FAIL; + + *str = p; + return PARSE_OPERAND_SUCCESS; + } + + if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) + { + inst.error = _(reg_expected_msgs[REG_TYPE_RN]); + return PARSE_OPERAND_FAIL; + } + inst.operands[i].reg = reg; + inst.operands[i].isreg = 1; + + if (skip_past_comma (&p) == SUCCESS) + { + inst.operands[i].preind = 1; + + if (*p == '+') p++; + else if (*p == '-') p++, inst.operands[i].negative = 1; + + if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) + { + inst.operands[i].imm = reg; + inst.operands[i].immisreg = 1; + + if (skip_past_comma (&p) == SUCCESS) + if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) + return PARSE_OPERAND_FAIL; + } + else if (skip_past_char (&p, ':') == SUCCESS) + { + /* FIXME: '@' should be used here, but it's filtered out by generic + code before we get to see it here. This may be subject to + change. */ + expressionS exp; + my_get_expression (&exp, &p, GE_NO_PREFIX); + if (exp.X_op != O_constant) + { + inst.error = _("alignment must be constant"); + return PARSE_OPERAND_FAIL; + } + inst.operands[i].imm = exp.X_add_number << 8; + inst.operands[i].immisalign = 1; + /* Alignments are not pre-indexes. */ + inst.operands[i].preind = 0; + } + else + { + if (inst.operands[i].negative) + { + inst.operands[i].negative = 0; + p--; + } + + if (group_relocations + && ((*p == '#' && *(p + 1) == ':') || *p == ':')) + { + struct group_reloc_table_entry *entry; + + /* Skip over the #: or : sequence. */ + if (*p == '#') + p += 2; + else + p++; + + /* Try to parse a group relocation. Anything else is an + error. */ + if (find_group_reloc_table_entry (&p, &entry) == FAIL) + { + inst.error = _("unknown group relocation"); + return PARSE_OPERAND_FAIL_NO_BACKTRACK; + } + + /* We now have the group relocation table entry corresponding to + the name in the assembler source. Next, we parse the + expression. */ + if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) + return PARSE_OPERAND_FAIL_NO_BACKTRACK; + + /* Record the relocation type. */ + switch (group_type) + { + case GROUP_LDR: + inst.reloc.type = entry->ldr_code; + break; + + case GROUP_LDRS: + inst.reloc.type = entry->ldrs_code; + break; + + case GROUP_LDC: + inst.reloc.type = entry->ldc_code; + break; + + default: + gas_assert (0); + } + + if (inst.reloc.type == 0) + { + inst.error = _("this group relocation is not allowed on this instruction"); + return PARSE_OPERAND_FAIL_NO_BACKTRACK; + } + } + else + if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) + return PARSE_OPERAND_FAIL; + } + } + + if (skip_past_char (&p, ']') == FAIL) + { + inst.error = _("']' expected"); + return PARSE_OPERAND_FAIL; + } + + if (skip_past_char (&p, '!') == SUCCESS) + inst.operands[i].writeback = 1; + + else if (skip_past_comma (&p) == SUCCESS) + { + if (skip_past_char (&p, '{') == SUCCESS) + { + /* [Rn], {expr} - unindexed, with option */ + if (parse_immediate (&p, &inst.operands[i].imm, + 0, 255, TRUE) == FAIL) + return PARSE_OPERAND_FAIL; + + if (skip_past_char (&p, '}') == FAIL) + { + inst.error = _("'}' expected at end of 'option' field"); + return PARSE_OPERAND_FAIL; + } + if (inst.operands[i].preind) + { + inst.error = _("cannot combine index with option"); + return PARSE_OPERAND_FAIL; + } + *str = p; + return PARSE_OPERAND_SUCCESS; + } + else + { + inst.operands[i].postind = 1; + inst.operands[i].writeback = 1; + + if (inst.operands[i].preind) + { + inst.error = _("cannot combine pre- and post-indexing"); + return PARSE_OPERAND_FAIL; + } + + if (*p == '+') p++; + else if (*p == '-') p++, inst.operands[i].negative = 1; + + if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) + { + /* We might be using the immediate for alignment already. If we + are, OR the register number into the low-order bits. */ + if (inst.operands[i].immisalign) + inst.operands[i].imm |= reg; + else + inst.operands[i].imm = reg; + inst.operands[i].immisreg = 1; + + if (skip_past_comma (&p) == SUCCESS) + if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) + return PARSE_OPERAND_FAIL; + } + else + { + if (inst.operands[i].negative) + { + inst.operands[i].negative = 0; + p--; + } + if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) + return PARSE_OPERAND_FAIL; + } + } + } + + /* If at this point neither .preind nor .postind is set, we have a + bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ + if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) + { + inst.operands[i].preind = 1; + inst.reloc.exp.X_op = O_constant; + inst.reloc.exp.X_add_number = 0; + } + *str = p; + return PARSE_OPERAND_SUCCESS; +} + +static int +parse_address (char **str, int i) +{ + return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS + ? SUCCESS : FAIL; +} + +static parse_operand_result +parse_address_group_reloc (char **str, int i, group_reloc_type type) +{ + return parse_address_main (str, i, 1, type); +} + +/* Parse an operand for a MOVW or MOVT instruction. */ +static int +parse_half (char **str) +{ + char * p; + + p = *str; + skip_past_char (&p, '#'); + if (strncasecmp (p, ":lower16:", 9) == 0) + inst.reloc.type = BFD_RELOC_ARM_MOVW; + else if (strncasecmp (p, ":upper16:", 9) == 0) + inst.reloc.type = BFD_RELOC_ARM_MOVT; + + if (inst.reloc.type != BFD_RELOC_UNUSED) + { + p += 9; + skip_whitespace (p); + } + + if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) + return FAIL; + + if (inst.reloc.type == BFD_RELOC_UNUSED) + { + if (inst.reloc.exp.X_op != O_constant) + { + inst.error = _("constant expression expected"); + return FAIL; + } + if (inst.reloc.exp.X_add_number < 0 + || inst.reloc.exp.X_add_number > 0xffff) + { + inst.error = _("immediate value out of range"); + return FAIL; + } + } + *str = p; + return SUCCESS; +} + +/* Miscellaneous. */ + +/* Parse a PSR flag operand. The value returned is FAIL on syntax error, + or a bitmask suitable to be or-ed into the ARM msr instruction. */ +static int +parse_psr (char **str) +{ + char *p; + unsigned long psr_field; + const struct asm_psr *psr; + char *start; + + /* CPSR's and SPSR's can now be lowercase. This is just a convenience + feature for ease of use and backwards compatibility. */ + p = *str; + if (strncasecmp (p, "SPSR", 4) == 0) + psr_field = SPSR_BIT; + else if (strncasecmp (p, "CPSR", 4) == 0) + psr_field = 0; + else + { + start = p; + do + p++; + while (ISALNUM (*p) || *p == '_'); + + psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); + if (!psr) + return FAIL; + + *str = p; + return psr->field; + } + + p += 4; + if (*p == '_') + { + /* A suffix follows. */ + p++; + start = p; + + do + p++; + while (ISALNUM (*p) || *p == '_'); + + psr = hash_find_n (arm_psr_hsh, start, p - start); + if (!psr) + goto error; + + psr_field |= psr->field; + } + else + { + if (ISALNUM (*p)) + goto error; /* Garbage after "[CS]PSR". */ + + psr_field |= (PSR_c | PSR_f); + } + *str = p; + return psr_field; + + error: + inst.error = _("flag for {c}psr instruction expected"); + return FAIL; +} + +/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a + value suitable for splatting into the AIF field of the instruction. */ + +static int +parse_cps_flags (char **str) +{ + int val = 0; + int saw_a_flag = 0; + char *s = *str; + + for (;;) + switch (*s++) + { + case '\0': case ',': + goto done; + + case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; + case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; + case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; + + default: + inst.error = _("unrecognized CPS flag"); + return FAIL; + } + + done: + if (saw_a_flag == 0) + { + inst.error = _("missing CPS flags"); + return FAIL; + } + + *str = s - 1; + return val; +} + +/* Parse an endian specifier ("BE" or "LE", case insensitive); + returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ + +static int +parse_endian_specifier (char **str) +{ + int little_endian; + char *s = *str; + + if (strncasecmp (s, "BE", 2)) + little_endian = 0; + else if (strncasecmp (s, "LE", 2)) + little_endian = 1; + else + { + inst.error = _("valid endian specifiers are be or le"); + return FAIL; + } + + if (ISALNUM (s[2]) || s[2] == '_') + { + inst.error = _("valid endian specifiers are be or le"); + return FAIL; + } + + *str = s + 2; + return little_endian; +} + +/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a + value suitable for poking into the rotate field of an sxt or sxta + instruction, or FAIL on error. */ + +static int +parse_ror (char **str) +{ + int rot; + char *s = *str; + + if (strncasecmp (s, "ROR", 3) == 0) + s += 3; + else + { + inst.error = _("missing rotation field after comma"); + return FAIL; + } + + if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) + return FAIL; + + switch (rot) + { + case 0: *str = s; return 0x0; + case 8: *str = s; return 0x1; + case 16: *str = s; return 0x2; + case 24: *str = s; return 0x3; + + default: + inst.error = _("rotation can only be 0, 8, 16, or 24"); + return FAIL; + } +} + +/* Parse a conditional code (from conds[] below). The value returned is in the + range 0 .. 14, or FAIL. */ +static int +parse_cond (char **str) +{ + char *q; + const struct asm_cond *c; + int n; + /* Condition codes are always 2 characters, so matching up to + 3 characters is sufficient. */ + char cond[3]; + + q = *str; + n = 0; + while (ISALPHA (*q) && n < 3) + { + cond[n] = TOLOWER (*q); + q++; + n++; + } + + c = hash_find_n (arm_cond_hsh, cond, n); + if (!c) + { + inst.error = _("condition required"); + return FAIL; + } + + *str = q; + return c->value; +} + +/* Parse an option for a barrier instruction. Returns the encoding for the + option, or FAIL. */ +static int +parse_barrier (char **str) +{ + char *p, *q; + const struct asm_barrier_opt *o; + + p = q = *str; + while (ISALPHA (*q)) + q++; + + o = hash_find_n (arm_barrier_opt_hsh, p, q - p); + if (!o) + return FAIL; + + *str = q; + return o->value; +} + +/* Parse the operands of a table branch instruction. Similar to a memory + operand. */ +static int +parse_tb (char **str) +{ + char * p = *str; + int reg; + + if (skip_past_char (&p, '[') == FAIL) + { + inst.error = _("'[' expected"); + return FAIL; + } + + if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) + { + inst.error = _(reg_expected_msgs[REG_TYPE_RN]); + return FAIL; + } + inst.operands[0].reg = reg; + + if (skip_past_comma (&p) == FAIL) + { + inst.error = _("',' expected"); + return FAIL; + } + + if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) + { + inst.error = _(reg_expected_msgs[REG_TYPE_RN]); + return FAIL; + } + inst.operands[0].imm = reg; + + if (skip_past_comma (&p) == SUCCESS) + { + if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) + return FAIL; + if (inst.reloc.exp.X_add_number != 1) + { + inst.error = _("invalid shift"); + return FAIL; + } + inst.operands[0].shifted = 1; + } + + if (skip_past_char (&p, ']') == FAIL) + { + inst.error = _("']' expected"); + return FAIL; + } + *str = p; + return SUCCESS; +} + +/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more + information on the types the operands can take and how they are encoded. + Up to four operands may be read; this function handles setting the + ".present" field for each read operand itself. + Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, + else returns FAIL. */ + +static int +parse_neon_mov (char **str, int *which_operand) +{ + int i = *which_operand, val; + enum arm_reg_type rtype; + char *ptr = *str; + struct neon_type_el optype; + + if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) + { + /* Case 4: VMOV. , . */ + inst.operands[i].reg = val; + inst.operands[i].isscalar = 1; + inst.operands[i].vectype = optype; + inst.operands[i++].present = 1; + + if (skip_past_comma (&ptr) == FAIL) + goto wanted_comma; + + if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) + goto wanted_arm; + + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i].present = 1; + } + else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) + != FAIL) + { + /* Cases 0, 1, 2, 3, 5 (D only). */ + if (skip_past_comma (&ptr) == FAIL) + goto wanted_comma; + + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i].isquad = (rtype == REG_TYPE_NQ); + inst.operands[i].issingle = (rtype == REG_TYPE_VFS); + inst.operands[i].isvec = 1; + inst.operands[i].vectype = optype; + inst.operands[i++].present = 1; + + if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) + { + /* Case 5: VMOV , , . + Case 13: VMOV , */ + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i].present = 1; + + if (rtype == REG_TYPE_NQ) + { + first_error (_("can't use Neon quad register here")); + return FAIL; + } + else if (rtype != REG_TYPE_VFS) + { + i++; + if (skip_past_comma (&ptr) == FAIL) + goto wanted_comma; + if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) + goto wanted_arm; + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i].present = 1; + } + } + else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, + &optype)) != FAIL) + { + /* Case 0: VMOV , + Case 1: VMOV
, + Case 8: VMOV.F32 , + Case 15: VMOV , , , */ + + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i].isquad = (rtype == REG_TYPE_NQ); + inst.operands[i].issingle = (rtype == REG_TYPE_VFS); + inst.operands[i].isvec = 1; + inst.operands[i].vectype = optype; + inst.operands[i].present = 1; + + if (skip_past_comma (&ptr) == SUCCESS) + { + /* Case 15. */ + i++; + + if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) + goto wanted_arm; + + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i++].present = 1; + + if (skip_past_comma (&ptr) == FAIL) + goto wanted_comma; + + if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) + goto wanted_arm; + + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i++].present = 1; + } + } + else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) + /* Case 2: VMOV.
, # + Case 3: VMOV.
, # + Case 10: VMOV.F32 , # + Case 11: VMOV.F64
, # */ + inst.operands[i].immisfloat = 1; + else if (parse_big_immediate (&ptr, i) == SUCCESS) + /* Case 2: VMOV.
, # + Case 3: VMOV.
, # */ + ; + else + { + first_error (_("expected or or operand")); + return FAIL; + } + } + else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) + { + /* Cases 6, 7. */ + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i++].present = 1; + + if (skip_past_comma (&ptr) == FAIL) + goto wanted_comma; + + if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) + { + /* Case 6: VMOV.
, */ + inst.operands[i].reg = val; + inst.operands[i].isscalar = 1; + inst.operands[i].present = 1; + inst.operands[i].vectype = optype; + } + else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) + { + /* Case 7: VMOV , , */ + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i++].present = 1; + + if (skip_past_comma (&ptr) == FAIL) + goto wanted_comma; + + if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) + == FAIL) + { + first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); + return FAIL; + } + + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i].isvec = 1; + inst.operands[i].issingle = (rtype == REG_TYPE_VFS); + inst.operands[i].vectype = optype; + inst.operands[i].present = 1; + + if (rtype == REG_TYPE_VFS) + { + /* Case 14. */ + i++; + if (skip_past_comma (&ptr) == FAIL) + goto wanted_comma; + if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, + &optype)) == FAIL) + { + first_error (_(reg_expected_msgs[REG_TYPE_VFS])); + return FAIL; + } + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i].isvec = 1; + inst.operands[i].issingle = 1; + inst.operands[i].vectype = optype; + inst.operands[i].present = 1; + } + } + else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) + != FAIL) + { + /* Case 13. */ + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + inst.operands[i].isvec = 1; + inst.operands[i].issingle = 1; + inst.operands[i].vectype = optype; + inst.operands[i++].present = 1; + } + } + else + { + first_error (_("parse error")); + return FAIL; + } + + /* Successfully parsed the operands. Update args. */ + *which_operand = i; + *str = ptr; + return SUCCESS; + + wanted_comma: + first_error (_("expected comma")); + return FAIL; + + wanted_arm: + first_error (_(reg_expected_msgs[REG_TYPE_RN])); + return FAIL; +} + +/* Matcher codes for parse_operands. */ +enum operand_parse_code +{ + OP_stop, /* end of line */ + + OP_RR, /* ARM register */ + OP_RRnpc, /* ARM register, not r15 */ + OP_RRnpcb, /* ARM register, not r15, in square brackets */ + OP_RRw, /* ARM register, not r15, optional trailing ! */ + OP_RCP, /* Coprocessor number */ + OP_RCN, /* Coprocessor register */ + OP_RF, /* FPA register */ + OP_RVS, /* VFP single precision register */ + OP_RVD, /* VFP double precision register (0..15) */ + OP_RND, /* Neon double precision register (0..31) */ + OP_RNQ, /* Neon quad precision register */ + OP_RVSD, /* VFP single or double precision register */ + OP_RNDQ, /* Neon double or quad precision register */ + OP_RNSDQ, /* Neon single, double or quad precision register */ + OP_RNSC, /* Neon scalar D[X] */ + OP_RVC, /* VFP control register */ + OP_RMF, /* Maverick F register */ + OP_RMD, /* Maverick D register */ + OP_RMFX, /* Maverick FX register */ + OP_RMDX, /* Maverick DX register */ + OP_RMAX, /* Maverick AX register */ + OP_RMDS, /* Maverick DSPSC register */ + OP_RIWR, /* iWMMXt wR register */ + OP_RIWC, /* iWMMXt wC register */ + OP_RIWG, /* iWMMXt wCG register */ + OP_RXA, /* XScale accumulator register */ + + OP_REGLST, /* ARM register list */ + OP_VRSLST, /* VFP single-precision register list */ + OP_VRDLST, /* VFP double-precision register list */ + OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ + OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ + OP_NSTRLST, /* Neon element/structure list */ + + OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ + OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ + OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ + OP_RR_RNSC, /* ARM reg or Neon scalar. */ + OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ + OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ + OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ + OP_VMOV, /* Neon VMOV operands. */ + OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ + OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ + OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ + + OP_I0, /* immediate zero */ + OP_I7, /* immediate value 0 .. 7 */ + OP_I15, /* 0 .. 15 */ + OP_I16, /* 1 .. 16 */ + OP_I16z, /* 0 .. 16 */ + OP_I31, /* 0 .. 31 */ + OP_I31w, /* 0 .. 31, optional trailing ! */ + OP_I32, /* 1 .. 32 */ + OP_I32z, /* 0 .. 32 */ + OP_I63, /* 0 .. 63 */ + OP_I63s, /* -64 .. 63 */ + OP_I64, /* 1 .. 64 */ + OP_I64z, /* 0 .. 64 */ + OP_I255, /* 0 .. 255 */ + + OP_I4b, /* immediate, prefix optional, 1 .. 4 */ + OP_I7b, /* 0 .. 7 */ + OP_I15b, /* 0 .. 15 */ + OP_I31b, /* 0 .. 31 */ + + OP_SH, /* shifter operand */ + OP_SHG, /* shifter operand with possible group relocation */ + OP_ADDR, /* Memory address expression (any mode) */ + OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ + OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ + OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ + OP_EXP, /* arbitrary expression */ + OP_EXPi, /* same, with optional immediate prefix */ + OP_EXPr, /* same, with optional relocation suffix */ + OP_HALF, /* 0 .. 65535 or low/high reloc. */ + + OP_CPSF, /* CPS flags */ + OP_ENDI, /* Endianness specifier */ + OP_PSR, /* CPSR/SPSR mask for msr */ + OP_COND, /* conditional code */ + OP_TB, /* Table branch. */ + + OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ + OP_APSR_RR, /* ARM register or "APSR_nzcv". */ + + OP_RRnpc_I0, /* ARM register or literal 0 */ + OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ + OP_RR_EXi, /* ARM register or expression with imm prefix */ + OP_RF_IF, /* FPA register or immediate */ + OP_RIWR_RIWC, /* iWMMXt R or C reg */ + OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ + + /* Optional operands. */ + OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ + OP_oI31b, /* 0 .. 31 */ + OP_oI32b, /* 1 .. 32 */ + OP_oIffffb, /* 0 .. 65535 */ + OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ + + OP_oRR, /* ARM register */ + OP_oRRnpc, /* ARM register, not the PC */ + OP_oRRw, /* ARM register, not r15, optional trailing ! */ + OP_oRND, /* Optional Neon double precision register */ + OP_oRNQ, /* Optional Neon quad precision register */ + OP_oRNDQ, /* Optional Neon double or quad precision register */ + OP_oRNSDQ, /* Optional single, double or quad precision vector register */ + OP_oSHll, /* LSL immediate */ + OP_oSHar, /* ASR immediate */ + OP_oSHllar, /* LSL or ASR immediate */ + OP_oROR, /* ROR 0/8/16/24 */ + OP_oBARRIER, /* Option argument for a barrier instruction. */ + + OP_FIRST_OPTIONAL = OP_oI7b +}; + +/* Generic instruction operand parser. This does no encoding and no + semantic validation; it merely squirrels values away in the inst + structure. Returns SUCCESS or FAIL depending on whether the + specified grammar matched. */ +static int +parse_operands (char *str, const unsigned char *pattern) +{ + unsigned const char *upat = pattern; + char *backtrack_pos = 0; + const char *backtrack_error = 0; + int i, val, backtrack_index = 0; + enum arm_reg_type rtype; + parse_operand_result result; + +#define po_char_or_fail(chr) \ + do \ + { \ + if (skip_past_char (&str, chr) == FAIL) \ + goto bad_args; \ + } \ + while (0) + +#define po_reg_or_fail(regtype) \ + do \ + { \ + val = arm_typed_reg_parse (& str, regtype, & rtype, \ + & inst.operands[i].vectype); \ + if (val == FAIL) \ + { \ + first_error (_(reg_expected_msgs[regtype])); \ + goto failure; \ + } \ + inst.operands[i].reg = val; \ + inst.operands[i].isreg = 1; \ + inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ + inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ + inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ + || rtype == REG_TYPE_VFD \ + || rtype == REG_TYPE_NQ); \ + } \ + while (0) + +#define po_reg_or_goto(regtype, label) \ + do \ + { \ + val = arm_typed_reg_parse (& str, regtype, & rtype, \ + & inst.operands[i].vectype); \ + if (val == FAIL) \ + goto label; \ + \ + inst.operands[i].reg = val; \ + inst.operands[i].isreg = 1; \ + inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ + inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ + inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ + || rtype == REG_TYPE_VFD \ + || rtype == REG_TYPE_NQ); \ + } \ + while (0) + +#define po_imm_or_fail(min, max, popt) \ + do \ + { \ + if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ + goto failure; \ + inst.operands[i].imm = val; \ + } \ + while (0) + +#define po_scalar_or_goto(elsz, label) \ + do \ + { \ + val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ + if (val == FAIL) \ + goto label; \ + inst.operands[i].reg = val; \ + inst.operands[i].isscalar = 1; \ + } \ + while (0) + +#define po_misc_or_fail(expr) \ + do \ + { \ + if (expr) \ + goto failure; \ + } \ + while (0) + +#define po_misc_or_fail_no_backtrack(expr) \ + do \ + { \ + result = expr; \ + if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ + backtrack_pos = 0; \ + if (result != PARSE_OPERAND_SUCCESS) \ + goto failure; \ + } \ + while (0) + + skip_whitespace (str); + + for (i = 0; upat[i] != OP_stop; i++) + { + if (upat[i] >= OP_FIRST_OPTIONAL) + { + /* Remember where we are in case we need to backtrack. */ + gas_assert (!backtrack_pos); + backtrack_pos = str; + backtrack_error = inst.error; + backtrack_index = i; + } + + if (i > 0 && (i > 1 || inst.operands[0].present)) + po_char_or_fail (','); + + switch (upat[i]) + { + /* Registers */ + case OP_oRRnpc: + case OP_RRnpc: + case OP_oRR: + case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; + case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; + case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; + case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; + case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; + case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; + case OP_oRND: + case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; + case OP_RVC: + po_reg_or_goto (REG_TYPE_VFC, coproc_reg); + break; + /* Also accept generic coprocessor regs for unknown registers. */ + coproc_reg: + po_reg_or_fail (REG_TYPE_CN); + break; + case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; + case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; + case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; + case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; + case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; + case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; + case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; + case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; + case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; + case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; + case OP_oRNQ: + case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; + case OP_oRNDQ: + case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; + case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; + case OP_oRNSDQ: + case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; + + /* Neon scalar. Using an element size of 8 means that some invalid + scalars are accepted here, so deal with those in later code. */ + case OP_RNSC: po_scalar_or_goto (8, failure); break; + + /* WARNING: We can expand to two operands here. This has the potential + to totally confuse the backtracking mechanism! It will be OK at + least as long as we don't try to use optional args as well, + though. */ + case OP_NILO: + { + po_reg_or_goto (REG_TYPE_NDQ, try_imm); + inst.operands[i].present = 1; + i++; + skip_past_comma (&str); + po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); + break; + one_reg_only: + /* Optional register operand was omitted. Unfortunately, it's in + operands[i-1] and we need it to be in inst.operands[i]. Fix that + here (this is a bit grotty). */ + inst.operands[i] = inst.operands[i-1]; + inst.operands[i-1].present = 0; + break; + try_imm: + /* There's a possibility of getting a 64-bit immediate here, so + we need special handling. */ + if (parse_big_immediate (&str, i) == FAIL) + { + inst.error = _("immediate value is out of range"); + goto failure; + } + } + break; + + case OP_RNDQ_I0: + { + po_reg_or_goto (REG_TYPE_NDQ, try_imm0); + break; + try_imm0: + po_imm_or_fail (0, 0, TRUE); + } + break; + + case OP_RVSD_I0: + po_reg_or_goto (REG_TYPE_VFSD, try_imm0); + break; + + case OP_RR_RNSC: + { + po_scalar_or_goto (8, try_rr); + break; + try_rr: + po_reg_or_fail (REG_TYPE_RN); + } + break; + + case OP_RNSDQ_RNSC: + { + po_scalar_or_goto (8, try_nsdq); + break; + try_nsdq: + po_reg_or_fail (REG_TYPE_NSDQ); + } + break; + + case OP_RNDQ_RNSC: + { + po_scalar_or_goto (8, try_ndq); + break; + try_ndq: + po_reg_or_fail (REG_TYPE_NDQ); + } + break; + + case OP_RND_RNSC: + { + po_scalar_or_goto (8, try_vfd); + break; + try_vfd: + po_reg_or_fail (REG_TYPE_VFD); + } + break; + + case OP_VMOV: + /* WARNING: parse_neon_mov can move the operand counter, i. If we're + not careful then bad things might happen. */ + po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); + break; + + case OP_RNDQ_IMVNb: + { + po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); + break; + try_mvnimm: + /* There's a possibility of getting a 64-bit immediate here, so + we need special handling. */ + if (parse_big_immediate (&str, i) == FAIL) + { + inst.error = _("immediate value is out of range"); + goto failure; + } + } + break; + + case OP_RNDQ_I63b: + { + po_reg_or_goto (REG_TYPE_NDQ, try_shimm); + break; + try_shimm: + po_imm_or_fail (0, 63, TRUE); + } + break; + + case OP_RRnpcb: + po_char_or_fail ('['); + po_reg_or_fail (REG_TYPE_RN); + po_char_or_fail (']'); + break; + + case OP_RRw: + case OP_oRRw: + po_reg_or_fail (REG_TYPE_RN); + if (skip_past_char (&str, '!') == SUCCESS) + inst.operands[i].writeback = 1; + break; + + /* Immediates */ + case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; + case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; + case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; + case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; + case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; + case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; + case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; + case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; + case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; + case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; + case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; + case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; + + case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; + case OP_oI7b: + case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; + case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; + case OP_oI31b: + case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; + case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; + case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; + + /* Immediate variants */ + case OP_oI255c: + po_char_or_fail ('{'); + po_imm_or_fail (0, 255, TRUE); + po_char_or_fail ('}'); + break; + + case OP_I31w: + /* The expression parser chokes on a trailing !, so we have + to find it first and zap it. */ + { + char *s = str; + while (*s && *s != ',') + s++; + if (s[-1] == '!') + { + s[-1] = '\0'; + inst.operands[i].writeback = 1; + } + po_imm_or_fail (0, 31, TRUE); + if (str == s - 1) + str = s; + } + break; + + /* Expressions */ + case OP_EXPi: EXPi: + po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, + GE_OPT_PREFIX)); + break; + + case OP_EXP: + po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, + GE_NO_PREFIX)); + break; + + case OP_EXPr: EXPr: + po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, + GE_NO_PREFIX)); + if (inst.reloc.exp.X_op == O_symbol) + { + val = parse_reloc (&str); + if (val == -1) + { + inst.error = _("unrecognized relocation suffix"); + goto failure; + } + else if (val != BFD_RELOC_UNUSED) + { + inst.operands[i].imm = val; + inst.operands[i].hasreloc = 1; + } + } + break; + + /* Operand for MOVW or MOVT. */ + case OP_HALF: + po_misc_or_fail (parse_half (&str)); + break; + + /* Register or expression. */ + case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; + case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; + + /* Register or immediate. */ + case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; + I0: po_imm_or_fail (0, 0, FALSE); break; + + case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; + IF: + if (!is_immediate_prefix (*str)) + goto bad_args; + str++; + val = parse_fpa_immediate (&str); + if (val == FAIL) + goto failure; + /* FPA immediates are encoded as registers 8-15. + parse_fpa_immediate has already applied the offset. */ + inst.operands[i].reg = val; + inst.operands[i].isreg = 1; + break; + + case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; + I32z: po_imm_or_fail (0, 32, FALSE); break; + + /* Two kinds of register. */ + case OP_RIWR_RIWC: + { + struct reg_entry *rege = arm_reg_parse_multi (&str); + if (!rege + || (rege->type != REG_TYPE_MMXWR + && rege->type != REG_TYPE_MMXWC + && rege->type != REG_TYPE_MMXWCG)) + { + inst.error = _("iWMMXt data or control register expected"); + goto failure; + } + inst.operands[i].reg = rege->number; + inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); + } + break; + + case OP_RIWC_RIWG: + { + struct reg_entry *rege = arm_reg_parse_multi (&str); + if (!rege + || (rege->type != REG_TYPE_MMXWC + && rege->type != REG_TYPE_MMXWCG)) + { + inst.error = _("iWMMXt control register expected"); + goto failure; + } + inst.operands[i].reg = rege->number; + inst.operands[i].isreg = 1; + } + break; + + /* Misc */ + case OP_CPSF: val = parse_cps_flags (&str); break; + case OP_ENDI: val = parse_endian_specifier (&str); break; + case OP_oROR: val = parse_ror (&str); break; + case OP_PSR: val = parse_psr (&str); break; + case OP_COND: val = parse_cond (&str); break; + case OP_oBARRIER:val = parse_barrier (&str); break; + + case OP_RVC_PSR: + po_reg_or_goto (REG_TYPE_VFC, try_psr); + inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ + break; + try_psr: + val = parse_psr (&str); + break; + + case OP_APSR_RR: + po_reg_or_goto (REG_TYPE_RN, try_apsr); + break; + try_apsr: + /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS + instruction). */ + if (strncasecmp (str, "APSR_", 5) == 0) + { + unsigned found = 0; + str += 5; + while (found < 15) + switch (*str++) + { + case 'c': found = (found & 1) ? 16 : found | 1; break; + case 'n': found = (found & 2) ? 16 : found | 2; break; + case 'z': found = (found & 4) ? 16 : found | 4; break; + case 'v': found = (found & 8) ? 16 : found | 8; break; + default: found = 16; + } + if (found != 15) + goto failure; + inst.operands[i].isvec = 1; + } + else + goto failure; + break; + + case OP_TB: + po_misc_or_fail (parse_tb (&str)); + break; + + /* Register lists. */ + case OP_REGLST: + val = parse_reg_list (&str); + if (*str == '^') + { + inst.operands[1].writeback = 1; + str++; + } + break; + + case OP_VRSLST: + val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); + break; + + case OP_VRDLST: + val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); + break; + + case OP_VRSDLST: + /* Allow Q registers too. */ + val = parse_vfp_reg_list (&str, &inst.operands[i].reg, + REGLIST_NEON_D); + if (val == FAIL) + { + inst.error = NULL; + val = parse_vfp_reg_list (&str, &inst.operands[i].reg, + REGLIST_VFP_S); + inst.operands[i].issingle = 1; + } + break; + + case OP_NRDLST: + val = parse_vfp_reg_list (&str, &inst.operands[i].reg, + REGLIST_NEON_D); + break; + + case OP_NSTRLST: + val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, + &inst.operands[i].vectype); + break; + + /* Addressing modes */ + case OP_ADDR: + po_misc_or_fail (parse_address (&str, i)); + break; + + case OP_ADDRGLDR: + po_misc_or_fail_no_backtrack ( + parse_address_group_reloc (&str, i, GROUP_LDR)); + break; + + case OP_ADDRGLDRS: + po_misc_or_fail_no_backtrack ( + parse_address_group_reloc (&str, i, GROUP_LDRS)); + break; + + case OP_ADDRGLDC: + po_misc_or_fail_no_backtrack ( + parse_address_group_reloc (&str, i, GROUP_LDC)); + break; + + case OP_SH: + po_misc_or_fail (parse_shifter_operand (&str, i)); + break; + + case OP_SHG: + po_misc_or_fail_no_backtrack ( + parse_shifter_operand_group_reloc (&str, i)); + break; + + case OP_oSHll: + po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); + break; + + case OP_oSHar: + po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); + break; + + case OP_oSHllar: + po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); + break; + + default: + as_fatal (_("unhandled operand code %d"), upat[i]); + } + + /* Various value-based sanity checks and shared operations. We + do not signal immediate failures for the register constraints; + this allows a syntax error to take precedence. */ + switch (upat[i]) + { + case OP_oRRnpc: + case OP_RRnpc: + case OP_RRnpcb: + case OP_RRw: + case OP_oRRw: + case OP_RRnpc_I0: + if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) + inst.error = BAD_PC; + break; + + case OP_CPSF: + case OP_ENDI: + case OP_oROR: + case OP_PSR: + case OP_RVC_PSR: + case OP_COND: + case OP_oBARRIER: + case OP_REGLST: + case OP_VRSLST: + case OP_VRDLST: + case OP_VRSDLST: + case OP_NRDLST: + case OP_NSTRLST: + if (val == FAIL) + goto failure; + inst.operands[i].imm = val; + break; + + default: + break; + } + + /* If we get here, this operand was successfully parsed. */ + inst.operands[i].present = 1; + continue; + + bad_args: + inst.error = BAD_ARGS; + + failure: + if (!backtrack_pos) + { + /* The parse routine should already have set inst.error, but set a + default here just in case. */ + if (!inst.error) + inst.error = _("syntax error"); + return FAIL; + } + + /* Do not backtrack over a trailing optional argument that + absorbed some text. We will only fail again, with the + 'garbage following instruction' error message, which is + probably less helpful than the current one. */ + if (backtrack_index == i && backtrack_pos != str + && upat[i+1] == OP_stop) + { + if (!inst.error) + inst.error = _("syntax error"); + return FAIL; + } + + /* Try again, skipping the optional argument at backtrack_pos. */ + str = backtrack_pos; + inst.error = backtrack_error; + inst.operands[backtrack_index].present = 0; + i = backtrack_index; + backtrack_pos = 0; + } + + /* Check that we have parsed all the arguments. */ + if (*str != '\0' && !inst.error) + inst.error = _("garbage following instruction"); + + return inst.error ? FAIL : SUCCESS; +} + +#undef po_char_or_fail +#undef po_reg_or_fail +#undef po_reg_or_goto +#undef po_imm_or_fail +#undef po_scalar_or_fail + +/* Shorthand macro for instruction encoding functions issuing errors. */ +#define constraint(expr, err) \ + do \ + { \ + if (expr) \ + { \ + inst.error = err; \ + return; \ + } \ + } \ + while (0) + +/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 + instructions are unpredictable if these registers are used. This + is the BadReg predicate in ARM's Thumb-2 documentation. */ +#define reject_bad_reg(reg) \ + do \ + if (reg == REG_SP || reg == REG_PC) \ + { \ + inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ + return; \ + } \ + while (0) + +/* If REG is R13 (the stack pointer), warn that its use is + deprecated. */ +#define warn_deprecated_sp(reg) \ + do \ + if (warn_on_deprecated && reg == REG_SP) \ + as_warn (_("use of r13 is deprecated")); \ + while (0) + +/* Functions for operand encoding. ARM, then Thumb. */ + +#define rotate_left(v, n) (v << n | v >> (32 - n)) + +/* If VAL can be encoded in the immediate field of an ARM instruction, + return the encoded form. Otherwise, return FAIL. */ + +static unsigned int +encode_arm_immediate (unsigned int val) +{ + unsigned int a, i; + + for (i = 0; i < 32; i += 2) + if ((a = rotate_left (val, i)) <= 0xff) + return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ + + return FAIL; +} + +/* If VAL can be encoded in the immediate field of a Thumb32 instruction, + return the encoded form. Otherwise, return FAIL. */ +static unsigned int +encode_thumb32_immediate (unsigned int val) +{ + unsigned int a, i; + + if (val <= 0xff) + return val; + + for (i = 1; i <= 24; i++) + { + a = val >> i; + if ((val & ~(0xff << i)) == 0) + return ((val >> i) & 0x7f) | ((32 - i) << 7); + } + + a = val & 0xff; + if (val == ((a << 16) | a)) + return 0x100 | a; + if (val == ((a << 24) | (a << 16) | (a << 8) | a)) + return 0x300 | a; + + a = val & 0xff00; + if (val == ((a << 16) | a)) + return 0x200 | (a >> 8); + + return FAIL; +} +/* Encode a VFP SP or DP register number into inst.instruction. */ + +static void +encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) +{ + if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) + && reg > 15) + { + if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) + { + if (thumb_mode) + ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, + fpu_vfp_ext_d32); + else + ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, + fpu_vfp_ext_d32); + } + else + { + first_error (_("D register out of range for selected VFP version")); + return; + } + } + + switch (pos) + { + case VFP_REG_Sd: + inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); + break; + + case VFP_REG_Sn: + inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); + break; + + case VFP_REG_Sm: + inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); + break; + + case VFP_REG_Dd: + inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); + break; + + case VFP_REG_Dn: + inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); + break; + + case VFP_REG_Dm: + inst.instruction |= (reg & 15) | ((reg >> 4) << 5); + break; + + default: + abort (); + } +} + +/* Encode a in an ARM-format instruction. The immediate, + if any, is handled by md_apply_fix. */ +static void +encode_arm_shift (int i) +{ + if (inst.operands[i].shift_kind == SHIFT_RRX) + inst.instruction |= SHIFT_ROR << 5; + else + { + inst.instruction |= inst.operands[i].shift_kind << 5; + if (inst.operands[i].immisreg) + { + inst.instruction |= SHIFT_BY_REG; + inst.instruction |= inst.operands[i].imm << 8; + } + else + inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; + } +} + +static void +encode_arm_shifter_operand (int i) +{ + if (inst.operands[i].isreg) + { + inst.instruction |= inst.operands[i].reg; + encode_arm_shift (i); + } + else + inst.instruction |= INST_IMMEDIATE; +} + +/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ +static void +encode_arm_addr_mode_common (int i, bfd_boolean is_t) +{ + gas_assert (inst.operands[i].isreg); + inst.instruction |= inst.operands[i].reg << 16; + + if (inst.operands[i].preind) + { + if (is_t) + { + inst.error = _("instruction does not accept preindexed addressing"); + return; + } + inst.instruction |= PRE_INDEX; + if (inst.operands[i].writeback) + inst.instruction |= WRITE_BACK; + + } + else if (inst.operands[i].postind) + { + gas_assert (inst.operands[i].writeback); + if (is_t) + inst.instruction |= WRITE_BACK; + } + else /* unindexed - only for coprocessor */ + { + inst.error = _("instruction does not accept unindexed addressing"); + return; + } + + if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) + && (((inst.instruction & 0x000f0000) >> 16) + == ((inst.instruction & 0x0000f000) >> 12))) + as_warn ((inst.instruction & LOAD_BIT) + ? _("destination register same as write-back base") + : _("source register same as write-back base")); +} + +/* inst.operands[i] was set up by parse_address. Encode it into an + ARM-format mode 2 load or store instruction. If is_t is true, + reject forms that cannot be used with a T instruction (i.e. not + post-indexed). */ +static void +encode_arm_addr_mode_2 (int i, bfd_boolean is_t) +{ + encode_arm_addr_mode_common (i, is_t); + + if (inst.operands[i].immisreg) + { + inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ + inst.instruction |= inst.operands[i].imm; + if (!inst.operands[i].negative) + inst.instruction |= INDEX_UP; + if (inst.operands[i].shifted) + { + if (inst.operands[i].shift_kind == SHIFT_RRX) + inst.instruction |= SHIFT_ROR << 5; + else + { + inst.instruction |= inst.operands[i].shift_kind << 5; + inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; + } + } + } + else /* immediate offset in inst.reloc */ + { + if (inst.reloc.type == BFD_RELOC_UNUSED) + inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; + } +} + +/* inst.operands[i] was set up by parse_address. Encode it into an + ARM-format mode 3 load or store instruction. Reject forms that + cannot be used with such instructions. If is_t is true, reject + forms that cannot be used with a T instruction (i.e. not + post-indexed). */ +static void +encode_arm_addr_mode_3 (int i, bfd_boolean is_t) +{ + if (inst.operands[i].immisreg && inst.operands[i].shifted) + { + inst.error = _("instruction does not accept scaled register index"); + return; + } + + encode_arm_addr_mode_common (i, is_t); + + if (inst.operands[i].immisreg) + { + inst.instruction |= inst.operands[i].imm; + if (!inst.operands[i].negative) + inst.instruction |= INDEX_UP; + } + else /* immediate offset in inst.reloc */ + { + inst.instruction |= HWOFFSET_IMM; + if (inst.reloc.type == BFD_RELOC_UNUSED) + inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; + } +} + +/* inst.operands[i] was set up by parse_address. Encode it into an + ARM-format instruction. Reject all forms which cannot be encoded + into a coprocessor load/store instruction. If wb_ok is false, + reject use of writeback; if unind_ok is false, reject use of + unindexed addressing. If reloc_override is not 0, use it instead + of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one + (in which case it is preserved). */ + +static int +encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) +{ + inst.instruction |= inst.operands[i].reg << 16; + + gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); + + if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ + { + gas_assert (!inst.operands[i].writeback); + if (!unind_ok) + { + inst.error = _("instruction does not support unindexed addressing"); + return FAIL; + } + inst.instruction |= inst.operands[i].imm; + inst.instruction |= INDEX_UP; + return SUCCESS; + } + + if (inst.operands[i].preind) + inst.instruction |= PRE_INDEX; + + if (inst.operands[i].writeback) + { + if (inst.operands[i].reg == REG_PC) + { + inst.error = _("pc may not be used with write-back"); + return FAIL; + } + if (!wb_ok) + { + inst.error = _("instruction does not support writeback"); + return FAIL; + } + inst.instruction |= WRITE_BACK; + } + + if (reloc_override) + inst.reloc.type = reloc_override; + else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC + || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) + && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) + { + if (thumb_mode) + inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; + else + inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; + } + + return SUCCESS; +} + +/* inst.reloc.exp describes an "=expr" load pseudo-operation. + Determine whether it can be performed with a move instruction; if + it can, convert inst.instruction to that move instruction and + return TRUE; if it can't, convert inst.instruction to a literal-pool + load and return FALSE. If this is not a valid thing to do in the + current context, set inst.error and return TRUE. + + inst.operands[i] describes the destination register. */ + +static bfd_boolean +move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) +{ + unsigned long tbit; + + if (thumb_p) + tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; + else + tbit = LOAD_BIT; + + if ((inst.instruction & tbit) == 0) + { + inst.error = _("invalid pseudo operation"); + return TRUE; + } + if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) + { + inst.error = _("constant expression expected"); + return TRUE; + } + if (inst.reloc.exp.X_op == O_constant) + { + if (thumb_p) + { + if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) + { + /* This can be done with a mov(1) instruction. */ + inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); + inst.instruction |= inst.reloc.exp.X_add_number; + return TRUE; + } + } + else + { + int value = encode_arm_immediate (inst.reloc.exp.X_add_number); + if (value != FAIL) + { + /* This can be done with a mov instruction. */ + inst.instruction &= LITERAL_MASK; + inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); + inst.instruction |= value & 0xfff; + return TRUE; + } + + value = encode_arm_immediate (~inst.reloc.exp.X_add_number); + if (value != FAIL) + { + /* This can be done with a mvn instruction. */ + inst.instruction &= LITERAL_MASK; + inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); + inst.instruction |= value & 0xfff; + return TRUE; + } + } + } + + if (add_to_lit_pool () == FAIL) + { + inst.error = _("literal pool insertion failed"); + return TRUE; + } + inst.operands[1].reg = REG_PC; + inst.operands[1].isreg = 1; + inst.operands[1].preind = 1; + inst.reloc.pc_rel = 1; + inst.reloc.type = (thumb_p + ? BFD_RELOC_ARM_THUMB_OFFSET + : (mode_3 + ? BFD_RELOC_ARM_HWLITERAL + : BFD_RELOC_ARM_LITERAL)); + return FALSE; +} + +/* Functions for instruction encoding, sorted by sub-architecture. + First some generics; their names are taken from the conventional + bit positions for register arguments in ARM format instructions. */ + +static void +do_noargs (void) +{ +} + +static void +do_rd (void) +{ + inst.instruction |= inst.operands[0].reg << 12; +} + +static void +do_rd_rm (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg; +} + +static void +do_rd_rn (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; +} + +static void +do_rn_rd (void) +{ + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[1].reg << 12; +} + +static void +do_rd_rm_rn (void) +{ + unsigned Rn = inst.operands[2].reg; + /* Enforce restrictions on SWP instruction. */ + if ((inst.instruction & 0x0fbfffff) == 0x01000090) + constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, + _("Rn must not overlap other operands")); + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= Rn << 16; +} + +static void +do_rd_rn_rm (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; +} + +static void +do_rm_rd_rn (void) +{ + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= inst.operands[2].reg << 16; +} + +static void +do_imm0 (void) +{ + inst.instruction |= inst.operands[0].imm; +} + +static void +do_rd_cpaddr (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + encode_arm_cp_address (1, TRUE, TRUE, 0); +} + +/* ARM instructions, in alphabetical order by function name (except + that wrapper functions appear immediately after the function they + wrap). */ + +/* This is a pseudo-op of the form "adr rd, label" to be converted + into a relative address of the form "add rd, pc, #label-.-8". */ + +static void +do_adr (void) +{ + inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ + + /* Frag hacking will turn this into a sub instruction if the offset turns + out to be negative. */ + inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; + inst.reloc.pc_rel = 1; + inst.reloc.exp.X_add_number -= 8; +} + +/* This is a pseudo-op of the form "adrl rd, label" to be converted + into a relative address of the form: + add rd, pc, #low(label-.-8)" + add rd, rd, #high(label-.-8)" */ + +static void +do_adrl (void) +{ + inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ + + /* Frag hacking will turn this into a sub instruction if the offset turns + out to be negative. */ + inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; + inst.reloc.pc_rel = 1; + inst.size = INSN_SIZE * 2; + inst.reloc.exp.X_add_number -= 8; +} + +static void +do_arit (void) +{ + if (!inst.operands[1].present) + inst.operands[1].reg = inst.operands[0].reg; + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + encode_arm_shifter_operand (2); +} + +static void +do_barrier (void) +{ + if (inst.operands[0].present) + { + constraint ((inst.instruction & 0xf0) != 0x40 + && inst.operands[0].imm != 0xf, + _("bad barrier type")); + inst.instruction |= inst.operands[0].imm; + } + else + inst.instruction |= 0xf; +} + +static void +do_bfc (void) +{ + unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; + constraint (msb > 32, _("bit-field extends past end of register")); + /* The instruction encoding stores the LSB and MSB, + not the LSB and width. */ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].imm << 7; + inst.instruction |= (msb - 1) << 16; +} + +static void +do_bfi (void) +{ + unsigned int msb; + + /* #0 in second position is alternative syntax for bfc, which is + the same instruction but with REG_PC in the Rm field. */ + if (!inst.operands[1].isreg) + inst.operands[1].reg = REG_PC; + + msb = inst.operands[2].imm + inst.operands[3].imm; + constraint (msb > 32, _("bit-field extends past end of register")); + /* The instruction encoding stores the LSB and MSB, + not the LSB and width. */ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].imm << 7; + inst.instruction |= (msb - 1) << 16; +} + +static void +do_bfx (void) +{ + constraint (inst.operands[2].imm + inst.operands[3].imm > 32, + _("bit-field extends past end of register")); + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].imm << 7; + inst.instruction |= (inst.operands[3].imm - 1) << 16; +} + +/* ARM V5 breakpoint instruction (argument parse) + BKPT <16 bit unsigned immediate> + Instruction is not conditional. + The bit pattern given in insns[] has the COND_ALWAYS condition, + and it is an error if the caller tried to override that. */ + +static void +do_bkpt (void) +{ + /* Top 12 of 16 bits to bits 19:8. */ + inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; + + /* Bottom 4 of 16 bits to bits 3:0. */ + inst.instruction |= inst.operands[0].imm & 0xf; +} + +static void +encode_branch (int default_reloc) +{ + if (inst.operands[0].hasreloc) + { + constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, + _("the only suffix valid here is '(plt)'")); + inst.reloc.type = BFD_RELOC_ARM_PLT32; + } + else + { + inst.reloc.type = default_reloc; + } + inst.reloc.pc_rel = 1; +} + +static void +do_branch (void) +{ +#ifdef OBJ_ELF + if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) + encode_branch (BFD_RELOC_ARM_PCREL_JUMP); + else +#endif + encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); +} + +static void +do_bl (void) +{ +#ifdef OBJ_ELF + if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) + { + if (inst.cond == COND_ALWAYS) + encode_branch (BFD_RELOC_ARM_PCREL_CALL); + else + encode_branch (BFD_RELOC_ARM_PCREL_JUMP); + } + else +#endif + encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); +} + +/* ARM V5 branch-link-exchange instruction (argument parse) + BLX ie BLX(1) + BLX{} ie BLX(2) + Unfortunately, there are two different opcodes for this mnemonic. + So, the insns[].value is not used, and the code here zaps values + into inst.instruction. + Also, the can be 25 bits, hence has its own reloc. */ + +static void +do_blx (void) +{ + if (inst.operands[0].isreg) + { + /* Arg is a register; the opcode provided by insns[] is correct. + It is not illegal to do "blx pc", just useless. */ + if (inst.operands[0].reg == REG_PC) + as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); + + inst.instruction |= inst.operands[0].reg; + } + else + { + /* Arg is an address; this instruction cannot be executed + conditionally, and the opcode must be adjusted. + We retain the BFD_RELOC_ARM_PCREL_BLX till the very end + where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ + constraint (inst.cond != COND_ALWAYS, BAD_COND); + inst.instruction = 0xfa000000; + encode_branch (BFD_RELOC_ARM_PCREL_BLX); + } +} + +static void +do_bx (void) +{ + bfd_boolean want_reloc; + + if (inst.operands[0].reg == REG_PC) + as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); + + inst.instruction |= inst.operands[0].reg; + /* Output R_ARM_V4BX relocations if is an EABI object that looks like + it is for ARMv4t or earlier. */ + want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); + if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) + want_reloc = TRUE; + +#ifdef OBJ_ELF + if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) +#endif + want_reloc = FALSE; + + if (want_reloc) + inst.reloc.type = BFD_RELOC_ARM_V4BX; +} + + +/* ARM v5TEJ. Jump to Jazelle code. */ + +static void +do_bxj (void) +{ + if (inst.operands[0].reg == REG_PC) + as_tsktsk (_("use of r15 in bxj is not really useful")); + + inst.instruction |= inst.operands[0].reg; +} + +/* Co-processor data operation: + CDP{cond} , , , , {, } + CDP2 , , , , {, } */ +static void +do_cdp (void) +{ + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].imm << 20; + inst.instruction |= inst.operands[2].reg << 12; + inst.instruction |= inst.operands[3].reg << 16; + inst.instruction |= inst.operands[4].reg; + inst.instruction |= inst.operands[5].imm << 5; +} + +static void +do_cmp (void) +{ + inst.instruction |= inst.operands[0].reg << 16; + encode_arm_shifter_operand (1); +} + +/* Transfer between coprocessor and ARM registers. + MRC{cond} , , , , {, } + MRC2 + MCR{cond} + MCR2 + + No special properties. */ + +static void +do_co_reg (void) +{ + unsigned Rd; + + Rd = inst.operands[2].reg; + if (thumb_mode) + { + if (inst.instruction == 0xee000010 + || inst.instruction == 0xfe000010) + /* MCR, MCR2 */ + reject_bad_reg (Rd); + else + /* MRC, MRC2 */ + constraint (Rd == REG_SP, BAD_SP); + } + else + { + /* MCR */ + if (inst.instruction == 0xe000010) + constraint (Rd == REG_PC, BAD_PC); + } + + + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].imm << 21; + inst.instruction |= Rd << 12; + inst.instruction |= inst.operands[3].reg << 16; + inst.instruction |= inst.operands[4].reg; + inst.instruction |= inst.operands[5].imm << 5; +} + +/* Transfer between coprocessor register and pair of ARM registers. + MCRR{cond} , , , , . + MCRR2 + MRRC{cond} + MRRC2 + + Two XScale instructions are special cases of these: + + MAR{cond} acc0, , == MCRR{cond} p0, #0, , , c0 + MRA{cond} acc0, , == MRRC{cond} p0, #0, , , c0 + + Result unpredictable if Rd or Rn is R15. */ + +static void +do_co_reg2c (void) +{ + unsigned Rd, Rn; + + Rd = inst.operands[2].reg; + Rn = inst.operands[3].reg; + + if (thumb_mode) + { + reject_bad_reg (Rd); + reject_bad_reg (Rn); + } + else + { + constraint (Rd == REG_PC, BAD_PC); + constraint (Rn == REG_PC, BAD_PC); + } + + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].imm << 4; + inst.instruction |= Rd << 12; + inst.instruction |= Rn << 16; + inst.instruction |= inst.operands[4].reg; +} + +static void +do_cpsi (void) +{ + inst.instruction |= inst.operands[0].imm << 6; + if (inst.operands[1].present) + { + inst.instruction |= CPSI_MMOD; + inst.instruction |= inst.operands[1].imm; + } +} + +static void +do_dbg (void) +{ + inst.instruction |= inst.operands[0].imm; +} + +static void +do_it (void) +{ + /* There is no IT instruction in ARM mode. We + process it to do the validation as if in + thumb mode, just in case the code gets + assembled for thumb using the unified syntax. */ + + inst.size = 0; + if (unified_syntax) + { + set_it_insn_type (IT_INSN); + now_it.mask = (inst.instruction & 0xf) | 0x10; + now_it.cc = inst.operands[0].imm; + } +} + +static void +do_ldmstm (void) +{ + int base_reg = inst.operands[0].reg; + int range = inst.operands[1].imm; + + inst.instruction |= base_reg << 16; + inst.instruction |= range; + + if (inst.operands[1].writeback) + inst.instruction |= LDM_TYPE_2_OR_3; + + if (inst.operands[0].writeback) + { + inst.instruction |= WRITE_BACK; + /* Check for unpredictable uses of writeback. */ + if (inst.instruction & LOAD_BIT) + { + /* Not allowed in LDM type 2. */ + if ((inst.instruction & LDM_TYPE_2_OR_3) + && ((range & (1 << REG_PC)) == 0)) + as_warn (_("writeback of base register is UNPREDICTABLE")); + /* Only allowed if base reg not in list for other types. */ + else if (range & (1 << base_reg)) + as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); + } + else /* STM. */ + { + /* Not allowed for type 2. */ + if (inst.instruction & LDM_TYPE_2_OR_3) + as_warn (_("writeback of base register is UNPREDICTABLE")); + /* Only allowed if base reg not in list, or first in list. */ + else if ((range & (1 << base_reg)) + && (range & ((1 << base_reg) - 1))) + as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); + } + } +} + +/* ARMv5TE load-consecutive (argument parse) + Mode is like LDRH. + + LDRccD R, mode + STRccD R, mode. */ + +static void +do_ldrd (void) +{ + constraint (inst.operands[0].reg % 2 != 0, + _("first destination register must be even")); + constraint (inst.operands[1].present + && inst.operands[1].reg != inst.operands[0].reg + 1, + _("can only load two consecutive registers")); + constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); + constraint (!inst.operands[2].isreg, _("'[' expected")); + + if (!inst.operands[1].present) + inst.operands[1].reg = inst.operands[0].reg + 1; + + if (inst.instruction & LOAD_BIT) + { + /* encode_arm_addr_mode_3 will diagnose overlap between the base + register and the first register written; we have to diagnose + overlap between the base and the second register written here. */ + + if (inst.operands[2].reg == inst.operands[1].reg + && (inst.operands[2].writeback || inst.operands[2].postind)) + as_warn (_("base register written back, and overlaps " + "second destination register")); + + /* For an index-register load, the index register must not overlap the + destination (even if not write-back). */ + else if (inst.operands[2].immisreg + && ((unsigned) inst.operands[2].imm == inst.operands[0].reg + || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) + as_warn (_("index register overlaps destination register")); + } + + inst.instruction |= inst.operands[0].reg << 12; + encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); +} + +static void +do_ldrex (void) +{ + constraint (!inst.operands[1].isreg || !inst.operands[1].preind + || inst.operands[1].postind || inst.operands[1].writeback + || inst.operands[1].immisreg || inst.operands[1].shifted + || inst.operands[1].negative + /* This can arise if the programmer has written + strex rN, rM, foo + or if they have mistakenly used a register name as the last + operand, eg: + strex rN, rM, rX + It is very difficult to distinguish between these two cases + because "rX" might actually be a label. ie the register + name has been occluded by a symbol of the same name. So we + just generate a general 'bad addressing mode' type error + message and leave it up to the programmer to discover the + true cause and fix their mistake. */ + || (inst.operands[1].reg == REG_PC), + BAD_ADDR_MODE); + + constraint (inst.reloc.exp.X_op != O_constant + || inst.reloc.exp.X_add_number != 0, + _("offset must be zero in ARM encoding")); + + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.reloc.type = BFD_RELOC_UNUSED; +} + +static void +do_ldrexd (void) +{ + constraint (inst.operands[0].reg % 2 != 0, + _("even register required")); + constraint (inst.operands[1].present + && inst.operands[1].reg != inst.operands[0].reg + 1, + _("can only load two consecutive registers")); + /* If op 1 were present and equal to PC, this function wouldn't + have been called in the first place. */ + constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); + + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[2].reg << 16; +} + +static void +do_ldst (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + if (!inst.operands[1].isreg) + if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) + return; + encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); +} + +static void +do_ldstt (void) +{ + /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and + reject [Rn,...]. */ + if (inst.operands[1].preind) + { + constraint (inst.reloc.exp.X_op != O_constant + || inst.reloc.exp.X_add_number != 0, + _("this instruction requires a post-indexed address")); + + inst.operands[1].preind = 0; + inst.operands[1].postind = 1; + inst.operands[1].writeback = 1; + } + inst.instruction |= inst.operands[0].reg << 12; + encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); +} + +/* Halfword and signed-byte load/store operations. */ + +static void +do_ldstv4 (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + if (!inst.operands[1].isreg) + if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) + return; + encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); +} + +static void +do_ldsttv4 (void) +{ + /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and + reject [Rn,...]. */ + if (inst.operands[1].preind) + { + constraint (inst.reloc.exp.X_op != O_constant + || inst.reloc.exp.X_add_number != 0, + _("this instruction requires a post-indexed address")); + + inst.operands[1].preind = 0; + inst.operands[1].postind = 1; + inst.operands[1].writeback = 1; + } + inst.instruction |= inst.operands[0].reg << 12; + encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); +} + +/* Co-processor register load/store. + Format: {cond}[L] CP#,CRd,
*/ +static void +do_lstc (void) +{ + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].reg << 12; + encode_arm_cp_address (2, TRUE, TRUE, 0); +} + +static void +do_mlas (void) +{ + /* This restriction does not apply to mls (nor to mla in v6 or later). */ + if (inst.operands[0].reg == inst.operands[1].reg + && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) + && !(inst.instruction & 0x00400000)) + as_tsktsk (_("Rd and Rm should be different in mla")); + + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 8; + inst.instruction |= inst.operands[3].reg << 12; +} + +static void +do_mov (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + encode_arm_shifter_operand (1); +} + +/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #. */ +static void +do_mov16 (void) +{ + bfd_vma imm; + bfd_boolean top; + + top = (inst.instruction & 0x00400000) != 0; + constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, + _(":lower16: not allowed this instruction")); + constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, + _(":upper16: not allowed instruction")); + inst.instruction |= inst.operands[0].reg << 12; + if (inst.reloc.type == BFD_RELOC_UNUSED) + { + imm = inst.reloc.exp.X_add_number; + /* The value is in two pieces: 0:11, 16:19. */ + inst.instruction |= (imm & 0x00000fff); + inst.instruction |= (imm & 0x0000f000) << 4; + } +} + +static void do_vfp_nsyn_opcode (const char *); + +static int +do_vfp_nsyn_mrs (void) +{ + if (inst.operands[0].isvec) + { + if (inst.operands[1].reg != 1) + first_error (_("operand 1 must be FPSCR")); + memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); + memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); + do_vfp_nsyn_opcode ("fmstat"); + } + else if (inst.operands[1].isvec) + do_vfp_nsyn_opcode ("fmrx"); + else + return FAIL; + + return SUCCESS; +} + +static int +do_vfp_nsyn_msr (void) +{ + if (inst.operands[0].isvec) + do_vfp_nsyn_opcode ("fmxr"); + else + return FAIL; + + return SUCCESS; +} + +static void +do_mrs (void) +{ + if (do_vfp_nsyn_mrs () == SUCCESS) + return; + + /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ + constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) + != (PSR_c|PSR_f), + _("'CPSR' or 'SPSR' expected")); + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= (inst.operands[1].imm & SPSR_BIT); +} + +/* Two possible forms: + "{C|S}PSR_, Rm", + "{C|S}PSR_f, #expression". */ + +static void +do_msr (void) +{ + if (do_vfp_nsyn_msr () == SUCCESS) + return; + + inst.instruction |= inst.operands[0].imm; + if (inst.operands[1].isreg) + inst.instruction |= inst.operands[1].reg; + else + { + inst.instruction |= INST_IMMEDIATE; + inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; + inst.reloc.pc_rel = 0; + } +} + +static void +do_mul (void) +{ + if (!inst.operands[2].present) + inst.operands[2].reg = inst.operands[0].reg; + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 8; + + if (inst.operands[0].reg == inst.operands[1].reg + && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) + as_tsktsk (_("Rd and Rm should be different in mul")); +} + +/* Long Multiply Parser + UMULL RdLo, RdHi, Rm, Rs + SMULL RdLo, RdHi, Rm, Rs + UMLAL RdLo, RdHi, Rm, Rs + SMLAL RdLo, RdHi, Rm, Rs. */ + +static void +do_mull (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; + inst.instruction |= inst.operands[3].reg << 8; + + /* rdhi and rdlo must be different. */ + if (inst.operands[0].reg == inst.operands[1].reg) + as_tsktsk (_("rdhi and rdlo must be different")); + + /* rdhi, rdlo and rm must all be different before armv6. */ + if ((inst.operands[0].reg == inst.operands[2].reg + || inst.operands[1].reg == inst.operands[2].reg) + && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) + as_tsktsk (_("rdhi, rdlo and rm must all be different")); +} + +static void +do_nop (void) +{ + if (inst.operands[0].present + || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) + { + /* Architectural NOP hints are CPSR sets with no bits selected. */ + inst.instruction &= 0xf0000000; + inst.instruction |= 0x0320f000; + if (inst.operands[0].present) + inst.instruction |= inst.operands[0].imm; + } +} + +/* ARM V6 Pack Halfword Bottom Top instruction (argument parse). + PKHBT {} , , {, LSL #} + Condition defaults to COND_ALWAYS. + Error if Rd, Rn or Rm are R15. */ + +static void +do_pkhbt (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; + if (inst.operands[3].present) + encode_arm_shift (3); +} + +/* ARM V6 PKHTB (Argument Parse). */ + +static void +do_pkhtb (void) +{ + if (!inst.operands[3].present) + { + /* If the shift specifier is omitted, turn the instruction + into pkhbt rd, rm, rn. */ + inst.instruction &= 0xfff00010; + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 16; + } + else + { + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; + encode_arm_shift (3); + } +} + +/* ARMv5TE: Preload-Cache + + PLD + + Syntactically, like LDR with B=1, W=0, L=1. */ + +static void +do_pld (void) +{ + constraint (!inst.operands[0].isreg, + _("'[' expected after PLD mnemonic")); + constraint (inst.operands[0].postind, + _("post-indexed expression used in preload instruction")); + constraint (inst.operands[0].writeback, + _("writeback used in preload instruction")); + constraint (!inst.operands[0].preind, + _("unindexed addressing used in preload instruction")); + encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); +} + +/* ARMv7: PLI */ +static void +do_pli (void) +{ + constraint (!inst.operands[0].isreg, + _("'[' expected after PLI mnemonic")); + constraint (inst.operands[0].postind, + _("post-indexed expression used in preload instruction")); + constraint (inst.operands[0].writeback, + _("writeback used in preload instruction")); + constraint (!inst.operands[0].preind, + _("unindexed addressing used in preload instruction")); + encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); + inst.instruction &= ~PRE_INDEX; +} + +static void +do_push_pop (void) +{ + inst.operands[1] = inst.operands[0]; + memset (&inst.operands[0], 0, sizeof inst.operands[0]); + inst.operands[0].isreg = 1; + inst.operands[0].writeback = 1; + inst.operands[0].reg = REG_SP; + do_ldmstm (); +} + +/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the + word at the specified address and the following word + respectively. + Unconditionally executed. + Error if Rn is R15. */ + +static void +do_rfe (void) +{ + inst.instruction |= inst.operands[0].reg << 16; + if (inst.operands[0].writeback) + inst.instruction |= WRITE_BACK; +} + +/* ARM V6 ssat (argument parse). */ + +static void +do_ssat (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= (inst.operands[1].imm - 1) << 16; + inst.instruction |= inst.operands[2].reg; + + if (inst.operands[3].present) + encode_arm_shift (3); +} + +/* ARM V6 usat (argument parse). */ + +static void +do_usat (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].imm << 16; + inst.instruction |= inst.operands[2].reg; + + if (inst.operands[3].present) + encode_arm_shift (3); +} + +/* ARM V6 ssat16 (argument parse). */ + +static void +do_ssat16 (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= ((inst.operands[1].imm - 1) << 16); + inst.instruction |= inst.operands[2].reg; +} + +static void +do_usat16 (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].imm << 16; + inst.instruction |= inst.operands[2].reg; +} + +/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while + preserving the other bits. + + setend , where is either + BE or LE. */ + +static void +do_setend (void) +{ + if (inst.operands[0].imm) + inst.instruction |= 0x200; +} + +static void +do_shift (void) +{ + unsigned int Rm = (inst.operands[1].present + ? inst.operands[1].reg + : inst.operands[0].reg); + + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= Rm; + if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ + { + inst.instruction |= inst.operands[2].reg << 8; + inst.instruction |= SHIFT_BY_REG; + } + else + inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; +} + +static void +do_smc (void) +{ + inst.reloc.type = BFD_RELOC_ARM_SMC; + inst.reloc.pc_rel = 0; +} + +static void +do_swi (void) +{ + inst.reloc.type = BFD_RELOC_ARM_SWI; + inst.reloc.pc_rel = 0; +} + +/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) + SMLAxy{cond} Rd,Rm,Rs,Rn + SMLAWy{cond} Rd,Rm,Rs,Rn + Error if any register is R15. */ + +static void +do_smla (void) +{ + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 8; + inst.instruction |= inst.operands[3].reg << 12; +} + +/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) + SMLALxy{cond} Rdlo,Rdhi,Rm,Rs + Error if any register is R15. + Warning if Rdlo == Rdhi. */ + +static void +do_smlal (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; + inst.instruction |= inst.operands[3].reg << 8; + + if (inst.operands[0].reg == inst.operands[1].reg) + as_tsktsk (_("rdhi and rdlo must be different")); +} + +/* ARM V5E (El Segundo) signed-multiply (argument parse) + SMULxy{cond} Rd,Rm,Rs + Error if any register is R15. */ + +static void +do_smul (void) +{ + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 8; +} + +/* ARM V6 srs (argument parse). The variable fields in the encoding are + the same for both ARM and Thumb-2. */ + +static void +do_srs (void) +{ + int reg; + + if (inst.operands[0].present) + { + reg = inst.operands[0].reg; + constraint (reg != REG_SP, _("SRS base register must be r13")); + } + else + reg = REG_SP; + + inst.instruction |= reg << 16; + inst.instruction |= inst.operands[1].imm; + if (inst.operands[0].writeback || inst.operands[1].writeback) + inst.instruction |= WRITE_BACK; +} + +/* ARM V6 strex (argument parse). */ + +static void +do_strex (void) +{ + constraint (!inst.operands[2].isreg || !inst.operands[2].preind + || inst.operands[2].postind || inst.operands[2].writeback + || inst.operands[2].immisreg || inst.operands[2].shifted + || inst.operands[2].negative + /* See comment in do_ldrex(). */ + || (inst.operands[2].reg == REG_PC), + BAD_ADDR_MODE); + + constraint (inst.operands[0].reg == inst.operands[1].reg + || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); + + constraint (inst.reloc.exp.X_op != O_constant + || inst.reloc.exp.X_add_number != 0, + _("offset must be zero in ARM encoding")); + + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 16; + inst.reloc.type = BFD_RELOC_UNUSED; +} + +static void +do_strexd (void) +{ + constraint (inst.operands[1].reg % 2 != 0, + _("even register required")); + constraint (inst.operands[2].present + && inst.operands[2].reg != inst.operands[1].reg + 1, + _("can only store two consecutive registers")); + /* If op 2 were present and equal to PC, this function wouldn't + have been called in the first place. */ + constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); + + constraint (inst.operands[0].reg == inst.operands[1].reg + || inst.operands[0].reg == inst.operands[1].reg + 1 + || inst.operands[0].reg == inst.operands[3].reg, + BAD_OVERLAP); + + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[3].reg << 16; +} + +/* ARM V6 SXTAH extracts a 16-bit value from a register, sign + extends it to 32-bits, and adds the result to a value in another + register. You can specify a rotation by 0, 8, 16, or 24 bits + before extracting the 16-bit value. + SXTAH{} , , {, } + Condition defaults to COND_ALWAYS. + Error if any register uses R15. */ + +static void +do_sxtah (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; + inst.instruction |= inst.operands[3].imm << 10; +} + +/* ARM V6 SXTH. + + SXTH {} , {, } + Condition defaults to COND_ALWAYS. + Error if any register uses R15. */ + +static void +do_sxth (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].imm << 10; +} + +/* VFP instructions. In a logical order: SP variant first, monad + before dyad, arithmetic then move then load/store. */ + +static void +do_vfp_sp_monadic (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); +} + +static void +do_vfp_sp_dyadic (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); + encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); +} + +static void +do_vfp_sp_compare_z (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); +} + +static void +do_vfp_dp_sp_cvt (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); +} + +static void +do_vfp_sp_dp_cvt (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); +} + +static void +do_vfp_reg_from_sp (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); +} + +static void +do_vfp_reg2_from_sp2 (void) +{ + constraint (inst.operands[2].imm != 2, + _("only two consecutive VFP SP registers allowed here")); + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); +} + +static void +do_vfp_sp_from_reg (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); + inst.instruction |= inst.operands[1].reg << 12; +} + +static void +do_vfp_sp2_from_reg2 (void) +{ + constraint (inst.operands[0].imm != 2, + _("only two consecutive VFP SP registers allowed here")); + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= inst.operands[2].reg << 16; +} + +static void +do_vfp_sp_ldst (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); + encode_arm_cp_address (1, FALSE, TRUE, 0); +} + +static void +do_vfp_dp_ldst (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); + encode_arm_cp_address (1, FALSE, TRUE, 0); +} + + +static void +vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) +{ + if (inst.operands[0].writeback) + inst.instruction |= WRITE_BACK; + else + constraint (ldstm_type != VFP_LDSTMIA, + _("this addressing mode requires base-register writeback")); + inst.instruction |= inst.operands[0].reg << 16; + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); + inst.instruction |= inst.operands[1].imm; +} + +static void +vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) +{ + int count; + + if (inst.operands[0].writeback) + inst.instruction |= WRITE_BACK; + else + constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, + _("this addressing mode requires base-register writeback")); + + inst.instruction |= inst.operands[0].reg << 16; + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); + + count = inst.operands[1].imm << 1; + if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) + count += 1; + + inst.instruction |= count; +} + +static void +do_vfp_sp_ldstmia (void) +{ + vfp_sp_ldstm (VFP_LDSTMIA); +} + +static void +do_vfp_sp_ldstmdb (void) +{ + vfp_sp_ldstm (VFP_LDSTMDB); +} + +static void +do_vfp_dp_ldstmia (void) +{ + vfp_dp_ldstm (VFP_LDSTMIA); +} + +static void +do_vfp_dp_ldstmdb (void) +{ + vfp_dp_ldstm (VFP_LDSTMDB); +} + +static void +do_vfp_xp_ldstmia (void) +{ + vfp_dp_ldstm (VFP_LDSTMIAX); +} + +static void +do_vfp_xp_ldstmdb (void) +{ + vfp_dp_ldstm (VFP_LDSTMDBX); +} + +static void +do_vfp_dp_rd_rm (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); +} + +static void +do_vfp_dp_rn_rd (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); +} + +static void +do_vfp_dp_rd_rn (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); +} + +static void +do_vfp_dp_rd_rn_rm (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); + encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); +} + +static void +do_vfp_dp_rd (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); +} + +static void +do_vfp_dp_rm_rd_rn (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); + encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); +} + +/* VFPv3 instructions. */ +static void +do_vfp_sp_const (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); + inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; + inst.instruction |= (inst.operands[1].imm & 0x0f); +} + +static void +do_vfp_dp_const (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); + inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; + inst.instruction |= (inst.operands[1].imm & 0x0f); +} + +static void +vfp_conv (int srcsize) +{ + unsigned immbits = srcsize - inst.operands[1].imm; + inst.instruction |= (immbits & 1) << 5; + inst.instruction |= (immbits >> 1); +} + +static void +do_vfp_sp_conv_16 (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); + vfp_conv (16); +} + +static void +do_vfp_dp_conv_16 (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); + vfp_conv (16); +} + +static void +do_vfp_sp_conv_32 (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); + vfp_conv (32); +} + +static void +do_vfp_dp_conv_32 (void) +{ + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); + vfp_conv (32); +} + +/* FPA instructions. Also in a logical order. */ + +static void +do_fpa_cmp (void) +{ + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[1].reg; +} + +static void +do_fpa_ldmstm (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + switch (inst.operands[1].imm) + { + case 1: inst.instruction |= CP_T_X; break; + case 2: inst.instruction |= CP_T_Y; break; + case 3: inst.instruction |= CP_T_Y | CP_T_X; break; + case 4: break; + default: abort (); + } + + if (inst.instruction & (PRE_INDEX | INDEX_UP)) + { + /* The instruction specified "ea" or "fd", so we can only accept + [Rn]{!}. The instruction does not really support stacking or + unstacking, so we have to emulate these by setting appropriate + bits and offsets. */ + constraint (inst.reloc.exp.X_op != O_constant + || inst.reloc.exp.X_add_number != 0, + _("this instruction does not support indexing")); + + if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) + inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; + + if (!(inst.instruction & INDEX_UP)) + inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; + + if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) + { + inst.operands[2].preind = 0; + inst.operands[2].postind = 1; + } + } + + encode_arm_cp_address (2, TRUE, TRUE, 0); +} + +/* iWMMXt instructions: strictly in alphabetical order. */ + +static void +do_iwmmxt_tandorc (void) +{ + constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); +} + +static void +do_iwmmxt_textrc (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].imm; +} + +static void +do_iwmmxt_textrm (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].imm; +} + +static void +do_iwmmxt_tinsr (void) +{ + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= inst.operands[2].imm; +} + +static void +do_iwmmxt_tmia (void) +{ + inst.instruction |= inst.operands[0].reg << 5; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 12; +} + +static void +do_iwmmxt_waligni (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; + inst.instruction |= inst.operands[3].imm << 20; +} + +static void +do_iwmmxt_wmerge (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; + inst.instruction |= inst.operands[3].imm << 21; +} + +static void +do_iwmmxt_wmov (void) +{ + /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[1].reg; +} + +static void +do_iwmmxt_wldstbh (void) +{ + int reloc; + inst.instruction |= inst.operands[0].reg << 12; + if (thumb_mode) + reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; + else + reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; + encode_arm_cp_address (1, TRUE, FALSE, reloc); +} + +static void +do_iwmmxt_wldstw (void) +{ + /* RIWR_RIWC clears .isreg for a control register. */ + if (!inst.operands[0].isreg) + { + constraint (inst.cond != COND_ALWAYS, BAD_COND); + inst.instruction |= 0xf0000000; + } + + inst.instruction |= inst.operands[0].reg << 12; + encode_arm_cp_address (1, TRUE, TRUE, 0); +} + +static void +do_iwmmxt_wldstd (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) + && inst.operands[1].immisreg) + { + inst.instruction &= ~0x1a000ff; + inst.instruction |= (0xf << 28); + if (inst.operands[1].preind) + inst.instruction |= PRE_INDEX; + if (!inst.operands[1].negative) + inst.instruction |= INDEX_UP; + if (inst.operands[1].writeback) + inst.instruction |= WRITE_BACK; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.reloc.exp.X_add_number << 4; + inst.instruction |= inst.operands[1].imm; + } + else + encode_arm_cp_address (1, TRUE, FALSE, 0); +} + +static void +do_iwmmxt_wshufh (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); + inst.instruction |= (inst.operands[2].imm & 0x0f); +} + +static void +do_iwmmxt_wzero (void) +{ + /* WZERO reg is an alias for WANDN reg, reg, reg. */ + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[0].reg << 16; +} + +static void +do_iwmmxt_wrwrwr_or_imm5 (void) +{ + if (inst.operands[2].isreg) + do_rd_rn_rm (); + else { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), + _("immediate operand requires iWMMXt2")); + do_rd_rn (); + if (inst.operands[2].imm == 0) + { + switch ((inst.instruction >> 20) & 0xf) + { + case 4: + case 5: + case 6: + case 7: + /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ + inst.operands[2].imm = 16; + inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); + break; + case 8: + case 9: + case 10: + case 11: + /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ + inst.operands[2].imm = 32; + inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); + break; + case 12: + case 13: + case 14: + case 15: + { + /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ + unsigned long wrn; + wrn = (inst.instruction >> 16) & 0xf; + inst.instruction &= 0xff0fff0f; + inst.instruction |= wrn; + /* Bail out here; the instruction is now assembled. */ + return; + } + } + } + /* Map 32 -> 0, etc. */ + inst.operands[2].imm &= 0x1f; + inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); + } +} + +/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register + operations first, then control, shift, and load/store. */ + +/* Insns like "foo X,Y,Z". */ + +static void +do_mav_triple (void) +{ + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 12; +} + +/* Insns like "foo W,X,Y,Z". + where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ + +static void +do_mav_quad (void) +{ + inst.instruction |= inst.operands[0].reg << 5; + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= inst.operands[2].reg << 16; + inst.instruction |= inst.operands[3].reg; +} + +/* cfmvsc32 DSPSC,MVDX[15:0]. */ +static void +do_mav_dspsc (void) +{ + inst.instruction |= inst.operands[1].reg << 12; +} + +/* Maverick shift immediate instructions. + cfsh32 MVFX[15:0],MVFX[15:0],Shift[6:0]. + cfsh64 MVDX[15:0],MVDX[15:0],Shift[6:0]. */ + +static void +do_mav_shift (void) +{ + int imm = inst.operands[2].imm; + + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + + /* Bits 0-3 of the insn should have bits 0-3 of the immediate. + Bits 5-7 of the insn should have bits 4-6 of the immediate. + Bit 4 should be 0. */ + imm = (imm & 0xf) | ((imm & 0x70) << 1); + + inst.instruction |= imm; +} + +/* XScale instructions. Also sorted arithmetic before move. */ + +/* Xscale multiply-accumulate (argument parse) + MIAcc acc0,Rm,Rs + MIAPHcc acc0,Rm,Rs + MIAxycc acc0,Rm,Rs. */ + +static void +do_xsc_mia (void) +{ + inst.instruction |= inst.operands[1].reg; + inst.instruction |= inst.operands[2].reg << 12; +} + +/* Xscale move-accumulator-register (argument parse) + + MARcc acc0,RdLo,RdHi. */ + +static void +do_xsc_mar (void) +{ + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= inst.operands[2].reg << 16; +} + +/* Xscale move-register-accumulator (argument parse) + + MRAcc RdLo,RdHi,acc0. */ + +static void +do_xsc_mra (void) +{ + constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; +} + +/* Encoding functions relevant only to Thumb. */ + +/* inst.operands[i] is a shifted-register operand; encode + it into inst.instruction in the format used by Thumb32. */ + +static void +encode_thumb32_shifted_operand (int i) +{ + unsigned int value = inst.reloc.exp.X_add_number; + unsigned int shift = inst.operands[i].shift_kind; + + constraint (inst.operands[i].immisreg, + _("shift by register not allowed in thumb mode")); + inst.instruction |= inst.operands[i].reg; + if (shift == SHIFT_RRX) + inst.instruction |= SHIFT_ROR << 4; + else + { + constraint (inst.reloc.exp.X_op != O_constant, + _("expression too complex")); + + constraint (value > 32 + || (value == 32 && (shift == SHIFT_LSL + || shift == SHIFT_ROR)), + _("shift expression is too large")); + + if (value == 0) + shift = SHIFT_LSL; + else if (value == 32) + value = 0; + + inst.instruction |= shift << 4; + inst.instruction |= (value & 0x1c) << 10; + inst.instruction |= (value & 0x03) << 6; + } +} + + +/* inst.operands[i] was set up by parse_address. Encode it into a + Thumb32 format load or store instruction. Reject forms that cannot + be used with such instructions. If is_t is true, reject forms that + cannot be used with a T instruction; if is_d is true, reject forms + that cannot be used with a D instruction. */ + +static void +encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) +{ + bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); + + constraint (!inst.operands[i].isreg, + _("Instruction does not support =N addresses")); + + inst.instruction |= inst.operands[i].reg << 16; + if (inst.operands[i].immisreg) + { + constraint (is_pc, _("cannot use register index with PC-relative addressing")); + constraint (is_t || is_d, _("cannot use register index with this instruction")); + constraint (inst.operands[i].negative, + _("Thumb does not support negative register indexing")); + constraint (inst.operands[i].postind, + _("Thumb does not support register post-indexing")); + constraint (inst.operands[i].writeback, + _("Thumb does not support register indexing with writeback")); + constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, + _("Thumb supports only LSL in shifted register indexing")); + + inst.instruction |= inst.operands[i].imm; + if (inst.operands[i].shifted) + { + constraint (inst.reloc.exp.X_op != O_constant, + _("expression too complex")); + constraint (inst.reloc.exp.X_add_number < 0 + || inst.reloc.exp.X_add_number > 3, + _("shift out of range")); + inst.instruction |= inst.reloc.exp.X_add_number << 4; + } + inst.reloc.type = BFD_RELOC_UNUSED; + } + else if (inst.operands[i].preind) + { + constraint (is_pc && inst.operands[i].writeback, + _("cannot use writeback with PC-relative addressing")); + constraint (is_t && inst.operands[i].writeback, + _("cannot use writeback with this instruction")); + + if (is_d) + { + inst.instruction |= 0x01000000; + if (inst.operands[i].writeback) + inst.instruction |= 0x00200000; + } + else + { + inst.instruction |= 0x00000c00; + if (inst.operands[i].writeback) + inst.instruction |= 0x00000100; + } + inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; + } + else if (inst.operands[i].postind) + { + gas_assert (inst.operands[i].writeback); + constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); + constraint (is_t, _("cannot use post-indexing with this instruction")); + + if (is_d) + inst.instruction |= 0x00200000; + else + inst.instruction |= 0x00000900; + inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; + } + else /* unindexed - only for coprocessor */ + inst.error = _("instruction does not accept unindexed addressing"); +} + +/* Table of Thumb instructions which exist in both 16- and 32-bit + encodings (the latter only in post-V6T2 cores). The index is the + value used in the insns table below. When there is more than one + possible 16-bit encoding for the instruction, this table always + holds variant (1). + Also contains several pseudo-instructions used during relaxation. */ +#define T16_32_TAB \ + X(adc, 4140, eb400000), \ + X(adcs, 4140, eb500000), \ + X(add, 1c00, eb000000), \ + X(adds, 1c00, eb100000), \ + X(addi, 0000, f1000000), \ + X(addis, 0000, f1100000), \ + X(add_pc,000f, f20f0000), \ + X(add_sp,000d, f10d0000), \ + X(adr, 000f, f20f0000), \ + X(and, 4000, ea000000), \ + X(ands, 4000, ea100000), \ + X(asr, 1000, fa40f000), \ + X(asrs, 1000, fa50f000), \ + X(b, e000, f000b000), \ + X(bcond, d000, f0008000), \ + X(bic, 4380, ea200000), \ + X(bics, 4380, ea300000), \ + X(cmn, 42c0, eb100f00), \ + X(cmp, 2800, ebb00f00), \ + X(cpsie, b660, f3af8400), \ + X(cpsid, b670, f3af8600), \ + X(cpy, 4600, ea4f0000), \ + X(dec_sp,80dd, f1ad0d00), \ + X(eor, 4040, ea800000), \ + X(eors, 4040, ea900000), \ + X(inc_sp,00dd, f10d0d00), \ + X(ldmia, c800, e8900000), \ + X(ldr, 6800, f8500000), \ + X(ldrb, 7800, f8100000), \ + X(ldrh, 8800, f8300000), \ + X(ldrsb, 5600, f9100000), \ + X(ldrsh, 5e00, f9300000), \ + X(ldr_pc,4800, f85f0000), \ + X(ldr_pc2,4800, f85f0000), \ + X(ldr_sp,9800, f85d0000), \ + X(lsl, 0000, fa00f000), \ + X(lsls, 0000, fa10f000), \ + X(lsr, 0800, fa20f000), \ + X(lsrs, 0800, fa30f000), \ + X(mov, 2000, ea4f0000), \ + X(movs, 2000, ea5f0000), \ + X(mul, 4340, fb00f000), \ + X(muls, 4340, ffffffff), /* no 32b muls */ \ + X(mvn, 43c0, ea6f0000), \ + X(mvns, 43c0, ea7f0000), \ + X(neg, 4240, f1c00000), /* rsb #0 */ \ + X(negs, 4240, f1d00000), /* rsbs #0 */ \ + X(orr, 4300, ea400000), \ + X(orrs, 4300, ea500000), \ + X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ + X(push, b400, e92d0000), /* stmdb sp!,... */ \ + X(rev, ba00, fa90f080), \ + X(rev16, ba40, fa90f090), \ + X(revsh, bac0, fa90f0b0), \ + X(ror, 41c0, fa60f000), \ + X(rors, 41c0, fa70f000), \ + X(sbc, 4180, eb600000), \ + X(sbcs, 4180, eb700000), \ + X(stmia, c000, e8800000), \ + X(str, 6000, f8400000), \ + X(strb, 7000, f8000000), \ + X(strh, 8000, f8200000), \ + X(str_sp,9000, f84d0000), \ + X(sub, 1e00, eba00000), \ + X(subs, 1e00, ebb00000), \ + X(subi, 8000, f1a00000), \ + X(subis, 8000, f1b00000), \ + X(sxtb, b240, fa4ff080), \ + X(sxth, b200, fa0ff080), \ + X(tst, 4200, ea100f00), \ + X(uxtb, b2c0, fa5ff080), \ + X(uxth, b280, fa1ff080), \ + X(nop, bf00, f3af8000), \ + X(yield, bf10, f3af8001), \ + X(wfe, bf20, f3af8002), \ + X(wfi, bf30, f3af8003), \ + X(sev, bf40, f3af8004), + +/* To catch errors in encoding functions, the codes are all offset by + 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined + as 16-bit instructions. */ +#define X(a,b,c) T_MNEM_##a +enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; +#undef X + +#define X(a,b,c) 0x##b +static const unsigned short thumb_op16[] = { T16_32_TAB }; +#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) +#undef X + +#define X(a,b,c) 0x##c +static const unsigned int thumb_op32[] = { T16_32_TAB }; +#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) +#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) +#undef X +#undef T16_32_TAB + +/* Thumb instruction encoders, in alphabetical order. */ + +/* ADDW or SUBW. */ + +static void +do_t_add_sub_w (void) +{ + int Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + + /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this + is the SP-{plus,minus}-immediate form of the instruction. */ + if (Rn == REG_SP) + constraint (Rd == REG_PC, BAD_PC); + else + reject_bad_reg (Rd); + + inst.instruction |= (Rn << 16) | (Rd << 8); + inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; +} + +/* Parse an add or subtract instruction. We get here with inst.instruction + equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ + +static void +do_t_add_sub (void) +{ + int Rd, Rs, Rn; + + Rd = inst.operands[0].reg; + Rs = (inst.operands[1].present + ? inst.operands[1].reg /* Rd, Rs, foo */ + : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ + + if (Rd == REG_PC) + set_it_insn_type_last (); + + if (unified_syntax) + { + bfd_boolean flags; + bfd_boolean narrow; + int opcode; + + flags = (inst.instruction == T_MNEM_adds + || inst.instruction == T_MNEM_subs); + if (flags) + narrow = !in_it_block (); + else + narrow = in_it_block (); + if (!inst.operands[2].isreg) + { + int add; + + constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); + + add = (inst.instruction == T_MNEM_add + || inst.instruction == T_MNEM_adds); + opcode = 0; + if (inst.size_req != 4) + { + /* Attempt to use a narrow opcode, with relaxation if + appropriate. */ + if (Rd == REG_SP && Rs == REG_SP && !flags) + opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; + else if (Rd <= 7 && Rs == REG_SP && add && !flags) + opcode = T_MNEM_add_sp; + else if (Rd <= 7 && Rs == REG_PC && add && !flags) + opcode = T_MNEM_add_pc; + else if (Rd <= 7 && Rs <= 7 && narrow) + { + if (flags) + opcode = add ? T_MNEM_addis : T_MNEM_subis; + else + opcode = add ? T_MNEM_addi : T_MNEM_subi; + } + if (opcode) + { + inst.instruction = THUMB_OP16(opcode); + inst.instruction |= (Rd << 4) | Rs; + inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; + if (inst.size_req != 2) + inst.relax = opcode; + } + else + constraint (inst.size_req == 2, BAD_HIREG); + } + if (inst.size_req == 4 + || (inst.size_req != 2 && !opcode)) + { + if (Rd == REG_PC) + { + constraint (add, BAD_PC); + constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, + _("only SUBS PC, LR, #const allowed")); + constraint (inst.reloc.exp.X_op != O_constant, + _("expression too complex")); + constraint (inst.reloc.exp.X_add_number < 0 + || inst.reloc.exp.X_add_number > 0xff, + _("immediate value out of range")); + inst.instruction = T2_SUBS_PC_LR + | inst.reloc.exp.X_add_number; + inst.reloc.type = BFD_RELOC_UNUSED; + return; + } + else if (Rs == REG_PC) + { + /* Always use addw/subw. */ + inst.instruction = add ? 0xf20f0000 : 0xf2af0000; + inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; + } + else + { + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction = (inst.instruction & 0xe1ffffff) + | 0x10000000; + if (flags) + inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; + else + inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; + } + inst.instruction |= Rd << 8; + inst.instruction |= Rs << 16; + } + } + else + { + Rn = inst.operands[2].reg; + /* See if we can do this with a 16-bit instruction. */ + if (!inst.operands[2].shifted && inst.size_req != 4) + { + if (Rd > 7 || Rs > 7 || Rn > 7) + narrow = FALSE; + + if (narrow) + { + inst.instruction = ((inst.instruction == T_MNEM_adds + || inst.instruction == T_MNEM_add) + ? T_OPCODE_ADD_R3 + : T_OPCODE_SUB_R3); + inst.instruction |= Rd | (Rs << 3) | (Rn << 6); + return; + } + + if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) + { + /* Thumb-1 cores (except v6-M) require at least one high + register in a narrow non flag setting add. */ + if (Rd > 7 || Rn > 7 + || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) + || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) + { + if (Rd == Rn) + { + Rn = Rs; + Rs = Rd; + } + inst.instruction = T_OPCODE_ADD_HI; + inst.instruction |= (Rd & 8) << 4; + inst.instruction |= (Rd & 7); + inst.instruction |= Rn << 3; + return; + } + } + } + + constraint (Rd == REG_PC, BAD_PC); + constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); + constraint (Rs == REG_PC, BAD_PC); + reject_bad_reg (Rn); + + /* If we get here, it can't be done in 16 bits. */ + constraint (inst.operands[2].shifted && inst.operands[2].immisreg, + _("shift must be constant")); + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rd << 8; + inst.instruction |= Rs << 16; + encode_thumb32_shifted_operand (2); + } + } + else + { + constraint (inst.instruction == T_MNEM_adds + || inst.instruction == T_MNEM_subs, + BAD_THUMB32); + + if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ + { + constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) + || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), + BAD_HIREG); + + inst.instruction = (inst.instruction == T_MNEM_add + ? 0x0000 : 0x8000); + inst.instruction |= (Rd << 4) | Rs; + inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; + return; + } + + Rn = inst.operands[2].reg; + constraint (inst.operands[2].shifted, _("unshifted register required")); + + /* We now have Rd, Rs, and Rn set to registers. */ + if (Rd > 7 || Rs > 7 || Rn > 7) + { + /* Can't do this for SUB. */ + constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); + inst.instruction = T_OPCODE_ADD_HI; + inst.instruction |= (Rd & 8) << 4; + inst.instruction |= (Rd & 7); + if (Rs == Rd) + inst.instruction |= Rn << 3; + else if (Rn == Rd) + inst.instruction |= Rs << 3; + else + constraint (1, _("dest must overlap one source register")); + } + else + { + inst.instruction = (inst.instruction == T_MNEM_add + ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); + inst.instruction |= Rd | (Rs << 3) | (Rn << 6); + } + } +} + +static void +do_t_adr (void) +{ + unsigned Rd; + + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + + if (unified_syntax && inst.size_req == 0 && Rd <= 7) + { + /* Defer to section relaxation. */ + inst.relax = inst.instruction; + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd << 4; + } + else if (unified_syntax && inst.size_req != 2) + { + /* Generate a 32-bit opcode. */ + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rd << 8; + inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; + inst.reloc.pc_rel = 1; + } + else + { + /* Generate a 16-bit opcode. */ + inst.instruction = THUMB_OP16 (inst.instruction); + inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; + inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ + inst.reloc.pc_rel = 1; + + inst.instruction |= Rd << 4; + } +} + +/* Arithmetic instructions for which there is just one 16-bit + instruction encoding, and it allows only two low registers. + For maximal compatibility with ARM syntax, we allow three register + operands even when Thumb-32 instructions are not available, as long + as the first two are identical. For instance, both "sbc r0,r1" and + "sbc r0,r0,r1" are allowed. */ +static void +do_t_arit3 (void) +{ + int Rd, Rs, Rn; + + Rd = inst.operands[0].reg; + Rs = (inst.operands[1].present + ? inst.operands[1].reg /* Rd, Rs, foo */ + : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rs); + if (inst.operands[2].isreg) + reject_bad_reg (Rn); + + if (unified_syntax) + { + if (!inst.operands[2].isreg) + { + /* For an immediate, we always generate a 32-bit opcode; + section relaxation will shrink it later if possible. */ + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; + inst.instruction |= Rd << 8; + inst.instruction |= Rs << 16; + inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; + } + else + { + bfd_boolean narrow; + + /* See if we can do this with a 16-bit instruction. */ + if (THUMB_SETS_FLAGS (inst.instruction)) + narrow = !in_it_block (); + else + narrow = in_it_block (); + + if (Rd > 7 || Rn > 7 || Rs > 7) + narrow = FALSE; + if (inst.operands[2].shifted) + narrow = FALSE; + if (inst.size_req == 4) + narrow = FALSE; + + if (narrow + && Rd == Rs) + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd; + inst.instruction |= Rn << 3; + return; + } + + /* If we get here, it can't be done in 16 bits. */ + constraint (inst.operands[2].shifted + && inst.operands[2].immisreg, + _("shift must be constant")); + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rd << 8; + inst.instruction |= Rs << 16; + encode_thumb32_shifted_operand (2); + } + } + else + { + /* On its face this is a lie - the instruction does set the + flags. However, the only supported mnemonic in this mode + says it doesn't. */ + constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); + + constraint (!inst.operands[2].isreg || inst.operands[2].shifted, + _("unshifted register required")); + constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); + constraint (Rd != Rs, + _("dest and source1 must be the same register")); + + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd; + inst.instruction |= Rn << 3; + } +} + +/* Similarly, but for instructions where the arithmetic operation is + commutative, so we can allow either of them to be different from + the destination operand in a 16-bit instruction. For instance, all + three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are + accepted. */ +static void +do_t_arit3c (void) +{ + int Rd, Rs, Rn; + + Rd = inst.operands[0].reg; + Rs = (inst.operands[1].present + ? inst.operands[1].reg /* Rd, Rs, foo */ + : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rs); + if (inst.operands[2].isreg) + reject_bad_reg (Rn); + + if (unified_syntax) + { + if (!inst.operands[2].isreg) + { + /* For an immediate, we always generate a 32-bit opcode; + section relaxation will shrink it later if possible. */ + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; + inst.instruction |= Rd << 8; + inst.instruction |= Rs << 16; + inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; + } + else + { + bfd_boolean narrow; + + /* See if we can do this with a 16-bit instruction. */ + if (THUMB_SETS_FLAGS (inst.instruction)) + narrow = !in_it_block (); + else + narrow = in_it_block (); + + if (Rd > 7 || Rn > 7 || Rs > 7) + narrow = FALSE; + if (inst.operands[2].shifted) + narrow = FALSE; + if (inst.size_req == 4) + narrow = FALSE; + + if (narrow) + { + if (Rd == Rs) + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd; + inst.instruction |= Rn << 3; + return; + } + if (Rd == Rn) + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd; + inst.instruction |= Rs << 3; + return; + } + } + + /* If we get here, it can't be done in 16 bits. */ + constraint (inst.operands[2].shifted + && inst.operands[2].immisreg, + _("shift must be constant")); + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rd << 8; + inst.instruction |= Rs << 16; + encode_thumb32_shifted_operand (2); + } + } + else + { + /* On its face this is a lie - the instruction does set the + flags. However, the only supported mnemonic in this mode + says it doesn't. */ + constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); + + constraint (!inst.operands[2].isreg || inst.operands[2].shifted, + _("unshifted register required")); + constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); + + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd; + + if (Rd == Rs) + inst.instruction |= Rn << 3; + else if (Rd == Rn) + inst.instruction |= Rs << 3; + else + constraint (1, _("dest must overlap one source register")); + } +} + +static void +do_t_barrier (void) +{ + if (inst.operands[0].present) + { + constraint ((inst.instruction & 0xf0) != 0x40 + && inst.operands[0].imm != 0xf, + _("bad barrier type")); + inst.instruction |= inst.operands[0].imm; + } + else + inst.instruction |= 0xf; +} + +static void +do_t_bfc (void) +{ + unsigned Rd; + unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; + constraint (msb > 32, _("bit-field extends past end of register")); + /* The instruction encoding stores the LSB and MSB, + not the LSB and width. */ + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + inst.instruction |= Rd << 8; + inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; + inst.instruction |= (inst.operands[1].imm & 0x03) << 6; + inst.instruction |= msb - 1; +} + +static void +do_t_bfi (void) +{ + int Rd, Rn; + unsigned int msb; + + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + + /* #0 in second position is alternative syntax for bfc, which is + the same instruction but with REG_PC in the Rm field. */ + if (!inst.operands[1].isreg) + Rn = REG_PC; + else + { + Rn = inst.operands[1].reg; + reject_bad_reg (Rn); + } + + msb = inst.operands[2].imm + inst.operands[3].imm; + constraint (msb > 32, _("bit-field extends past end of register")); + /* The instruction encoding stores the LSB and MSB, + not the LSB and width. */ + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; + inst.instruction |= (inst.operands[2].imm & 0x03) << 6; + inst.instruction |= msb - 1; +} + +static void +do_t_bfx (void) +{ + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + + constraint (inst.operands[2].imm + inst.operands[3].imm > 32, + _("bit-field extends past end of register")); + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; + inst.instruction |= (inst.operands[2].imm & 0x03) << 6; + inst.instruction |= inst.operands[3].imm - 1; +} + +/* ARM V5 Thumb BLX (argument parse) + BLX which is BLX(1) + BLX which is BLX(2) + Unfortunately, there are two different opcodes for this mnemonic. + So, the insns[].value is not used, and the code here zaps values + into inst.instruction. + + ??? How to take advantage of the additional two bits of displacement + available in Thumb32 mode? Need new relocation? */ + +static void +do_t_blx (void) +{ + set_it_insn_type_last (); + + if (inst.operands[0].isreg) + { + constraint (inst.operands[0].reg == REG_PC, BAD_PC); + /* We have a register, so this is BLX(2). */ + inst.instruction |= inst.operands[0].reg << 3; + } + else + { + /* No register. This must be BLX(1). */ + inst.instruction = 0xf000e800; + inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; + inst.reloc.pc_rel = 1; + } +} + +static void +do_t_branch (void) +{ + int opcode; + int cond; + + cond = inst.cond; + set_it_insn_type (IF_INSIDE_IT_LAST_INSN); + + if (in_it_block ()) + { + /* Conditional branches inside IT blocks are encoded as unconditional + branches. */ + cond = COND_ALWAYS; + } + else + cond = inst.cond; + + if (cond != COND_ALWAYS) + opcode = T_MNEM_bcond; + else + opcode = inst.instruction; + + if (unified_syntax && inst.size_req == 4) + { + inst.instruction = THUMB_OP32(opcode); + if (cond == COND_ALWAYS) + inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; + else + { + gas_assert (cond != 0xF); + inst.instruction |= cond << 22; + inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; + } + } + else + { + inst.instruction = THUMB_OP16(opcode); + if (cond == COND_ALWAYS) + inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; + else + { + inst.instruction |= cond << 8; + inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; + } + /* Allow section relaxation. */ + if (unified_syntax && inst.size_req != 2) + inst.relax = opcode; + } + + inst.reloc.pc_rel = 1; +} + +static void +do_t_bkpt (void) +{ + constraint (inst.cond != COND_ALWAYS, + _("instruction is always unconditional")); + if (inst.operands[0].present) + { + constraint (inst.operands[0].imm > 255, + _("immediate value out of range")); + inst.instruction |= inst.operands[0].imm; + set_it_insn_type (NEUTRAL_IT_INSN); + } +} + +static void +do_t_branch23 (void) +{ + set_it_insn_type_last (); + inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; + inst.reloc.pc_rel = 1; + +#if defined(OBJ_COFF) + /* If the destination of the branch is a defined symbol which does not have + the THUMB_FUNC attribute, then we must be calling a function which has + the (interfacearm) attribute. We look for the Thumb entry point to that + function and change the branch to refer to that function instead. */ + if ( inst.reloc.exp.X_op == O_symbol + && inst.reloc.exp.X_add_symbol != NULL + && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) + && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) + inst.reloc.exp.X_add_symbol = + find_real_start (inst.reloc.exp.X_add_symbol); +#endif +} + +static void +do_t_bx (void) +{ + set_it_insn_type_last (); + inst.instruction |= inst.operands[0].reg << 3; + /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc + should cause the alignment to be checked once it is known. This is + because BX PC only works if the instruction is word aligned. */ +} + +static void +do_t_bxj (void) +{ + int Rm; + + set_it_insn_type_last (); + Rm = inst.operands[0].reg; + reject_bad_reg (Rm); + inst.instruction |= Rm << 16; +} + +static void +do_t_clz (void) +{ + unsigned Rd; + unsigned Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rm << 16; + inst.instruction |= Rm; +} + +static void +do_t_cps (void) +{ + set_it_insn_type (OUTSIDE_IT_INSN); + inst.instruction |= inst.operands[0].imm; +} + +static void +do_t_cpsi (void) +{ + set_it_insn_type (OUTSIDE_IT_INSN); + if (unified_syntax + && (inst.operands[1].present || inst.size_req == 4) + && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) + { + unsigned int imod = (inst.instruction & 0x0030) >> 4; + inst.instruction = 0xf3af8000; + inst.instruction |= imod << 9; + inst.instruction |= inst.operands[0].imm << 5; + if (inst.operands[1].present) + inst.instruction |= 0x100 | inst.operands[1].imm; + } + else + { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) + && (inst.operands[0].imm & 4), + _("selected processor does not support 'A' form " + "of this instruction")); + constraint (inst.operands[1].present || inst.size_req == 4, + _("Thumb does not support the 2-argument " + "form of this instruction")); + inst.instruction |= inst.operands[0].imm; + } +} + +/* THUMB CPY instruction (argument parse). */ + +static void +do_t_cpy (void) +{ + if (inst.size_req == 4) + { + inst.instruction = THUMB_OP32 (T_MNEM_mov); + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].reg; + } + else + { + inst.instruction |= (inst.operands[0].reg & 0x8) << 4; + inst.instruction |= (inst.operands[0].reg & 0x7); + inst.instruction |= inst.operands[1].reg << 3; + } +} + +static void +do_t_cbz (void) +{ + set_it_insn_type (OUTSIDE_IT_INSN); + constraint (inst.operands[0].reg > 7, BAD_HIREG); + inst.instruction |= inst.operands[0].reg; + inst.reloc.pc_rel = 1; + inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; +} + +static void +do_t_dbg (void) +{ + inst.instruction |= inst.operands[0].imm; +} + +static void +do_t_div (void) +{ + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rn = (inst.operands[1].present + ? inst.operands[1].reg : Rd); + Rm = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; +} + +static void +do_t_hint (void) +{ + if (unified_syntax && inst.size_req == 4) + inst.instruction = THUMB_OP32 (inst.instruction); + else + inst.instruction = THUMB_OP16 (inst.instruction); +} + +static void +do_t_it (void) +{ + unsigned int cond = inst.operands[0].imm; + + set_it_insn_type (IT_INSN); + now_it.mask = (inst.instruction & 0xf) | 0x10; + now_it.cc = cond; + + /* If the condition is a negative condition, invert the mask. */ + if ((cond & 0x1) == 0x0) + { + unsigned int mask = inst.instruction & 0x000f; + + if ((mask & 0x7) == 0) + /* no conversion needed */; + else if ((mask & 0x3) == 0) + mask ^= 0x8; + else if ((mask & 0x1) == 0) + mask ^= 0xC; + else + mask ^= 0xE; + + inst.instruction &= 0xfff0; + inst.instruction |= mask; + } + + inst.instruction |= cond << 4; +} + +/* Helper function used for both push/pop and ldm/stm. */ +static void +encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) +{ + bfd_boolean load; + + load = (inst.instruction & (1 << 20)) != 0; + + if (mask & (1 << 13)) + inst.error = _("SP not allowed in register list"); + if (load) + { + if (mask & (1 << 15)) + { + if (mask & (1 << 14)) + inst.error = _("LR and PC should not both be in register list"); + else + set_it_insn_type_last (); + } + + if ((mask & (1 << base)) != 0 + && writeback) + as_warn (_("base register should not be in register list " + "when written back")); + } + else + { + if (mask & (1 << 15)) + inst.error = _("PC not allowed in register list"); + + if (mask & (1 << base)) + as_warn (_("value stored for r%d is UNPREDICTABLE"), base); + } + + if ((mask & (mask - 1)) == 0) + { + /* Single register transfers implemented as str/ldr. */ + if (writeback) + { + if (inst.instruction & (1 << 23)) + inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ + else + inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ + } + else + { + if (inst.instruction & (1 << 23)) + inst.instruction = 0x00800000; /* ia -> [base] */ + else + inst.instruction = 0x00000c04; /* db -> [base, #-4] */ + } + + inst.instruction |= 0xf8400000; + if (load) + inst.instruction |= 0x00100000; + + mask = ffs (mask) - 1; + mask <<= 12; + } + else if (writeback) + inst.instruction |= WRITE_BACK; + + inst.instruction |= mask; + inst.instruction |= base << 16; +} + +static void +do_t_ldmstm (void) +{ + /* This really doesn't seem worth it. */ + constraint (inst.reloc.type != BFD_RELOC_UNUSED, + _("expression too complex")); + constraint (inst.operands[1].writeback, + _("Thumb load/store multiple does not support {reglist}^")); + + if (unified_syntax) + { + bfd_boolean narrow; + unsigned mask; + + narrow = FALSE; + /* See if we can use a 16-bit instruction. */ + if (inst.instruction < 0xffff /* not ldmdb/stmdb */ + && inst.size_req != 4 + && !(inst.operands[1].imm & ~0xff)) + { + mask = 1 << inst.operands[0].reg; + + if (inst.operands[0].reg <= 7 + && (inst.instruction == T_MNEM_stmia + ? inst.operands[0].writeback + : (inst.operands[0].writeback + == !(inst.operands[1].imm & mask)))) + { + if (inst.instruction == T_MNEM_stmia + && (inst.operands[1].imm & mask) + && (inst.operands[1].imm & (mask - 1))) + as_warn (_("value stored for r%d is UNPREDICTABLE"), + inst.operands[0].reg); + + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].imm; + narrow = TRUE; + } + else if (inst.operands[0] .reg == REG_SP + && inst.operands[0].writeback) + { + inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia + ? T_MNEM_push : T_MNEM_pop); + inst.instruction |= inst.operands[1].imm; + narrow = TRUE; + } + } + + if (!narrow) + { + if (inst.instruction < 0xffff) + inst.instruction = THUMB_OP32 (inst.instruction); + + encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, + inst.operands[0].writeback); + } + } + else + { + constraint (inst.operands[0].reg > 7 + || (inst.operands[1].imm & ~0xff), BAD_HIREG); + constraint (inst.instruction != T_MNEM_ldmia + && inst.instruction != T_MNEM_stmia, + _("Thumb-2 instruction only valid in unified syntax")); + if (inst.instruction == T_MNEM_stmia) + { + if (!inst.operands[0].writeback) + as_warn (_("this instruction will write back the base register")); + if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) + && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) + as_warn (_("value stored for r%d is UNPREDICTABLE"), + inst.operands[0].reg); + } + else + { + if (!inst.operands[0].writeback + && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) + as_warn (_("this instruction will write back the base register")); + else if (inst.operands[0].writeback + && (inst.operands[1].imm & (1 << inst.operands[0].reg))) + as_warn (_("this instruction will not write back the base register")); + } + + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].imm; + } +} + +static void +do_t_ldrex (void) +{ + constraint (!inst.operands[1].isreg || !inst.operands[1].preind + || inst.operands[1].postind || inst.operands[1].writeback + || inst.operands[1].immisreg || inst.operands[1].shifted + || inst.operands[1].negative, + BAD_ADDR_MODE); + + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; +} + +static void +do_t_ldrexd (void) +{ + if (!inst.operands[1].present) + { + constraint (inst.operands[0].reg == REG_LR, + _("r14 not allowed as first register " + "when second register is omitted")); + inst.operands[1].reg = inst.operands[0].reg + 1; + } + constraint (inst.operands[0].reg == inst.operands[1].reg, + BAD_OVERLAP); + + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 8; + inst.instruction |= inst.operands[2].reg << 16; +} + +static void +do_t_ldst (void) +{ + unsigned long opcode; + int Rn; + + if (inst.operands[0].isreg + && !inst.operands[0].preind + && inst.operands[0].reg == REG_PC) + set_it_insn_type_last (); + + opcode = inst.instruction; + if (unified_syntax) + { + if (!inst.operands[1].isreg) + { + if (opcode <= 0xffff) + inst.instruction = THUMB_OP32 (opcode); + if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) + return; + } + if (inst.operands[1].isreg + && !inst.operands[1].writeback + && !inst.operands[1].shifted && !inst.operands[1].postind + && !inst.operands[1].negative && inst.operands[0].reg <= 7 + && opcode <= 0xffff + && inst.size_req != 4) + { + /* Insn may have a 16-bit form. */ + Rn = inst.operands[1].reg; + if (inst.operands[1].immisreg) + { + inst.instruction = THUMB_OP16 (opcode); + /* [Rn, Rik] */ + if (Rn <= 7 && inst.operands[1].imm <= 7) + goto op16; + } + else if ((Rn <= 7 && opcode != T_MNEM_ldrsh + && opcode != T_MNEM_ldrsb) + || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) + || (Rn == REG_SP && opcode == T_MNEM_str)) + { + /* [Rn, #const] */ + if (Rn > 7) + { + if (Rn == REG_PC) + { + if (inst.reloc.pc_rel) + opcode = T_MNEM_ldr_pc2; + else + opcode = T_MNEM_ldr_pc; + } + else + { + if (opcode == T_MNEM_ldr) + opcode = T_MNEM_ldr_sp; + else + opcode = T_MNEM_str_sp; + } + inst.instruction = inst.operands[0].reg << 8; + } + else + { + inst.instruction = inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 3; + } + inst.instruction |= THUMB_OP16 (opcode); + if (inst.size_req == 2) + inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; + else + inst.relax = opcode; + return; + } + } + /* Definitely a 32-bit variant. */ + inst.instruction = THUMB_OP32 (opcode); + inst.instruction |= inst.operands[0].reg << 12; + encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); + return; + } + + constraint (inst.operands[0].reg > 7, BAD_HIREG); + + if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) + { + /* Only [Rn,Rm] is acceptable. */ + constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); + constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg + || inst.operands[1].postind || inst.operands[1].shifted + || inst.operands[1].negative, + _("Thumb does not support this addressing mode")); + inst.instruction = THUMB_OP16 (inst.instruction); + goto op16; + } + + inst.instruction = THUMB_OP16 (inst.instruction); + if (!inst.operands[1].isreg) + if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) + return; + + constraint (!inst.operands[1].preind + || inst.operands[1].shifted + || inst.operands[1].writeback, + _("Thumb does not support this addressing mode")); + if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) + { + constraint (inst.instruction & 0x0600, + _("byte or halfword not valid for base register")); + constraint (inst.operands[1].reg == REG_PC + && !(inst.instruction & THUMB_LOAD_BIT), + _("r15 based store not allowed")); + constraint (inst.operands[1].immisreg, + _("invalid base register for register offset")); + + if (inst.operands[1].reg == REG_PC) + inst.instruction = T_OPCODE_LDR_PC; + else if (inst.instruction & THUMB_LOAD_BIT) + inst.instruction = T_OPCODE_LDR_SP; + else + inst.instruction = T_OPCODE_STR_SP; + + inst.instruction |= inst.operands[0].reg << 8; + inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; + return; + } + + constraint (inst.operands[1].reg > 7, BAD_HIREG); + if (!inst.operands[1].immisreg) + { + /* Immediate offset. */ + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 3; + inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; + return; + } + + /* Register offset. */ + constraint (inst.operands[1].imm > 7, BAD_HIREG); + constraint (inst.operands[1].negative, + _("Thumb does not support this addressing mode")); + + op16: + switch (inst.instruction) + { + case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; + case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; + case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; + case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; + case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; + case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; + case 0x5600 /* ldrsb */: + case 0x5e00 /* ldrsh */: break; + default: abort (); + } + + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 3; + inst.instruction |= inst.operands[1].imm << 6; +} + +static void +do_t_ldstd (void) +{ + if (!inst.operands[1].present) + { + inst.operands[1].reg = inst.operands[0].reg + 1; + constraint (inst.operands[0].reg == REG_LR, + _("r14 not allowed here")); + } + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 8; + encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); +} + +static void +do_t_ldstt (void) +{ + inst.instruction |= inst.operands[0].reg << 12; + encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); +} + +static void +do_t_mla (void) +{ + unsigned Rd, Rn, Rm, Ra; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + Ra = inst.operands[3].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + reject_bad_reg (Ra); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; + inst.instruction |= Ra << 12; +} + +static void +do_t_mlal (void) +{ + unsigned RdLo, RdHi, Rn, Rm; + + RdLo = inst.operands[0].reg; + RdHi = inst.operands[1].reg; + Rn = inst.operands[2].reg; + Rm = inst.operands[3].reg; + + reject_bad_reg (RdLo); + reject_bad_reg (RdHi); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= RdLo << 12; + inst.instruction |= RdHi << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; +} + +static void +do_t_mov_cmp (void) +{ + unsigned Rn, Rm; + + Rn = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + if (Rn == REG_PC) + set_it_insn_type_last (); + + if (unified_syntax) + { + int r0off = (inst.instruction == T_MNEM_mov + || inst.instruction == T_MNEM_movs) ? 8 : 16; + unsigned long opcode; + bfd_boolean narrow; + bfd_boolean low_regs; + + low_regs = (Rn <= 7 && Rm <= 7); + opcode = inst.instruction; + if (in_it_block ()) + narrow = opcode != T_MNEM_movs; + else + narrow = opcode != T_MNEM_movs || low_regs; + if (inst.size_req == 4 + || inst.operands[1].shifted) + narrow = FALSE; + + /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ + if (opcode == T_MNEM_movs && inst.operands[1].isreg + && !inst.operands[1].shifted + && Rn == REG_PC + && Rm == REG_LR) + { + inst.instruction = T2_SUBS_PC_LR; + return; + } + + if (opcode == T_MNEM_cmp) + { + constraint (Rn == REG_PC, BAD_PC); + if (narrow) + { + /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, + but valid. */ + warn_deprecated_sp (Rm); + /* R15 was documented as a valid choice for Rm in ARMv6, + but as UNPREDICTABLE in ARMv7. ARM's proprietary + tools reject R15, so we do too. */ + constraint (Rm == REG_PC, BAD_PC); + } + else + reject_bad_reg (Rm); + } + else if (opcode == T_MNEM_mov + || opcode == T_MNEM_movs) + { + if (inst.operands[1].isreg) + { + if (opcode == T_MNEM_movs) + { + reject_bad_reg (Rn); + reject_bad_reg (Rm); + } + else if ((Rn == REG_SP || Rn == REG_PC) + && (Rm == REG_SP || Rm == REG_PC)) + reject_bad_reg (Rm); + } + else + reject_bad_reg (Rn); + } + + if (!inst.operands[1].isreg) + { + /* Immediate operand. */ + if (!in_it_block () && opcode == T_MNEM_mov) + narrow = 0; + if (low_regs && narrow) + { + inst.instruction = THUMB_OP16 (opcode); + inst.instruction |= Rn << 8; + if (inst.size_req == 2) + inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; + else + inst.relax = opcode; + } + else + { + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; + inst.instruction |= Rn << r0off; + inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; + } + } + else if (inst.operands[1].shifted && inst.operands[1].immisreg + && (inst.instruction == T_MNEM_mov + || inst.instruction == T_MNEM_movs)) + { + /* Register shifts are encoded as separate shift instructions. */ + bfd_boolean flags = (inst.instruction == T_MNEM_movs); + + if (in_it_block ()) + narrow = !flags; + else + narrow = flags; + + if (inst.size_req == 4) + narrow = FALSE; + + if (!low_regs || inst.operands[1].imm > 7) + narrow = FALSE; + + if (Rn != Rm) + narrow = FALSE; + + switch (inst.operands[1].shift_kind) + { + case SHIFT_LSL: + opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); + break; + case SHIFT_ASR: + opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); + break; + case SHIFT_LSR: + opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); + break; + case SHIFT_ROR: + opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); + break; + default: + abort (); + } + + inst.instruction = opcode; + if (narrow) + { + inst.instruction |= Rn; + inst.instruction |= inst.operands[1].imm << 3; + } + else + { + if (flags) + inst.instruction |= CONDS_BIT; + + inst.instruction |= Rn << 8; + inst.instruction |= Rm << 16; + inst.instruction |= inst.operands[1].imm; + } + } + else if (!narrow) + { + /* Some mov with immediate shift have narrow variants. + Register shifts are handled above. */ + if (low_regs && inst.operands[1].shifted + && (inst.instruction == T_MNEM_mov + || inst.instruction == T_MNEM_movs)) + { + if (in_it_block ()) + narrow = (inst.instruction == T_MNEM_mov); + else + narrow = (inst.instruction == T_MNEM_movs); + } + + if (narrow) + { + switch (inst.operands[1].shift_kind) + { + case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; + case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; + case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; + default: narrow = FALSE; break; + } + } + + if (narrow) + { + inst.instruction |= Rn; + inst.instruction |= Rm << 3; + inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; + } + else + { + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rn << r0off; + encode_thumb32_shifted_operand (1); + } + } + else + switch (inst.instruction) + { + case T_MNEM_mov: + inst.instruction = T_OPCODE_MOV_HR; + inst.instruction |= (Rn & 0x8) << 4; + inst.instruction |= (Rn & 0x7); + inst.instruction |= Rm << 3; + break; + + case T_MNEM_movs: + /* We know we have low registers at this point. + Generate ADD Rd, Rs, #0. */ + inst.instruction = T_OPCODE_ADD_I3; + inst.instruction |= Rn; + inst.instruction |= Rm << 3; + break; + + case T_MNEM_cmp: + if (low_regs) + { + inst.instruction = T_OPCODE_CMP_LR; + inst.instruction |= Rn; + inst.instruction |= Rm << 3; + } + else + { + inst.instruction = T_OPCODE_CMP_HR; + inst.instruction |= (Rn & 0x8) << 4; + inst.instruction |= (Rn & 0x7); + inst.instruction |= Rm << 3; + } + break; + } + return; + } + + inst.instruction = THUMB_OP16 (inst.instruction); + + /* PR 10443: Do not silently ignore shifted operands. */ + constraint (inst.operands[1].shifted, + _("shifts in CMP/MOV instructions are only supported in unified syntax")); + + if (inst.operands[1].isreg) + { + if (Rn < 8 && Rm < 8) + { + /* A move of two lowregs is encoded as ADD Rd, Rs, #0 + since a MOV instruction produces unpredictable results. */ + if (inst.instruction == T_OPCODE_MOV_I8) + inst.instruction = T_OPCODE_ADD_I3; + else + inst.instruction = T_OPCODE_CMP_LR; + + inst.instruction |= Rn; + inst.instruction |= Rm << 3; + } + else + { + if (inst.instruction == T_OPCODE_MOV_I8) + inst.instruction = T_OPCODE_MOV_HR; + else + inst.instruction = T_OPCODE_CMP_HR; + do_t_cpy (); + } + } + else + { + constraint (Rn > 7, + _("only lo regs allowed with immediate")); + inst.instruction |= Rn << 8; + inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; + } +} + +static void +do_t_mov16 (void) +{ + unsigned Rd; + bfd_vma imm; + bfd_boolean top; + + top = (inst.instruction & 0x00800000) != 0; + if (inst.reloc.type == BFD_RELOC_ARM_MOVW) + { + constraint (top, _(":lower16: not allowed this instruction")); + inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; + } + else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) + { + constraint (!top, _(":upper16: not allowed this instruction")); + inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; + } + + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + + inst.instruction |= Rd << 8; + if (inst.reloc.type == BFD_RELOC_UNUSED) + { + imm = inst.reloc.exp.X_add_number; + inst.instruction |= (imm & 0xf000) << 4; + inst.instruction |= (imm & 0x0800) << 15; + inst.instruction |= (imm & 0x0700) << 4; + inst.instruction |= (imm & 0x00ff); + } +} + +static void +do_t_mvn_tst (void) +{ + unsigned Rn, Rm; + + Rn = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + if (inst.instruction == T_MNEM_cmp + || inst.instruction == T_MNEM_cmn) + constraint (Rn == REG_PC, BAD_PC); + else + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + if (unified_syntax) + { + int r0off = (inst.instruction == T_MNEM_mvn + || inst.instruction == T_MNEM_mvns) ? 8 : 16; + bfd_boolean narrow; + + if (inst.size_req == 4 + || inst.instruction > 0xffff + || inst.operands[1].shifted + || Rn > 7 || Rm > 7) + narrow = FALSE; + else if (inst.instruction == T_MNEM_cmn) + narrow = TRUE; + else if (THUMB_SETS_FLAGS (inst.instruction)) + narrow = !in_it_block (); + else + narrow = in_it_block (); + + if (!inst.operands[1].isreg) + { + /* For an immediate, we always generate a 32-bit opcode; + section relaxation will shrink it later if possible. */ + if (inst.instruction < 0xffff) + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; + inst.instruction |= Rn << r0off; + inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; + } + else + { + /* See if we can do this with a 16-bit instruction. */ + if (narrow) + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rn; + inst.instruction |= Rm << 3; + } + else + { + constraint (inst.operands[1].shifted + && inst.operands[1].immisreg, + _("shift must be constant")); + if (inst.instruction < 0xffff) + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rn << r0off; + encode_thumb32_shifted_operand (1); + } + } + } + else + { + constraint (inst.instruction > 0xffff + || inst.instruction == T_MNEM_mvns, BAD_THUMB32); + constraint (!inst.operands[1].isreg || inst.operands[1].shifted, + _("unshifted register required")); + constraint (Rn > 7 || Rm > 7, + BAD_HIREG); + + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rn; + inst.instruction |= Rm << 3; + } +} + +static void +do_t_mrs (void) +{ + unsigned Rd; + int flags; + + if (do_vfp_nsyn_mrs () == SUCCESS) + return; + + flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); + if (flags == 0) + { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), + _("selected processor does not support " + "requested special purpose register")); + } + else + { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), + _("selected processor does not support " + "requested special purpose register")); + /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ + constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), + _("'CPSR' or 'SPSR' expected")); + } + + Rd = inst.operands[0].reg; + reject_bad_reg (Rd); + + inst.instruction |= Rd << 8; + inst.instruction |= (flags & SPSR_BIT) >> 2; + inst.instruction |= inst.operands[1].imm & 0xff; +} + +static void +do_t_msr (void) +{ + int flags; + unsigned Rn; + + if (do_vfp_nsyn_msr () == SUCCESS) + return; + + constraint (!inst.operands[1].isreg, + _("Thumb encoding does not support an immediate here")); + flags = inst.operands[0].imm; + if (flags & ~0xff) + { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), + _("selected processor does not support " + "requested special purpose register")); + } + else + { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), + _("selected processor does not support " + "requested special purpose register")); + flags |= PSR_f; + } + + Rn = inst.operands[1].reg; + reject_bad_reg (Rn); + + inst.instruction |= (flags & SPSR_BIT) >> 2; + inst.instruction |= (flags & ~SPSR_BIT) >> 8; + inst.instruction |= (flags & 0xff); + inst.instruction |= Rn << 16; +} + +static void +do_t_mul (void) +{ + bfd_boolean narrow; + unsigned Rd, Rn, Rm; + + if (!inst.operands[2].present) + inst.operands[2].reg = inst.operands[0].reg; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + + if (unified_syntax) + { + if (inst.size_req == 4 + || (Rd != Rn + && Rd != Rm) + || Rn > 7 + || Rm > 7) + narrow = FALSE; + else if (inst.instruction == T_MNEM_muls) + narrow = !in_it_block (); + else + narrow = in_it_block (); + } + else + { + constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); + constraint (Rn > 7 || Rm > 7, + BAD_HIREG); + narrow = TRUE; + } + + if (narrow) + { + /* 16-bit MULS/Conditional MUL. */ + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd; + + if (Rd == Rn) + inst.instruction |= Rm << 3; + else if (Rd == Rm) + inst.instruction |= Rn << 3; + else + constraint (1, _("dest must overlap one source register")); + } + else + { + constraint (inst.instruction != T_MNEM_mul, + _("Thumb-2 MUL must not set flags")); + /* 32-bit MUL. */ + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm << 0; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + } +} + +static void +do_t_mull (void) +{ + unsigned RdLo, RdHi, Rn, Rm; + + RdLo = inst.operands[0].reg; + RdHi = inst.operands[1].reg; + Rn = inst.operands[2].reg; + Rm = inst.operands[3].reg; + + reject_bad_reg (RdLo); + reject_bad_reg (RdHi); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= RdLo << 12; + inst.instruction |= RdHi << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; + + if (RdLo == RdHi) + as_tsktsk (_("rdhi and rdlo must be different")); +} + +static void +do_t_nop (void) +{ + set_it_insn_type (NEUTRAL_IT_INSN); + + if (unified_syntax) + { + if (inst.size_req == 4 || inst.operands[0].imm > 15) + { + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= inst.operands[0].imm; + } + else + { + /* PR9722: Check for Thumb2 availability before + generating a thumb2 nop instruction. */ + if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= inst.operands[0].imm << 4; + } + else + inst.instruction = 0x46c0; + } + } + else + { + constraint (inst.operands[0].present, + _("Thumb does not support NOP with hints")); + inst.instruction = 0x46c0; + } +} + +static void +do_t_neg (void) +{ + if (unified_syntax) + { + bfd_boolean narrow; + + if (THUMB_SETS_FLAGS (inst.instruction)) + narrow = !in_it_block (); + else + narrow = in_it_block (); + if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) + narrow = FALSE; + if (inst.size_req == 4) + narrow = FALSE; + + if (!narrow) + { + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].reg << 16; + } + else + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 3; + } + } + else + { + constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, + BAD_HIREG); + constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); + + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 3; + } +} + +static void +do_t_orn (void) +{ + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; + + reject_bad_reg (Rd); + /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ + reject_bad_reg (Rn); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + + if (!inst.operands[2].isreg) + { + inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; + inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; + } + else + { + unsigned Rm; + + Rm = inst.operands[2].reg; + reject_bad_reg (Rm); + + constraint (inst.operands[2].shifted + && inst.operands[2].immisreg, + _("shift must be constant")); + encode_thumb32_shifted_operand (2); + } +} + +static void +do_t_pkhbt (void) +{ + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; + if (inst.operands[3].present) + { + unsigned int val = inst.reloc.exp.X_add_number; + constraint (inst.reloc.exp.X_op != O_constant, + _("expression too complex")); + inst.instruction |= (val & 0x1c) << 10; + inst.instruction |= (val & 0x03) << 6; + } +} + +static void +do_t_pkhtb (void) +{ + if (!inst.operands[3].present) + { + unsigned Rtmp; + + inst.instruction &= ~0x00000020; + + /* PR 10168. Swap the Rm and Rn registers. */ + Rtmp = inst.operands[1].reg; + inst.operands[1].reg = inst.operands[2].reg; + inst.operands[2].reg = Rtmp; + } + do_t_pkhbt (); +} + +static void +do_t_pld (void) +{ + if (inst.operands[0].immisreg) + reject_bad_reg (inst.operands[0].imm); + + encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); +} + +static void +do_t_push_pop (void) +{ + unsigned mask; + + constraint (inst.operands[0].writeback, + _("push/pop do not support {reglist}^")); + constraint (inst.reloc.type != BFD_RELOC_UNUSED, + _("expression too complex")); + + mask = inst.operands[0].imm; + if ((mask & ~0xff) == 0) + inst.instruction = THUMB_OP16 (inst.instruction) | mask; + else if ((inst.instruction == T_MNEM_push + && (mask & ~0xff) == 1 << REG_LR) + || (inst.instruction == T_MNEM_pop + && (mask & ~0xff) == 1 << REG_PC)) + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= THUMB_PP_PC_LR; + inst.instruction |= mask & 0xff; + } + else if (unified_syntax) + { + inst.instruction = THUMB_OP32 (inst.instruction); + encode_thumb2_ldmstm (13, mask, TRUE); + } + else + { + inst.error = _("invalid register list to push/pop instruction"); + return; + } +} + +static void +do_t_rbit (void) +{ + unsigned Rd, Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rm << 16; + inst.instruction |= Rm; +} + +static void +do_t_rev (void) +{ + unsigned Rd, Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + + if (Rd <= 7 && Rm <= 7 + && inst.size_req != 4) + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd; + inst.instruction |= Rm << 3; + } + else if (unified_syntax) + { + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rd << 8; + inst.instruction |= Rm << 16; + inst.instruction |= Rm; + } + else + inst.error = BAD_HIREG; +} + +static void +do_t_rrx (void) +{ + unsigned Rd, Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rm; +} + +static void +do_t_rsb (void) +{ + unsigned Rd, Rs; + + Rd = inst.operands[0].reg; + Rs = (inst.operands[1].present + ? inst.operands[1].reg /* Rd, Rs, foo */ + : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ + + reject_bad_reg (Rd); + reject_bad_reg (Rs); + if (inst.operands[2].isreg) + reject_bad_reg (inst.operands[2].reg); + + inst.instruction |= Rd << 8; + inst.instruction |= Rs << 16; + if (!inst.operands[2].isreg) + { + bfd_boolean narrow; + + if ((inst.instruction & 0x00100000) != 0) + narrow = !in_it_block (); + else + narrow = in_it_block (); + + if (Rd > 7 || Rs > 7) + narrow = FALSE; + + if (inst.size_req == 4 || !unified_syntax) + narrow = FALSE; + + if (inst.reloc.exp.X_op != O_constant + || inst.reloc.exp.X_add_number != 0) + narrow = FALSE; + + /* Turn rsb #0 into 16-bit neg. We should probably do this via + relaxation, but it doesn't seem worth the hassle. */ + if (narrow) + { + inst.reloc.type = BFD_RELOC_UNUSED; + inst.instruction = THUMB_OP16 (T_MNEM_negs); + inst.instruction |= Rs << 3; + inst.instruction |= Rd; + } + else + { + inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; + inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; + } + } + else + encode_thumb32_shifted_operand (2); +} + +static void +do_t_setend (void) +{ + set_it_insn_type (OUTSIDE_IT_INSN); + if (inst.operands[0].imm) + inst.instruction |= 0x8; +} + +static void +do_t_shift (void) +{ + if (!inst.operands[1].present) + inst.operands[1].reg = inst.operands[0].reg; + + if (unified_syntax) + { + bfd_boolean narrow; + int shift_kind; + + switch (inst.instruction) + { + case T_MNEM_asr: + case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; + case T_MNEM_lsl: + case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; + case T_MNEM_lsr: + case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; + case T_MNEM_ror: + case T_MNEM_rors: shift_kind = SHIFT_ROR; break; + default: abort (); + } + + if (THUMB_SETS_FLAGS (inst.instruction)) + narrow = !in_it_block (); + else + narrow = in_it_block (); + if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) + narrow = FALSE; + if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) + narrow = FALSE; + if (inst.operands[2].isreg + && (inst.operands[1].reg != inst.operands[0].reg + || inst.operands[2].reg > 7)) + narrow = FALSE; + if (inst.size_req == 4) + narrow = FALSE; + + reject_bad_reg (inst.operands[0].reg); + reject_bad_reg (inst.operands[1].reg); + + if (!narrow) + { + if (inst.operands[2].isreg) + { + reject_bad_reg (inst.operands[2].reg); + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= inst.operands[2].reg; + } + else + { + inst.operands[1].shifted = 1; + inst.operands[1].shift_kind = shift_kind; + inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) + ? T_MNEM_movs : T_MNEM_mov); + inst.instruction |= inst.operands[0].reg << 8; + encode_thumb32_shifted_operand (1); + /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ + inst.reloc.type = BFD_RELOC_UNUSED; + } + } + else + { + if (inst.operands[2].isreg) + { + switch (shift_kind) + { + case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; + case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; + case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; + case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; + default: abort (); + } + + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[2].reg << 3; + } + else + { + switch (shift_kind) + { + case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; + case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; + case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; + default: abort (); + } + inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 3; + } + } + } + else + { + constraint (inst.operands[0].reg > 7 + || inst.operands[1].reg > 7, BAD_HIREG); + constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); + + if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ + { + constraint (inst.operands[2].reg > 7, BAD_HIREG); + constraint (inst.operands[0].reg != inst.operands[1].reg, + _("source1 and dest must be same register")); + + switch (inst.instruction) + { + case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; + case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; + case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; + case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; + default: abort (); + } + + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[2].reg << 3; + } + else + { + switch (inst.instruction) + { + case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; + case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; + case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; + case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; + default: abort (); + } + inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 3; + } + } +} + +static void +do_t_simd (void) +{ + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; +} + +static void +do_t_smc (void) +{ + unsigned int value = inst.reloc.exp.X_add_number; + constraint (inst.reloc.exp.X_op != O_constant, + _("expression too complex")); + inst.reloc.type = BFD_RELOC_UNUSED; + inst.instruction |= (value & 0xf000) >> 12; + inst.instruction |= (value & 0x0ff0); + inst.instruction |= (value & 0x000f) << 16; +} + +static void +do_t_ssat_usat (int bias) +{ + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + + inst.instruction |= Rd << 8; + inst.instruction |= inst.operands[1].imm - bias; + inst.instruction |= Rn << 16; + + if (inst.operands[3].present) + { + offsetT shift_amount = inst.reloc.exp.X_add_number; + + inst.reloc.type = BFD_RELOC_UNUSED; + + constraint (inst.reloc.exp.X_op != O_constant, + _("expression too complex")); + + if (shift_amount != 0) + { + constraint (shift_amount > 31, + _("shift expression is too large")); + + if (inst.operands[3].shift_kind == SHIFT_ASR) + inst.instruction |= 0x00200000; /* sh bit. */ + + inst.instruction |= (shift_amount & 0x1c) << 10; + inst.instruction |= (shift_amount & 0x03) << 6; + } + } +} + +static void +do_t_ssat (void) +{ + do_t_ssat_usat (1); +} + +static void +do_t_ssat16 (void) +{ + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + + inst.instruction |= Rd << 8; + inst.instruction |= inst.operands[1].imm - 1; + inst.instruction |= Rn << 16; +} + +static void +do_t_strex (void) +{ + constraint (!inst.operands[2].isreg || !inst.operands[2].preind + || inst.operands[2].postind || inst.operands[2].writeback + || inst.operands[2].immisreg || inst.operands[2].shifted + || inst.operands[2].negative, + BAD_ADDR_MODE); + + inst.instruction |= inst.operands[0].reg << 8; + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= inst.operands[2].reg << 16; + inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; +} + +static void +do_t_strexd (void) +{ + if (!inst.operands[2].present) + inst.operands[2].reg = inst.operands[1].reg + 1; + + constraint (inst.operands[0].reg == inst.operands[1].reg + || inst.operands[0].reg == inst.operands[2].reg + || inst.operands[0].reg == inst.operands[3].reg + || inst.operands[1].reg == inst.operands[2].reg, + BAD_OVERLAP); + + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= inst.operands[2].reg << 8; + inst.instruction |= inst.operands[3].reg << 16; +} + +static void +do_t_sxtah (void) +{ + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rn = inst.operands[1].reg; + Rm = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; + inst.instruction |= inst.operands[3].imm << 4; +} + +static void +do_t_sxth (void) +{ + unsigned Rd, Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rm); + + if (inst.instruction <= 0xffff + && inst.size_req != 4 + && Rd <= 7 && Rm <= 7 + && (!inst.operands[2].present || inst.operands[2].imm == 0)) + { + inst.instruction = THUMB_OP16 (inst.instruction); + inst.instruction |= Rd; + inst.instruction |= Rm << 3; + } + else if (unified_syntax) + { + if (inst.instruction <= 0xffff) + inst.instruction = THUMB_OP32 (inst.instruction); + inst.instruction |= Rd << 8; + inst.instruction |= Rm; + inst.instruction |= inst.operands[2].imm << 4; + } + else + { + constraint (inst.operands[2].present && inst.operands[2].imm != 0, + _("Thumb encoding does not support rotation")); + constraint (1, BAD_HIREG); + } +} + +static void +do_t_swi (void) +{ + inst.reloc.type = BFD_RELOC_ARM_SWI; +} + +static void +do_t_tb (void) +{ + unsigned Rn, Rm; + int half; + + half = (inst.instruction & 0x10) != 0; + set_it_insn_type_last (); + constraint (inst.operands[0].immisreg, + _("instruction requires register index")); + + Rn = inst.operands[0].reg; + Rm = inst.operands[0].imm; + + constraint (Rn == REG_SP, BAD_SP); + reject_bad_reg (Rm); + + constraint (!half && inst.operands[0].shifted, + _("instruction does not allow shifted index")); + inst.instruction |= (Rn << 16) | Rm; +} + +static void +do_t_usat (void) +{ + do_t_ssat_usat (0); +} + +static void +do_t_usat16 (void) +{ + unsigned Rd, Rn; + + Rd = inst.operands[0].reg; + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + + inst.instruction |= Rd << 8; + inst.instruction |= inst.operands[1].imm; + inst.instruction |= Rn << 16; +} + +/* Neon instruction encoder helpers. */ + +/* Encodings for the different types for various Neon opcodes. */ + +/* An "invalid" code for the following tables. */ +#define N_INV -1u + +struct neon_tab_entry +{ + unsigned integer; + unsigned float_or_poly; + unsigned scalar_or_imm; +}; + +/* Map overloaded Neon opcodes to their respective encodings. */ +#define NEON_ENC_TAB \ + X(vabd, 0x0000700, 0x1200d00, N_INV), \ + X(vmax, 0x0000600, 0x0000f00, N_INV), \ + X(vmin, 0x0000610, 0x0200f00, N_INV), \ + X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ + X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ + X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ + X(vadd, 0x0000800, 0x0000d00, N_INV), \ + X(vsub, 0x1000800, 0x0200d00, N_INV), \ + X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ + X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ + X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ + /* Register variants of the following two instructions are encoded as + vcge / vcgt with the operands reversed. */ \ + X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ + X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ + X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ + X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ + X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ + X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ + X(vmlal, 0x0800800, N_INV, 0x0800240), \ + X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ + X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ + X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ + X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ + X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ + X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ + X(vshl, 0x0000400, N_INV, 0x0800510), \ + X(vqshl, 0x0000410, N_INV, 0x0800710), \ + X(vand, 0x0000110, N_INV, 0x0800030), \ + X(vbic, 0x0100110, N_INV, 0x0800030), \ + X(veor, 0x1000110, N_INV, N_INV), \ + X(vorn, 0x0300110, N_INV, 0x0800010), \ + X(vorr, 0x0200110, N_INV, 0x0800010), \ + X(vmvn, 0x1b00580, N_INV, 0x0800030), \ + X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ + X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ + X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ + X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ + X(vst1, 0x0000000, 0x0800000, N_INV), \ + X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ + X(vst2, 0x0000100, 0x0800100, N_INV), \ + X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ + X(vst3, 0x0000200, 0x0800200, N_INV), \ + X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ + X(vst4, 0x0000300, 0x0800300, N_INV), \ + X(vmovn, 0x1b20200, N_INV, N_INV), \ + X(vtrn, 0x1b20080, N_INV, N_INV), \ + X(vqmovn, 0x1b20200, N_INV, N_INV), \ + X(vqmovun, 0x1b20240, N_INV, N_INV), \ + X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ + X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ + X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ + X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ + X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ + X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ + X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) + +enum neon_opc +{ +#define X(OPC,I,F,S) N_MNEM_##OPC +NEON_ENC_TAB +#undef X +}; + +static const struct neon_tab_entry neon_enc_tab[] = +{ +#define X(OPC,I,F,S) { (I), (F), (S) } +NEON_ENC_TAB +#undef X +}; + +#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) +#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) +#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) +#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) +#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) +#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) +#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) +#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) +#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) +#define NEON_ENC_SINGLE(X) \ + ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) +#define NEON_ENC_DOUBLE(X) \ + ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) + +/* Define shapes for instruction operands. The following mnemonic characters + are used in this table: + + F - VFP S register + D - Neon D register + Q - Neon Q register + I - Immediate + S - Scalar + R - ARM register + L - D register list + + This table is used to generate various data: + - enumerations of the form NS_DDR to be used as arguments to + neon_select_shape. + - a table classifying shapes into single, double, quad, mixed. + - a table used to drive neon_select_shape. */ + +#define NEON_SHAPE_DEF \ + X(3, (D, D, D), DOUBLE), \ + X(3, (Q, Q, Q), QUAD), \ + X(3, (D, D, I), DOUBLE), \ + X(3, (Q, Q, I), QUAD), \ + X(3, (D, D, S), DOUBLE), \ + X(3, (Q, Q, S), QUAD), \ + X(2, (D, D), DOUBLE), \ + X(2, (Q, Q), QUAD), \ + X(2, (D, S), DOUBLE), \ + X(2, (Q, S), QUAD), \ + X(2, (D, R), DOUBLE), \ + X(2, (Q, R), QUAD), \ + X(2, (D, I), DOUBLE), \ + X(2, (Q, I), QUAD), \ + X(3, (D, L, D), DOUBLE), \ + X(2, (D, Q), MIXED), \ + X(2, (Q, D), MIXED), \ + X(3, (D, Q, I), MIXED), \ + X(3, (Q, D, I), MIXED), \ + X(3, (Q, D, D), MIXED), \ + X(3, (D, Q, Q), MIXED), \ + X(3, (Q, Q, D), MIXED), \ + X(3, (Q, D, S), MIXED), \ + X(3, (D, Q, S), MIXED), \ + X(4, (D, D, D, I), DOUBLE), \ + X(4, (Q, Q, Q, I), QUAD), \ + X(2, (F, F), SINGLE), \ + X(3, (F, F, F), SINGLE), \ + X(2, (F, I), SINGLE), \ + X(2, (F, D), MIXED), \ + X(2, (D, F), MIXED), \ + X(3, (F, F, I), MIXED), \ + X(4, (R, R, F, F), SINGLE), \ + X(4, (F, F, R, R), SINGLE), \ + X(3, (D, R, R), DOUBLE), \ + X(3, (R, R, D), DOUBLE), \ + X(2, (S, R), SINGLE), \ + X(2, (R, S), SINGLE), \ + X(2, (F, R), SINGLE), \ + X(2, (R, F), SINGLE) + +#define S2(A,B) NS_##A##B +#define S3(A,B,C) NS_##A##B##C +#define S4(A,B,C,D) NS_##A##B##C##D + +#define X(N, L, C) S##N L + +enum neon_shape +{ + NEON_SHAPE_DEF, + NS_NULL +}; + +#undef X +#undef S2 +#undef S3 +#undef S4 + +enum neon_shape_class +{ + SC_SINGLE, + SC_DOUBLE, + SC_QUAD, + SC_MIXED +}; + +#define X(N, L, C) SC_##C + +static enum neon_shape_class neon_shape_class[] = +{ + NEON_SHAPE_DEF +}; + +#undef X + +enum neon_shape_el +{ + SE_F, + SE_D, + SE_Q, + SE_I, + SE_S, + SE_R, + SE_L +}; + +/* Register widths of above. */ +static unsigned neon_shape_el_size[] = +{ + 32, + 64, + 128, + 0, + 32, + 32, + 0 +}; + +struct neon_shape_info +{ + unsigned els; + enum neon_shape_el el[NEON_MAX_TYPE_ELS]; +}; + +#define S2(A,B) { SE_##A, SE_##B } +#define S3(A,B,C) { SE_##A, SE_##B, SE_##C } +#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } + +#define X(N, L, C) { N, S##N L } + +static struct neon_shape_info neon_shape_tab[] = +{ + NEON_SHAPE_DEF +}; + +#undef X +#undef S2 +#undef S3 +#undef S4 + +/* Bit masks used in type checking given instructions. + 'N_EQK' means the type must be the same as (or based on in some way) the key + type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is + set, various other bits can be set as well in order to modify the meaning of + the type constraint. */ + +enum neon_type_mask +{ + N_S8 = 0x0000001, + N_S16 = 0x0000002, + N_S32 = 0x0000004, + N_S64 = 0x0000008, + N_U8 = 0x0000010, + N_U16 = 0x0000020, + N_U32 = 0x0000040, + N_U64 = 0x0000080, + N_I8 = 0x0000100, + N_I16 = 0x0000200, + N_I32 = 0x0000400, + N_I64 = 0x0000800, + N_8 = 0x0001000, + N_16 = 0x0002000, + N_32 = 0x0004000, + N_64 = 0x0008000, + N_P8 = 0x0010000, + N_P16 = 0x0020000, + N_F16 = 0x0040000, + N_F32 = 0x0080000, + N_F64 = 0x0100000, + N_KEY = 0x1000000, /* Key element (main type specifier). */ + N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ + N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ + N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ + N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ + N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ + N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ + N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ + N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ + N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ + N_UTYP = 0, + N_MAX_NONSPECIAL = N_F64 +}; + +#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) + +#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) +#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) +#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) +#define N_SUF_32 (N_SU_32 | N_F32) +#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) +#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) + +/* Pass this as the first type argument to neon_check_type to ignore types + altogether. */ +#define N_IGNORE_TYPE (N_KEY | N_EQK) + +/* Select a "shape" for the current instruction (describing register types or + sizes) from a list of alternatives. Return NS_NULL if the current instruction + doesn't fit. For non-polymorphic shapes, checking is usually done as a + function of operand parsing, so this function doesn't need to be called. + Shapes should be listed in order of decreasing length. */ + +static enum neon_shape +neon_select_shape (enum neon_shape shape, ...) +{ + va_list ap; + enum neon_shape first_shape = shape; + + /* Fix missing optional operands. FIXME: we don't know at this point how + many arguments we should have, so this makes the assumption that we have + > 1. This is true of all current Neon opcodes, I think, but may not be + true in the future. */ + if (!inst.operands[1].present) + inst.operands[1] = inst.operands[0]; + + va_start (ap, shape); + + for (; shape != NS_NULL; shape = va_arg (ap, int)) + { + unsigned j; + int matches = 1; + + for (j = 0; j < neon_shape_tab[shape].els; j++) + { + if (!inst.operands[j].present) + { + matches = 0; + break; + } + + switch (neon_shape_tab[shape].el[j]) + { + case SE_F: + if (!(inst.operands[j].isreg + && inst.operands[j].isvec + && inst.operands[j].issingle + && !inst.operands[j].isquad)) + matches = 0; + break; + + case SE_D: + if (!(inst.operands[j].isreg + && inst.operands[j].isvec + && !inst.operands[j].isquad + && !inst.operands[j].issingle)) + matches = 0; + break; + + case SE_R: + if (!(inst.operands[j].isreg + && !inst.operands[j].isvec)) + matches = 0; + break; + + case SE_Q: + if (!(inst.operands[j].isreg + && inst.operands[j].isvec + && inst.operands[j].isquad + && !inst.operands[j].issingle)) + matches = 0; + break; + + case SE_I: + if (!(!inst.operands[j].isreg + && !inst.operands[j].isscalar)) + matches = 0; + break; + + case SE_S: + if (!(!inst.operands[j].isreg + && inst.operands[j].isscalar)) + matches = 0; + break; + + case SE_L: + break; + } + } + if (matches) + break; + } + + va_end (ap); + + if (shape == NS_NULL && first_shape != NS_NULL) + first_error (_("invalid instruction shape")); + + return shape; +} + +/* True if SHAPE is predominantly a quadword operation (most of the time, this + means the Q bit should be set). */ + +static int +neon_quad (enum neon_shape shape) +{ + return neon_shape_class[shape] == SC_QUAD; +} + +static void +neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, + unsigned *g_size) +{ + /* Allow modification to be made to types which are constrained to be + based on the key element, based on bits set alongside N_EQK. */ + if ((typebits & N_EQK) != 0) + { + if ((typebits & N_HLF) != 0) + *g_size /= 2; + else if ((typebits & N_DBL) != 0) + *g_size *= 2; + if ((typebits & N_SGN) != 0) + *g_type = NT_signed; + else if ((typebits & N_UNS) != 0) + *g_type = NT_unsigned; + else if ((typebits & N_INT) != 0) + *g_type = NT_integer; + else if ((typebits & N_FLT) != 0) + *g_type = NT_float; + else if ((typebits & N_SIZ) != 0) + *g_type = NT_untyped; + } +} + +/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" + operand type, i.e. the single type specified in a Neon instruction when it + is the only one given. */ + +static struct neon_type_el +neon_type_promote (struct neon_type_el *key, unsigned thisarg) +{ + struct neon_type_el dest = *key; + + gas_assert ((thisarg & N_EQK) != 0); + + neon_modify_type_size (thisarg, &dest.type, &dest.size); + + return dest; +} + +/* Convert Neon type and size into compact bitmask representation. */ + +static enum neon_type_mask +type_chk_of_el_type (enum neon_el_type type, unsigned size) +{ + switch (type) + { + case NT_untyped: + switch (size) + { + case 8: return N_8; + case 16: return N_16; + case 32: return N_32; + case 64: return N_64; + default: ; + } + break; + + case NT_integer: + switch (size) + { + case 8: return N_I8; + case 16: return N_I16; + case 32: return N_I32; + case 64: return N_I64; + default: ; + } + break; + + case NT_float: + switch (size) + { + case 16: return N_F16; + case 32: return N_F32; + case 64: return N_F64; + default: ; + } + break; + + case NT_poly: + switch (size) + { + case 8: return N_P8; + case 16: return N_P16; + default: ; + } + break; + + case NT_signed: + switch (size) + { + case 8: return N_S8; + case 16: return N_S16; + case 32: return N_S32; + case 64: return N_S64; + default: ; + } + break; + + case NT_unsigned: + switch (size) + { + case 8: return N_U8; + case 16: return N_U16; + case 32: return N_U32; + case 64: return N_U64; + default: ; + } + break; + + default: ; + } + + return N_UTYP; +} + +/* Convert compact Neon bitmask type representation to a type and size. Only + handles the case where a single bit is set in the mask. */ + +static int +el_type_of_type_chk (enum neon_el_type *type, unsigned *size, + enum neon_type_mask mask) +{ + if ((mask & N_EQK) != 0) + return FAIL; + + if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) + *size = 8; + else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) + *size = 16; + else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) + *size = 32; + else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) + *size = 64; + else + return FAIL; + + if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) + *type = NT_signed; + else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) + *type = NT_unsigned; + else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) + *type = NT_integer; + else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) + *type = NT_untyped; + else if ((mask & (N_P8 | N_P16)) != 0) + *type = NT_poly; + else if ((mask & (N_F32 | N_F64)) != 0) + *type = NT_float; + else + return FAIL; + + return SUCCESS; +} + +/* Modify a bitmask of allowed types. This is only needed for type + relaxation. */ + +static unsigned +modify_types_allowed (unsigned allowed, unsigned mods) +{ + unsigned size; + enum neon_el_type type; + unsigned destmask; + int i; + + destmask = 0; + + for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) + { + if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) + { + neon_modify_type_size (mods, &type, &size); + destmask |= type_chk_of_el_type (type, size); + } + } + + return destmask; +} + +/* Check type and return type classification. + The manual states (paraphrase): If one datatype is given, it indicates the + type given in: + - the second operand, if there is one + - the operand, if there is no second operand + - the result, if there are no operands. + This isn't quite good enough though, so we use a concept of a "key" datatype + which is set on a per-instruction basis, which is the one which matters when + only one data type is written. + Note: this function has side-effects (e.g. filling in missing operands). All + Neon instructions should call it before performing bit encoding. */ + +static struct neon_type_el +neon_check_type (unsigned els, enum neon_shape ns, ...) +{ + va_list ap; + unsigned i, pass, key_el = 0; + unsigned types[NEON_MAX_TYPE_ELS]; + enum neon_el_type k_type = NT_invtype; + unsigned k_size = -1u; + struct neon_type_el badtype = {NT_invtype, -1}; + unsigned key_allowed = 0; + + /* Optional registers in Neon instructions are always (not) in operand 1. + Fill in the missing operand here, if it was omitted. */ + if (els > 1 && !inst.operands[1].present) + inst.operands[1] = inst.operands[0]; + + /* Suck up all the varargs. */ + va_start (ap, ns); + for (i = 0; i < els; i++) + { + unsigned thisarg = va_arg (ap, unsigned); + if (thisarg == N_IGNORE_TYPE) + { + va_end (ap); + return badtype; + } + types[i] = thisarg; + if ((thisarg & N_KEY) != 0) + key_el = i; + } + va_end (ap); + + if (inst.vectype.elems > 0) + for (i = 0; i < els; i++) + if (inst.operands[i].vectype.type != NT_invtype) + { + first_error (_("types specified in both the mnemonic and operands")); + return badtype; + } + + /* Duplicate inst.vectype elements here as necessary. + FIXME: No idea if this is exactly the same as the ARM assembler, + particularly when an insn takes one register and one non-register + operand. */ + if (inst.vectype.elems == 1 && els > 1) + { + unsigned j; + inst.vectype.elems = els; + inst.vectype.el[key_el] = inst.vectype.el[0]; + for (j = 0; j < els; j++) + if (j != key_el) + inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], + types[j]); + } + else if (inst.vectype.elems == 0 && els > 0) + { + unsigned j; + /* No types were given after the mnemonic, so look for types specified + after each operand. We allow some flexibility here; as long as the + "key" operand has a type, we can infer the others. */ + for (j = 0; j < els; j++) + if (inst.operands[j].vectype.type != NT_invtype) + inst.vectype.el[j] = inst.operands[j].vectype; + + if (inst.operands[key_el].vectype.type != NT_invtype) + { + for (j = 0; j < els; j++) + if (inst.operands[j].vectype.type == NT_invtype) + inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], + types[j]); + } + else + { + first_error (_("operand types can't be inferred")); + return badtype; + } + } + else if (inst.vectype.elems != els) + { + first_error (_("type specifier has the wrong number of parts")); + return badtype; + } + + for (pass = 0; pass < 2; pass++) + { + for (i = 0; i < els; i++) + { + unsigned thisarg = types[i]; + unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) + ? modify_types_allowed (key_allowed, thisarg) : thisarg; + enum neon_el_type g_type = inst.vectype.el[i].type; + unsigned g_size = inst.vectype.el[i].size; + + /* Decay more-specific signed & unsigned types to sign-insensitive + integer types if sign-specific variants are unavailable. */ + if ((g_type == NT_signed || g_type == NT_unsigned) + && (types_allowed & N_SU_ALL) == 0) + g_type = NT_integer; + + /* If only untyped args are allowed, decay any more specific types to + them. Some instructions only care about signs for some element + sizes, so handle that properly. */ + if ((g_size == 8 && (types_allowed & N_8) != 0) + || (g_size == 16 && (types_allowed & N_16) != 0) + || (g_size == 32 && (types_allowed & N_32) != 0) + || (g_size == 64 && (types_allowed & N_64) != 0)) + g_type = NT_untyped; + + if (pass == 0) + { + if ((thisarg & N_KEY) != 0) + { + k_type = g_type; + k_size = g_size; + key_allowed = thisarg & ~N_KEY; + } + } + else + { + if ((thisarg & N_VFP) != 0) + { + enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; + unsigned regwidth = neon_shape_el_size[regshape], match; + + /* In VFP mode, operands must match register widths. If we + have a key operand, use its width, else use the width of + the current operand. */ + if (k_size != -1u) + match = k_size; + else + match = g_size; + + if (regwidth != match) + { + first_error (_("operand size must match register width")); + return badtype; + } + } + + if ((thisarg & N_EQK) == 0) + { + unsigned given_type = type_chk_of_el_type (g_type, g_size); + + if ((given_type & types_allowed) == 0) + { + first_error (_("bad type in Neon instruction")); + return badtype; + } + } + else + { + enum neon_el_type mod_k_type = k_type; + unsigned mod_k_size = k_size; + neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); + if (g_type != mod_k_type || g_size != mod_k_size) + { + first_error (_("inconsistent types in Neon instruction")); + return badtype; + } + } + } + } + } + + return inst.vectype.el[key_el]; +} + +/* Neon-style VFP instruction forwarding. */ + +/* Thumb VFP instructions have 0xE in the condition field. */ + +static void +do_vfp_cond_or_thumb (void) +{ + if (thumb_mode) + inst.instruction |= 0xe0000000; + else + inst.instruction |= inst.cond << 28; +} + +/* Look up and encode a simple mnemonic, for use as a helper function for the + Neon-style VFP syntax. This avoids duplication of bits of the insns table, + etc. It is assumed that operand parsing has already been done, and that the + operands are in the form expected by the given opcode (this isn't necessarily + the same as the form in which they were parsed, hence some massaging must + take place before this function is called). + Checks current arch version against that in the looked-up opcode. */ + +static void +do_vfp_nsyn_opcode (const char *opname) +{ + const struct asm_opcode *opcode; + + opcode = hash_find (arm_ops_hsh, opname); + + if (!opcode) + abort (); + + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, + thumb_mode ? *opcode->tvariant : *opcode->avariant), + _(BAD_FPU)); + + if (thumb_mode) + { + inst.instruction = opcode->tvalue; + opcode->tencode (); + } + else + { + inst.instruction = (inst.cond << 28) | opcode->avalue; + opcode->aencode (); + } +} + +static void +do_vfp_nsyn_add_sub (enum neon_shape rs) +{ + int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; + + if (rs == NS_FFF) + { + if (is_add) + do_vfp_nsyn_opcode ("fadds"); + else + do_vfp_nsyn_opcode ("fsubs"); + } + else + { + if (is_add) + do_vfp_nsyn_opcode ("faddd"); + else + do_vfp_nsyn_opcode ("fsubd"); + } +} + +/* Check operand types to see if this is a VFP instruction, and if so call + PFN (). */ + +static int +try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) +{ + enum neon_shape rs; + struct neon_type_el et; + + switch (args) + { + case 2: + rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); + et = neon_check_type (2, rs, + N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); + break; + + case 3: + rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); + et = neon_check_type (3, rs, + N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); + break; + + default: + abort (); + } + + if (et.type != NT_invtype) + { + pfn (rs); + return SUCCESS; + } + else + inst.error = NULL; + + return FAIL; +} + +static void +do_vfp_nsyn_mla_mls (enum neon_shape rs) +{ + int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; + + if (rs == NS_FFF) + { + if (is_mla) + do_vfp_nsyn_opcode ("fmacs"); + else + do_vfp_nsyn_opcode ("fmscs"); + } + else + { + if (is_mla) + do_vfp_nsyn_opcode ("fmacd"); + else + do_vfp_nsyn_opcode ("fmscd"); + } +} + +static void +do_vfp_nsyn_mul (enum neon_shape rs) +{ + if (rs == NS_FFF) + do_vfp_nsyn_opcode ("fmuls"); + else + do_vfp_nsyn_opcode ("fmuld"); +} + +static void +do_vfp_nsyn_abs_neg (enum neon_shape rs) +{ + int is_neg = (inst.instruction & 0x80) != 0; + neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); + + if (rs == NS_FF) + { + if (is_neg) + do_vfp_nsyn_opcode ("fnegs"); + else + do_vfp_nsyn_opcode ("fabss"); + } + else + { + if (is_neg) + do_vfp_nsyn_opcode ("fnegd"); + else + do_vfp_nsyn_opcode ("fabsd"); + } +} + +/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision + insns belong to Neon, and are handled elsewhere. */ + +static void +do_vfp_nsyn_ldm_stm (int is_dbmode) +{ + int is_ldm = (inst.instruction & (1 << 20)) != 0; + if (is_ldm) + { + if (is_dbmode) + do_vfp_nsyn_opcode ("fldmdbs"); + else + do_vfp_nsyn_opcode ("fldmias"); + } + else + { + if (is_dbmode) + do_vfp_nsyn_opcode ("fstmdbs"); + else + do_vfp_nsyn_opcode ("fstmias"); + } +} + +static void +do_vfp_nsyn_sqrt (void) +{ + enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); + neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); + + if (rs == NS_FF) + do_vfp_nsyn_opcode ("fsqrts"); + else + do_vfp_nsyn_opcode ("fsqrtd"); +} + +static void +do_vfp_nsyn_div (void) +{ + enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); + neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, + N_F32 | N_F64 | N_KEY | N_VFP); + + if (rs == NS_FFF) + do_vfp_nsyn_opcode ("fdivs"); + else + do_vfp_nsyn_opcode ("fdivd"); +} + +static void +do_vfp_nsyn_nmul (void) +{ + enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); + neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, + N_F32 | N_F64 | N_KEY | N_VFP); + + if (rs == NS_FFF) + { + inst.instruction = NEON_ENC_SINGLE (inst.instruction); + do_vfp_sp_dyadic (); + } + else + { + inst.instruction = NEON_ENC_DOUBLE (inst.instruction); + do_vfp_dp_rd_rn_rm (); + } + do_vfp_cond_or_thumb (); +} + +static void +do_vfp_nsyn_cmp (void) +{ + if (inst.operands[1].isreg) + { + enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); + neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); + + if (rs == NS_FF) + { + inst.instruction = NEON_ENC_SINGLE (inst.instruction); + do_vfp_sp_monadic (); + } + else + { + inst.instruction = NEON_ENC_DOUBLE (inst.instruction); + do_vfp_dp_rd_rm (); + } + } + else + { + enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); + neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); + + switch (inst.instruction & 0x0fffffff) + { + case N_MNEM_vcmp: + inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; + break; + case N_MNEM_vcmpe: + inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; + break; + default: + abort (); + } + + if (rs == NS_FI) + { + inst.instruction = NEON_ENC_SINGLE (inst.instruction); + do_vfp_sp_compare_z (); + } + else + { + inst.instruction = NEON_ENC_DOUBLE (inst.instruction); + do_vfp_dp_rd (); + } + } + do_vfp_cond_or_thumb (); +} + +static void +nsyn_insert_sp (void) +{ + inst.operands[1] = inst.operands[0]; + memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); + inst.operands[0].reg = REG_SP; + inst.operands[0].isreg = 1; + inst.operands[0].writeback = 1; + inst.operands[0].present = 1; +} + +static void +do_vfp_nsyn_push (void) +{ + nsyn_insert_sp (); + if (inst.operands[1].issingle) + do_vfp_nsyn_opcode ("fstmdbs"); + else + do_vfp_nsyn_opcode ("fstmdbd"); +} + +static void +do_vfp_nsyn_pop (void) +{ + nsyn_insert_sp (); + if (inst.operands[1].issingle) + do_vfp_nsyn_opcode ("fldmias"); + else + do_vfp_nsyn_opcode ("fldmiad"); +} + +/* Fix up Neon data-processing instructions, ORing in the correct bits for + ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ + +static unsigned +neon_dp_fixup (unsigned i) +{ + if (thumb_mode) + { + /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ + if (i & (1 << 24)) + i |= 1 << 28; + + i &= ~(1 << 24); + + i |= 0xef000000; + } + else + i |= 0xf2000000; + + return i; +} + +/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 + (0, 1, 2, 3). */ + +static unsigned +neon_logbits (unsigned x) +{ + return ffs (x) - 4; +} + +#define LOW4(R) ((R) & 0xf) +#define HI1(R) (((R) >> 4) & 1) + +/* Encode insns with bit pattern: + + |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| + | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | + + SIZE is passed in bits. -1 means size field isn't changed, in case it has a + different meaning for some instruction. */ + +static void +neon_three_same (int isquad, int ubit, int size) +{ + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= LOW4 (inst.operands[2].reg); + inst.instruction |= HI1 (inst.operands[2].reg) << 5; + inst.instruction |= (isquad != 0) << 6; + inst.instruction |= (ubit != 0) << 24; + if (size != -1) + inst.instruction |= neon_logbits (size) << 20; + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +/* Encode instructions of the form: + + |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| + | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | + + Don't write size if SIZE == -1. */ + +static void +neon_two_same (int qbit, int ubit, int size) +{ + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= (qbit != 0) << 6; + inst.instruction |= (ubit != 0) << 24; + + if (size != -1) + inst.instruction |= neon_logbits (size) << 18; + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +/* Neon instruction encoders, in approximate order of appearance. */ + +static void +do_neon_dyadic_i_su (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_SU_32 | N_KEY); + neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); +} + +static void +do_neon_dyadic_i64_su (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_SU_ALL | N_KEY); + neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); +} + +static void +neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, + unsigned immbits) +{ + unsigned size = et.size >> 3; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= (isquad != 0) << 6; + inst.instruction |= immbits << 16; + inst.instruction |= (size >> 3) << 7; + inst.instruction |= (size & 0x7) << 19; + if (write_ubit) + inst.instruction |= (uval != 0) << 24; + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +static void +do_neon_shl_imm (void) +{ + if (!inst.operands[2].isreg) + { + enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); + inst.instruction = NEON_ENC_IMMED (inst.instruction); + neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); + } + else + { + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); + unsigned int tmp; + + /* VSHL/VQSHL 3-register variants have syntax such as: + vshl.xx Dd, Dm, Dn + whereas other 3-register operations encoded by neon_three_same have + syntax like: + vadd.xx Dd, Dn, Dm + (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg + here. */ + tmp = inst.operands[2].reg; + inst.operands[2].reg = inst.operands[1].reg; + inst.operands[1].reg = tmp; + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); + } +} + +static void +do_neon_qshl_imm (void) +{ + if (!inst.operands[2].isreg) + { + enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); + + inst.instruction = NEON_ENC_IMMED (inst.instruction); + neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, + inst.operands[2].imm); + } + else + { + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); + unsigned int tmp; + + /* See note in do_neon_shl_imm. */ + tmp = inst.operands[2].reg; + inst.operands[2].reg = inst.operands[1].reg; + inst.operands[1].reg = tmp; + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); + } +} + +static void +do_neon_rshl (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_SU_ALL | N_KEY); + unsigned int tmp; + + tmp = inst.operands[2].reg; + inst.operands[2].reg = inst.operands[1].reg; + inst.operands[1].reg = tmp; + neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); +} + +static int +neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) +{ + /* Handle .I8 pseudo-instructions. */ + if (size == 8) + { + /* Unfortunately, this will make everything apart from zero out-of-range. + FIXME is this the intended semantics? There doesn't seem much point in + accepting .I8 if so. */ + immediate |= immediate << 8; + size = 16; + } + + if (size >= 32) + { + if (immediate == (immediate & 0x000000ff)) + { + *immbits = immediate; + return 0x1; + } + else if (immediate == (immediate & 0x0000ff00)) + { + *immbits = immediate >> 8; + return 0x3; + } + else if (immediate == (immediate & 0x00ff0000)) + { + *immbits = immediate >> 16; + return 0x5; + } + else if (immediate == (immediate & 0xff000000)) + { + *immbits = immediate >> 24; + return 0x7; + } + if ((immediate & 0xffff) != (immediate >> 16)) + goto bad_immediate; + immediate &= 0xffff; + } + + if (immediate == (immediate & 0x000000ff)) + { + *immbits = immediate; + return 0x9; + } + else if (immediate == (immediate & 0x0000ff00)) + { + *immbits = immediate >> 8; + return 0xb; + } + + bad_immediate: + first_error (_("immediate value out of range")); + return FAIL; +} + +/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits + A, B, C, D. */ + +static int +neon_bits_same_in_bytes (unsigned imm) +{ + return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) + && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) + && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) + && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); +} + +/* For immediate of above form, return 0bABCD. */ + +static unsigned +neon_squash_bits (unsigned imm) +{ + return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) + | ((imm & 0x01000000) >> 21); +} + +/* Compress quarter-float representation to 0b...000 abcdefgh. */ + +static unsigned +neon_qfloat_bits (unsigned imm) +{ + return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); +} + +/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into + the instruction. *OP is passed as the initial value of the op field, and + may be set to a different value depending on the constant (i.e. + "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not + MVN). If the immediate looks like a repeated pattern then also + try smaller element sizes. */ + +static int +neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, + unsigned *immbits, int *op, int size, + enum neon_el_type type) +{ + /* Only permit float immediates (including 0.0/-0.0) if the operand type is + float. */ + if (type == NT_float && !float_p) + return FAIL; + + if (type == NT_float && is_quarter_float (immlo) && immhi == 0) + { + if (size != 32 || *op == 1) + return FAIL; + *immbits = neon_qfloat_bits (immlo); + return 0xf; + } + + if (size == 64) + { + if (neon_bits_same_in_bytes (immhi) + && neon_bits_same_in_bytes (immlo)) + { + if (*op == 1) + return FAIL; + *immbits = (neon_squash_bits (immhi) << 4) + | neon_squash_bits (immlo); + *op = 1; + return 0xe; + } + + if (immhi != immlo) + return FAIL; + } + + if (size >= 32) + { + if (immlo == (immlo & 0x000000ff)) + { + *immbits = immlo; + return 0x0; + } + else if (immlo == (immlo & 0x0000ff00)) + { + *immbits = immlo >> 8; + return 0x2; + } + else if (immlo == (immlo & 0x00ff0000)) + { + *immbits = immlo >> 16; + return 0x4; + } + else if (immlo == (immlo & 0xff000000)) + { + *immbits = immlo >> 24; + return 0x6; + } + else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) + { + *immbits = (immlo >> 8) & 0xff; + return 0xc; + } + else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) + { + *immbits = (immlo >> 16) & 0xff; + return 0xd; + } + + if ((immlo & 0xffff) != (immlo >> 16)) + return FAIL; + immlo &= 0xffff; + } + + if (size >= 16) + { + if (immlo == (immlo & 0x000000ff)) + { + *immbits = immlo; + return 0x8; + } + else if (immlo == (immlo & 0x0000ff00)) + { + *immbits = immlo >> 8; + return 0xa; + } + + if ((immlo & 0xff) != (immlo >> 8)) + return FAIL; + immlo &= 0xff; + } + + if (immlo == (immlo & 0x000000ff)) + { + /* Don't allow MVN with 8-bit immediate. */ + if (*op == 1) + return FAIL; + *immbits = immlo; + return 0xe; + } + + return FAIL; +} + +/* Write immediate bits [7:0] to the following locations: + + |28/24|23 19|18 16|15 4|3 0| + | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| + + This function is used by VMOV/VMVN/VORR/VBIC. */ + +static void +neon_write_immbits (unsigned immbits) +{ + inst.instruction |= immbits & 0xf; + inst.instruction |= ((immbits >> 4) & 0x7) << 16; + inst.instruction |= ((immbits >> 7) & 0x1) << 24; +} + +/* Invert low-order SIZE bits of XHI:XLO. */ + +static void +neon_invert_size (unsigned *xlo, unsigned *xhi, int size) +{ + unsigned immlo = xlo ? *xlo : 0; + unsigned immhi = xhi ? *xhi : 0; + + switch (size) + { + case 8: + immlo = (~immlo) & 0xff; + break; + + case 16: + immlo = (~immlo) & 0xffff; + break; + + case 64: + immhi = (~immhi) & 0xffffffff; + /* fall through. */ + + case 32: + immlo = (~immlo) & 0xffffffff; + break; + + default: + abort (); + } + + if (xlo) + *xlo = immlo; + + if (xhi) + *xhi = immhi; +} + +static void +do_neon_logic (void) +{ + if (inst.operands[2].present && inst.operands[2].isreg) + { + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + neon_check_type (3, rs, N_IGNORE_TYPE); + /* U bit and size field were set as part of the bitmask. */ + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + neon_three_same (neon_quad (rs), 0, -1); + } + else + { + enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); + enum neon_opc opcode = inst.instruction & 0x0fffffff; + unsigned immbits; + int cmode; + + if (et.type == NT_invtype) + return; + + inst.instruction = NEON_ENC_IMMED (inst.instruction); + + immbits = inst.operands[1].imm; + if (et.size == 64) + { + /* .i64 is a pseudo-op, so the immediate must be a repeating + pattern. */ + if (immbits != (inst.operands[1].regisimm ? + inst.operands[1].reg : 0)) + { + /* Set immbits to an invalid constant. */ + immbits = 0xdeadbeef; + } + } + + switch (opcode) + { + case N_MNEM_vbic: + cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); + break; + + case N_MNEM_vorr: + cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); + break; + + case N_MNEM_vand: + /* Pseudo-instruction for VBIC. */ + neon_invert_size (&immbits, 0, et.size); + cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); + break; + + case N_MNEM_vorn: + /* Pseudo-instruction for VORR. */ + neon_invert_size (&immbits, 0, et.size); + cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); + break; + + default: + abort (); + } + + if (cmode == FAIL) + return; + + inst.instruction |= neon_quad (rs) << 6; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= cmode << 8; + neon_write_immbits (immbits); + + inst.instruction = neon_dp_fixup (inst.instruction); + } +} + +static void +do_neon_bitfield (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + neon_check_type (3, rs, N_IGNORE_TYPE); + neon_three_same (neon_quad (rs), 0, -1); +} + +static void +neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, + unsigned destbits) +{ + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, + types | N_KEY); + if (et.type == NT_float) + { + inst.instruction = NEON_ENC_FLOAT (inst.instruction); + neon_three_same (neon_quad (rs), 0, -1); + } + else + { + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); + } +} + +static void +do_neon_dyadic_if_su (void) +{ + neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); +} + +static void +do_neon_dyadic_if_su_d (void) +{ + /* This version only allow D registers, but that constraint is enforced during + operand parsing so we don't need to do anything extra here. */ + neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); +} + +static void +do_neon_dyadic_if_i_d (void) +{ + /* The "untyped" case can't happen. Do this to stop the "U" bit being + affected if we specify unsigned args. */ + neon_dyadic_misc (NT_untyped, N_IF_32, 0); +} + +enum vfp_or_neon_is_neon_bits +{ + NEON_CHECK_CC = 1, + NEON_CHECK_ARCH = 2 +}; + +/* Call this function if an instruction which may have belonged to the VFP or + Neon instruction sets, but turned out to be a Neon instruction (due to the + operand types involved, etc.). We have to check and/or fix-up a couple of + things: + + - Make sure the user hasn't attempted to make a Neon instruction + conditional. + - Alter the value in the condition code field if necessary. + - Make sure that the arch supports Neon instructions. + + Which of these operations take place depends on bits from enum + vfp_or_neon_is_neon_bits. + + WARNING: This function has side effects! If NEON_CHECK_CC is used and the + current instruction's condition is COND_ALWAYS, the condition field is + changed to inst.uncond_value. This is necessary because instructions shared + between VFP and Neon may be conditional for the VFP variants only, and the + unconditional Neon version must have, e.g., 0xF in the condition field. */ + +static int +vfp_or_neon_is_neon (unsigned check) +{ + /* Conditions are always legal in Thumb mode (IT blocks). */ + if (!thumb_mode && (check & NEON_CHECK_CC)) + { + if (inst.cond != COND_ALWAYS) + { + first_error (_(BAD_COND)); + return FAIL; + } + if (inst.uncond_value != -1) + inst.instruction |= inst.uncond_value << 28; + } + + if ((check & NEON_CHECK_ARCH) + && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) + { + first_error (_(BAD_FPU)); + return FAIL; + } + + return SUCCESS; +} + +static void +do_neon_addsub_if_i (void) +{ + if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) + return; + + if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + return; + + /* The "untyped" case can't happen. Do this to stop the "U" bit being + affected if we specify unsigned args. */ + neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); +} + +/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the + result to be: + V A,B (A is operand 0, B is operand 2) + to mean: + V A,B,A + not: + V A,B,B + so handle that case specially. */ + +static void +neon_exchange_operands (void) +{ + void *scratch = alloca (sizeof (inst.operands[0])); + if (inst.operands[1].present) + { + /* Swap operands[1] and operands[2]. */ + memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); + inst.operands[1] = inst.operands[2]; + memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); + } + else + { + inst.operands[1] = inst.operands[2]; + inst.operands[2] = inst.operands[0]; + } +} + +static void +neon_compare (unsigned regtypes, unsigned immtypes, int invert) +{ + if (inst.operands[2].isreg) + { + if (invert) + neon_exchange_operands (); + neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); + } + else + { + enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK | N_SIZ, immtypes | N_KEY); + + inst.instruction = NEON_ENC_IMMED (inst.instruction); + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= neon_quad (rs) << 6; + inst.instruction |= (et.type == NT_float) << 10; + inst.instruction |= neon_logbits (et.size) << 18; + + inst.instruction = neon_dp_fixup (inst.instruction); + } +} + +static void +do_neon_cmp (void) +{ + neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); +} + +static void +do_neon_cmp_inv (void) +{ + neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); +} + +static void +do_neon_ceq (void) +{ + neon_compare (N_IF_32, N_IF_32, FALSE); +} + +/* For multiply instructions, we have the possibility of 16-bit or 32-bit + scalars, which are encoded in 5 bits, M : Rm. + For 16-bit scalars, the register is encoded in Rm[2:0] and the index in + M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the + index in M. */ + +static unsigned +neon_scalar_for_mul (unsigned scalar, unsigned elsize) +{ + unsigned regno = NEON_SCALAR_REG (scalar); + unsigned elno = NEON_SCALAR_INDEX (scalar); + + switch (elsize) + { + case 16: + if (regno > 7 || elno > 3) + goto bad_scalar; + return regno | (elno << 3); + + case 32: + if (regno > 15 || elno > 1) + goto bad_scalar; + return regno | (elno << 4); + + default: + bad_scalar: + first_error (_("scalar out of range for multiply instruction")); + } + + return 0; +} + +/* Encode multiply / multiply-accumulate scalar instructions. */ + +static void +neon_mul_mac (struct neon_type_el et, int ubit) +{ + unsigned scalar; + + /* Give a more helpful error message if we have an invalid type. */ + if (et.type == NT_invtype) + return; + + scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= LOW4 (scalar); + inst.instruction |= HI1 (scalar) << 5; + inst.instruction |= (et.type == NT_float) << 8; + inst.instruction |= neon_logbits (et.size) << 20; + inst.instruction |= (ubit != 0) << 24; + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +static void +do_neon_mac_maybe_scalar (void) +{ + if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) + return; + + if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + return; + + if (inst.operands[2].isscalar) + { + enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); + inst.instruction = NEON_ENC_SCALAR (inst.instruction); + neon_mul_mac (et, neon_quad (rs)); + } + else + { + /* The "untyped" case can't happen. Do this to stop the "U" bit being + affected if we specify unsigned args. */ + neon_dyadic_misc (NT_untyped, N_IF_32, 0); + } +} + +static void +do_neon_tst (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); + neon_three_same (neon_quad (rs), 0, et.size); +} + +/* VMUL with 3 registers allows the P8 type. The scalar version supports the + same types as the MAC equivalents. The polynomial type for this instruction + is encoded the same as the integer type. */ + +static void +do_neon_mul (void) +{ + if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) + return; + + if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + return; + + if (inst.operands[2].isscalar) + do_neon_mac_maybe_scalar (); + else + neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); +} + +static void +do_neon_qdmulh (void) +{ + if (inst.operands[2].isscalar) + { + enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); + inst.instruction = NEON_ENC_SCALAR (inst.instruction); + neon_mul_mac (et, neon_quad (rs)); + } + else + { + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + /* The U bit (rounding) comes from bit mask. */ + neon_three_same (neon_quad (rs), 0, et.size); + } +} + +static void +do_neon_fcmp_absolute (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); + /* Size field comes from bit mask. */ + neon_three_same (neon_quad (rs), 1, -1); +} + +static void +do_neon_fcmp_absolute_inv (void) +{ + neon_exchange_operands (); + do_neon_fcmp_absolute (); +} + +static void +do_neon_step (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); + neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); + neon_three_same (neon_quad (rs), 0, -1); +} + +static void +do_neon_abs_neg (void) +{ + enum neon_shape rs; + struct neon_type_el et; + + if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) + return; + + if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + return; + + rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); + + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= neon_quad (rs) << 6; + inst.instruction |= (et.type == NT_float) << 10; + inst.instruction |= neon_logbits (et.size) << 18; + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +static void +do_neon_sli (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); + int imm = inst.operands[2].imm; + constraint (imm < 0 || (unsigned)imm >= et.size, + _("immediate out of range for insert")); + neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); +} + +static void +do_neon_sri (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); + int imm = inst.operands[2].imm; + constraint (imm < 1 || (unsigned)imm > et.size, + _("immediate out of range for insert")); + neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); +} + +static void +do_neon_qshlu_imm (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); + int imm = inst.operands[2].imm; + constraint (imm < 0 || (unsigned)imm >= et.size, + _("immediate out of range for shift")); + /* Only encodes the 'U present' variant of the instruction. + In this case, signed types have OP (bit 8) set to 0. + Unsigned types have OP set to 1. */ + inst.instruction |= (et.type == NT_unsigned) << 8; + /* The rest of the bits are the same as other immediate shifts. */ + neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); +} + +static void +do_neon_qmovn (void) +{ + struct neon_type_el et = neon_check_type (2, NS_DQ, + N_EQK | N_HLF, N_SU_16_64 | N_KEY); + /* Saturating move where operands can be signed or unsigned, and the + destination has the same signedness. */ + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + if (et.type == NT_unsigned) + inst.instruction |= 0xc0; + else + inst.instruction |= 0x80; + neon_two_same (0, 1, et.size / 2); +} + +static void +do_neon_qmovun (void) +{ + struct neon_type_el et = neon_check_type (2, NS_DQ, + N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); + /* Saturating move with unsigned results. Operands must be signed. */ + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + neon_two_same (0, 1, et.size / 2); +} + +static void +do_neon_rshift_sat_narrow (void) +{ + /* FIXME: Types for narrowing. If operands are signed, results can be signed + or unsigned. If operands are unsigned, results must also be unsigned. */ + struct neon_type_el et = neon_check_type (2, NS_DQI, + N_EQK | N_HLF, N_SU_16_64 | N_KEY); + int imm = inst.operands[2].imm; + /* This gets the bounds check, size encoding and immediate bits calculation + right. */ + et.size /= 2; + + /* VQ{R}SHRN.I
, , #0 is a synonym for + VQMOVN.I
, . */ + if (imm == 0) + { + inst.operands[2].present = 0; + inst.instruction = N_MNEM_vqmovn; + do_neon_qmovn (); + return; + } + + constraint (imm < 1 || (unsigned)imm > et.size, + _("immediate out of range")); + neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); +} + +static void +do_neon_rshift_sat_narrow_u (void) +{ + /* FIXME: Types for narrowing. If operands are signed, results can be signed + or unsigned. If operands are unsigned, results must also be unsigned. */ + struct neon_type_el et = neon_check_type (2, NS_DQI, + N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); + int imm = inst.operands[2].imm; + /* This gets the bounds check, size encoding and immediate bits calculation + right. */ + et.size /= 2; + + /* VQSHRUN.I
, , #0 is a synonym for + VQMOVUN.I
, . */ + if (imm == 0) + { + inst.operands[2].present = 0; + inst.instruction = N_MNEM_vqmovun; + do_neon_qmovun (); + return; + } + + constraint (imm < 1 || (unsigned)imm > et.size, + _("immediate out of range")); + /* FIXME: The manual is kind of unclear about what value U should have in + VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it + must be 1. */ + neon_imm_shift (TRUE, 1, 0, et, et.size - imm); +} + +static void +do_neon_movn (void) +{ + struct neon_type_el et = neon_check_type (2, NS_DQ, + N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + neon_two_same (0, 1, et.size / 2); +} + +static void +do_neon_rshift_narrow (void) +{ + struct neon_type_el et = neon_check_type (2, NS_DQI, + N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); + int imm = inst.operands[2].imm; + /* This gets the bounds check, size encoding and immediate bits calculation + right. */ + et.size /= 2; + + /* If immediate is zero then we are a pseudo-instruction for + VMOVN.I
, */ + if (imm == 0) + { + inst.operands[2].present = 0; + inst.instruction = N_MNEM_vmovn; + do_neon_movn (); + return; + } + + constraint (imm < 1 || (unsigned)imm > et.size, + _("immediate out of range for narrowing operation")); + neon_imm_shift (FALSE, 0, 0, et, et.size - imm); +} + +static void +do_neon_shll (void) +{ + /* FIXME: Type checking when lengthening. */ + struct neon_type_el et = neon_check_type (2, NS_QDI, + N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); + unsigned imm = inst.operands[2].imm; + + if (imm == et.size) + { + /* Maximum shift variant. */ + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= neon_logbits (et.size) << 18; + + inst.instruction = neon_dp_fixup (inst.instruction); + } + else + { + /* A more-specific type check for non-max versions. */ + et = neon_check_type (2, NS_QDI, + N_EQK | N_DBL, N_SU_32 | N_KEY); + inst.instruction = NEON_ENC_IMMED (inst.instruction); + neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); + } +} + +/* Check the various types for the VCVT instruction, and return which version + the current instruction is. */ + +static int +neon_cvt_flavour (enum neon_shape rs) +{ +#define CVT_VAR(C,X,Y) \ + et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ + if (et.type != NT_invtype) \ + { \ + inst.error = NULL; \ + return (C); \ + } + struct neon_type_el et; + unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF + || rs == NS_FF) ? N_VFP : 0; + /* The instruction versions which take an immediate take one register + argument, which is extended to the width of the full register. Thus the + "source" and "destination" registers must have the same width. Hack that + here by making the size equal to the key (wider, in this case) operand. */ + unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; + + CVT_VAR (0, N_S32, N_F32); + CVT_VAR (1, N_U32, N_F32); + CVT_VAR (2, N_F32, N_S32); + CVT_VAR (3, N_F32, N_U32); + /* Half-precision conversions. */ + CVT_VAR (4, N_F32, N_F16); + CVT_VAR (5, N_F16, N_F32); + + whole_reg = N_VFP; + + /* VFP instructions. */ + CVT_VAR (6, N_F32, N_F64); + CVT_VAR (7, N_F64, N_F32); + CVT_VAR (8, N_S32, N_F64 | key); + CVT_VAR (9, N_U32, N_F64 | key); + CVT_VAR (10, N_F64 | key, N_S32); + CVT_VAR (11, N_F64 | key, N_U32); + /* VFP instructions with bitshift. */ + CVT_VAR (12, N_F32 | key, N_S16); + CVT_VAR (13, N_F32 | key, N_U16); + CVT_VAR (14, N_F64 | key, N_S16); + CVT_VAR (15, N_F64 | key, N_U16); + CVT_VAR (16, N_S16, N_F32 | key); + CVT_VAR (17, N_U16, N_F32 | key); + CVT_VAR (18, N_S16, N_F64 | key); + CVT_VAR (19, N_U16, N_F64 | key); + + return -1; +#undef CVT_VAR +} + +/* Neon-syntax VFP conversions. */ + +static void +do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) +{ + const char *opname = 0; + + if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) + { + /* Conversions with immediate bitshift. */ + const char *enc[] = + { + "ftosls", + "ftouls", + "fsltos", + "fultos", + NULL, + NULL, + NULL, + NULL, + "ftosld", + "ftould", + "fsltod", + "fultod", + "fshtos", + "fuhtos", + "fshtod", + "fuhtod", + "ftoshs", + "ftouhs", + "ftoshd", + "ftouhd" + }; + + if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) + { + opname = enc[flavour]; + constraint (inst.operands[0].reg != inst.operands[1].reg, + _("operands 0 and 1 must be the same register")); + inst.operands[1] = inst.operands[2]; + memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); + } + } + else + { + /* Conversions without bitshift. */ + const char *enc[] = + { + "ftosis", + "ftouis", + "fsitos", + "fuitos", + "NULL", + "NULL", + "fcvtsd", + "fcvtds", + "ftosid", + "ftouid", + "fsitod", + "fuitod" + }; + + if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) + opname = enc[flavour]; + } + + if (opname) + do_vfp_nsyn_opcode (opname); +} + +static void +do_vfp_nsyn_cvtz (void) +{ + enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); + int flavour = neon_cvt_flavour (rs); + const char *enc[] = + { + "ftosizs", + "ftouizs", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "ftosizd", + "ftouizd" + }; + + if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) + do_vfp_nsyn_opcode (enc[flavour]); +} + +static void +do_neon_cvt (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, + NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); + int flavour = neon_cvt_flavour (rs); + + /* VFP rather than Neon conversions. */ + if (flavour >= 6) + { + do_vfp_nsyn_cvt (rs, flavour); + return; + } + + switch (rs) + { + case NS_DDI: + case NS_QQI: + { + unsigned immbits; + unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; + + if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + return; + + /* Fixed-point conversion with #0 immediate is encoded as an + integer conversion. */ + if (inst.operands[2].present && inst.operands[2].imm == 0) + goto int_encode; + immbits = 32 - inst.operands[2].imm; + inst.instruction = NEON_ENC_IMMED (inst.instruction); + if (flavour != -1) + inst.instruction |= enctab[flavour]; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= neon_quad (rs) << 6; + inst.instruction |= 1 << 21; + inst.instruction |= immbits << 16; + + inst.instruction = neon_dp_fixup (inst.instruction); + } + break; + + case NS_DD: + case NS_QQ: + int_encode: + { + unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; + + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + + if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + return; + + if (flavour != -1) + inst.instruction |= enctab[flavour]; + + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= neon_quad (rs) << 6; + inst.instruction |= 2 << 18; + + inst.instruction = neon_dp_fixup (inst.instruction); + } + break; + + /* Half-precision conversions for Advanced SIMD -- neon. */ + case NS_QD: + case NS_DQ: + + if ((rs == NS_DQ) + && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) + { + as_bad (_("operand size must match register width")); + break; + } + + if ((rs == NS_QD) + && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) + { + as_bad (_("operand size must match register width")); + break; + } + + if (rs == NS_DQ) + inst.instruction = 0x3b60600; + else + inst.instruction = 0x3b60700; + + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction = neon_dp_fixup (inst.instruction); + break; + + default: + /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ + do_vfp_nsyn_cvt (rs, flavour); + } +} + +static void +do_neon_cvtb (void) +{ + inst.instruction = 0xeb20a40; + + /* The sizes are attached to the mnemonic. */ + if (inst.vectype.el[0].type != NT_invtype + && inst.vectype.el[0].size == 16) + inst.instruction |= 0x00010000; + + /* Programmer's syntax: the sizes are attached to the operands. */ + else if (inst.operands[0].vectype.type != NT_invtype + && inst.operands[0].vectype.size == 16) + inst.instruction |= 0x00010000; + + encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); + encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); + do_vfp_cond_or_thumb (); +} + + +static void +do_neon_cvtt (void) +{ + do_neon_cvtb (); + inst.instruction |= 0x80; +} + +static void +neon_move_immediate (void) +{ + enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); + unsigned immlo, immhi = 0, immbits; + int op, cmode, float_p; + + constraint (et.type == NT_invtype, + _("operand size must be specified for immediate VMOV")); + + /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ + op = (inst.instruction & (1 << 5)) != 0; + + immlo = inst.operands[1].imm; + if (inst.operands[1].regisimm) + immhi = inst.operands[1].reg; + + constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, + _("immediate has bits set outside the operand size")); + + float_p = inst.operands[1].immisfloat; + + if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, + et.size, et.type)) == FAIL) + { + /* Invert relevant bits only. */ + neon_invert_size (&immlo, &immhi, et.size); + /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable + with one or the other; those cases are caught by + neon_cmode_for_move_imm. */ + op = !op; + if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, + &op, et.size, et.type)) == FAIL) + { + first_error (_("immediate out of range")); + return; + } + } + + inst.instruction &= ~(1 << 5); + inst.instruction |= op << 5; + + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= neon_quad (rs) << 6; + inst.instruction |= cmode << 8; + + neon_write_immbits (immbits); +} + +static void +do_neon_mvn (void) +{ + if (inst.operands[1].isreg) + { + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= neon_quad (rs) << 6; + } + else + { + inst.instruction = NEON_ENC_IMMED (inst.instruction); + neon_move_immediate (); + } + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +/* Encode instructions of form: + + |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| + | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ + +static void +neon_mixed_length (struct neon_type_el et, unsigned size) +{ + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= LOW4 (inst.operands[2].reg); + inst.instruction |= HI1 (inst.operands[2].reg) << 5; + inst.instruction |= (et.type == NT_unsigned) << 24; + inst.instruction |= neon_logbits (size) << 20; + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +static void +do_neon_dyadic_long (void) +{ + /* FIXME: Type checking for lengthening op. */ + struct neon_type_el et = neon_check_type (3, NS_QDD, + N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); + neon_mixed_length (et, et.size); +} + +static void +do_neon_abal (void) +{ + struct neon_type_el et = neon_check_type (3, NS_QDD, + N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); + neon_mixed_length (et, et.size); +} + +static void +neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) +{ + if (inst.operands[2].isscalar) + { + struct neon_type_el et = neon_check_type (3, NS_QDS, + N_EQK | N_DBL, N_EQK, regtypes | N_KEY); + inst.instruction = NEON_ENC_SCALAR (inst.instruction); + neon_mul_mac (et, et.type == NT_unsigned); + } + else + { + struct neon_type_el et = neon_check_type (3, NS_QDD, + N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + neon_mixed_length (et, et.size); + } +} + +static void +do_neon_mac_maybe_scalar_long (void) +{ + neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); +} + +static void +do_neon_dyadic_wide (void) +{ + struct neon_type_el et = neon_check_type (3, NS_QQD, + N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); + neon_mixed_length (et, et.size); +} + +static void +do_neon_dyadic_narrow (void) +{ + struct neon_type_el et = neon_check_type (3, NS_QDD, + N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); + /* Operand sign is unimportant, and the U bit is part of the opcode, + so force the operand type to integer. */ + et.type = NT_integer; + neon_mixed_length (et, et.size / 2); +} + +static void +do_neon_mul_sat_scalar_long (void) +{ + neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); +} + +static void +do_neon_vmull (void) +{ + if (inst.operands[2].isscalar) + do_neon_mac_maybe_scalar_long (); + else + { + struct neon_type_el et = neon_check_type (3, NS_QDD, + N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); + if (et.type == NT_poly) + inst.instruction = NEON_ENC_POLY (inst.instruction); + else + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + /* For polynomial encoding, size field must be 0b00 and the U bit must be + zero. Should be OK as-is. */ + neon_mixed_length (et, et.size); + } +} + +static void +do_neon_ext (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); + unsigned imm = (inst.operands[3].imm * et.size) / 8; + + constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), + _("shift out of range")); + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= LOW4 (inst.operands[2].reg); + inst.instruction |= HI1 (inst.operands[2].reg) << 5; + inst.instruction |= neon_quad (rs) << 6; + inst.instruction |= imm << 8; + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +static void +do_neon_rev (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_8 | N_16 | N_32 | N_KEY); + unsigned op = (inst.instruction >> 7) & 3; + /* N (width of reversed regions) is encoded as part of the bitmask. We + extract it here to check the elements to be reversed are smaller. + Otherwise we'd get a reserved instruction. */ + unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; + gas_assert (elsize != 0); + constraint (et.size >= elsize, + _("elements must be smaller than reversal region")); + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_dup (void) +{ + if (inst.operands[1].isscalar) + { + enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_8 | N_16 | N_32 | N_KEY); + unsigned sizebits = et.size >> 3; + unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); + int logsize = neon_logbits (et.size); + unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; + + if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) + return; + + inst.instruction = NEON_ENC_SCALAR (inst.instruction); + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (dm); + inst.instruction |= HI1 (dm) << 5; + inst.instruction |= neon_quad (rs) << 6; + inst.instruction |= x << 17; + inst.instruction |= sizebits << 16; + + inst.instruction = neon_dp_fixup (inst.instruction); + } + else + { + enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_8 | N_16 | N_32 | N_KEY, N_EQK); + /* Duplicate ARM register to lanes of vector. */ + inst.instruction = NEON_ENC_ARMREG (inst.instruction); + switch (et.size) + { + case 8: inst.instruction |= 0x400000; break; + case 16: inst.instruction |= 0x000020; break; + case 32: inst.instruction |= 0x000000; break; + default: break; + } + inst.instruction |= LOW4 (inst.operands[1].reg) << 12; + inst.instruction |= LOW4 (inst.operands[0].reg) << 16; + inst.instruction |= HI1 (inst.operands[0].reg) << 7; + inst.instruction |= neon_quad (rs) << 21; + /* The encoding for this instruction is identical for the ARM and Thumb + variants, except for the condition field. */ + do_vfp_cond_or_thumb (); + } +} + +/* VMOV has particularly many variations. It can be one of: + 0. VMOV , + 1. VMOV
, + (Register operations, which are VORR with Rm = Rn.) + 2. VMOV.
, # + 3. VMOV.
, # + (Immediate loads.) + 4. VMOV. , + (ARM register to scalar.) + 5. VMOV , , + (Two ARM registers to vector.) + 6. VMOV.
, + (Scalar to ARM register.) + 7. VMOV , , + (Vector to two ARM registers.) + 8. VMOV.F32 , + 9. VMOV.F64
, + (VFP register moves.) + 10. VMOV.F32 , #imm + 11. VMOV.F64
, #imm + (VFP float immediate load.) + 12. VMOV , + (VFP single to ARM reg.) + 13. VMOV , + (ARM reg to VFP single.) + 14. VMOV , , , + (Two ARM regs to two VFP singles.) + 15. VMOV , , , + (Two VFP singles to two ARM regs.) + + These cases can be disambiguated using neon_select_shape, except cases 1/9 + and 3/11 which depend on the operand type too. + + All the encoded bits are hardcoded by this function. + + Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). + Cases 5, 7 may be used with VFPv2 and above. + + FIXME: Some of the checking may be a bit sloppy (in a couple of cases you + can specify a type where it doesn't make sense to, and is ignored). */ + +static void +do_neon_mov (void) +{ + enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, + NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, + NS_NULL); + struct neon_type_el et; + const char *ldconst = 0; + + switch (rs) + { + case NS_DD: /* case 1/9. */ + et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); + /* It is not an error here if no type is given. */ + inst.error = NULL; + if (et.type == NT_float && et.size == 64) + { + do_vfp_nsyn_opcode ("fcpyd"); + break; + } + /* fall through. */ + + case NS_QQ: /* case 0/1. */ + { + if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + return; + /* The architecture manual I have doesn't explicitly state which + value the U bit should have for register->register moves, but + the equivalent VORR instruction has U = 0, so do that. */ + inst.instruction = 0x0200110; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg); + inst.instruction |= HI1 (inst.operands[1].reg) << 5; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= neon_quad (rs) << 6; + + inst.instruction = neon_dp_fixup (inst.instruction); + } + break; + + case NS_DI: /* case 3/11. */ + et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); + inst.error = NULL; + if (et.type == NT_float && et.size == 64) + { + /* case 11 (fconstd). */ + ldconst = "fconstd"; + goto encode_fconstd; + } + /* fall through. */ + + case NS_QI: /* case 2/3. */ + if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) + return; + inst.instruction = 0x0800010; + neon_move_immediate (); + inst.instruction = neon_dp_fixup (inst.instruction); + break; + + case NS_SR: /* case 4. */ + { + unsigned bcdebits = 0; + struct neon_type_el et = neon_check_type (2, NS_NULL, + N_8 | N_16 | N_32 | N_KEY, N_EQK); + int logsize = neon_logbits (et.size); + unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); + unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); + + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), + _(BAD_FPU)); + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) + && et.size != 32, _(BAD_FPU)); + constraint (et.type == NT_invtype, _("bad type for scalar")); + constraint (x >= 64 / et.size, _("scalar index out of range")); + + switch (et.size) + { + case 8: bcdebits = 0x8; break; + case 16: bcdebits = 0x1; break; + case 32: bcdebits = 0x0; break; + default: ; + } + + bcdebits |= x << logsize; + + inst.instruction = 0xe000b10; + do_vfp_cond_or_thumb (); + inst.instruction |= LOW4 (dn) << 16; + inst.instruction |= HI1 (dn) << 7; + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= (bcdebits & 3) << 5; + inst.instruction |= (bcdebits >> 2) << 21; + } + break; + + case NS_DRR: /* case 5 (fmdrr). */ + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), + _(BAD_FPU)); + + inst.instruction = 0xc400b10; + do_vfp_cond_or_thumb (); + inst.instruction |= LOW4 (inst.operands[0].reg); + inst.instruction |= HI1 (inst.operands[0].reg) << 5; + inst.instruction |= inst.operands[1].reg << 12; + inst.instruction |= inst.operands[2].reg << 16; + break; + + case NS_RS: /* case 6. */ + { + struct neon_type_el et = neon_check_type (2, NS_NULL, + N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); + unsigned logsize = neon_logbits (et.size); + unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); + unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); + unsigned abcdebits = 0; + + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), + _(BAD_FPU)); + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) + && et.size != 32, _(BAD_FPU)); + constraint (et.type == NT_invtype, _("bad type for scalar")); + constraint (x >= 64 / et.size, _("scalar index out of range")); + + switch (et.size) + { + case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; + case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; + case 32: abcdebits = 0x00; break; + default: ; + } + + abcdebits |= x << logsize; + inst.instruction = 0xe100b10; + do_vfp_cond_or_thumb (); + inst.instruction |= LOW4 (dn) << 16; + inst.instruction |= HI1 (dn) << 7; + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= (abcdebits & 3) << 5; + inst.instruction |= (abcdebits >> 2) << 21; + } + break; + + case NS_RRD: /* case 7 (fmrrd). */ + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), + _(BAD_FPU)); + + inst.instruction = 0xc500b10; + do_vfp_cond_or_thumb (); + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= inst.operands[1].reg << 16; + inst.instruction |= LOW4 (inst.operands[2].reg); + inst.instruction |= HI1 (inst.operands[2].reg) << 5; + break; + + case NS_FF: /* case 8 (fcpys). */ + do_vfp_nsyn_opcode ("fcpys"); + break; + + case NS_FI: /* case 10 (fconsts). */ + ldconst = "fconsts"; + encode_fconstd: + if (is_quarter_float (inst.operands[1].imm)) + { + inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); + do_vfp_nsyn_opcode (ldconst); + } + else + first_error (_("immediate out of range")); + break; + + case NS_RF: /* case 12 (fmrs). */ + do_vfp_nsyn_opcode ("fmrs"); + break; + + case NS_FR: /* case 13 (fmsr). */ + do_vfp_nsyn_opcode ("fmsr"); + break; + + /* The encoders for the fmrrs and fmsrr instructions expect three operands + (one of which is a list), but we have parsed four. Do some fiddling to + make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 + expect. */ + case NS_RRFF: /* case 14 (fmrrs). */ + constraint (inst.operands[3].reg != inst.operands[2].reg + 1, + _("VFP registers must be adjacent")); + inst.operands[2].imm = 2; + memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); + do_vfp_nsyn_opcode ("fmrrs"); + break; + + case NS_FFRR: /* case 15 (fmsrr). */ + constraint (inst.operands[1].reg != inst.operands[0].reg + 1, + _("VFP registers must be adjacent")); + inst.operands[1] = inst.operands[2]; + inst.operands[2] = inst.operands[3]; + inst.operands[0].imm = 2; + memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); + do_vfp_nsyn_opcode ("fmsrr"); + break; + + default: + abort (); + } +} + +static void +do_neon_rshift_round_imm (void) +{ + enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); + int imm = inst.operands[2].imm; + + /* imm == 0 case is encoded as VMOV for V{R}SHR. */ + if (imm == 0) + { + inst.operands[2].present = 0; + do_neon_mov (); + return; + } + + constraint (imm < 1 || (unsigned)imm > et.size, + _("immediate out of range for shift")); + neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, + et.size - imm); +} + +static void +do_neon_movl (void) +{ + struct neon_type_el et = neon_check_type (2, NS_QD, + N_EQK | N_DBL, N_SU_32 | N_KEY); + unsigned sizebits = et.size >> 3; + inst.instruction |= sizebits << 19; + neon_two_same (0, et.type == NT_unsigned, -1); +} + +static void +do_neon_trn (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_8 | N_16 | N_32 | N_KEY); + inst.instruction = NEON_ENC_INTEGER (inst.instruction); + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_zip_uzp (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_8 | N_16 | N_32 | N_KEY); + if (rs == NS_DD && et.size == 32) + { + /* Special case: encode as VTRN.32
, . */ + inst.instruction = N_MNEM_vtrn; + do_neon_trn (); + return; + } + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_sat_abs_neg (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_pair_long (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); + /* Unsigned is encoded in OP field (bit 7) for these instruction. */ + inst.instruction |= (et.type == NT_unsigned) << 7; + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_recip_est (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); + inst.instruction |= (et.type == NT_float) << 8; + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_cls (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_clz (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_cnt (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + struct neon_type_el et = neon_check_type (2, rs, + N_EQK | N_INT, N_8 | N_KEY); + neon_two_same (neon_quad (rs), 1, et.size); +} + +static void +do_neon_swp (void) +{ + enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); + neon_two_same (neon_quad (rs), 1, -1); +} + +static void +do_neon_tbl_tbx (void) +{ + unsigned listlenbits; + neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); + + if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) + { + first_error (_("bad list length for table lookup")); + return; + } + + listlenbits = inst.operands[1].imm - 1; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= LOW4 (inst.operands[2].reg); + inst.instruction |= HI1 (inst.operands[2].reg) << 5; + inst.instruction |= listlenbits << 8; + + inst.instruction = neon_dp_fixup (inst.instruction); +} + +static void +do_neon_ldm_stm (void) +{ + /* P, U and L bits are part of bitmask. */ + int is_dbmode = (inst.instruction & (1 << 24)) != 0; + unsigned offsetbits = inst.operands[1].imm * 2; + + if (inst.operands[1].issingle) + { + do_vfp_nsyn_ldm_stm (is_dbmode); + return; + } + + constraint (is_dbmode && !inst.operands[0].writeback, + _("writeback (!) must be used for VLDMDB and VSTMDB")); + + constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, + _("register list must contain at least 1 and at most 16 " + "registers")); + + inst.instruction |= inst.operands[0].reg << 16; + inst.instruction |= inst.operands[0].writeback << 21; + inst.instruction |= LOW4 (inst.operands[1].reg) << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 22; + + inst.instruction |= offsetbits; + + do_vfp_cond_or_thumb (); +} + +static void +do_neon_ldr_str (void) +{ + int is_ldr = (inst.instruction & (1 << 20)) != 0; + + if (inst.operands[0].issingle) + { + if (is_ldr) + do_vfp_nsyn_opcode ("flds"); + else + do_vfp_nsyn_opcode ("fsts"); + } + else + { + if (is_ldr) + do_vfp_nsyn_opcode ("fldd"); + else + do_vfp_nsyn_opcode ("fstd"); + } +} + +/* "interleave" version also handles non-interleaving register VLD1/VST1 + instructions. */ + +static void +do_neon_ld_st_interleave (void) +{ + struct neon_type_el et = neon_check_type (1, NS_NULL, + N_8 | N_16 | N_32 | N_64); + unsigned alignbits = 0; + unsigned idx; + /* The bits in this table go: + 0: register stride of one (0) or two (1) + 1,2: register list length, minus one (1, 2, 3, 4). + 3,4: in instruction type, minus one (VLD / VST). + We use -1 for invalid entries. */ + const int typetable[] = + { + 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ + -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ + -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ + -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ + }; + int typebits; + + if (et.type == NT_invtype) + return; + + if (inst.operands[1].immisalign) + switch (inst.operands[1].imm >> 8) + { + case 64: alignbits = 1; break; + case 128: + if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) + goto bad_alignment; + alignbits = 2; + break; + case 256: + if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) + goto bad_alignment; + alignbits = 3; + break; + default: + bad_alignment: + first_error (_("bad alignment")); + return; + } + + inst.instruction |= alignbits << 4; + inst.instruction |= neon_logbits (et.size) << 6; + + /* Bits [4:6] of the immediate in a list specifier encode register stride + (minus 1) in bit 4, and list length in bits [5:6]. We put the of + VLD/VST in bits [9:8] of the initial bitmask. Suck it out here, look + up the right value for "type" in a table based on this value and the given + list style, then stick it back. */ + idx = ((inst.operands[0].imm >> 4) & 7) + | (((inst.instruction >> 8) & 3) << 3); + + typebits = typetable[idx]; + + constraint (typebits == -1, _("bad list type for instruction")); + + inst.instruction &= ~0xf00; + inst.instruction |= typebits << 8; +} + +/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. + *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 + otherwise. The variable arguments are a list of pairs of legal (size, align) + values, terminated with -1. */ + +static int +neon_alignment_bit (int size, int align, int *do_align, ...) +{ + va_list ap; + int result = FAIL, thissize, thisalign; + + if (!inst.operands[1].immisalign) + { + *do_align = 0; + return SUCCESS; + } + + va_start (ap, do_align); + + do + { + thissize = va_arg (ap, int); + if (thissize == -1) + break; + thisalign = va_arg (ap, int); + + if (size == thissize && align == thisalign) + result = SUCCESS; + } + while (result != SUCCESS); + + va_end (ap); + + if (result == SUCCESS) + *do_align = 1; + else + first_error (_("unsupported alignment for instruction")); + + return result; +} + +static void +do_neon_ld_st_lane (void) +{ + struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); + int align_good, do_align = 0; + int logsize = neon_logbits (et.size); + int align = inst.operands[1].imm >> 8; + int n = (inst.instruction >> 8) & 3; + int max_el = 64 / et.size; + + if (et.type == NT_invtype) + return; + + constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, + _("bad list length")); + constraint (NEON_LANE (inst.operands[0].imm) >= max_el, + _("scalar index out of range")); + constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 + && et.size == 8, + _("stride of 2 unavailable when element size is 8")); + + switch (n) + { + case 0: /* VLD1 / VST1. */ + align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, + 32, 32, -1); + if (align_good == FAIL) + return; + if (do_align) + { + unsigned alignbits = 0; + switch (et.size) + { + case 16: alignbits = 0x1; break; + case 32: alignbits = 0x3; break; + default: ; + } + inst.instruction |= alignbits << 4; + } + break; + + case 1: /* VLD2 / VST2. */ + align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, + 32, 64, -1); + if (align_good == FAIL) + return; + if (do_align) + inst.instruction |= 1 << 4; + break; + + case 2: /* VLD3 / VST3. */ + constraint (inst.operands[1].immisalign, + _("can't use alignment with this instruction")); + break; + + case 3: /* VLD4 / VST4. */ + align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, + 16, 64, 32, 64, 32, 128, -1); + if (align_good == FAIL) + return; + if (do_align) + { + unsigned alignbits = 0; + switch (et.size) + { + case 8: alignbits = 0x1; break; + case 16: alignbits = 0x1; break; + case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; + default: ; + } + inst.instruction |= alignbits << 4; + } + break; + + default: ; + } + + /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ + if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) + inst.instruction |= 1 << (4 + logsize); + + inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); + inst.instruction |= logsize << 10; +} + +/* Encode single n-element structure to all lanes VLD instructions. */ + +static void +do_neon_ld_dup (void) +{ + struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); + int align_good, do_align = 0; + + if (et.type == NT_invtype) + return; + + switch ((inst.instruction >> 8) & 3) + { + case 0: /* VLD1. */ + gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); + align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, + &do_align, 16, 16, 32, 32, -1); + if (align_good == FAIL) + return; + switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) + { + case 1: break; + case 2: inst.instruction |= 1 << 5; break; + default: first_error (_("bad list length")); return; + } + inst.instruction |= neon_logbits (et.size) << 6; + break; + + case 1: /* VLD2. */ + align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, + &do_align, 8, 16, 16, 32, 32, 64, -1); + if (align_good == FAIL) + return; + constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, + _("bad list length")); + if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) + inst.instruction |= 1 << 5; + inst.instruction |= neon_logbits (et.size) << 6; + break; + + case 2: /* VLD3. */ + constraint (inst.operands[1].immisalign, + _("can't use alignment with this instruction")); + constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, + _("bad list length")); + if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) + inst.instruction |= 1 << 5; + inst.instruction |= neon_logbits (et.size) << 6; + break; + + case 3: /* VLD4. */ + { + int align = inst.operands[1].imm >> 8; + align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, + 16, 64, 32, 64, 32, 128, -1); + if (align_good == FAIL) + return; + constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, + _("bad list length")); + if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) + inst.instruction |= 1 << 5; + if (et.size == 32 && align == 128) + inst.instruction |= 0x3 << 6; + else + inst.instruction |= neon_logbits (et.size) << 6; + } + break; + + default: ; + } + + inst.instruction |= do_align << 4; +} + +/* Disambiguate VLD and VST instructions, and fill in common bits (those + apart from bits [11:4]. */ + +static void +do_neon_ldx_stx (void) +{ + switch (NEON_LANE (inst.operands[0].imm)) + { + case NEON_INTERLEAVE_LANES: + inst.instruction = NEON_ENC_INTERLV (inst.instruction); + do_neon_ld_st_interleave (); + break; + + case NEON_ALL_LANES: + inst.instruction = NEON_ENC_DUP (inst.instruction); + do_neon_ld_dup (); + break; + + default: + inst.instruction = NEON_ENC_LANE (inst.instruction); + do_neon_ld_st_lane (); + } + + /* L bit comes from bit mask. */ + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= inst.operands[1].reg << 16; + + if (inst.operands[1].postind) + { + int postreg = inst.operands[1].imm & 0xf; + constraint (!inst.operands[1].immisreg, + _("post-index must be a register")); + constraint (postreg == 0xd || postreg == 0xf, + _("bad register for post-index")); + inst.instruction |= postreg; + } + else if (inst.operands[1].writeback) + { + inst.instruction |= 0xd; + } + else + inst.instruction |= 0xf; + + if (thumb_mode) + inst.instruction |= 0xf9000000; + else + inst.instruction |= 0xf4000000; +} + +/* Overall per-instruction processing. */ + +/* We need to be able to fix up arbitrary expressions in some statements. + This is so that we can handle symbols that are an arbitrary distance from + the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), + which returns part of an address in a form which will be valid for + a data instruction. We do this by pushing the expression into a symbol + in the expr_section, and creating a fix for that. */ + +static void +fix_new_arm (fragS * frag, + int where, + short int size, + expressionS * exp, + int pc_rel, + int reloc) +{ + fixS * new_fix; + + switch (exp->X_op) + { + case O_constant: + case O_symbol: + case O_add: + case O_subtract: + new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); + break; + + default: + new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, + pc_rel, reloc); + break; + } + + /* Mark whether the fix is to a THUMB instruction, or an ARM + instruction. */ + new_fix->tc_fix_data = thumb_mode; +} + +/* Create a frg for an instruction requiring relaxation. */ +static void +output_relax_insn (void) +{ + char * to; + symbolS *sym; + int offset; + + /* The size of the instruction is unknown, so tie the debug info to the + start of the instruction. */ + dwarf2_emit_insn (0); + + switch (inst.reloc.exp.X_op) + { + case O_symbol: + sym = inst.reloc.exp.X_add_symbol; + offset = inst.reloc.exp.X_add_number; + break; + case O_constant: + sym = NULL; + offset = inst.reloc.exp.X_add_number; + break; + default: + sym = make_expr_symbol (&inst.reloc.exp); + offset = 0; + break; + } + to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, + inst.relax, sym, offset, NULL/*offset, opcode*/); + md_number_to_chars (to, inst.instruction, THUMB_SIZE); +} + +/* Write a 32-bit thumb instruction to buf. */ +static void +put_thumb32_insn (char * buf, unsigned long insn) +{ + md_number_to_chars (buf, insn >> 16, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); +} + +static void +output_inst (const char * str) +{ + char * to = NULL; + + if (inst.error) + { + as_bad ("%s -- `%s'", inst.error, str); + return; + } + if (inst.relax) + { + output_relax_insn (); + return; + } + if (inst.size == 0) + return; + + to = frag_more (inst.size); + /* PR 9814: Record the thumb mode into the current frag so that we know + what type of NOP padding to use, if necessary. We override any previous + setting so that if the mode has changed then the NOPS that we use will + match the encoding of the last instruction in the frag. */ + frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; + + if (thumb_mode && (inst.size > THUMB_SIZE)) + { + gas_assert (inst.size == (2 * THUMB_SIZE)); + put_thumb32_insn (to, inst.instruction); + } + else if (inst.size > INSN_SIZE) + { + gas_assert (inst.size == (2 * INSN_SIZE)); + md_number_to_chars (to, inst.instruction, INSN_SIZE); + md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); + } + else + md_number_to_chars (to, inst.instruction, inst.size); + + if (inst.reloc.type != BFD_RELOC_UNUSED) + fix_new_arm (frag_now, to - frag_now->fr_literal, + inst.size, & inst.reloc.exp, inst.reloc.pc_rel, + inst.reloc.type); + + dwarf2_emit_insn (inst.size); +} + +static char * +output_it_inst (int cond, int mask, char * to) +{ + unsigned long instruction = 0xbf00; + + mask &= 0xf; + instruction |= mask; + instruction |= cond << 4; + + if (to == NULL) + { + to = frag_more (2); +#ifdef OBJ_ELF + dwarf2_emit_insn (2); +#endif + } + + md_number_to_chars (to, instruction, 2); + + return to; +} + +/* Tag values used in struct asm_opcode's tag field. */ +enum opcode_tag +{ + OT_unconditional, /* Instruction cannot be conditionalized. + The ARM condition field is still 0xE. */ + OT_unconditionalF, /* Instruction cannot be conditionalized + and carries 0xF in its ARM condition field. */ + OT_csuffix, /* Instruction takes a conditional suffix. */ + OT_csuffixF, /* Some forms of the instruction take a conditional + suffix, others place 0xF where the condition field + would be. */ + OT_cinfix3, /* Instruction takes a conditional infix, + beginning at character index 3. (In + unified mode, it becomes a suffix.) */ + OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for + tsts, cmps, cmns, and teqs. */ + OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at + character index 3, even in unified mode. Used for + legacy instructions where suffix and infix forms + may be ambiguous. */ + OT_csuf_or_in3, /* Instruction takes either a conditional + suffix or an infix at character index 3. */ + OT_odd_infix_unc, /* This is the unconditional variant of an + instruction that takes a conditional infix + at an unusual position. In unified mode, + this variant will accept a suffix. */ + OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 + are the conditional variants of instructions that + take conditional infixes in unusual positions. + The infix appears at character index + (tag - OT_odd_infix_0). These are not accepted + in unified mode. */ +}; + +/* Subroutine of md_assemble, responsible for looking up the primary + opcode from the mnemonic the user wrote. STR points to the + beginning of the mnemonic. + + This is not simply a hash table lookup, because of conditional + variants. Most instructions have conditional variants, which are + expressed with a _conditional affix_ to the mnemonic. If we were + to encode each conditional variant as a literal string in the opcode + table, it would have approximately 20,000 entries. + + Most mnemonics take this affix as a suffix, and in unified syntax, + 'most' is upgraded to 'all'. However, in the divided syntax, some + instructions take the affix as an infix, notably the s-variants of + the arithmetic instructions. Of those instructions, all but six + have the infix appear after the third character of the mnemonic. + + Accordingly, the algorithm for looking up primary opcodes given + an identifier is: + + 1. Look up the identifier in the opcode table. + If we find a match, go to step U. + + 2. Look up the last two characters of the identifier in the + conditions table. If we find a match, look up the first N-2 + characters of the identifier in the opcode table. If we + find a match, go to step CE. + + 3. Look up the fourth and fifth characters of the identifier in + the conditions table. If we find a match, extract those + characters from the identifier, and look up the remaining + characters in the opcode table. If we find a match, go + to step CM. + + 4. Fail. + + U. Examine the tag field of the opcode structure, in case this is + one of the six instructions with its conditional infix in an + unusual place. If it is, the tag tells us where to find the + infix; look it up in the conditions table and set inst.cond + accordingly. Otherwise, this is an unconditional instruction. + Again set inst.cond accordingly. Return the opcode structure. + + CE. Examine the tag field to make sure this is an instruction that + should receive a conditional suffix. If it is not, fail. + Otherwise, set inst.cond from the suffix we already looked up, + and return the opcode structure. + + CM. Examine the tag field to make sure this is an instruction that + should receive a conditional infix after the third character. + If it is not, fail. Otherwise, undo the edits to the current + line of input and proceed as for case CE. */ + +static const struct asm_opcode * +opcode_lookup (char **str) +{ + char *end, *base; + char *affix; + const struct asm_opcode *opcode; + const struct asm_cond *cond; + char save[2]; + bfd_boolean neon_supported; + + neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1); + + /* Scan up to the end of the mnemonic, which must end in white space, + '.' (in unified mode, or for Neon instructions), or end of string. */ + for (base = end = *str; *end != '\0'; end++) + if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.')) + break; + + if (end == base) + return NULL; + + /* Handle a possible width suffix and/or Neon type suffix. */ + if (end[0] == '.') + { + int offset = 2; + + /* The .w and .n suffixes are only valid if the unified syntax is in + use. */ + if (unified_syntax && end[1] == 'w') + inst.size_req = 4; + else if (unified_syntax && end[1] == 'n') + inst.size_req = 2; + else + offset = 0; + + inst.vectype.elems = 0; + + *str = end + offset; + + if (end[offset] == '.') + { + /* See if we have a Neon type suffix (possible in either unified or + non-unified ARM syntax mode). */ + if (parse_neon_type (&inst.vectype, str) == FAIL) + return NULL; + } + else if (end[offset] != '\0' && end[offset] != ' ') + return NULL; + } + else + *str = end; + + /* Look for unaffixed or special-case affixed mnemonic. */ + opcode = hash_find_n (arm_ops_hsh, base, end - base); + if (opcode) + { + /* step U */ + if (opcode->tag < OT_odd_infix_0) + { + inst.cond = COND_ALWAYS; + return opcode; + } + + if (warn_on_deprecated && unified_syntax) + as_warn (_("conditional infixes are deprecated in unified syntax")); + affix = base + (opcode->tag - OT_odd_infix_0); + cond = hash_find_n (arm_cond_hsh, affix, 2); + gas_assert (cond); + + inst.cond = cond->value; + return opcode; + } + + /* Cannot have a conditional suffix on a mnemonic of less than two + characters. */ + if (end - base < 3) + return NULL; + + /* Look for suffixed mnemonic. */ + affix = end - 2; + cond = hash_find_n (arm_cond_hsh, affix, 2); + opcode = hash_find_n (arm_ops_hsh, base, affix - base); + if (opcode && cond) + { + /* step CE */ + switch (opcode->tag) + { + case OT_cinfix3_legacy: + /* Ignore conditional suffixes matched on infix only mnemonics. */ + break; + + case OT_cinfix3: + case OT_cinfix3_deprecated: + case OT_odd_infix_unc: + if (!unified_syntax) + return 0; + /* else fall through */ + + case OT_csuffix: + case OT_csuffixF: + case OT_csuf_or_in3: + inst.cond = cond->value; + return opcode; + + case OT_unconditional: + case OT_unconditionalF: + if (thumb_mode) + inst.cond = cond->value; + else + { + /* Delayed diagnostic. */ + inst.error = BAD_COND; + inst.cond = COND_ALWAYS; + } + return opcode; + + default: + return NULL; + } + } + + /* Cannot have a usual-position infix on a mnemonic of less than + six characters (five would be a suffix). */ + if (end - base < 6) + return NULL; + + /* Look for infixed mnemonic in the usual position. */ + affix = base + 3; + cond = hash_find_n (arm_cond_hsh, affix, 2); + if (!cond) + return NULL; + + memcpy (save, affix, 2); + memmove (affix, affix + 2, (end - affix) - 2); + opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); + memmove (affix + 2, affix, (end - affix) - 2); + memcpy (affix, save, 2); + + if (opcode + && (opcode->tag == OT_cinfix3 + || opcode->tag == OT_cinfix3_deprecated + || opcode->tag == OT_csuf_or_in3 + || opcode->tag == OT_cinfix3_legacy)) + { + /* Step CM. */ + if (warn_on_deprecated && unified_syntax + && (opcode->tag == OT_cinfix3 + || opcode->tag == OT_cinfix3_deprecated)) + as_warn (_("conditional infixes are deprecated in unified syntax")); + + inst.cond = cond->value; + return opcode; + } + + return NULL; +} + +/* This function generates an initial IT instruction, leaving its block + virtually open for the new instructions. Eventually, + the mask will be updated by now_it_add_mask () each time + a new instruction needs to be included in the IT block. + Finally, the block is closed with close_automatic_it_block (). + The block closure can be requested either from md_assemble (), + a tencode (), or due to a label hook. */ + +static void +new_automatic_it_block (int cond) +{ + now_it.state = AUTOMATIC_IT_BLOCK; + now_it.mask = 0x18; + now_it.cc = cond; + now_it.block_length = 1; + mapping_state (MAP_THUMB); + now_it.insn = output_it_inst (cond, now_it.mask, NULL); +} + +/* Close an automatic IT block. + See comments in new_automatic_it_block (). */ + +static void +close_automatic_it_block (void) +{ + now_it.mask = 0x10; + now_it.block_length = 0; +} + +/* Update the mask of the current automatically-generated IT + instruction. See comments in new_automatic_it_block (). */ + +static void +now_it_add_mask (int cond) +{ +#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) +#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ + | ((bitvalue) << (nbit))) + const int resulting_bit = (cond & 1); + + now_it.mask &= 0xf; + now_it.mask = SET_BIT_VALUE (now_it.mask, + resulting_bit, + (5 - now_it.block_length)); + now_it.mask = SET_BIT_VALUE (now_it.mask, + 1, + ((5 - now_it.block_length) - 1) ); + output_it_inst (now_it.cc, now_it.mask, now_it.insn); + +#undef CLEAR_BIT +#undef SET_BIT_VALUE +} + +/* The IT blocks handling machinery is accessed through the these functions: + it_fsm_pre_encode () from md_assemble () + set_it_insn_type () optional, from the tencode functions + set_it_insn_type_last () ditto + in_it_block () ditto + it_fsm_post_encode () from md_assemble () + force_automatic_it_block_close () from label habdling functions + + Rationale: + 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), + initializing the IT insn type with a generic initial value depending + on the inst.condition. + 2) During the tencode function, two things may happen: + a) The tencode function overrides the IT insn type by + calling either set_it_insn_type (type) or set_it_insn_type_last (). + b) The tencode function queries the IT block state by + calling in_it_block () (i.e. to determine narrow/not narrow mode). + + Both set_it_insn_type and in_it_block run the internal FSM state + handling function (handle_it_state), because: a) setting the IT insn + type may incur in an invalid state (exiting the function), + and b) querying the state requires the FSM to be updated. + Specifically we want to avoid creating an IT block for conditional + branches, so it_fsm_pre_encode is actually a guess and we can't + determine whether an IT block is required until the tencode () routine + has decided what type of instruction this actually it. + Because of this, if set_it_insn_type and in_it_block have to be used, + set_it_insn_type has to be called first. + + set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that + determines the insn IT type depending on the inst.cond code. + When a tencode () routine encodes an instruction that can be + either outside an IT block, or, in the case of being inside, has to be + the last one, set_it_insn_type_last () will determine the proper + IT instruction type based on the inst.cond code. Otherwise, + set_it_insn_type can be called for overriding that logic or + for covering other cases. + + Calling handle_it_state () may not transition the IT block state to + OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be + still queried. Instead, if the FSM determines that the state should + be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed + after the tencode () function: that's what it_fsm_post_encode () does. + + Since in_it_block () calls the state handling function to get an + updated state, an error may occur (due to invalid insns combination). + In that case, inst.error is set. + Therefore, inst.error has to be checked after the execution of + the tencode () routine. + + 3) Back in md_assemble(), it_fsm_post_encode () is called to commit + any pending state change (if any) that didn't take place in + handle_it_state () as explained above. */ + +static void +it_fsm_pre_encode (void) +{ + if (inst.cond != COND_ALWAYS) + inst.it_insn_type = INSIDE_IT_INSN; + else + inst.it_insn_type = OUTSIDE_IT_INSN; + + now_it.state_handled = 0; +} + +/* IT state FSM handling function. */ + +static int +handle_it_state (void) +{ + now_it.state_handled = 1; + + switch (now_it.state) + { + case OUTSIDE_IT_BLOCK: + switch (inst.it_insn_type) + { + case OUTSIDE_IT_INSN: + break; + + case INSIDE_IT_INSN: + case INSIDE_IT_LAST_INSN: + if (thumb_mode == 0) + { + if (unified_syntax + && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) + as_tsktsk (_("Warning: conditional outside an IT block"\ + " for Thumb.")); + } + else + { + if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) + && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) + { + /* Automatically generate the IT instruction. */ + new_automatic_it_block (inst.cond); + if (inst.it_insn_type == INSIDE_IT_LAST_INSN) + close_automatic_it_block (); + } + else + { + inst.error = BAD_OUT_IT; + return FAIL; + } + } + break; + + case IF_INSIDE_IT_LAST_INSN: + case NEUTRAL_IT_INSN: + break; + + case IT_INSN: + now_it.state = MANUAL_IT_BLOCK; + now_it.block_length = 0; + break; + } + break; + + case AUTOMATIC_IT_BLOCK: + /* Three things may happen now: + a) We should increment current it block size; + b) We should close current it block (closing insn or 4 insns); + c) We should close current it block and start a new one (due + to incompatible conditions or + 4 insns-length block reached). */ + + switch (inst.it_insn_type) + { + case OUTSIDE_IT_INSN: + /* The closure of the block shall happen immediatelly, + so any in_it_block () call reports the block as closed. */ + force_automatic_it_block_close (); + break; + + case INSIDE_IT_INSN: + case INSIDE_IT_LAST_INSN: + case IF_INSIDE_IT_LAST_INSN: + now_it.block_length++; + + if (now_it.block_length > 4 + || !now_it_compatible (inst.cond)) + { + force_automatic_it_block_close (); + if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) + new_automatic_it_block (inst.cond); + } + else + { + now_it_add_mask (inst.cond); + } + + if (now_it.state == AUTOMATIC_IT_BLOCK + && (inst.it_insn_type == INSIDE_IT_LAST_INSN + || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) + close_automatic_it_block (); + break; + + case NEUTRAL_IT_INSN: + now_it.block_length++; + + if (now_it.block_length > 4) + force_automatic_it_block_close (); + else + now_it_add_mask (now_it.cc & 1); + break; + + case IT_INSN: + close_automatic_it_block (); + now_it.state = MANUAL_IT_BLOCK; + break; + } + break; + + case MANUAL_IT_BLOCK: + { + /* Check conditional suffixes. */ + const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; + int is_last; + now_it.mask <<= 1; + now_it.mask &= 0x1f; + is_last = (now_it.mask == 0x10); + + switch (inst.it_insn_type) + { + case OUTSIDE_IT_INSN: + inst.error = BAD_NOT_IT; + return FAIL; + + case INSIDE_IT_INSN: + if (cond != inst.cond) + { + inst.error = BAD_IT_COND; + return FAIL; + } + break; + + case INSIDE_IT_LAST_INSN: + case IF_INSIDE_IT_LAST_INSN: + if (cond != inst.cond) + { + inst.error = BAD_IT_COND; + return FAIL; + } + if (!is_last) + { + inst.error = BAD_BRANCH; + return FAIL; + } + break; + + case NEUTRAL_IT_INSN: + /* The BKPT instruction is unconditional even in an IT block. */ + break; + + case IT_INSN: + inst.error = BAD_IT_IT; + return FAIL; + } + } + break; + } + + return SUCCESS; +} + +static void +it_fsm_post_encode (void) +{ + int is_last; + + if (!now_it.state_handled) + handle_it_state (); + + is_last = (now_it.mask == 0x10); + if (is_last) + { + now_it.state = OUTSIDE_IT_BLOCK; + now_it.mask = 0; + } +} + +static void +force_automatic_it_block_close (void) +{ + if (now_it.state == AUTOMATIC_IT_BLOCK) + { + close_automatic_it_block (); + now_it.state = OUTSIDE_IT_BLOCK; + now_it.mask = 0; + } +} + +static int +in_it_block (void) +{ + if (!now_it.state_handled) + handle_it_state (); + + return now_it.state != OUTSIDE_IT_BLOCK; +} + +void +md_assemble (char *str) +{ + char *p = str; + const struct asm_opcode * opcode; + + /* Align the previous label if needed. */ + if (last_label_seen != NULL) + { + symbol_set_frag (last_label_seen, frag_now); + S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); + S_SET_SEGMENT (last_label_seen, now_seg); + } + + memset (&inst, '\0', sizeof (inst)); + inst.reloc.type = BFD_RELOC_UNUSED; + + opcode = opcode_lookup (&p); + if (!opcode) + { + /* It wasn't an instruction, but it might be a register alias of + the form alias .req reg, or a Neon .dn/.qn directive. */ + if (! create_register_alias (str, p) + && ! create_neon_reg_alias (str, p)) + as_bad (_("bad instruction `%s'"), str); + + return; + } + + if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) + as_warn (_("s suffix on comparison instruction is deprecated")); + + /* The value which unconditional instructions should have in place of the + condition field. */ + inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; + + if (thumb_mode) + { + arm_feature_set variant; + + variant = cpu_variant; + /* Only allow coprocessor instructions on Thumb-2 capable devices. */ + if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) + ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); + /* Check that this instruction is supported for this CPU. */ + if (!opcode->tvariant + || (thumb_mode == 1 + && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) + { + as_bad (_("selected processor does not support `%s'"), str); + return; + } + if (inst.cond != COND_ALWAYS && !unified_syntax + && opcode->tencode != do_t_branch) + { + as_bad (_("Thumb does not support conditional execution")); + return; + } + + if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) + { + if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 + && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) + || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) + { + /* Two things are addressed here. + 1) Implicit require narrow instructions on Thumb-1. + This avoids relaxation accidentally introducing Thumb-2 + instructions. + 2) Reject wide instructions in non Thumb-2 cores. */ + if (inst.size_req == 0) + inst.size_req = 2; + else if (inst.size_req == 4) + { + as_bad (_("selected processor does not support `%s'"), str); + return; + } + } + } + + inst.instruction = opcode->tvalue; + + if (!parse_operands (p, opcode->operands)) + { + /* Prepare the it_insn_type for those encodings that don't set + it. */ + it_fsm_pre_encode (); + + opcode->tencode (); + + it_fsm_post_encode (); + } + + if (!(inst.error || inst.relax)) + { + gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); + inst.size = (inst.instruction > 0xffff ? 4 : 2); + if (inst.size_req && inst.size_req != inst.size) + { + as_bad (_("cannot honor width suffix -- `%s'"), str); + return; + } + } + + /* Something has gone badly wrong if we try to relax a fixed size + instruction. */ + gas_assert (inst.size_req == 0 || !inst.relax); + + ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, + *opcode->tvariant); + /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly + set those bits when Thumb-2 32-bit instructions are seen. ie. + anything other than bl/blx and v6-M instructions. + This is overly pessimistic for relaxable instructions. */ + if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) + || inst.relax) + && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) + || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) + ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, + arm_ext_v6t2); + + if (!inst.error) + { + mapping_state (MAP_THUMB); + } + } + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) + { + bfd_boolean is_bx; + + /* bx is allowed on v5 cores, and sometimes on v4 cores. */ + is_bx = (opcode->aencode == do_bx); + + /* Check that this instruction is supported for this CPU. */ + if (!(is_bx && fix_v4bx) + && !(opcode->avariant && + ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) + { + as_bad (_("selected processor does not support `%s'"), str); + return; + } + if (inst.size_req) + { + as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); + return; + } + + inst.instruction = opcode->avalue; + if (opcode->tag == OT_unconditionalF) + inst.instruction |= 0xF << 28; + else + inst.instruction |= inst.cond << 28; + inst.size = INSN_SIZE; + if (!parse_operands (p, opcode->operands)) + { + it_fsm_pre_encode (); + opcode->aencode (); + it_fsm_post_encode (); + } + /* Arm mode bx is marked as both v4T and v5 because it's still required + on a hypothetical non-thumb v5 core. */ + if (is_bx) + ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); + else + ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, + *opcode->avariant); + if (!inst.error) + { + mapping_state (MAP_ARM); + } + } + else + { + as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " + "-- `%s'"), str); + return; + } + output_inst (str); +} + +static void +check_it_blocks_finished (void) +{ +#ifdef OBJ_ELF + asection *sect; + + for (sect = stdoutput->sections; sect != NULL; sect = sect->next) + if (seg_info (sect)->tc_segment_info_data.current_it.state + == MANUAL_IT_BLOCK) + { + as_warn (_("section '%s' finished with an open IT block."), + sect->name); + } +#else + if (now_it.state == MANUAL_IT_BLOCK) + as_warn (_("file finished with an open IT block.")); +#endif +} + +/* Various frobbings of labels and their addresses. */ + +void +arm_start_line_hook (void) +{ + last_label_seen = NULL; +} + +void +arm_frob_label (symbolS * sym) +{ + last_label_seen = sym; + + ARM_SET_THUMB (sym, thumb_mode); + +#if defined OBJ_COFF || defined OBJ_ELF + ARM_SET_INTERWORK (sym, support_interwork); +#endif + + force_automatic_it_block_close (); + + /* Note - do not allow local symbols (.Lxxx) to be labelled + as Thumb functions. This is because these labels, whilst + they exist inside Thumb code, are not the entry points for + possible ARM->Thumb calls. Also, these labels can be used + as part of a computed goto or switch statement. eg gcc + can generate code that looks like this: + + ldr r2, [pc, .Laaa] + lsl r3, r3, #2 + ldr r2, [r3, r2] + mov pc, r2 + + .Lbbb: .word .Lxxx + .Lccc: .word .Lyyy + ..etc... + .Laaa: .word Lbbb + + The first instruction loads the address of the jump table. + The second instruction converts a table index into a byte offset. + The third instruction gets the jump address out of the table. + The fourth instruction performs the jump. + + If the address stored at .Laaa is that of a symbol which has the + Thumb_Func bit set, then the linker will arrange for this address + to have the bottom bit set, which in turn would mean that the + address computation performed by the third instruction would end + up with the bottom bit set. Since the ARM is capable of unaligned + word loads, the instruction would then load the incorrect address + out of the jump table, and chaos would ensue. */ + if (label_is_thumb_function_name + && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') + && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) + { + /* When the address of a Thumb function is taken the bottom + bit of that address should be set. This will allow + interworking between Arm and Thumb functions to work + correctly. */ + + THUMB_SET_FUNC (sym, 1); + + label_is_thumb_function_name = FALSE; + } + + dwarf2_emit_label (sym); +} + +bfd_boolean +arm_data_in_code (void) +{ + if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) + { + *input_line_pointer = '/'; + input_line_pointer += 5; + *input_line_pointer = 0; + return TRUE; + } + + return FALSE; +} + +char * +arm_canonicalize_symbol_name (char * name) +{ + int len; + + if (thumb_mode && (len = strlen (name)) > 5 + && streq (name + len - 5, "/data")) + *(name + len - 5) = 0; + + return name; +} + +/* Table of all register names defined by default. The user can + define additional names with .req. Note that all register names + should appear in both upper and lowercase variants. Some registers + also have mixed-case names. */ + +#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } +#define REGNUM(p,n,t) REGDEF(p##n, n, t) +#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) +#define REGSET(p,t) \ + REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ + REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ + REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ + REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) +#define REGSETH(p,t) \ + REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ + REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ + REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ + REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) +#define REGSET2(p,t) \ + REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ + REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ + REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ + REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) + +static const struct reg_entry reg_names[] = +{ + /* ARM integer registers. */ + REGSET(r, RN), REGSET(R, RN), + + /* ATPCS synonyms. */ + REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), + REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), + REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), + + REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), + REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), + REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), + + /* Well-known aliases. */ + REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), + REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), + + REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), + REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), + + /* Coprocessor numbers. */ + REGSET(p, CP), REGSET(P, CP), + + /* Coprocessor register numbers. The "cr" variants are for backward + compatibility. */ + REGSET(c, CN), REGSET(C, CN), + REGSET(cr, CN), REGSET(CR, CN), + + /* FPA registers. */ + REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), + REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), + + REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), + REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), + + /* VFP SP registers. */ + REGSET(s,VFS), REGSET(S,VFS), + REGSETH(s,VFS), REGSETH(S,VFS), + + /* VFP DP Registers. */ + REGSET(d,VFD), REGSET(D,VFD), + /* Extra Neon DP registers. */ + REGSETH(d,VFD), REGSETH(D,VFD), + + /* Neon QP registers. */ + REGSET2(q,NQ), REGSET2(Q,NQ), + + /* VFP control registers. */ + REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), + REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), + REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), + REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), + REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), + REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), + + /* Maverick DSP coprocessor registers. */ + REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), + REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), + + REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), + REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), + REGDEF(dspsc,0,DSPSC), + + REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), + REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), + REGDEF(DSPSC,0,DSPSC), + + /* iWMMXt data registers - p0, c0-15. */ + REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), + + /* iWMMXt control registers - p1, c0-3. */ + REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), + REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), + REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), + REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), + + /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ + REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), + REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), + REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), + REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), + + /* XScale accumulator registers. */ + REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), +}; +#undef REGDEF +#undef REGNUM +#undef REGSET + +/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled + within psr_required_here. */ +static const struct asm_psr psrs[] = +{ + /* Backward compatibility notation. Note that "all" is no longer + truly all possible PSR bits. */ + {"all", PSR_c | PSR_f}, + {"flg", PSR_f}, + {"ctl", PSR_c}, + + /* Individual flags. */ + {"f", PSR_f}, + {"c", PSR_c}, + {"x", PSR_x}, + {"s", PSR_s}, + /* Combinations of flags. */ + {"fs", PSR_f | PSR_s}, + {"fx", PSR_f | PSR_x}, + {"fc", PSR_f | PSR_c}, + {"sf", PSR_s | PSR_f}, + {"sx", PSR_s | PSR_x}, + {"sc", PSR_s | PSR_c}, + {"xf", PSR_x | PSR_f}, + {"xs", PSR_x | PSR_s}, + {"xc", PSR_x | PSR_c}, + {"cf", PSR_c | PSR_f}, + {"cs", PSR_c | PSR_s}, + {"cx", PSR_c | PSR_x}, + {"fsx", PSR_f | PSR_s | PSR_x}, + {"fsc", PSR_f | PSR_s | PSR_c}, + {"fxs", PSR_f | PSR_x | PSR_s}, + {"fxc", PSR_f | PSR_x | PSR_c}, + {"fcs", PSR_f | PSR_c | PSR_s}, + {"fcx", PSR_f | PSR_c | PSR_x}, + {"sfx", PSR_s | PSR_f | PSR_x}, + {"sfc", PSR_s | PSR_f | PSR_c}, + {"sxf", PSR_s | PSR_x | PSR_f}, + {"sxc", PSR_s | PSR_x | PSR_c}, + {"scf", PSR_s | PSR_c | PSR_f}, + {"scx", PSR_s | PSR_c | PSR_x}, + {"xfs", PSR_x | PSR_f | PSR_s}, + {"xfc", PSR_x | PSR_f | PSR_c}, + {"xsf", PSR_x | PSR_s | PSR_f}, + {"xsc", PSR_x | PSR_s | PSR_c}, + {"xcf", PSR_x | PSR_c | PSR_f}, + {"xcs", PSR_x | PSR_c | PSR_s}, + {"cfs", PSR_c | PSR_f | PSR_s}, + {"cfx", PSR_c | PSR_f | PSR_x}, + {"csf", PSR_c | PSR_s | PSR_f}, + {"csx", PSR_c | PSR_s | PSR_x}, + {"cxf", PSR_c | PSR_x | PSR_f}, + {"cxs", PSR_c | PSR_x | PSR_s}, + {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, + {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, + {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, + {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, + {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, + {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, + {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, + {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, + {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, + {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, + {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, + {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, + {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, + {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, + {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, + {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, + {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, + {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, + {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, + {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, + {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, + {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, + {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, + {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, +}; + +/* Table of V7M psr names. */ +static const struct asm_psr v7m_psrs[] = +{ + {"apsr", 0 }, {"APSR", 0 }, + {"iapsr", 1 }, {"IAPSR", 1 }, + {"eapsr", 2 }, {"EAPSR", 2 }, + {"psr", 3 }, {"PSR", 3 }, + {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, + {"ipsr", 5 }, {"IPSR", 5 }, + {"epsr", 6 }, {"EPSR", 6 }, + {"iepsr", 7 }, {"IEPSR", 7 }, + {"msp", 8 }, {"MSP", 8 }, + {"psp", 9 }, {"PSP", 9 }, + {"primask", 16}, {"PRIMASK", 16}, + {"basepri", 17}, {"BASEPRI", 17}, + {"basepri_max", 18}, {"BASEPRI_MAX", 18}, + {"faultmask", 19}, {"FAULTMASK", 19}, + {"control", 20}, {"CONTROL", 20} +}; + +/* Table of all shift-in-operand names. */ +static const struct asm_shift_name shift_names [] = +{ + { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, + { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, + { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, + { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, + { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, + { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } +}; + +/* Table of all explicit relocation names. */ +#ifdef OBJ_ELF +static struct reloc_entry reloc_names[] = +{ + { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, + { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, + { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, + { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, + { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, + { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, + { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, + { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, + { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, + { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, + { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} +}; +#endif + +/* Table of all conditional affixes. 0xF is not defined as a condition code. */ +static const struct asm_cond conds[] = +{ + {"eq", 0x0}, + {"ne", 0x1}, + {"cs", 0x2}, {"hs", 0x2}, + {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, + {"mi", 0x4}, + {"pl", 0x5}, + {"vs", 0x6}, + {"vc", 0x7}, + {"hi", 0x8}, + {"ls", 0x9}, + {"ge", 0xa}, + {"lt", 0xb}, + {"gt", 0xc}, + {"le", 0xd}, + {"al", 0xe} +}; + +static struct asm_barrier_opt barrier_opt_names[] = +{ + { "sy", 0xf }, + { "un", 0x7 }, + { "st", 0xe }, + { "unst", 0x6 } +}; + +/* Table of ARM-format instructions. */ + +/* Macros for gluing together operand strings. N.B. In all cases + other than OPS0, the trailing OP_stop comes from default + zero-initialization of the unspecified elements of the array. */ +#define OPS0() { OP_stop, } +#define OPS1(a) { OP_##a, } +#define OPS2(a,b) { OP_##a,OP_##b, } +#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } +#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } +#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } +#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } + +/* These macros abstract out the exact format of the mnemonic table and + save some repeated characters. */ + +/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ +#define TxCE(mnem, op, top, nops, ops, ae, te) \ + { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ + THUMB_VARIANT, do_##ae, do_##te } + +/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for + a T_MNEM_xyz enumerator. */ +#define TCE(mnem, aop, top, nops, ops, ae, te) \ + TxCE (mnem, aop, 0x##top, nops, ops, ae, te) +#define tCE(mnem, aop, top, nops, ops, ae, te) \ + TxCE (mnem, aop, T_MNEM_##top, nops, ops, ae, te) + +/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional + infix after the third character. */ +#define TxC3(mnem, op, top, nops, ops, ae, te) \ + { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ + THUMB_VARIANT, do_##ae, do_##te } +#define TxC3w(mnem, op, top, nops, ops, ae, te) \ + { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ + THUMB_VARIANT, do_##ae, do_##te } +#define TC3(mnem, aop, top, nops, ops, ae, te) \ + TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) +#define TC3w(mnem, aop, top, nops, ops, ae, te) \ + TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) +#define tC3(mnem, aop, top, nops, ops, ae, te) \ + TxC3 (mnem, aop, T_MNEM_##top, nops, ops, ae, te) +#define tC3w(mnem, aop, top, nops, ops, ae, te) \ + TxC3w (mnem, aop, T_MNEM_##top, nops, ops, ae, te) + +/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to + appear in the condition table. */ +#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ + { #m1 #m2 #m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (#m1) - 1, \ + 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } + +#define TxCM(m1, m2, op, top, nops, ops, ae, te) \ + TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ + TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) + +#define TCM(m1,m2, aop, top, nops, ops, ae, te) \ + TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) +#define tCM(m1,m2, aop, top, nops, ops, ae, te) \ + TxCM (m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) + +/* Mnemonic that cannot be conditionalized. The ARM condition-code + field is still 0xE. Many of the Thumb variants can be executed + conditionally, so this is checked separately. */ +#define TUE(mnem, op, top, nops, ops, ae, te) \ + { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ + THUMB_VARIANT, do_##ae, do_##te } + +/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM + condition code field. */ +#define TUF(mnem, op, top, nops, ops, ae, te) \ + { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ + THUMB_VARIANT, do_##ae, do_##te } + +/* ARM-only variants of all the above. */ +#define CE(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } + +#define C3(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } + +/* Legacy mnemonics that always have conditional infix after the third + character. */ +#define CL(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ + 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } + +/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ +#define cCE(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } + +/* Legacy coprocessor instructions where conditional infix and conditional + suffix are ambiguous. For consistency this includes all FPA instructions, + not just the potentially ambiguous ones. */ +#define cCL(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ + 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } + +/* Coprocessor, takes either a suffix or a position-3 infix + (for an FPA corner case). */ +#define C3E(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_csuf_or_in3, \ + 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } + +#define xCM_(m1, m2, m3, op, nops, ops, ae) \ + { #m1 #m2 #m3, OPS##nops ops, \ + sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (#m1) - 1, \ + 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } + +#define CM(m1, m2, op, nops, ops, ae) \ + xCM_ (m1, , m2, op, nops, ops, ae), \ + xCM_ (m1, eq, m2, op, nops, ops, ae), \ + xCM_ (m1, ne, m2, op, nops, ops, ae), \ + xCM_ (m1, cs, m2, op, nops, ops, ae), \ + xCM_ (m1, hs, m2, op, nops, ops, ae), \ + xCM_ (m1, cc, m2, op, nops, ops, ae), \ + xCM_ (m1, ul, m2, op, nops, ops, ae), \ + xCM_ (m1, lo, m2, op, nops, ops, ae), \ + xCM_ (m1, mi, m2, op, nops, ops, ae), \ + xCM_ (m1, pl, m2, op, nops, ops, ae), \ + xCM_ (m1, vs, m2, op, nops, ops, ae), \ + xCM_ (m1, vc, m2, op, nops, ops, ae), \ + xCM_ (m1, hi, m2, op, nops, ops, ae), \ + xCM_ (m1, ls, m2, op, nops, ops, ae), \ + xCM_ (m1, ge, m2, op, nops, ops, ae), \ + xCM_ (m1, lt, m2, op, nops, ops, ae), \ + xCM_ (m1, gt, m2, op, nops, ops, ae), \ + xCM_ (m1, le, m2, op, nops, ops, ae), \ + xCM_ (m1, al, m2, op, nops, ops, ae) + +#define UE(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } + +#define UF(mnem, op, nops, ops, ae) \ + { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } + +/* Neon data-processing. ARM versions are unconditional with cond=0xf. + The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we + use the same encoding function for each. */ +#define NUF(mnem, op, nops, ops, enc) \ + { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ + ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } + +/* Neon data processing, version which indirects through neon_enc_tab for + the various overloaded versions of opcodes. */ +#define nUF(mnem, op, nops, ops, enc) \ + { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ + ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } + +/* Neon insn with conditional suffix for the ARM version, non-overloaded + version. */ +#define NCE_tag(mnem, op, nops, ops, enc, tag) \ + { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ + THUMB_VARIANT, do_##enc, do_##enc } + +#define NCE(mnem, op, nops, ops, enc) \ + NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) + +#define NCEF(mnem, op, nops, ops, enc) \ + NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) + +/* Neon insn with conditional suffix for the ARM version, overloaded types. */ +#define nCE_tag(mnem, op, nops, ops, enc, tag) \ + { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ + ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } + +#define nCE(mnem, op, nops, ops, enc) \ + nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) + +#define nCEF(mnem, op, nops, ops, enc) \ + nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) + +#define do_0 0 + +/* Thumb-only, unconditional. */ +#define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te) + +static const struct asm_opcode insns[] = +{ +#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ +#define THUMB_VARIANT &arm_ext_v4t + tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), + tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), + tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), + tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), + tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), + tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), + tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), + tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), + tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), + tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), + tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), + tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), + tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), + tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), + tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), + tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), + + /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism + for setting PSR flag bits. They are obsolete in V6 and do not + have Thumb equivalents. */ + tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), + tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), + CL(tstp, 110f000, 2, (RR, SH), cmp), + tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), + tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), + CL(cmpp, 150f000, 2, (RR, SH), cmp), + tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), + tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), + CL(cmnp, 170f000, 2, (RR, SH), cmp), + + tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), + tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), + tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), + tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), + + tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), + tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), + tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), + tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), + + tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), + tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), + tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), + tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), + tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), + tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), + + TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), + TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), + tCE(b, a000000, b, 1, (EXPr), branch, t_branch), + TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), + + /* Pseudo ops. */ + tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), + C3(adrl, 28f0000, 2, (RR, EXP), adrl), + tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), + + /* Thumb-compatibility pseudo ops. */ + tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), + tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), + tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), + tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), + tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), + tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), + tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), + tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), + tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), + tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), + tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), + tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), + + /* These may simplify to neg. */ + TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), + TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6 + + TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), + + /* V1 instructions with no Thumb analogue prior to V6T2. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 + + TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), + TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), + CL(teqp, 130f000, 2, (RR, SH), cmp), + + TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), + TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), + TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), + TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), + + TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), + TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), + + TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), + TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), + + /* V1 instructions with no Thumb analogue at all. */ + CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), + C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), + + C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), + C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), + C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), + C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), + C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), + C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), + C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), + C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v4t + + tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), + tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 + + TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), + C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), + + /* Generic coprocessor instructions. */ + TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), + TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), + TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), + TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), + TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), + TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ + + CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), + C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_msr + + TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), + TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 + + TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), + CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), + TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), + CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), + TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), + CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), + TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), + CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v4t + + tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), + tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), + tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), + tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), + tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), + tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v4t_5 + + /* ARM Architecture 4T. */ + /* Note: bx (and blx) are required on V5, even if the processor does + not support Thumb. */ + TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v5t + + /* Note: blx has 2 variants; the .value coded here is for + BLX(2). Only this variant has conditional execution. */ + TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), + TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 + + TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), + TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), + TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), + TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), + TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), + TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), + TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ + + TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), + TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), + TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), + TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), + + TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), + TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), + + TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), + TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), + TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), + TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), + + TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + + TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + + TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), + TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), + TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), + TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ + + TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), + TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), + TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), + + TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), + TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ + + TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6 + + TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), + TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), + tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), + tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), + tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), + tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), + tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), + tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), + tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), + TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 + + TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), + TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), + TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), + TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), + + TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), + TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), + +/* ARM V6 not included in V7M (eg. integer SIMD). */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6_notm + + TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), + TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), + TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), + TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(qasx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for QASX. */ + TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(qsax, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for QSAX. */ + TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(sasx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for SASX. */ + TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(shasx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for SHASX. */ + TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(shsax, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for SHSAX. */ + TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(ssax, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for SSAX. */ + TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uasx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for UASX. */ + TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uhasx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for UHASX. */ + TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uhsax, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for UHSAX. */ + TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uqasx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for UQASX. */ + TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uqsax, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for UQSAX. */ + TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(usax, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + /* Old name for USAX. */ + TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), + UF(rfeib, 9900a00, 1, (RRw), rfe), + UF(rfeda, 8100a00, 1, (RRw), rfe), + TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), + TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), + UF(rfefa, 9900a00, 1, (RRw), rfe), + UF(rfeea, 8100a00, 1, (RRw), rfe), + TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), + TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), + TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), + TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), + TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), + TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), + TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), + TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), + TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), + TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), + TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), + TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), + TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), + TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), + UF(srsib, 9c00500, 2, (oRRw, I31w), srs), + UF(srsda, 8400500, 2, (oRRw, I31w), srs), + TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs), + TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), + TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), + TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), + TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), + TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v6k +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6k + + tCE(yield, 320f001, yield, 0, (), noargs, t_hint), + tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), + tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), + tCE(sev, 320f004, sev, 0, (), noargs, t_hint), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6_notm + + TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), + TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 + + TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), + TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), + TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), + TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), + TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v6z + + TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v6t2 + + TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), + TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), + TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), + TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), + + TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), + TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), + TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), + TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), + + TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), + TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), + TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), + TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), + + UT(cbnz, b900, 2, (RR, EXP), t_cbz), + UT(cbz, b100, 2, (RR, EXP), t_cbz), + + /* ARM does not really have an IT instruction, so always allow it. + The opcode is copied from Thumb in order to allow warnings in + -mimplicit-it=[never | arm] modes. */ +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v1 + + TUE(it, bf08, bf08, 1, (COND), it, t_it), + TUE(itt, bf0c, bf0c, 1, (COND), it, t_it), + TUE(ite, bf04, bf04, 1, (COND), it, t_it), + TUE(ittt, bf0e, bf0e, 1, (COND), it, t_it), + TUE(itet, bf06, bf06, 1, (COND), it, t_it), + TUE(itte, bf0a, bf0a, 1, (COND), it, t_it), + TUE(itee, bf02, bf02, 1, (COND), it, t_it), + TUE(itttt, bf0f, bf0f, 1, (COND), it, t_it), + TUE(itett, bf07, bf07, 1, (COND), it, t_it), + TUE(ittet, bf0b, bf0b, 1, (COND), it, t_it), + TUE(iteet, bf03, bf03, 1, (COND), it, t_it), + TUE(ittte, bf0d, bf0d, 1, (COND), it, t_it), + TUE(itete, bf05, bf05, 1, (COND), it, t_it), + TUE(ittee, bf09, bf09, 1, (COND), it, t_it), + TUE(iteee, bf01, bf01, 1, (COND), it, t_it), + /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ + TC3(rrx, 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), + TC3(rrxs, 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), + + /* Thumb2 only instructions. */ +#undef ARM_VARIANT +#define ARM_VARIANT NULL + + TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), + TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), + TCE(orn, 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), + TCE(orns, 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), + TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), + TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), + + /* Thumb-2 hardware division instructions (R and M profiles only). */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_div + + TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), + TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), + + /* ARM V6M/V7 instructions. */ +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_barrier +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_barrier + + TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), + TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), + TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), + + /* ARM V7 instructions. */ +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v7 +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v7 + + TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), + TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), + +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ + + cCE(wfs, e200110, 1, (RR), rd), + cCE(rfs, e300110, 1, (RR), rd), + cCE(wfc, e400110, 1, (RR), rd), + cCE(rfc, e500110, 1, (RR), rd), + + cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), + cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), + cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), + cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), + + cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), + cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), + cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), + cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), + + cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), + cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), + cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), + cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), + cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), + cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), + cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), + cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), + cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), + cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), + cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), + cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), + + cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), + cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), + cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), + cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), + cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), + cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), + cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), + cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), + cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), + cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), + cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), + cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), + + cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), + cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), + cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), + cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), + cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), + cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), + cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), + cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), + cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), + cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), + cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), + cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), + + cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), + cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), + cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), + cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), + cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), + cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), + cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), + cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), + cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), + cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), + cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), + cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), + + cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), + cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), + cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), + cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), + cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), + cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), + cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), + cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), + cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), + cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), + cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), + cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), + + cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), + cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), + cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), + cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), + cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), + cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), + cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), + cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), + cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), + cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), + cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), + cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), + + cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), + cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), + cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), + cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), + cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), + cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), + cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), + cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), + cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), + cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), + cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), + cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), + + cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), + cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), + cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), + cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), + cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), + cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), + cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), + cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), + cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), + cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), + cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), + cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), + + cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), + cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), + cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), + cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), + cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), + cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), + cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), + cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), + cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), + cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), + cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), + cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), + + cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), + cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), + cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), + cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), + cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), + cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), + cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), + cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), + cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), + cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), + cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), + cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), + + cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), + cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), + cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), + cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), + cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), + cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), + cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), + cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), + cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), + cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), + cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), + cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), + + cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), + cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), + cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), + cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), + cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), + cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), + cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), + cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), + cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), + cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), + cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), + cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), + + cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), + cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), + cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), + cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), + cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), + cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), + cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), + cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), + cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), + cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), + cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), + cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), + + cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), + cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), + cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), + cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), + cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), + cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), + cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), + cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), + cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), + cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), + cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), + cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), + + cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), + cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), + cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), + cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), + cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), + cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), + cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), + cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), + cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), + cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), + cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), + cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), + + cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), + cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), + cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), + cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), + cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), + cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), + cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), + cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), + cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), + cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), + cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), + cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), + + cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), + cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), + + cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), + C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), + cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), + C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), + + cCL(flts, e000110, 2, (RF, RR), rn_rd), + cCL(fltsp, e000130, 2, (RF, RR), rn_rd), + cCL(fltsm, e000150, 2, (RF, RR), rn_rd), + cCL(fltsz, e000170, 2, (RF, RR), rn_rd), + cCL(fltd, e000190, 2, (RF, RR), rn_rd), + cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), + cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), + cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), + cCL(flte, e080110, 2, (RF, RR), rn_rd), + cCL(fltep, e080130, 2, (RF, RR), rn_rd), + cCL(fltem, e080150, 2, (RF, RR), rn_rd), + cCL(fltez, e080170, 2, (RF, RR), rn_rd), + + /* The implementation of the FIX instruction is broken on some + assemblers, in that it accepts a precision specifier as well as a + rounding specifier, despite the fact that this is meaningless. + To be more compatible, we accept it as well, though of course it + does not set any bits. */ + cCE(fix, e100110, 2, (RR, RF), rd_rm), + cCL(fixp, e100130, 2, (RR, RF), rd_rm), + cCL(fixm, e100150, 2, (RR, RF), rd_rm), + cCL(fixz, e100170, 2, (RR, RF), rd_rm), + cCL(fixsp, e100130, 2, (RR, RF), rd_rm), + cCL(fixsm, e100150, 2, (RR, RF), rd_rm), + cCL(fixsz, e100170, 2, (RR, RF), rd_rm), + cCL(fixdp, e100130, 2, (RR, RF), rd_rm), + cCL(fixdm, e100150, 2, (RR, RF), rd_rm), + cCL(fixdz, e100170, 2, (RR, RF), rd_rm), + cCL(fixep, e100130, 2, (RR, RF), rd_rm), + cCL(fixem, e100150, 2, (RR, RF), rd_rm), + cCL(fixez, e100170, 2, (RR, RF), rd_rm), + + /* Instructions that were new with the real FPA, call them V2. */ +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_fpa_ext_v2 + + cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), + cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), + +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ + + /* Moves and type conversions. */ + cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), + cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), + cCE(fmstat, ef1fa10, 0, (), noargs), + cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), + cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), + + /* Memory operations. */ + cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), + cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), + cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), + cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), + cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), + cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), + cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), + cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), + cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), + cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), + cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), + cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), + cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), + cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), + cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), + cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), + cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), + cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), + + /* Monadic operations. */ + cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), + + /* Dyadic operations. */ + cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), + + /* Comparisons. */ + cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), + cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), + cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), + +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ + + /* Moves and type conversions. */ + cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), + cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), + cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), + cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), + cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), + cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), + cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), + cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), + cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), + cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), + + /* Memory operations. */ + cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), + cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), + cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), + cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), + cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), + cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), + cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), + cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), + cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), + cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), + + /* Monadic operations. */ + cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), + cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), + cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), + + /* Dyadic operations. */ + cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), + + /* Comparisons. */ + cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), + cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), + cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), + cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), + +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_vfp_ext_v2 + + cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), + cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), + cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), + cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), + +/* Instructions which may belong to either the Neon or VFP instruction sets. + Individual encoder functions perform additional architecture checks. */ +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_vfp_ext_v1xd +#undef THUMB_VARIANT +#define THUMB_VARIANT & fpu_vfp_ext_v1xd + + /* These mnemonics are unique to VFP. */ + NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), + NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), + nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), + nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), + nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), + nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), + nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), + NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), + NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), + NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), + + /* Mnemonics shared by Neon and VFP. */ + nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), + nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), + nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), + + nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), + nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), + + NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), + NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), + + NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), + NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), + NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), + NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), + NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), + NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), + NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), + NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), + + nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), + nCEF(vcvtb, vcvt, 2, (RVS, RVS), neon_cvtb), + nCEF(vcvtt, vcvt, 2, (RVS, RVS), neon_cvtt), + + + /* NOTE: All VMOV encoding is special-cased! */ + NCE(vmov, 0, 1, (VMOV), neon_mov), + NCE(vmovq, 0, 1, (VMOV), neon_mov), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & fpu_neon_ext_v1 +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_neon_ext_v1 + + /* Data processing with three registers of the same length. */ + /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ + NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), + NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), + NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), + NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), + NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), + NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), + NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), + NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), + /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ + NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), + NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), + NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), + NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), + NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), + NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), + NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), + NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), + /* If not immediate, fall back to neon_dyadic_i64_su. + shl_imm should accept I8 I16 I32 I64, + qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ + nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), + nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), + nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), + nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), + /* Logic ops, types optional & ignored. */ + nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), + nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), + nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), + nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), + nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), + nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), + nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), + nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), + nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), + nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), + /* Bitfield ops, untyped. */ + NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), + NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), + NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), + NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), + NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), + NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), + /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ + nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), + nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), + nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), + nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), + nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), + nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), + /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall + back to neon_dyadic_if_su. */ + nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), + nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), + nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), + nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), + nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), + nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), + nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), + nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), + /* Comparison. Type I8 I16 I32 F32. */ + nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), + nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), + /* As above, D registers only. */ + nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), + nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), + /* Int and float variants, signedness unimportant. */ + nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), + nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), + nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), + /* Add/sub take types I8 I16 I32 I64 F32. */ + nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), + nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), + /* vtst takes sizes 8, 16, 32. */ + NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), + NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), + /* VMUL takes I8 I16 I32 F32 P8. */ + nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), + /* VQD{R}MULH takes S16 S32. */ + nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), + nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), + nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), + nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), + NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), + NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), + NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), + NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), + NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), + NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), + NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), + NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), + NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), + NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), + NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), + NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), + + /* Two address, int/float. Types S8 S16 S32 F32. */ + NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), + NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), + + /* Data processing with two registers and a shift amount. */ + /* Right shifts, and variants with rounding. + Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ + NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), + NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), + NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), + NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), + NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), + NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), + NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), + NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), + /* Shift and insert. Sizes accepted 8 16 32 64. */ + NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), + NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), + NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), + NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), + /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ + NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), + NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), + /* Right shift immediate, saturating & narrowing, with rounding variants. + Types accepted S16 S32 S64 U16 U32 U64. */ + NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), + NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), + /* As above, unsigned. Types accepted S16 S32 S64. */ + NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), + NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), + /* Right shift narrowing. Types accepted I16 I32 I64. */ + NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), + NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), + /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ + nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), + /* CVT with optional immediate for fixed-point variant. */ + nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), + + nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), + nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), + + /* Data processing, three registers of different lengths. */ + /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ + NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), + NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), + NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), + NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), + /* If not scalar, fall back to neon_dyadic_long. + Vector types as above, scalar types S16 S32 U16 U32. */ + nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), + nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), + /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ + NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), + NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), + /* Dyadic, narrowing insns. Types I16 I32 I64. */ + NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), + NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), + NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), + NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), + /* Saturating doubling multiplies. Types S16 S32. */ + nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), + nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), + nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), + /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types + S16 S32 U16 U32. */ + nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), + + /* Extract. Size 8. */ + NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), + NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), + + /* Two registers, miscellaneous. */ + /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ + NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), + NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), + NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), + NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), + NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), + NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), + /* Vector replicate. Sizes 8 16 32. */ + nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), + nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), + /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ + NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), + /* VMOVN. Types I16 I32 I64. */ + nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), + /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ + nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), + /* VQMOVUN. Types S16 S32 S64. */ + nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), + /* VZIP / VUZP. Sizes 8 16 32. */ + NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), + NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), + NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), + NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), + /* VQABS / VQNEG. Types S8 S16 S32. */ + NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), + NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), + NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), + NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), + /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ + NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), + NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), + NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), + NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), + /* Reciprocal estimates. Types U32 F32. */ + NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), + NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), + NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), + NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), + /* VCLS. Types S8 S16 S32. */ + NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), + NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), + /* VCLZ. Types I8 I16 I32. */ + NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), + NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), + /* VCNT. Size 8. */ + NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), + NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), + /* Two address, untyped. */ + NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), + NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), + /* VTRN. Sizes 8 16 32. */ + nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), + nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), + + /* Table lookup. Size 8. */ + NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), + NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext + + /* Neon element/structure load/store. */ + nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), + nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), + nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), + nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), + nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), + nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), + nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), + nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), + +#undef THUMB_VARIANT +#define THUMB_VARIANT & fpu_vfp_ext_v3 +#undef ARM_VARIANT +#define ARM_VARIANT & fpu_vfp_ext_v3 + + cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), + cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), + cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), + cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), + cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), + cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), + cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), + cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), + cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), + cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), + cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), + cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), + cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), + cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), + cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), + cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), + cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), + cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), + +#undef THUMB_VARIANT +#undef ARM_VARIANT +#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ + + cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), + cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), + cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ + + cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), + cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), + cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), + cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), + cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), + cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), + cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), + cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), + cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), + cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), + cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), + cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), + cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), + cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), + cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), + cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), + cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), + cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), + cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), + cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), + cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), + cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), + cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), + cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), + cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), + cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), + cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), + cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), + cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), + cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), + cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), + cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), + cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), + cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), + cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), + cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), + cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), + cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), + cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), + cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), + cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), + cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ + + cCE(torvscb, e12f190, 1, (RR), iwmmxt_tandorc), + cCE(torvsch, e52f190, 1, (RR), iwmmxt_tandorc), + cCE(torvscw, e92f190, 1, (RR), iwmmxt_tandorc), + cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn), + cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn), + cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn), + cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), + cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ + + cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), + cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), + cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), + cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), + cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), + cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), + cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), + cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), + cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), + cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), + cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), + cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), + cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), + cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), + cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), + cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), + cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), + cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), + cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), + cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), + cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), + cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), + cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), + cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), + cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), + cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), + cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), + cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), + cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), + cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), + cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), + cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), + cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), + cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), + cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), + cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), + cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), + cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), + cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), + cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), + cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), + cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), + cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), + cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), + cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), + cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), + cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), + cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), + cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), + cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), + cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), + cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), + cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), + cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), + cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), + cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), + cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), + cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), + cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), + cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), + cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), + cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), + cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), + cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), + cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), + cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), + cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), + cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), + cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), + cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), + cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), + cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), +}; +#undef ARM_VARIANT +#undef THUMB_VARIANT +#undef TCE +#undef TCM +#undef TUE +#undef TUF +#undef TCC +#undef cCE +#undef cCL +#undef C3E +#undef CE +#undef CM +#undef UE +#undef UF +#undef UT +#undef NUF +#undef nUF +#undef NCE +#undef nCE +#undef OPS0 +#undef OPS1 +#undef OPS2 +#undef OPS3 +#undef OPS4 +#undef OPS5 +#undef OPS6 +#undef do_0 + +/* MD interface: bits in the object file. */ + +/* Turn an integer of n bytes (in val) into a stream of bytes appropriate + for use in the a.out file, and stores them in the array pointed to by buf. + This knows about the endian-ness of the target machine and does + THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) + 2 (short) and 4 (long) Floating numbers are put out as a series of + LITTLENUMS (shorts, here at least). */ + +void +md_number_to_chars (char * buf, valueT val, int n) +{ + if (target_big_endian) + number_to_chars_bigendian (buf, val, n); + else + number_to_chars_littleendian (buf, val, n); +} + +static valueT +md_chars_to_number (char * buf, int n) +{ + valueT result = 0; + unsigned char * where = (unsigned char *) buf; + + if (target_big_endian) + { + while (n--) + { + result <<= 8; + result |= (*where++ & 255); + } + } + else + { + while (n--) + { + result <<= 8; + result |= (where[n] & 255); + } + } + + return result; +} + +/* MD interface: Sections. */ + +/* Estimate the size of a frag before relaxing. Assume everything fits in + 2 bytes. */ + +int +md_estimate_size_before_relax (fragS * fragp, + segT segtype ATTRIBUTE_UNUSED) +{ + fragp->fr_var = 2; + return 2; +} + +/* Convert a machine dependent frag. */ + +void +md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) +{ + unsigned long insn; + unsigned long old_op; + char *buf; + expressionS exp; + fixS *fixp; + int reloc_type; + int pc_rel; + int opcode; + + buf = fragp->fr_literal + fragp->fr_fix; + + old_op = bfd_get_16(abfd, buf); + if (fragp->fr_symbol) + { + exp.X_op = O_symbol; + exp.X_add_symbol = fragp->fr_symbol; + } + else + { + exp.X_op = O_constant; + } + exp.X_add_number = fragp->fr_offset; + opcode = fragp->fr_subtype; + switch (opcode) + { + case T_MNEM_ldr_pc: + case T_MNEM_ldr_pc2: + case T_MNEM_ldr_sp: + case T_MNEM_str_sp: + case T_MNEM_ldr: + case T_MNEM_ldrb: + case T_MNEM_ldrh: + case T_MNEM_str: + case T_MNEM_strb: + case T_MNEM_strh: + if (fragp->fr_var == 4) + { + insn = THUMB_OP32 (opcode); + if ((old_op >> 12) == 4 || (old_op >> 12) == 9) + { + insn |= (old_op & 0x700) << 4; + } + else + { + insn |= (old_op & 7) << 12; + insn |= (old_op & 0x38) << 13; + } + insn |= 0x00000c00; + put_thumb32_insn (buf, insn); + reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; + } + else + { + reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; + } + pc_rel = (opcode == T_MNEM_ldr_pc2); + break; + case T_MNEM_adr: + if (fragp->fr_var == 4) + { + insn = THUMB_OP32 (opcode); + insn |= (old_op & 0xf0) << 4; + put_thumb32_insn (buf, insn); + reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; + } + else + { + reloc_type = BFD_RELOC_ARM_THUMB_ADD; + exp.X_add_number -= 4; + } + pc_rel = 1; + break; + case T_MNEM_mov: + case T_MNEM_movs: + case T_MNEM_cmp: + case T_MNEM_cmn: + if (fragp->fr_var == 4) + { + int r0off = (opcode == T_MNEM_mov + || opcode == T_MNEM_movs) ? 0 : 8; + insn = THUMB_OP32 (opcode); + insn = (insn & 0xe1ffffff) | 0x10000000; + insn |= (old_op & 0x700) << r0off; + put_thumb32_insn (buf, insn); + reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; + } + else + { + reloc_type = BFD_RELOC_ARM_THUMB_IMM; + } + pc_rel = 0; + break; + case T_MNEM_b: + if (fragp->fr_var == 4) + { + insn = THUMB_OP32(opcode); + put_thumb32_insn (buf, insn); + reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; + } + else + reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; + pc_rel = 1; + break; + case T_MNEM_bcond: + if (fragp->fr_var == 4) + { + insn = THUMB_OP32(opcode); + insn |= (old_op & 0xf00) << 14; + put_thumb32_insn (buf, insn); + reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; + } + else + reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; + pc_rel = 1; + break; + case T_MNEM_add_sp: + case T_MNEM_add_pc: + case T_MNEM_inc_sp: + case T_MNEM_dec_sp: + if (fragp->fr_var == 4) + { + /* ??? Choose between add and addw. */ + insn = THUMB_OP32 (opcode); + insn |= (old_op & 0xf0) << 4; + put_thumb32_insn (buf, insn); + if (opcode == T_MNEM_add_pc) + reloc_type = BFD_RELOC_ARM_T32_IMM12; + else + reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; + } + else + reloc_type = BFD_RELOC_ARM_THUMB_ADD; + pc_rel = 0; + break; + + case T_MNEM_addi: + case T_MNEM_addis: + case T_MNEM_subi: + case T_MNEM_subis: + if (fragp->fr_var == 4) + { + insn = THUMB_OP32 (opcode); + insn |= (old_op & 0xf0) << 4; + insn |= (old_op & 0xf) << 16; + put_thumb32_insn (buf, insn); + if (insn & (1 << 20)) + reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; + else + reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; + } + else + reloc_type = BFD_RELOC_ARM_THUMB_ADD; + pc_rel = 0; + break; + default: + abort (); + } + fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, + reloc_type); + fixp->fx_file = fragp->fr_file; + fixp->fx_line = fragp->fr_line; + fragp->fr_fix += fragp->fr_var; +} + +/* Return the size of a relaxable immediate operand instruction. + SHIFT and SIZE specify the form of the allowable immediate. */ +static int +relax_immediate (fragS *fragp, int size, int shift) +{ + offsetT offset; + offsetT mask; + offsetT low; + + /* ??? Should be able to do better than this. */ + if (fragp->fr_symbol) + return 4; + + low = (1 << shift) - 1; + mask = (1 << (shift + size)) - (1 << shift); + offset = fragp->fr_offset; + /* Force misaligned offsets to 32-bit variant. */ + if (offset & low) + return 4; + if (offset & ~mask) + return 4; + return 2; +} + +/* Get the address of a symbol during relaxation. */ +static addressT +relaxed_symbol_addr (fragS *fragp, long stretch) +{ + fragS *sym_frag; + addressT addr; + symbolS *sym; + + sym = fragp->fr_symbol; + sym_frag = symbol_get_frag (sym); + know (S_GET_SEGMENT (sym) != absolute_section + || sym_frag == &zero_address_frag); + addr = S_GET_VALUE (sym) + fragp->fr_offset; + + /* If frag has yet to be reached on this pass, assume it will + move by STRETCH just as we did. If this is not so, it will + be because some frag between grows, and that will force + another pass. */ + + if (stretch != 0 + && sym_frag->relax_marker != fragp->relax_marker) + { + fragS *f; + + /* Adjust stretch for any alignment frag. Note that if have + been expanding the earlier code, the symbol may be + defined in what appears to be an earlier frag. FIXME: + This doesn't handle the fr_subtype field, which specifies + a maximum number of bytes to skip when doing an + alignment. */ + for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) + { + if (f->fr_type == rs_align || f->fr_type == rs_align_code) + { + if (stretch < 0) + stretch = - ((- stretch) + & ~ ((1 << (int) f->fr_offset) - 1)); + else + stretch &= ~ ((1 << (int) f->fr_offset) - 1); + if (stretch == 0) + break; + } + } + if (f != NULL) + addr += stretch; + } + + return addr; +} + +/* Return the size of a relaxable adr pseudo-instruction or PC-relative + load. */ +static int +relax_adr (fragS *fragp, asection *sec, long stretch) +{ + addressT addr; + offsetT val; + + /* Assume worst case for symbols not known to be in the same section. */ + if (!S_IS_DEFINED (fragp->fr_symbol) + || sec != S_GET_SEGMENT (fragp->fr_symbol)) + return 4; + + val = relaxed_symbol_addr (fragp, stretch); + addr = fragp->fr_address + fragp->fr_fix; + addr = (addr + 4) & ~3; + /* Force misaligned targets to 32-bit variant. */ + if (val & 3) + return 4; + val -= addr; + if (val < 0 || val > 1020) + return 4; + return 2; +} + +/* Return the size of a relaxable add/sub immediate instruction. */ +static int +relax_addsub (fragS *fragp, asection *sec) +{ + char *buf; + int op; + + buf = fragp->fr_literal + fragp->fr_fix; + op = bfd_get_16(sec->owner, buf); + if ((op & 0xf) == ((op >> 4) & 0xf)) + return relax_immediate (fragp, 8, 0); + else + return relax_immediate (fragp, 3, 0); +} + + +/* Return the size of a relaxable branch instruction. BITS is the + size of the offset field in the narrow instruction. */ + +static int +relax_branch (fragS *fragp, asection *sec, int bits, long stretch) +{ + addressT addr; + offsetT val; + offsetT limit; + + /* Assume worst case for symbols not known to be in the same section. */ + if (!S_IS_DEFINED (fragp->fr_symbol) + || sec != S_GET_SEGMENT (fragp->fr_symbol)) + return 4; + +#ifdef OBJ_ELF + if (S_IS_DEFINED (fragp->fr_symbol) + && ARM_IS_FUNC (fragp->fr_symbol)) + return 4; +#endif + + val = relaxed_symbol_addr (fragp, stretch); + addr = fragp->fr_address + fragp->fr_fix + 4; + val -= addr; + + /* Offset is a signed value *2 */ + limit = 1 << bits; + if (val >= limit || val < -limit) + return 4; + return 2; +} + + +/* Relax a machine dependent frag. This returns the amount by which + the current size of the frag should change. */ + +int +arm_relax_frag (asection *sec, fragS *fragp, long stretch) +{ + int oldsize; + int newsize; + + oldsize = fragp->fr_var; + switch (fragp->fr_subtype) + { + case T_MNEM_ldr_pc2: + newsize = relax_adr (fragp, sec, stretch); + break; + case T_MNEM_ldr_pc: + case T_MNEM_ldr_sp: + case T_MNEM_str_sp: + newsize = relax_immediate (fragp, 8, 2); + break; + case T_MNEM_ldr: + case T_MNEM_str: + newsize = relax_immediate (fragp, 5, 2); + break; + case T_MNEM_ldrh: + case T_MNEM_strh: + newsize = relax_immediate (fragp, 5, 1); + break; + case T_MNEM_ldrb: + case T_MNEM_strb: + newsize = relax_immediate (fragp, 5, 0); + break; + case T_MNEM_adr: + newsize = relax_adr (fragp, sec, stretch); + break; + case T_MNEM_mov: + case T_MNEM_movs: + case T_MNEM_cmp: + case T_MNEM_cmn: + newsize = relax_immediate (fragp, 8, 0); + break; + case T_MNEM_b: + newsize = relax_branch (fragp, sec, 11, stretch); + break; + case T_MNEM_bcond: + newsize = relax_branch (fragp, sec, 8, stretch); + break; + case T_MNEM_add_sp: + case T_MNEM_add_pc: + newsize = relax_immediate (fragp, 8, 2); + break; + case T_MNEM_inc_sp: + case T_MNEM_dec_sp: + newsize = relax_immediate (fragp, 7, 2); + break; + case T_MNEM_addi: + case T_MNEM_addis: + case T_MNEM_subi: + case T_MNEM_subis: + newsize = relax_addsub (fragp, sec); + break; + default: + abort (); + } + + fragp->fr_var = newsize; + /* Freeze wide instructions that are at or before the same location as + in the previous pass. This avoids infinite loops. + Don't freeze them unconditionally because targets may be artificially + misaligned by the expansion of preceding frags. */ + if (stretch <= 0 && newsize > 2) + { + md_convert_frag (sec->owner, sec, fragp); + frag_wane (fragp); + } + + return newsize - oldsize; +} + +/* Round up a section size to the appropriate boundary. */ + +valueT +md_section_align (segT segment ATTRIBUTE_UNUSED, + valueT size) +{ +#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) + if (OUTPUT_FLAVOR == bfd_target_aout_flavour) + { + /* For a.out, force the section size to be aligned. If we don't do + this, BFD will align it for us, but it will not write out the + final bytes of the section. This may be a bug in BFD, but it is + easier to fix it here since that is how the other a.out targets + work. */ + int align; + + align = bfd_get_section_alignment (stdoutput, segment); + size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); + } +#endif + + return size; +} + +/* This is called from HANDLE_ALIGN in write.c. Fill in the contents + of an rs_align_code fragment. */ + +void +arm_handle_align (fragS * fragP) +{ + static char const arm_noop[2][2][4] = + { + { /* ARMv1 */ + {0x00, 0x00, 0xa0, 0xe1}, /* LE */ + {0xe1, 0xa0, 0x00, 0x00}, /* BE */ + }, + { /* ARMv6k */ + {0x00, 0xf0, 0x20, 0xe3}, /* LE */ + {0xe3, 0x20, 0xf0, 0x00}, /* BE */ + }, + }; + static char const thumb_noop[2][2][2] = + { + { /* Thumb-1 */ + {0xc0, 0x46}, /* LE */ + {0x46, 0xc0}, /* BE */ + }, + { /* Thumb-2 */ + {0x00, 0xbf}, /* LE */ + {0xbf, 0x00} /* BE */ + } + }; + static char const wide_thumb_noop[2][4] = + { /* Wide Thumb-2 */ + {0xaf, 0xf3, 0x00, 0x80}, /* LE */ + {0xf3, 0xaf, 0x80, 0x00}, /* BE */ + }; + + unsigned bytes, fix, noop_size; + char * p; + const char * noop; + const char *narrow_noop = NULL; +#ifdef OBJ_ELF + enum mstate state; +#endif + + if (fragP->fr_type != rs_align_code) + return; + + bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; + p = fragP->fr_literal + fragP->fr_fix; + fix = 0; + + if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) + bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; + +#ifdef OBJ_ELF + gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); +#endif + + if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) + { + if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) + { + narrow_noop = thumb_noop[1][target_big_endian]; + noop = wide_thumb_noop[target_big_endian]; + } + else + noop = thumb_noop[0][target_big_endian]; + noop_size = 2; +#ifdef OBJ_ELF + state = MAP_THUMB; +#endif + } + else + { + noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] + [target_big_endian]; + noop_size = 4; +#ifdef OBJ_ELF + state = MAP_ARM; +#endif + } + + fragP->fr_var = noop_size; + + if (bytes & (noop_size - 1)) + { + fix = bytes & (noop_size - 1); +#ifdef OBJ_ELF + insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); +#endif + memset (p, 0, fix); + p += fix; + bytes -= fix; + } + + if (narrow_noop) + { + if (bytes & noop_size) + { + /* Insert a narrow noop. */ + memcpy (p, narrow_noop, noop_size); + p += noop_size; + bytes -= noop_size; + fix += noop_size; + } + + /* Use wide noops for the remainder */ + noop_size = 4; + } + + while (bytes >= noop_size) + { + memcpy (p, noop, noop_size); + p += noop_size; + bytes -= noop_size; + fix += noop_size; + } + + fragP->fr_fix += fix; +} + +/* Called from md_do_align. Used to create an alignment + frag in a code section. */ + +void +arm_frag_align_code (int n, int max) +{ + char * p; + + /* We assume that there will never be a requirement + to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ + if (max > MAX_MEM_FOR_RS_ALIGN_CODE) + { + char err_msg[128]; + + sprintf (err_msg, + _("alignments greater than %d bytes not supported in .text sections."), + MAX_MEM_FOR_RS_ALIGN_CODE + 1); + as_fatal ("%s", err_msg); + } + + p = frag_var (rs_align_code, + MAX_MEM_FOR_RS_ALIGN_CODE, + 1, + (relax_substateT) max, + (symbolS *) NULL, + (offsetT) n, + (char *) NULL); + *p = 0; +} + +/* Perform target specific initialisation of a frag. + Note - despite the name this initialisation is not done when the frag + is created, but only when its type is assigned. A frag can be created + and used a long time before its type is set, so beware of assuming that + this initialisationis performed first. */ + +#ifndef OBJ_ELF +void +arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) +{ + /* Record whether this frag is in an ARM or a THUMB area. */ + fragP->tc_frag_data.thumb_mode = thumb_mode; +} + +#else /* OBJ_ELF is defined. */ +void +arm_init_frag (fragS * fragP, int max_chars) +{ + /* If the current ARM vs THUMB mode has not already + been recorded into this frag then do so now. */ + if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) + { + fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; + + /* Record a mapping symbol for alignment frags. We will delete this + later if the alignment ends up empty. */ + switch (fragP->fr_type) + { + case rs_align: + case rs_align_test: + case rs_fill: + mapping_state_2 (MAP_DATA, max_chars); + break; + case rs_align_code: + mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); + break; + default: + break; + } + } +} + +/* When we change sections we need to issue a new mapping symbol. */ + +void +arm_elf_change_section (void) +{ + /* Link an unlinked unwind index table section to the .text section. */ + if (elf_section_type (now_seg) == SHT_ARM_EXIDX + && elf_linked_to_section (now_seg) == NULL) + elf_linked_to_section (now_seg) = text_section; +} + +int +arm_elf_section_type (const char * str, size_t len) +{ + if (len == 5 && strncmp (str, "exidx", 5) == 0) + return SHT_ARM_EXIDX; + + return -1; +} + +/* Code to deal with unwinding tables. */ + +static void add_unwind_adjustsp (offsetT); + +/* Generate any deferred unwind frame offset. */ + +static void +flush_pending_unwind (void) +{ + offsetT offset; + + offset = unwind.pending_offset; + unwind.pending_offset = 0; + if (offset != 0) + add_unwind_adjustsp (offset); +} + +/* Add an opcode to this list for this function. Two-byte opcodes should + be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse + order. */ + +static void +add_unwind_opcode (valueT op, int length) +{ + /* Add any deferred stack adjustment. */ + if (unwind.pending_offset) + flush_pending_unwind (); + + unwind.sp_restored = 0; + + if (unwind.opcode_count + length > unwind.opcode_alloc) + { + unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; + if (unwind.opcodes) + unwind.opcodes = xrealloc (unwind.opcodes, + unwind.opcode_alloc); + else + unwind.opcodes = xmalloc (unwind.opcode_alloc); + } + while (length > 0) + { + length--; + unwind.opcodes[unwind.opcode_count] = op & 0xff; + op >>= 8; + unwind.opcode_count++; + } +} + +/* Add unwind opcodes to adjust the stack pointer. */ + +static void +add_unwind_adjustsp (offsetT offset) +{ + valueT op; + + if (offset > 0x200) + { + /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ + char bytes[5]; + int n; + valueT o; + + /* Long form: 0xb2, uleb128. */ + /* This might not fit in a word so add the individual bytes, + remembering the list is built in reverse order. */ + o = (valueT) ((offset - 0x204) >> 2); + if (o == 0) + add_unwind_opcode (0, 1); + + /* Calculate the uleb128 encoding of the offset. */ + n = 0; + while (o) + { + bytes[n] = o & 0x7f; + o >>= 7; + if (o) + bytes[n] |= 0x80; + n++; + } + /* Add the insn. */ + for (; n; n--) + add_unwind_opcode (bytes[n - 1], 1); + add_unwind_opcode (0xb2, 1); + } + else if (offset > 0x100) + { + /* Two short opcodes. */ + add_unwind_opcode (0x3f, 1); + op = (offset - 0x104) >> 2; + add_unwind_opcode (op, 1); + } + else if (offset > 0) + { + /* Short opcode. */ + op = (offset - 4) >> 2; + add_unwind_opcode (op, 1); + } + else if (offset < 0) + { + offset = -offset; + while (offset > 0x100) + { + add_unwind_opcode (0x7f, 1); + offset -= 0x100; + } + op = ((offset - 4) >> 2) | 0x40; + add_unwind_opcode (op, 1); + } +} + +/* Finish the list of unwind opcodes for this function. */ +static void +finish_unwind_opcodes (void) +{ + valueT op; + + if (unwind.fp_used) + { + /* Adjust sp as necessary. */ + unwind.pending_offset += unwind.fp_offset - unwind.frame_size; + flush_pending_unwind (); + + /* After restoring sp from the frame pointer. */ + op = 0x90 | unwind.fp_reg; + add_unwind_opcode (op, 1); + } + else + flush_pending_unwind (); +} + + +/* Start an exception table entry. If idx is nonzero this is an index table + entry. */ + +static void +start_unwind_section (const segT text_seg, int idx) +{ + const char * text_name; + const char * prefix; + const char * prefix_once; + const char * group_name; + size_t prefix_len; + size_t text_len; + char * sec_name; + size_t sec_name_len; + int type; + int flags; + int linkonce; + + if (idx) + { + prefix = ELF_STRING_ARM_unwind; + prefix_once = ELF_STRING_ARM_unwind_once; + type = SHT_ARM_EXIDX; + } + else + { + prefix = ELF_STRING_ARM_unwind_info; + prefix_once = ELF_STRING_ARM_unwind_info_once; + type = SHT_PROGBITS; + } + + text_name = segment_name (text_seg); + if (streq (text_name, ".text")) + text_name = ""; + + if (strncmp (text_name, ".gnu.linkonce.t.", + strlen (".gnu.linkonce.t.")) == 0) + { + prefix = prefix_once; + text_name += strlen (".gnu.linkonce.t."); + } + + prefix_len = strlen (prefix); + text_len = strlen (text_name); + sec_name_len = prefix_len + text_len; + sec_name = xmalloc (sec_name_len + 1); + memcpy (sec_name, prefix, prefix_len); + memcpy (sec_name + prefix_len, text_name, text_len); + sec_name[prefix_len + text_len] = '\0'; + + flags = SHF_ALLOC; + linkonce = 0; + group_name = 0; + + /* Handle COMDAT group. */ + if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) + { + group_name = elf_group_name (text_seg); + if (group_name == NULL) + { + as_bad (_("Group section `%s' has no group signature"), + segment_name (text_seg)); + ignore_rest_of_line (); + return; + } + flags |= SHF_GROUP; + linkonce = 1; + } + + obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); + + /* Set the section link for index tables. */ + if (idx) + elf_linked_to_section (now_seg) = text_seg; +} + + +/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional + personality routine data. Returns zero, or the index table value for + and inline entry. */ + +static valueT +create_unwind_entry (int have_data) +{ + int size; + addressT where; + char *ptr; + /* The current word of data. */ + valueT data; + /* The number of bytes left in this word. */ + int n; + + finish_unwind_opcodes (); + + /* Remember the current text section. */ + unwind.saved_seg = now_seg; + unwind.saved_subseg = now_subseg; + + start_unwind_section (now_seg, 0); + + if (unwind.personality_routine == NULL) + { + if (unwind.personality_index == -2) + { + if (have_data) + as_bad (_("handlerdata in cantunwind frame")); + return 1; /* EXIDX_CANTUNWIND. */ + } + + /* Use a default personality routine if none is specified. */ + if (unwind.personality_index == -1) + { + if (unwind.opcode_count > 3) + unwind.personality_index = 1; + else + unwind.personality_index = 0; + } + + /* Space for the personality routine entry. */ + if (unwind.personality_index == 0) + { + if (unwind.opcode_count > 3) + as_bad (_("too many unwind opcodes for personality routine 0")); + + if (!have_data) + { + /* All the data is inline in the index table. */ + data = 0x80; + n = 3; + while (unwind.opcode_count > 0) + { + unwind.opcode_count--; + data = (data << 8) | unwind.opcodes[unwind.opcode_count]; + n--; + } + + /* Pad with "finish" opcodes. */ + while (n--) + data = (data << 8) | 0xb0; + + return data; + } + size = 0; + } + else + /* We get two opcodes "free" in the first word. */ + size = unwind.opcode_count - 2; + } + else + /* An extra byte is required for the opcode count. */ + size = unwind.opcode_count + 1; + + size = (size + 3) >> 2; + if (size > 0xff) + as_bad (_("too many unwind opcodes")); + + frag_align (2, 0, 0); + record_alignment (now_seg, 2); + unwind.table_entry = expr_build_dot (); + + /* Allocate the table entry. */ + ptr = frag_more ((size << 2) + 4); + where = frag_now_fix () - ((size << 2) + 4); + + switch (unwind.personality_index) + { + case -1: + /* ??? Should this be a PLT generating relocation? */ + /* Custom personality routine. */ + fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, + BFD_RELOC_ARM_PREL31); + + where += 4; + ptr += 4; + + /* Set the first byte to the number of additional words. */ + data = size - 1; + n = 3; + break; + + /* ABI defined personality routines. */ + case 0: + /* Three opcodes bytes are packed into the first word. */ + data = 0x80; + n = 3; + break; + + case 1: + case 2: + /* The size and first two opcode bytes go in the first word. */ + data = ((0x80 + unwind.personality_index) << 8) | size; + n = 2; + break; + + default: + /* Should never happen. */ + abort (); + } + + /* Pack the opcodes into words (MSB first), reversing the list at the same + time. */ + while (unwind.opcode_count > 0) + { + if (n == 0) + { + md_number_to_chars (ptr, data, 4); + ptr += 4; + n = 4; + data = 0; + } + unwind.opcode_count--; + n--; + data = (data << 8) | unwind.opcodes[unwind.opcode_count]; + } + + /* Finish off the last word. */ + if (n < 4) + { + /* Pad with "finish" opcodes. */ + while (n--) + data = (data << 8) | 0xb0; + + md_number_to_chars (ptr, data, 4); + } + + if (!have_data) + { + /* Add an empty descriptor if there is no user-specified data. */ + ptr = frag_more (4); + md_number_to_chars (ptr, 0, 4); + } + + return 0; +} + + +/* Initialize the DWARF-2 unwind information for this procedure. */ + +void +tc_arm_frame_initial_instructions (void) +{ + cfi_add_CFA_def_cfa (REG_SP, 0); +} +#endif /* OBJ_ELF */ + +/* Convert REGNAME to a DWARF-2 register number. */ + +int +tc_arm_regname_to_dw2regnum (char *regname) +{ + int reg = arm_reg_parse (®name, REG_TYPE_RN); + + if (reg == FAIL) + return -1; + + return reg; +} + +#ifdef TE_PE +void +tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) +{ + expressionS expr; + + expr.X_op = O_secrel; + expr.X_add_symbol = symbol; + expr.X_add_number = 0; + emit_expr (&expr, size); +} +#endif + +/* MD interface: Symbol and relocation handling. */ + +/* Return the address within the segment that a PC-relative fixup is + relative to. For ARM, PC-relative fixups applied to instructions + are generally relative to the location of the fixup plus 8 bytes. + Thumb branches are offset by 4, and Thumb loads relative to PC + require special handling. */ + +long +md_pcrel_from_section (fixS * fixP, segT seg) +{ + offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; + + /* If this is pc-relative and we are going to emit a relocation + then we just want to put out any pipeline compensation that the linker + will need. Otherwise we want to use the calculated base. + For WinCE we skip the bias for externals as well, since this + is how the MS ARM-CE assembler behaves and we want to be compatible. */ + if (fixP->fx_pcrel + && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) + || (arm_force_relocation (fixP) +#ifdef TE_WINCE + && !S_IS_EXTERNAL (fixP->fx_addsy) +#endif + ))) + base = 0; + + + switch (fixP->fx_r_type) + { + /* PC relative addressing on the Thumb is slightly odd as the + bottom two bits of the PC are forced to zero for the + calculation. This happens *after* application of the + pipeline offset. However, Thumb adrl already adjusts for + this, so we need not do it again. */ + case BFD_RELOC_ARM_THUMB_ADD: + return base & ~3; + + case BFD_RELOC_ARM_THUMB_OFFSET: + case BFD_RELOC_ARM_T32_OFFSET_IMM: + case BFD_RELOC_ARM_T32_ADD_PC12: + case BFD_RELOC_ARM_T32_CP_OFF_IMM: + return (base + 4) & ~3; + + /* Thumb branches are simply offset by +4. */ + case BFD_RELOC_THUMB_PCREL_BRANCH7: + case BFD_RELOC_THUMB_PCREL_BRANCH9: + case BFD_RELOC_THUMB_PCREL_BRANCH12: + case BFD_RELOC_THUMB_PCREL_BRANCH20: + case BFD_RELOC_THUMB_PCREL_BRANCH25: + return base + 4; + + case BFD_RELOC_THUMB_PCREL_BRANCH23: + if (fixP->fx_addsy + && ARM_IS_FUNC (fixP->fx_addsy) + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) + base = fixP->fx_where + fixP->fx_frag->fr_address; + return base + 4; + + /* BLX is like branches above, but forces the low two bits of PC to + zero. */ + case BFD_RELOC_THUMB_PCREL_BLX: + if (fixP->fx_addsy + && THUMB_IS_FUNC (fixP->fx_addsy) + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) + base = fixP->fx_where + fixP->fx_frag->fr_address; + return (base + 4) & ~3; + + /* ARM mode branches are offset by +8. However, the Windows CE + loader expects the relocation not to take this into account. */ + case BFD_RELOC_ARM_PCREL_BLX: + if (fixP->fx_addsy + && ARM_IS_FUNC (fixP->fx_addsy) + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) + base = fixP->fx_where + fixP->fx_frag->fr_address; + return base + 8; + + case BFD_RELOC_ARM_PCREL_CALL: + if (fixP->fx_addsy + && THUMB_IS_FUNC (fixP->fx_addsy) + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) + base = fixP->fx_where + fixP->fx_frag->fr_address; + return base + 8; + + case BFD_RELOC_ARM_PCREL_BRANCH: + case BFD_RELOC_ARM_PCREL_JUMP: + case BFD_RELOC_ARM_PLT32: +#ifdef TE_WINCE + /* When handling fixups immediately, because we have already + discovered the value of a symbol, or the address of the frag involved + we must account for the offset by +8, as the OS loader will never see the reloc. + see fixup_segment() in write.c + The S_IS_EXTERNAL test handles the case of global symbols. + Those need the calculated base, not just the pipe compensation the linker will need. */ + if (fixP->fx_pcrel + && fixP->fx_addsy != NULL + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) + return base + 8; + return base; +#else + return base + 8; +#endif + + + /* ARM mode loads relative to PC are also offset by +8. Unlike + branches, the Windows CE loader *does* expect the relocation + to take this into account. */ + case BFD_RELOC_ARM_OFFSET_IMM: + case BFD_RELOC_ARM_OFFSET_IMM8: + case BFD_RELOC_ARM_HWLITERAL: + case BFD_RELOC_ARM_LITERAL: + case BFD_RELOC_ARM_CP_OFF_IMM: + return base + 8; + + + /* Other PC-relative relocations are un-offset. */ + default: + return base; + } +} + +/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. + Otherwise we have no need to default values of symbols. */ + +symbolS * +md_undefined_symbol (char * name ATTRIBUTE_UNUSED) +{ +#ifdef OBJ_ELF + if (name[0] == '_' && name[1] == 'G' + && streq (name, GLOBAL_OFFSET_TABLE_NAME)) + { + if (!GOT_symbol) + { + if (symbol_find (name)) + as_bad (_("GOT already in the symbol table")); + + GOT_symbol = symbol_new (name, undefined_section, + (valueT) 0, & zero_address_frag); + } + + return GOT_symbol; + } +#endif + + return NULL; +} + +/* Subroutine of md_apply_fix. Check to see if an immediate can be + computed as two separate immediate values, added together. We + already know that this value cannot be computed by just one ARM + instruction. */ + +static unsigned int +validate_immediate_twopart (unsigned int val, + unsigned int * highpart) +{ + unsigned int a; + unsigned int i; + + for (i = 0; i < 32; i += 2) + if (((a = rotate_left (val, i)) & 0xff) != 0) + { + if (a & 0xff00) + { + if (a & ~ 0xffff) + continue; + * highpart = (a >> 8) | ((i + 24) << 7); + } + else if (a & 0xff0000) + { + if (a & 0xff000000) + continue; + * highpart = (a >> 16) | ((i + 16) << 7); + } + else + { + gas_assert (a & 0xff000000); + * highpart = (a >> 24) | ((i + 8) << 7); + } + + return (a & 0xff) | (i << 7); + } + + return FAIL; +} + +static int +validate_offset_imm (unsigned int val, int hwse) +{ + if ((hwse && val > 255) || val > 4095) + return FAIL; + return val; +} + +/* Subroutine of md_apply_fix. Do those data_ops which can take a + negative immediate constant by altering the instruction. A bit of + a hack really. + MOV <-> MVN + AND <-> BIC + ADC <-> SBC + by inverting the second operand, and + ADD <-> SUB + CMP <-> CMN + by negating the second operand. */ + +static int +negate_data_op (unsigned long * instruction, + unsigned long value) +{ + int op, new_inst; + unsigned long negated, inverted; + + negated = encode_arm_immediate (-value); + inverted = encode_arm_immediate (~value); + + op = (*instruction >> DATA_OP_SHIFT) & 0xf; + switch (op) + { + /* First negates. */ + case OPCODE_SUB: /* ADD <-> SUB */ + new_inst = OPCODE_ADD; + value = negated; + break; + + case OPCODE_ADD: + new_inst = OPCODE_SUB; + value = negated; + break; + + case OPCODE_CMP: /* CMP <-> CMN */ + new_inst = OPCODE_CMN; + value = negated; + break; + + case OPCODE_CMN: + new_inst = OPCODE_CMP; + value = negated; + break; + + /* Now Inverted ops. */ + case OPCODE_MOV: /* MOV <-> MVN */ + new_inst = OPCODE_MVN; + value = inverted; + break; + + case OPCODE_MVN: + new_inst = OPCODE_MOV; + value = inverted; + break; + + case OPCODE_AND: /* AND <-> BIC */ + new_inst = OPCODE_BIC; + value = inverted; + break; + + case OPCODE_BIC: + new_inst = OPCODE_AND; + value = inverted; + break; + + case OPCODE_ADC: /* ADC <-> SBC */ + new_inst = OPCODE_SBC; + value = inverted; + break; + + case OPCODE_SBC: + new_inst = OPCODE_ADC; + value = inverted; + break; + + /* We cannot do anything. */ + default: + return FAIL; + } + + if (value == (unsigned) FAIL) + return FAIL; + + *instruction &= OPCODE_MASK; + *instruction |= new_inst << DATA_OP_SHIFT; + return value; +} + +/* Like negate_data_op, but for Thumb-2. */ + +static unsigned int +thumb32_negate_data_op (offsetT *instruction, unsigned int value) +{ + int op, new_inst; + int rd; + unsigned int negated, inverted; + + negated = encode_thumb32_immediate (-value); + inverted = encode_thumb32_immediate (~value); + + rd = (*instruction >> 8) & 0xf; + op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; + switch (op) + { + /* ADD <-> SUB. Includes CMP <-> CMN. */ + case T2_OPCODE_SUB: + new_inst = T2_OPCODE_ADD; + value = negated; + break; + + case T2_OPCODE_ADD: + new_inst = T2_OPCODE_SUB; + value = negated; + break; + + /* ORR <-> ORN. Includes MOV <-> MVN. */ + case T2_OPCODE_ORR: + new_inst = T2_OPCODE_ORN; + value = inverted; + break; + + case T2_OPCODE_ORN: + new_inst = T2_OPCODE_ORR; + value = inverted; + break; + + /* AND <-> BIC. TST has no inverted equivalent. */ + case T2_OPCODE_AND: + new_inst = T2_OPCODE_BIC; + if (rd == 15) + value = FAIL; + else + value = inverted; + break; + + case T2_OPCODE_BIC: + new_inst = T2_OPCODE_AND; + value = inverted; + break; + + /* ADC <-> SBC */ + case T2_OPCODE_ADC: + new_inst = T2_OPCODE_SBC; + value = inverted; + break; + + case T2_OPCODE_SBC: + new_inst = T2_OPCODE_ADC; + value = inverted; + break; + + /* We cannot do anything. */ + default: + return FAIL; + } + + if (value == (unsigned int)FAIL) + return FAIL; + + *instruction &= T2_OPCODE_MASK; + *instruction |= new_inst << T2_DATA_OP_SHIFT; + return value; +} + +/* Read a 32-bit thumb instruction from buf. */ +static unsigned long +get_thumb32_insn (char * buf) +{ + unsigned long insn; + insn = md_chars_to_number (buf, THUMB_SIZE) << 16; + insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + + return insn; +} + + +/* We usually want to set the low bit on the address of thumb function + symbols. In particular .word foo - . should have the low bit set. + Generic code tries to fold the difference of two symbols to + a constant. Prevent this and force a relocation when the first symbols + is a thumb function. */ + +bfd_boolean +arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) +{ + if (op == O_subtract + && l->X_op == O_symbol + && r->X_op == O_symbol + && THUMB_IS_FUNC (l->X_add_symbol)) + { + l->X_op = O_subtract; + l->X_op_symbol = r->X_add_symbol; + l->X_add_number -= r->X_add_number; + return TRUE; + } + + /* Process as normal. */ + return FALSE; +} + +void +md_apply_fix (fixS * fixP, + valueT * valP, + segT seg) +{ + offsetT value = * valP; + offsetT newval; + unsigned int newimm; + unsigned long temp; + int sign; + char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; + + gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); + + /* Note whether this will delete the relocation. */ + + if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) + fixP->fx_done = 1; + + /* On a 64-bit host, silently truncate 'value' to 32 bits for + consistency with the behaviour on 32-bit hosts. Remember value + for emit_reloc. */ + value &= 0xffffffff; + value ^= 0x80000000; + value -= 0x80000000; + + *valP = value; + fixP->fx_addnumber = value; + + /* Same treatment for fixP->fx_offset. */ + fixP->fx_offset &= 0xffffffff; + fixP->fx_offset ^= 0x80000000; + fixP->fx_offset -= 0x80000000; + + switch (fixP->fx_r_type) + { + case BFD_RELOC_NONE: + /* This will need to go in the object file. */ + fixP->fx_done = 0; + break; + + case BFD_RELOC_ARM_IMMEDIATE: + /* We claim that this fixup has been processed here, + even if in fact we generate an error because we do + not have a reloc for it, so tc_gen_reloc will reject it. */ + fixP->fx_done = 1; + + if (fixP->fx_addsy + && ! S_IS_DEFINED (fixP->fx_addsy)) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("undefined symbol %s used as an immediate value"), + S_GET_NAME (fixP->fx_addsy)); + break; + } + + if (fixP->fx_addsy + && S_GET_SEGMENT (fixP->fx_addsy) != seg) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("symbol %s is in a different section"), + S_GET_NAME (fixP->fx_addsy)); + break; + } + + newimm = encode_arm_immediate (value); + temp = md_chars_to_number (buf, INSN_SIZE); + + /* If the instruction will fail, see if we can fix things up by + changing the opcode. */ + if (newimm == (unsigned int) FAIL + && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid constant (%lx) after fixup"), + (unsigned long) value); + break; + } + + newimm |= (temp & 0xfffff000); + md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); + break; + + case BFD_RELOC_ARM_ADRL_IMMEDIATE: + { + unsigned int highpart = 0; + unsigned int newinsn = 0xe1a00000; /* nop. */ + + if (fixP->fx_addsy + && ! S_IS_DEFINED (fixP->fx_addsy)) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("undefined symbol %s used as an immediate value"), + S_GET_NAME (fixP->fx_addsy)); + break; + } + + if (fixP->fx_addsy + && S_GET_SEGMENT (fixP->fx_addsy) != seg) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("symbol %s is in a different section"), + S_GET_NAME (fixP->fx_addsy)); + break; + } + + newimm = encode_arm_immediate (value); + temp = md_chars_to_number (buf, INSN_SIZE); + + /* If the instruction will fail, see if we can fix things up by + changing the opcode. */ + if (newimm == (unsigned int) FAIL + && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) + { + /* No ? OK - try using two ADD instructions to generate + the value. */ + newimm = validate_immediate_twopart (value, & highpart); + + /* Yes - then make sure that the second instruction is + also an add. */ + if (newimm != (unsigned int) FAIL) + newinsn = temp; + /* Still No ? Try using a negated value. */ + else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) + temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; + /* Otherwise - give up. */ + else + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("unable to compute ADRL instructions for PC offset of 0x%lx"), + (long) value); + break; + } + + /* Replace the first operand in the 2nd instruction (which + is the PC) with the destination register. We have + already added in the PC in the first instruction and we + do not want to do it again. */ + newinsn &= ~ 0xf0000; + newinsn |= ((newinsn & 0x0f000) << 4); + } + + newimm |= (temp & 0xfffff000); + md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); + + highpart |= (newinsn & 0xfffff000); + md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); + } + break; + + case BFD_RELOC_ARM_OFFSET_IMM: + if (!fixP->fx_done && seg->use_rela_p) + value = 0; + + case BFD_RELOC_ARM_LITERAL: + sign = value >= 0; + + if (value < 0) + value = - value; + + if (validate_offset_imm (value, 0) == FAIL) + { + if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid literal constant: pool needs to be closer")); + else + as_bad_where (fixP->fx_file, fixP->fx_line, + _("bad immediate value for offset (%ld)"), + (long) value); + break; + } + + newval = md_chars_to_number (buf, INSN_SIZE); + newval &= 0xff7ff000; + newval |= value | (sign ? INDEX_UP : 0); + md_number_to_chars (buf, newval, INSN_SIZE); + break; + + case BFD_RELOC_ARM_OFFSET_IMM8: + case BFD_RELOC_ARM_HWLITERAL: + sign = value >= 0; + + if (value < 0) + value = - value; + + if (validate_offset_imm (value, 1) == FAIL) + { + if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid literal constant: pool needs to be closer")); + else + as_bad (_("bad immediate value for 8-bit offset (%ld)"), + (long) value); + break; + } + + newval = md_chars_to_number (buf, INSN_SIZE); + newval &= 0xff7ff0f0; + newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); + md_number_to_chars (buf, newval, INSN_SIZE); + break; + + case BFD_RELOC_ARM_T32_OFFSET_U8: + if (value < 0 || value > 1020 || value % 4 != 0) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("bad immediate value for offset (%ld)"), (long) value); + value /= 4; + + newval = md_chars_to_number (buf+2, THUMB_SIZE); + newval |= value; + md_number_to_chars (buf+2, newval, THUMB_SIZE); + break; + + case BFD_RELOC_ARM_T32_OFFSET_IMM: + /* This is a complicated relocation used for all varieties of Thumb32 + load/store instruction with immediate offset: + + 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, + *4, optional writeback(W) + (doubleword load/store) + + 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel + 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit + 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) + 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit + 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit + + Uppercase letters indicate bits that are already encoded at + this point. Lowercase letters are our problem. For the + second block of instructions, the secondary opcode nybble + (bits 8..11) is present, and bit 23 is zero, even if this is + a PC-relative operation. */ + newval = md_chars_to_number (buf, THUMB_SIZE); + newval <<= 16; + newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); + + if ((newval & 0xf0000000) == 0xe0000000) + { + /* Doubleword load/store: 8-bit offset, scaled by 4. */ + if (value >= 0) + newval |= (1 << 23); + else + value = -value; + if (value % 4 != 0) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("offset not a multiple of 4")); + break; + } + value /= 4; + if (value > 0xff) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("offset out of range")); + break; + } + newval &= ~0xff; + } + else if ((newval & 0x000f0000) == 0x000f0000) + { + /* PC-relative, 12-bit offset. */ + if (value >= 0) + newval |= (1 << 23); + else + value = -value; + if (value > 0xfff) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("offset out of range")); + break; + } + newval &= ~0xfff; + } + else if ((newval & 0x00000100) == 0x00000100) + { + /* Writeback: 8-bit, +/- offset. */ + if (value >= 0) + newval |= (1 << 9); + else + value = -value; + if (value > 0xff) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("offset out of range")); + break; + } + newval &= ~0xff; + } + else if ((newval & 0x00000f00) == 0x00000e00) + { + /* T-instruction: positive 8-bit offset. */ + if (value < 0 || value > 0xff) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("offset out of range")); + break; + } + newval &= ~0xff; + newval |= value; + } + else + { + /* Positive 12-bit or negative 8-bit offset. */ + int limit; + if (value >= 0) + { + newval |= (1 << 23); + limit = 0xfff; + } + else + { + value = -value; + limit = 0xff; + } + if (value > limit) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("offset out of range")); + break; + } + newval &= ~limit; + } + + newval |= value; + md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); + break; + + case BFD_RELOC_ARM_SHIFT_IMM: + newval = md_chars_to_number (buf, INSN_SIZE); + if (((unsigned long) value) > 32 + || (value == 32 + && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("shift expression is too large")); + break; + } + + if (value == 0) + /* Shifts of zero must be done as lsl. */ + newval &= ~0x60; + else if (value == 32) + value = 0; + newval &= 0xfffff07f; + newval |= (value & 0x1f) << 7; + md_number_to_chars (buf, newval, INSN_SIZE); + break; + + case BFD_RELOC_ARM_T32_IMMEDIATE: + case BFD_RELOC_ARM_T32_ADD_IMM: + case BFD_RELOC_ARM_T32_IMM12: + case BFD_RELOC_ARM_T32_ADD_PC12: + /* We claim that this fixup has been processed here, + even if in fact we generate an error because we do + not have a reloc for it, so tc_gen_reloc will reject it. */ + fixP->fx_done = 1; + + if (fixP->fx_addsy + && ! S_IS_DEFINED (fixP->fx_addsy)) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("undefined symbol %s used as an immediate value"), + S_GET_NAME (fixP->fx_addsy)); + break; + } + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval <<= 16; + newval |= md_chars_to_number (buf+2, THUMB_SIZE); + + newimm = FAIL; + if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE + || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) + { + newimm = encode_thumb32_immediate (value); + if (newimm == (unsigned int) FAIL) + newimm = thumb32_negate_data_op (&newval, value); + } + if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE + && newimm == (unsigned int) FAIL) + { + /* Turn add/sum into addw/subw. */ + if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) + newval = (newval & 0xfeffffff) | 0x02000000; + + /* 12 bit immediate for addw/subw. */ + if (value < 0) + { + value = -value; + newval ^= 0x00a00000; + } + if (value > 0xfff) + newimm = (unsigned int) FAIL; + else + newimm = value; + } + + if (newimm == (unsigned int)FAIL) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid constant (%lx) after fixup"), + (unsigned long) value); + break; + } + + newval |= (newimm & 0x800) << 15; + newval |= (newimm & 0x700) << 4; + newval |= (newimm & 0x0ff); + + md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); + md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); + break; + + case BFD_RELOC_ARM_SMC: + if (((unsigned long) value) > 0xffff) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid smc expression")); + newval = md_chars_to_number (buf, INSN_SIZE); + newval |= (value & 0xf) | ((value & 0xfff0) << 4); + md_number_to_chars (buf, newval, INSN_SIZE); + break; + + case BFD_RELOC_ARM_SWI: + if (fixP->tc_fix_data != 0) + { + if (((unsigned long) value) > 0xff) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid swi expression")); + newval = md_chars_to_number (buf, THUMB_SIZE); + newval |= value; + md_number_to_chars (buf, newval, THUMB_SIZE); + } + else + { + if (((unsigned long) value) > 0x00ffffff) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid swi expression")); + newval = md_chars_to_number (buf, INSN_SIZE); + newval |= value; + md_number_to_chars (buf, newval, INSN_SIZE); + } + break; + + case BFD_RELOC_ARM_MULTI: + if (((unsigned long) value) > 0xffff) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid expression in load/store multiple")); + newval = value | md_chars_to_number (buf, INSN_SIZE); + md_number_to_chars (buf, newval, INSN_SIZE); + break; + +#ifdef OBJ_ELF + case BFD_RELOC_ARM_PCREL_CALL: + + if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) + && fixP->fx_addsy + && !S_IS_EXTERNAL (fixP->fx_addsy) + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && THUMB_IS_FUNC (fixP->fx_addsy)) + /* Flip the bl to blx. This is a simple flip + bit here because we generate PCREL_CALL for + unconditional bls. */ + { + newval = md_chars_to_number (buf, INSN_SIZE); + newval = newval | 0x10000000; + md_number_to_chars (buf, newval, INSN_SIZE); + temp = 1; + fixP->fx_done = 1; + } + else + temp = 3; + goto arm_branch_common; + + case BFD_RELOC_ARM_PCREL_JUMP: + if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) + && fixP->fx_addsy + && !S_IS_EXTERNAL (fixP->fx_addsy) + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && THUMB_IS_FUNC (fixP->fx_addsy)) + { + /* This would map to a bl, b, + b to a Thumb function. We + need to force a relocation for this particular + case. */ + newval = md_chars_to_number (buf, INSN_SIZE); + fixP->fx_done = 0; + } + + case BFD_RELOC_ARM_PLT32: +#endif + case BFD_RELOC_ARM_PCREL_BRANCH: + temp = 3; + goto arm_branch_common; + + case BFD_RELOC_ARM_PCREL_BLX: + + temp = 1; + if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) + && fixP->fx_addsy + && !S_IS_EXTERNAL (fixP->fx_addsy) + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && ARM_IS_FUNC (fixP->fx_addsy)) + { + /* Flip the blx to a bl and warn. */ + const char *name = S_GET_NAME (fixP->fx_addsy); + newval = 0xeb000000; + as_warn_where (fixP->fx_file, fixP->fx_line, + _("blx to '%s' an ARM ISA state function changed to bl"), + name); + md_number_to_chars (buf, newval, INSN_SIZE); + temp = 3; + fixP->fx_done = 1; + } + +#ifdef OBJ_ELF + if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) + fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; +#endif + + arm_branch_common: + /* We are going to store value (shifted right by two) in the + instruction, in a 24 bit, signed field. Bits 26 through 32 either + all clear or all set and bit 0 must be clear. For B/BL bit 1 must + also be be clear. */ + if (value & temp) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("misaligned branch destination")); + if ((value & (offsetT)0xfe000000) != (offsetT)0 + && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); + + if (fixP->fx_done || !seg->use_rela_p) + { + newval = md_chars_to_number (buf, INSN_SIZE); + newval |= (value >> 2) & 0x00ffffff; + /* Set the H bit on BLX instructions. */ + if (temp == 1) + { + if (value & 2) + newval |= 0x01000000; + else + newval &= ~0x01000000; + } + md_number_to_chars (buf, newval, INSN_SIZE); + } + break; + + case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ + /* CBZ can only branch forward. */ + + /* Attempts to use CBZ to branch to the next instruction + (which, strictly speaking, are prohibited) will be turned into + no-ops. + + FIXME: It may be better to remove the instruction completely and + perform relaxation. */ + if (value == -2) + { + newval = md_chars_to_number (buf, THUMB_SIZE); + newval = 0xbf00; /* NOP encoding T1 */ + md_number_to_chars (buf, newval, THUMB_SIZE); + } + else + { + if (value & ~0x7e) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); + + if (fixP->fx_done || !seg->use_rela_p) + { + newval = md_chars_to_number (buf, THUMB_SIZE); + newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); + md_number_to_chars (buf, newval, THUMB_SIZE); + } + } + break; + + case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ + if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); + + if (fixP->fx_done || !seg->use_rela_p) + { + newval = md_chars_to_number (buf, THUMB_SIZE); + newval |= (value & 0x1ff) >> 1; + md_number_to_chars (buf, newval, THUMB_SIZE); + } + break; + + case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ + if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); + + if (fixP->fx_done || !seg->use_rela_p) + { + newval = md_chars_to_number (buf, THUMB_SIZE); + newval |= (value & 0xfff) >> 1; + md_number_to_chars (buf, newval, THUMB_SIZE); + } + break; + + case BFD_RELOC_THUMB_PCREL_BRANCH20: + if (fixP->fx_addsy + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && !S_IS_EXTERNAL (fixP->fx_addsy) + && S_IS_DEFINED (fixP->fx_addsy) + && ARM_IS_FUNC (fixP->fx_addsy) + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) + { + /* Force a relocation for a branch 20 bits wide. */ + fixP->fx_done = 0; + } + if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("conditional branch out of range")); + + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT newval2; + addressT S, J1, J2, lo, hi; + + S = (value & 0x00100000) >> 20; + J2 = (value & 0x00080000) >> 19; + J1 = (value & 0x00040000) >> 18; + hi = (value & 0x0003f000) >> 12; + lo = (value & 0x00000ffe) >> 1; + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval |= (S << 10) | hi; + newval2 |= (J1 << 13) | (J2 << 11) | lo; + md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); + } + break; + + case BFD_RELOC_THUMB_PCREL_BLX: + + /* If there is a blx from a thumb state function to + another thumb function flip this to a bl and warn + about it. */ + + if (fixP->fx_addsy + && S_IS_DEFINED (fixP->fx_addsy) + && !S_IS_EXTERNAL (fixP->fx_addsy) + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && THUMB_IS_FUNC (fixP->fx_addsy)) + { + const char *name = S_GET_NAME (fixP->fx_addsy); + as_warn_where (fixP->fx_file, fixP->fx_line, + _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), + name); + newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval = newval | 0x1000; + md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); + fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; + fixP->fx_done = 1; + } + + + goto thumb_bl_common; + + case BFD_RELOC_THUMB_PCREL_BRANCH23: + + /* A bl from Thumb state ISA to an internal ARM state function + is converted to a blx. */ + if (fixP->fx_addsy + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && !S_IS_EXTERNAL (fixP->fx_addsy) + && S_IS_DEFINED (fixP->fx_addsy) + && ARM_IS_FUNC (fixP->fx_addsy) + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) + { + newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval = newval & ~0x1000; + md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); + fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; + fixP->fx_done = 1; + } + + thumb_bl_common: + +#ifdef OBJ_ELF + if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && + fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) + fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; +#endif + + if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); + + if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) + /* For a BLX instruction, make sure that the relocation is rounded up + to a word boundary. This follows the semantics of the instruction + which specifies that bit 1 of the target address will come from bit + 1 of the base address. */ + value = (value + 1) & ~ 1; + + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT newval2; + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval |= (value & 0x7fffff) >> 12; + newval2 |= (value & 0xfff) >> 1; + md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); + } + break; + + case BFD_RELOC_THUMB_PCREL_BRANCH25: + if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); + + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT newval2; + addressT S, I1, I2, lo, hi; + + S = (value & 0x01000000) >> 24; + I1 = (value & 0x00800000) >> 23; + I2 = (value & 0x00400000) >> 22; + hi = (value & 0x003ff000) >> 12; + lo = (value & 0x00000ffe) >> 1; + + I1 = !(I1 ^ S); + I2 = !(I2 ^ S); + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval |= (S << 10) | hi; + newval2 |= (I1 << 13) | (I2 << 11) | lo; + md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); + } + break; + + case BFD_RELOC_8: + if (fixP->fx_done || !seg->use_rela_p) + md_number_to_chars (buf, value, 1); + break; + + case BFD_RELOC_16: + if (fixP->fx_done || !seg->use_rela_p) + md_number_to_chars (buf, value, 2); + break; + +#ifdef OBJ_ELF + case BFD_RELOC_ARM_TLS_GD32: + case BFD_RELOC_ARM_TLS_LE32: + case BFD_RELOC_ARM_TLS_IE32: + case BFD_RELOC_ARM_TLS_LDM32: + case BFD_RELOC_ARM_TLS_LDO32: + S_SET_THREAD_LOCAL (fixP->fx_addsy); + /* fall through */ + + case BFD_RELOC_ARM_GOT32: + case BFD_RELOC_ARM_GOTOFF: + if (fixP->fx_done || !seg->use_rela_p) + md_number_to_chars (buf, 0, 4); + break; + + case BFD_RELOC_ARM_TARGET2: + /* TARGET2 is not partial-inplace, so we need to write the + addend here for REL targets, because it won't be written out + during reloc processing later. */ + if (fixP->fx_done || !seg->use_rela_p) + md_number_to_chars (buf, fixP->fx_offset, 4); + break; +#endif + + case BFD_RELOC_RVA: + case BFD_RELOC_32: + case BFD_RELOC_ARM_TARGET1: + case BFD_RELOC_ARM_ROSEGREL32: + case BFD_RELOC_ARM_SBREL32: + case BFD_RELOC_32_PCREL: +#ifdef TE_PE + case BFD_RELOC_32_SECREL: +#endif + if (fixP->fx_done || !seg->use_rela_p) +#ifdef TE_WINCE + /* For WinCE we only do this for pcrel fixups. */ + if (fixP->fx_done || fixP->fx_pcrel) +#endif + md_number_to_chars (buf, value, 4); + break; + +#ifdef OBJ_ELF + case BFD_RELOC_ARM_PREL31: + if (fixP->fx_done || !seg->use_rela_p) + { + newval = md_chars_to_number (buf, 4) & 0x80000000; + if ((value ^ (value >> 1)) & 0x40000000) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("rel31 relocation overflow")); + } + newval |= value & 0x7fffffff; + md_number_to_chars (buf, newval, 4); + } + break; +#endif + + case BFD_RELOC_ARM_CP_OFF_IMM: + case BFD_RELOC_ARM_T32_CP_OFF_IMM: + if (value < -1023 || value > 1023 || (value & 3)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("co-processor offset out of range")); + cp_off_common: + sign = value >= 0; + if (value < 0) + value = -value; + if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM + || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) + newval = md_chars_to_number (buf, INSN_SIZE); + else + newval = get_thumb32_insn (buf); + newval &= 0xff7fff00; + newval |= (value >> 2) | (sign ? INDEX_UP : 0); + if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM + || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) + md_number_to_chars (buf, newval, INSN_SIZE); + else + put_thumb32_insn (buf, newval); + break; + + case BFD_RELOC_ARM_CP_OFF_IMM_S2: + case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: + if (value < -255 || value > 255) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("co-processor offset out of range")); + value *= 4; + goto cp_off_common; + + case BFD_RELOC_ARM_THUMB_OFFSET: + newval = md_chars_to_number (buf, THUMB_SIZE); + /* Exactly what ranges, and where the offset is inserted depends + on the type of instruction, we can establish this from the + top 4 bits. */ + switch (newval >> 12) + { + case 4: /* PC load. */ + /* Thumb PC loads are somewhat odd, bit 1 of the PC is + forced to zero for these loads; md_pcrel_from has already + compensated for this. */ + if (value & 3) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid offset, target not word aligned (0x%08lX)"), + (((unsigned long) fixP->fx_frag->fr_address + + (unsigned long) fixP->fx_where) & ~3) + + (unsigned long) value); + + if (value & ~0x3fc) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid offset, value too big (0x%08lX)"), + (long) value); + + newval |= value >> 2; + break; + + case 9: /* SP load/store. */ + if (value & ~0x3fc) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid offset, value too big (0x%08lX)"), + (long) value); + newval |= value >> 2; + break; + + case 6: /* Word load/store. */ + if (value & ~0x7c) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid offset, value too big (0x%08lX)"), + (long) value); + newval |= value << 4; /* 6 - 2. */ + break; + + case 7: /* Byte load/store. */ + if (value & ~0x1f) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid offset, value too big (0x%08lX)"), + (long) value); + newval |= value << 6; + break; + + case 8: /* Halfword load/store. */ + if (value & ~0x3e) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid offset, value too big (0x%08lX)"), + (long) value); + newval |= value << 5; /* 6 - 1. */ + break; + + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + "Unable to process relocation for thumb opcode: %lx", + (unsigned long) newval); + break; + } + md_number_to_chars (buf, newval, THUMB_SIZE); + break; + + case BFD_RELOC_ARM_THUMB_ADD: + /* This is a complicated relocation, since we use it for all of + the following immediate relocations: + + 3bit ADD/SUB + 8bit ADD/SUB + 9bit ADD/SUB SP word-aligned + 10bit ADD PC/SP word-aligned + + The type of instruction being processed is encoded in the + instruction field: + + 0x8000 SUB + 0x00F0 Rd + 0x000F Rs + */ + newval = md_chars_to_number (buf, THUMB_SIZE); + { + int rd = (newval >> 4) & 0xf; + int rs = newval & 0xf; + int subtract = !!(newval & 0x8000); + + /* Check for HI regs, only very restricted cases allowed: + Adjusting SP, and using PC or SP to get an address. */ + if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) + || (rs > 7 && rs != REG_SP && rs != REG_PC)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid Hi register with immediate")); + + /* If value is negative, choose the opposite instruction. */ + if (value < 0) + { + value = -value; + subtract = !subtract; + if (value < 0) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("immediate value out of range")); + } + + if (rd == REG_SP) + { + if (value & ~0x1fc) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid immediate for stack address calculation")); + newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; + newval |= value >> 2; + } + else if (rs == REG_PC || rs == REG_SP) + { + if (subtract || value & ~0x3fc) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid immediate for address calculation (value = 0x%08lX)"), + (unsigned long) value); + newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); + newval |= rd << 8; + newval |= value >> 2; + } + else if (rs == rd) + { + if (value & ~0xff) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("immediate value out of range")); + newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; + newval |= (rd << 8) | value; + } + else + { + if (value & ~0x7) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("immediate value out of range")); + newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; + newval |= rd | (rs << 3) | (value << 6); + } + } + md_number_to_chars (buf, newval, THUMB_SIZE); + break; + + case BFD_RELOC_ARM_THUMB_IMM: + newval = md_chars_to_number (buf, THUMB_SIZE); + if (value < 0 || value > 255) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid immediate: %ld is out of range"), + (long) value); + newval |= value; + md_number_to_chars (buf, newval, THUMB_SIZE); + break; + + case BFD_RELOC_ARM_THUMB_SHIFT: + /* 5bit shift value (0..32). LSL cannot take 32. */ + newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; + temp = newval & 0xf800; + if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("invalid shift value: %ld"), (long) value); + /* Shifts of zero must be encoded as LSL. */ + if (value == 0) + newval = (newval & 0x003f) | T_OPCODE_LSL_I; + /* Shifts of 32 are encoded as zero. */ + else if (value == 32) + value = 0; + newval |= value << 6; + md_number_to_chars (buf, newval, THUMB_SIZE); + break; + + case BFD_RELOC_VTABLE_INHERIT: + case BFD_RELOC_VTABLE_ENTRY: + fixP->fx_done = 0; + return; + + case BFD_RELOC_ARM_MOVW: + case BFD_RELOC_ARM_MOVT: + case BFD_RELOC_ARM_THUMB_MOVW: + case BFD_RELOC_ARM_THUMB_MOVT: + if (fixP->fx_done || !seg->use_rela_p) + { + /* REL format relocations are limited to a 16-bit addend. */ + if (!fixP->fx_done) + { + if (value < -0x8000 || value > 0x7fff) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("offset out of range")); + } + else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT + || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) + { + value >>= 16; + } + + if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW + || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) + { + newval = get_thumb32_insn (buf); + newval &= 0xfbf08f00; + newval |= (value & 0xf000) << 4; + newval |= (value & 0x0800) << 15; + newval |= (value & 0x0700) << 4; + newval |= (value & 0x00ff); + put_thumb32_insn (buf, newval); + } + else + { + newval = md_chars_to_number (buf, 4); + newval &= 0xfff0f000; + newval |= value & 0x0fff; + newval |= (value & 0xf000) << 4; + md_number_to_chars (buf, newval, 4); + } + } + return; + + case BFD_RELOC_ARM_ALU_PC_G0_NC: + case BFD_RELOC_ARM_ALU_PC_G0: + case BFD_RELOC_ARM_ALU_PC_G1_NC: + case BFD_RELOC_ARM_ALU_PC_G1: + case BFD_RELOC_ARM_ALU_PC_G2: + case BFD_RELOC_ARM_ALU_SB_G0_NC: + case BFD_RELOC_ARM_ALU_SB_G0: + case BFD_RELOC_ARM_ALU_SB_G1_NC: + case BFD_RELOC_ARM_ALU_SB_G1: + case BFD_RELOC_ARM_ALU_SB_G2: + gas_assert (!fixP->fx_done); + if (!seg->use_rela_p) + { + bfd_vma insn; + bfd_vma encoded_addend; + bfd_vma addend_abs = abs (value); + + /* Check that the absolute value of the addend can be + expressed as an 8-bit constant plus a rotation. */ + encoded_addend = encode_arm_immediate (addend_abs); + if (encoded_addend == (unsigned int) FAIL) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("the offset 0x%08lX is not representable"), + (unsigned long) addend_abs); + + /* Extract the instruction. */ + insn = md_chars_to_number (buf, INSN_SIZE); + + /* If the addend is positive, use an ADD instruction. + Otherwise use a SUB. Take care not to destroy the S bit. */ + insn &= 0xff1fffff; + if (value < 0) + insn |= 1 << 22; + else + insn |= 1 << 23; + + /* Place the encoded addend into the first 12 bits of the + instruction. */ + insn &= 0xfffff000; + insn |= encoded_addend; + + /* Update the instruction. */ + md_number_to_chars (buf, insn, INSN_SIZE); + } + break; + + case BFD_RELOC_ARM_LDR_PC_G0: + case BFD_RELOC_ARM_LDR_PC_G1: + case BFD_RELOC_ARM_LDR_PC_G2: + case BFD_RELOC_ARM_LDR_SB_G0: + case BFD_RELOC_ARM_LDR_SB_G1: + case BFD_RELOC_ARM_LDR_SB_G2: + gas_assert (!fixP->fx_done); + if (!seg->use_rela_p) + { + bfd_vma insn; + bfd_vma addend_abs = abs (value); + + /* Check that the absolute value of the addend can be + encoded in 12 bits. */ + if (addend_abs >= 0x1000) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), + (unsigned long) addend_abs); + + /* Extract the instruction. */ + insn = md_chars_to_number (buf, INSN_SIZE); + + /* If the addend is negative, clear bit 23 of the instruction. + Otherwise set it. */ + if (value < 0) + insn &= ~(1 << 23); + else + insn |= 1 << 23; + + /* Place the absolute value of the addend into the first 12 bits + of the instruction. */ + insn &= 0xfffff000; + insn |= addend_abs; + + /* Update the instruction. */ + md_number_to_chars (buf, insn, INSN_SIZE); + } + break; + + case BFD_RELOC_ARM_LDRS_PC_G0: + case BFD_RELOC_ARM_LDRS_PC_G1: + case BFD_RELOC_ARM_LDRS_PC_G2: + case BFD_RELOC_ARM_LDRS_SB_G0: + case BFD_RELOC_ARM_LDRS_SB_G1: + case BFD_RELOC_ARM_LDRS_SB_G2: + gas_assert (!fixP->fx_done); + if (!seg->use_rela_p) + { + bfd_vma insn; + bfd_vma addend_abs = abs (value); + + /* Check that the absolute value of the addend can be + encoded in 8 bits. */ + if (addend_abs >= 0x100) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), + (unsigned long) addend_abs); + + /* Extract the instruction. */ + insn = md_chars_to_number (buf, INSN_SIZE); + + /* If the addend is negative, clear bit 23 of the instruction. + Otherwise set it. */ + if (value < 0) + insn &= ~(1 << 23); + else + insn |= 1 << 23; + + /* Place the first four bits of the absolute value of the addend + into the first 4 bits of the instruction, and the remaining + four into bits 8 .. 11. */ + insn &= 0xfffff0f0; + insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); + + /* Update the instruction. */ + md_number_to_chars (buf, insn, INSN_SIZE); + } + break; + + case BFD_RELOC_ARM_LDC_PC_G0: + case BFD_RELOC_ARM_LDC_PC_G1: + case BFD_RELOC_ARM_LDC_PC_G2: + case BFD_RELOC_ARM_LDC_SB_G0: + case BFD_RELOC_ARM_LDC_SB_G1: + case BFD_RELOC_ARM_LDC_SB_G2: + gas_assert (!fixP->fx_done); + if (!seg->use_rela_p) + { + bfd_vma insn; + bfd_vma addend_abs = abs (value); + + /* Check that the absolute value of the addend is a multiple of + four and, when divided by four, fits in 8 bits. */ + if (addend_abs & 0x3) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("bad offset 0x%08lX (must be word-aligned)"), + (unsigned long) addend_abs); + + if ((addend_abs >> 2) > 0xff) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("bad offset 0x%08lX (must be an 8-bit number of words)"), + (unsigned long) addend_abs); + + /* Extract the instruction. */ + insn = md_chars_to_number (buf, INSN_SIZE); + + /* If the addend is negative, clear bit 23 of the instruction. + Otherwise set it. */ + if (value < 0) + insn &= ~(1 << 23); + else + insn |= 1 << 23; + + /* Place the addend (divided by four) into the first eight + bits of the instruction. */ + insn &= 0xfffffff0; + insn |= addend_abs >> 2; + + /* Update the instruction. */ + md_number_to_chars (buf, insn, INSN_SIZE); + } + break; + + case BFD_RELOC_ARM_V4BX: + /* This will need to go in the object file. */ + fixP->fx_done = 0; + break; + + case BFD_RELOC_UNUSED: + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("bad relocation fixup type (%d)"), fixP->fx_r_type); + } +} + +/* Translate internal representation of relocation info to BFD target + format. */ + +arelent * +tc_gen_reloc (asection *section, fixS *fixp) +{ + arelent * reloc; + bfd_reloc_code_real_type code; + + reloc = xmalloc (sizeof (arelent)); + + reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + + if (fixp->fx_pcrel) + { + if (section->use_rela_p) + fixp->fx_offset -= md_pcrel_from_section (fixp, section); + else + fixp->fx_offset = reloc->address; + } + reloc->addend = fixp->fx_offset; + + switch (fixp->fx_r_type) + { + case BFD_RELOC_8: + if (fixp->fx_pcrel) + { + code = BFD_RELOC_8_PCREL; + break; + } + + case BFD_RELOC_16: + if (fixp->fx_pcrel) + { + code = BFD_RELOC_16_PCREL; + break; + } + + case BFD_RELOC_32: + if (fixp->fx_pcrel) + { + code = BFD_RELOC_32_PCREL; + break; + } + + case BFD_RELOC_ARM_MOVW: + if (fixp->fx_pcrel) + { + code = BFD_RELOC_ARM_MOVW_PCREL; + break; + } + + case BFD_RELOC_ARM_MOVT: + if (fixp->fx_pcrel) + { + code = BFD_RELOC_ARM_MOVT_PCREL; + break; + } + + case BFD_RELOC_ARM_THUMB_MOVW: + if (fixp->fx_pcrel) + { + code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; + break; + } + + case BFD_RELOC_ARM_THUMB_MOVT: + if (fixp->fx_pcrel) + { + code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; + break; + } + + case BFD_RELOC_NONE: + case BFD_RELOC_ARM_PCREL_BRANCH: + case BFD_RELOC_ARM_PCREL_BLX: + case BFD_RELOC_RVA: + case BFD_RELOC_THUMB_PCREL_BRANCH7: + case BFD_RELOC_THUMB_PCREL_BRANCH9: + case BFD_RELOC_THUMB_PCREL_BRANCH12: + case BFD_RELOC_THUMB_PCREL_BRANCH20: + case BFD_RELOC_THUMB_PCREL_BRANCH23: + case BFD_RELOC_THUMB_PCREL_BRANCH25: + case BFD_RELOC_VTABLE_ENTRY: + case BFD_RELOC_VTABLE_INHERIT: +#ifdef TE_PE + case BFD_RELOC_32_SECREL: +#endif + code = fixp->fx_r_type; + break; + + case BFD_RELOC_THUMB_PCREL_BLX: +#ifdef OBJ_ELF + if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) + code = BFD_RELOC_THUMB_PCREL_BRANCH23; + else +#endif + code = BFD_RELOC_THUMB_PCREL_BLX; + break; + + case BFD_RELOC_ARM_LITERAL: + case BFD_RELOC_ARM_HWLITERAL: + /* If this is called then the a literal has + been referenced across a section boundary. */ + as_bad_where (fixp->fx_file, fixp->fx_line, + _("literal referenced across section boundary")); + return NULL; + +#ifdef OBJ_ELF + case BFD_RELOC_ARM_GOT32: + case BFD_RELOC_ARM_GOTOFF: + case BFD_RELOC_ARM_PLT32: + case BFD_RELOC_ARM_TARGET1: + case BFD_RELOC_ARM_ROSEGREL32: + case BFD_RELOC_ARM_SBREL32: + case BFD_RELOC_ARM_PREL31: + case BFD_RELOC_ARM_TARGET2: + case BFD_RELOC_ARM_TLS_LE32: + case BFD_RELOC_ARM_TLS_LDO32: + case BFD_RELOC_ARM_PCREL_CALL: + case BFD_RELOC_ARM_PCREL_JUMP: + case BFD_RELOC_ARM_ALU_PC_G0_NC: + case BFD_RELOC_ARM_ALU_PC_G0: + case BFD_RELOC_ARM_ALU_PC_G1_NC: + case BFD_RELOC_ARM_ALU_PC_G1: + case BFD_RELOC_ARM_ALU_PC_G2: + case BFD_RELOC_ARM_LDR_PC_G0: + case BFD_RELOC_ARM_LDR_PC_G1: + case BFD_RELOC_ARM_LDR_PC_G2: + case BFD_RELOC_ARM_LDRS_PC_G0: + case BFD_RELOC_ARM_LDRS_PC_G1: + case BFD_RELOC_ARM_LDRS_PC_G2: + case BFD_RELOC_ARM_LDC_PC_G0: + case BFD_RELOC_ARM_LDC_PC_G1: + case BFD_RELOC_ARM_LDC_PC_G2: + case BFD_RELOC_ARM_ALU_SB_G0_NC: + case BFD_RELOC_ARM_ALU_SB_G0: + case BFD_RELOC_ARM_ALU_SB_G1_NC: + case BFD_RELOC_ARM_ALU_SB_G1: + case BFD_RELOC_ARM_ALU_SB_G2: + case BFD_RELOC_ARM_LDR_SB_G0: + case BFD_RELOC_ARM_LDR_SB_G1: + case BFD_RELOC_ARM_LDR_SB_G2: + case BFD_RELOC_ARM_LDRS_SB_G0: + case BFD_RELOC_ARM_LDRS_SB_G1: + case BFD_RELOC_ARM_LDRS_SB_G2: + case BFD_RELOC_ARM_LDC_SB_G0: + case BFD_RELOC_ARM_LDC_SB_G1: + case BFD_RELOC_ARM_LDC_SB_G2: + case BFD_RELOC_ARM_V4BX: + code = fixp->fx_r_type; + break; + + case BFD_RELOC_ARM_TLS_GD32: + case BFD_RELOC_ARM_TLS_IE32: + case BFD_RELOC_ARM_TLS_LDM32: + /* BFD will include the symbol's address in the addend. + But we don't want that, so subtract it out again here. */ + if (!S_IS_COMMON (fixp->fx_addsy)) + reloc->addend -= (*reloc->sym_ptr_ptr)->value; + code = fixp->fx_r_type; + break; +#endif + + case BFD_RELOC_ARM_IMMEDIATE: + as_bad_where (fixp->fx_file, fixp->fx_line, + _("internal relocation (type: IMMEDIATE) not fixed up")); + return NULL; + + case BFD_RELOC_ARM_ADRL_IMMEDIATE: + as_bad_where (fixp->fx_file, fixp->fx_line, + _("ADRL used for a symbol not defined in the same file")); + return NULL; + + case BFD_RELOC_ARM_OFFSET_IMM: + if (section->use_rela_p) + { + code = fixp->fx_r_type; + break; + } + + if (fixp->fx_addsy != NULL + && !S_IS_DEFINED (fixp->fx_addsy) + && S_IS_LOCAL (fixp->fx_addsy)) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + _("undefined local label `%s'"), + S_GET_NAME (fixp->fx_addsy)); + return NULL; + } + + as_bad_where (fixp->fx_file, fixp->fx_line, + _("internal_relocation (type: OFFSET_IMM) not fixed up")); + return NULL; + + default: + { + char * type; + + switch (fixp->fx_r_type) + { + case BFD_RELOC_NONE: type = "NONE"; break; + case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; + case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; + case BFD_RELOC_ARM_SMC: type = "SMC"; break; + case BFD_RELOC_ARM_SWI: type = "SWI"; break; + case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; + case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; + case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; + case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; + case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; + case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; + case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; + default: type = _(""); break; + } + as_bad_where (fixp->fx_file, fixp->fx_line, + _("cannot represent %s relocation in this object file format"), + type); + return NULL; + } + } + +#ifdef OBJ_ELF + if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) + && GOT_symbol + && fixp->fx_addsy == GOT_symbol) + { + code = BFD_RELOC_ARM_GOTPC; + reloc->addend = fixp->fx_offset = reloc->address; + } +#endif + + reloc->howto = bfd_reloc_type_lookup (stdoutput, code); + + if (reloc->howto == NULL) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + _("cannot represent %s relocation in this object file format"), + bfd_get_reloc_code_name (code)); + return NULL; + } + + /* HACK: Since arm ELF uses Rel instead of Rela, encode the + vtable entry to be used in the relocation's section offset. */ + if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) + reloc->address = fixp->fx_offset; + + return reloc; +} + +/* This fix_new is called by cons via TC_CONS_FIX_NEW. */ + +void +cons_fix_new_arm (fragS * frag, + int where, + int size, + expressionS * exp) +{ + bfd_reloc_code_real_type type; + int pcrel = 0; + + /* Pick a reloc. + FIXME: @@ Should look at CPU word size. */ + switch (size) + { + case 1: + type = BFD_RELOC_8; + break; + case 2: + type = BFD_RELOC_16; + break; + case 4: + default: + type = BFD_RELOC_32; + break; + case 8: + type = BFD_RELOC_64; + break; + } + +#ifdef TE_PE + if (exp->X_op == O_secrel) + { + exp->X_op = O_symbol; + type = BFD_RELOC_32_SECREL; + } +#endif + + fix_new_exp (frag, where, (int) size, exp, pcrel, type); +} + +#if defined (OBJ_COFF) +void +arm_validate_fix (fixS * fixP) +{ + /* If the destination of the branch is a defined symbol which does not have + the THUMB_FUNC attribute, then we must be calling a function which has + the (interfacearm) attribute. We look for the Thumb entry point to that + function and change the branch to refer to that function instead. */ + if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 + && fixP->fx_addsy != NULL + && S_IS_DEFINED (fixP->fx_addsy) + && ! THUMB_IS_FUNC (fixP->fx_addsy)) + { + fixP->fx_addsy = find_real_start (fixP->fx_addsy); + } +} +#endif + + +int +arm_force_relocation (struct fix * fixp) +{ +#if defined (OBJ_COFF) && defined (TE_PE) + if (fixp->fx_r_type == BFD_RELOC_RVA) + return 1; +#endif + + /* In case we have a call or a branch to a function in ARM ISA mode from + a thumb function or vice-versa force the relocation. These relocations + are cleared off for some cores that might have blx and simple transformations + are possible. */ + +#ifdef OBJ_ELF + switch (fixp->fx_r_type) + { + case BFD_RELOC_ARM_PCREL_JUMP: + case BFD_RELOC_ARM_PCREL_CALL: + case BFD_RELOC_THUMB_PCREL_BLX: + if (THUMB_IS_FUNC (fixp->fx_addsy)) + return 1; + break; + + case BFD_RELOC_ARM_PCREL_BLX: + case BFD_RELOC_THUMB_PCREL_BRANCH25: + case BFD_RELOC_THUMB_PCREL_BRANCH20: + case BFD_RELOC_THUMB_PCREL_BRANCH23: + if (ARM_IS_FUNC (fixp->fx_addsy)) + return 1; + break; + + default: + break; + } +#endif + + /* Resolve these relocations even if the symbol is extern or weak. */ + if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE + || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM + || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE + || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM + || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE + || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 + || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) + return 0; + + /* Always leave these relocations for the linker. */ + if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC + && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) + || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) + return 1; + + /* Always generate relocations against function symbols. */ + if (fixp->fx_r_type == BFD_RELOC_32 + && fixp->fx_addsy + && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) + return 1; + + return generic_force_reloc (fixp); +} + +#if defined (OBJ_ELF) || defined (OBJ_COFF) +/* Relocations against function names must be left unadjusted, + so that the linker can use this information to generate interworking + stubs. The MIPS version of this function + also prevents relocations that are mips-16 specific, but I do not + know why it does this. + + FIXME: + There is one other problem that ought to be addressed here, but + which currently is not: Taking the address of a label (rather + than a function) and then later jumping to that address. Such + addresses also ought to have their bottom bit set (assuming that + they reside in Thumb code), but at the moment they will not. */ + +bfd_boolean +arm_fix_adjustable (fixS * fixP) +{ + if (fixP->fx_addsy == NULL) + return 1; + + /* Preserve relocations against symbols with function type. */ + if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) + return FALSE; + + if (THUMB_IS_FUNC (fixP->fx_addsy) + && fixP->fx_subsy == NULL) + return FALSE; + + /* We need the symbol name for the VTABLE entries. */ + if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) + return FALSE; + + /* Don't allow symbols to be discarded on GOT related relocs. */ + if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 + || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 + || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF + || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 + || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 + || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 + || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 + || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 + || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) + return FALSE; + + /* Similarly for group relocations. */ + if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC + && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) + || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) + return FALSE; + + /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ + if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW + || fixP->fx_r_type == BFD_RELOC_ARM_MOVT + || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL + || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL + || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW + || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT + || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL + || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) + return FALSE; + + return TRUE; +} +#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ + +#ifdef OBJ_ELF + +const char * +elf32_arm_target_format (void) +{ +#ifdef TE_SYMBIAN + return (target_big_endian + ? "elf32-bigarm-symbian" + : "elf32-littlearm-symbian"); +#elif defined (TE_VXWORKS) + return (target_big_endian + ? "elf32-bigarm-vxworks" + : "elf32-littlearm-vxworks"); +#else + if (target_big_endian) + return "elf32-bigarm"; + else + return "elf32-littlearm"; +#endif +} + +void +armelf_frob_symbol (symbolS * symp, + int * puntp) +{ + elf_frob_symbol (symp, puntp); +} +#endif + +/* MD interface: Finalization. */ + +void +arm_cleanup (void) +{ + literal_pool * pool; + + /* Ensure that all the IT blocks are properly closed. */ + check_it_blocks_finished (); + + for (pool = list_of_pools; pool; pool = pool->next) + { + /* Put it at the end of the relevant section. */ + subseg_set (pool->section, pool->sub_section); +#ifdef OBJ_ELF + arm_elf_change_section (); +#endif + s_ltorg (0); + } +} + +#ifdef OBJ_ELF +/* Remove any excess mapping symbols generated for alignment frags in + SEC. We may have created a mapping symbol before a zero byte + alignment; remove it if there's a mapping symbol after the + alignment. */ +static void +check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, + void *dummy ATTRIBUTE_UNUSED) +{ + segment_info_type *seginfo = seg_info (sec); + fragS *fragp; + + if (seginfo == NULL || seginfo->frchainP == NULL) + return; + + for (fragp = seginfo->frchainP->frch_root; + fragp != NULL; + fragp = fragp->fr_next) + { + symbolS *sym = fragp->tc_frag_data.last_map; + fragS *next = fragp->fr_next; + + /* Variable-sized frags have been converted to fixed size by + this point. But if this was variable-sized to start with, + there will be a fixed-size frag after it. So don't handle + next == NULL. */ + if (sym == NULL || next == NULL) + continue; + + if (S_GET_VALUE (sym) < next->fr_address) + /* Not at the end of this frag. */ + continue; + know (S_GET_VALUE (sym) == next->fr_address); + + do + { + if (next->tc_frag_data.first_map != NULL) + { + /* Next frag starts with a mapping symbol. Discard this + one. */ + symbol_remove (sym, &symbol_rootP, &symbol_lastP); + break; + } + + if (next->fr_next == NULL) + { + /* This mapping symbol is at the end of the section. Discard + it. */ + know (next->fr_fix == 0 && next->fr_var == 0); + symbol_remove (sym, &symbol_rootP, &symbol_lastP); + break; + } + + /* As long as we have empty frags without any mapping symbols, + keep looking. */ + /* If the next frag is non-empty and does not start with a + mapping symbol, then this mapping symbol is required. */ + if (next->fr_address != next->fr_next->fr_address) + break; + + next = next->fr_next; + } + while (next != NULL); + } +} +#endif + +/* Adjust the symbol table. This marks Thumb symbols as distinct from + ARM ones. */ + +void +arm_adjust_symtab (void) +{ +#ifdef OBJ_COFF + symbolS * sym; + + for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) + { + if (ARM_IS_THUMB (sym)) + { + if (THUMB_IS_FUNC (sym)) + { + /* Mark the symbol as a Thumb function. */ + if ( S_GET_STORAGE_CLASS (sym) == C_STAT + || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ + S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); + + else if (S_GET_STORAGE_CLASS (sym) == C_EXT) + S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); + else + as_bad (_("%s: unexpected function type: %d"), + S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); + } + else switch (S_GET_STORAGE_CLASS (sym)) + { + case C_EXT: + S_SET_STORAGE_CLASS (sym, C_THUMBEXT); + break; + case C_STAT: + S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); + break; + case C_LABEL: + S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); + break; + default: + /* Do nothing. */ + break; + } + } + + if (ARM_IS_INTERWORK (sym)) + coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; + } +#endif +#ifdef OBJ_ELF + symbolS * sym; + char bind; + + for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) + { + if (ARM_IS_THUMB (sym)) + { + elf_symbol_type * elf_sym; + + elf_sym = elf_symbol (symbol_get_bfdsym (sym)); + bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); + + if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, + BFD_ARM_SPECIAL_SYM_TYPE_ANY)) + { + /* If it's a .thumb_func, declare it as so, + otherwise tag label as .code 16. */ + if (THUMB_IS_FUNC (sym)) + elf_sym->internal_elf_sym.st_info = + ELF_ST_INFO (bind, STT_ARM_TFUNC); + else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) + elf_sym->internal_elf_sym.st_info = + ELF_ST_INFO (bind, STT_ARM_16BIT); + } + } + } + + /* Remove any overlapping mapping symbols generated by alignment frags. */ + bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); +#endif +} + +/* MD interface: Initialization. */ + +static void +set_constant_flonums (void) +{ + int i; + + for (i = 0; i < NUM_FLOAT_VALS; i++) + if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) + abort (); +} + +/* Auto-select Thumb mode if it's the only available instruction set for the + given architecture. */ + +static void +autoselect_thumb_from_cpu_variant (void) +{ + if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) + opcode_select (16); +} + +void +md_begin (void) +{ + unsigned mach; + unsigned int i; + + if ( (arm_ops_hsh = hash_new ()) == NULL + || (arm_cond_hsh = hash_new ()) == NULL + || (arm_shift_hsh = hash_new ()) == NULL + || (arm_psr_hsh = hash_new ()) == NULL + || (arm_v7m_psr_hsh = hash_new ()) == NULL + || (arm_reg_hsh = hash_new ()) == NULL + || (arm_reloc_hsh = hash_new ()) == NULL + || (arm_barrier_opt_hsh = hash_new ()) == NULL) + as_fatal (_("virtual memory exhausted")); + + for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) + hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); + for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) + hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); + for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) + hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); + for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) + hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); + for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) + hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, + (void *) (v7m_psrs + i)); + for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) + hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); + for (i = 0; + i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); + i++) + hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, + (void *) (barrier_opt_names + i)); +#ifdef OBJ_ELF + for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) + hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i)); +#endif + + set_constant_flonums (); + + /* Set the cpu variant based on the command-line options. We prefer + -mcpu= over -march= if both are set (as for GCC); and we prefer + -mfpu= over any other way of setting the floating point unit. + Use of legacy options with new options are faulted. */ + if (legacy_cpu) + { + if (mcpu_cpu_opt || march_cpu_opt) + as_bad (_("use of old and new-style options to set CPU type")); + + mcpu_cpu_opt = legacy_cpu; + } + else if (!mcpu_cpu_opt) + mcpu_cpu_opt = march_cpu_opt; + + if (legacy_fpu) + { + if (mfpu_opt) + as_bad (_("use of old and new-style options to set FPU type")); + + mfpu_opt = legacy_fpu; + } + else if (!mfpu_opt) + { +#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ + || defined (TE_NetBSD) || defined (TE_VXWORKS)) + /* Some environments specify a default FPU. If they don't, infer it + from the processor. */ + if (mcpu_fpu_opt) + mfpu_opt = mcpu_fpu_opt; + else + mfpu_opt = march_fpu_opt; +#else + mfpu_opt = &fpu_default; +#endif + } + + if (!mfpu_opt) + { + if (mcpu_cpu_opt != NULL) + mfpu_opt = &fpu_default; + else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) + mfpu_opt = &fpu_arch_vfp_v2; + else + mfpu_opt = &fpu_arch_fpa; + } + +#ifdef CPU_DEFAULT + if (!mcpu_cpu_opt) + { + mcpu_cpu_opt = &cpu_default; + selected_cpu = cpu_default; + } +#else + if (mcpu_cpu_opt) + selected_cpu = *mcpu_cpu_opt; + else + mcpu_cpu_opt = &arm_arch_any; +#endif + + ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); + + autoselect_thumb_from_cpu_variant (); + + arm_arch_used = thumb_arch_used = arm_arch_none; + +#if defined OBJ_COFF || defined OBJ_ELF + { + unsigned int flags = 0; + +#if defined OBJ_ELF + flags = meabi_flags; + + switch (meabi_flags) + { + case EF_ARM_EABI_UNKNOWN: +#endif + /* Set the flags in the private structure. */ + if (uses_apcs_26) flags |= F_APCS26; + if (support_interwork) flags |= F_INTERWORK; + if (uses_apcs_float) flags |= F_APCS_FLOAT; + if (pic_code) flags |= F_PIC; + if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) + flags |= F_SOFT_FLOAT; + + switch (mfloat_abi_opt) + { + case ARM_FLOAT_ABI_SOFT: + case ARM_FLOAT_ABI_SOFTFP: + flags |= F_SOFT_FLOAT; + break; + + case ARM_FLOAT_ABI_HARD: + if (flags & F_SOFT_FLOAT) + as_bad (_("hard-float conflicts with specified fpu")); + break; + } + + /* Using pure-endian doubles (even if soft-float). */ + if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) + flags |= F_VFP_FLOAT; + +#if defined OBJ_ELF + if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) + flags |= EF_ARM_MAVERICK_FLOAT; + break; + + case EF_ARM_EABI_VER4: + case EF_ARM_EABI_VER5: + /* No additional flags to set. */ + break; + + default: + abort (); + } +#endif + bfd_set_private_flags (stdoutput, flags); + + /* We have run out flags in the COFF header to encode the + status of ATPCS support, so instead we create a dummy, + empty, debug section called .arm.atpcs. */ + if (atpcs) + { + asection * sec; + + sec = bfd_make_section (stdoutput, ".arm.atpcs"); + + if (sec != NULL) + { + bfd_set_section_flags + (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); + bfd_set_section_size (stdoutput, sec, 0); + bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); + } + } + } +#endif + + /* Record the CPU type as well. */ + if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) + mach = bfd_mach_arm_iWMMXt2; + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) + mach = bfd_mach_arm_iWMMXt; + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) + mach = bfd_mach_arm_XScale; + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) + mach = bfd_mach_arm_ep9312; + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) + mach = bfd_mach_arm_5TE; + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) + { + if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) + mach = bfd_mach_arm_5T; + else + mach = bfd_mach_arm_5; + } + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) + { + if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) + mach = bfd_mach_arm_4T; + else + mach = bfd_mach_arm_4; + } + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) + mach = bfd_mach_arm_3M; + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) + mach = bfd_mach_arm_3; + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) + mach = bfd_mach_arm_2a; + else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) + mach = bfd_mach_arm_2; + else + mach = bfd_mach_arm_unknown; + + bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); +} + +/* Command line processing. */ + +/* md_parse_option + Invocation line includes a switch not recognized by the base assembler. + See if it's a processor-specific option. + + This routine is somewhat complicated by the need for backwards + compatibility (since older releases of gcc can't be changed). + The new options try to make the interface as compatible as + possible with GCC. + + New options (supported) are: + + -mcpu= Assemble for selected processor + -march= Assemble for selected architecture + -mfpu= Assemble for selected FPU. + -EB/-mbig-endian Big-endian + -EL/-mlittle-endian Little-endian + -k Generate PIC code + -mthumb Start in Thumb mode + -mthumb-interwork Code supports ARM/Thumb interworking + + -m[no-]warn-deprecated Warn about deprecated features + + For now we will also provide support for: + + -mapcs-32 32-bit Program counter + -mapcs-26 26-bit Program counter + -macps-float Floats passed in FP registers + -mapcs-reentrant Reentrant code + -matpcs + (sometime these will probably be replaced with -mapcs= + and -matpcs=) + + The remaining options are only supported for back-wards compatibility. + Cpu variants, the arm part is optional: + -m[arm]1 Currently not supported. + -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor + -m[arm]3 Arm 3 processor + -m[arm]6[xx], Arm 6 processors + -m[arm]7[xx][t][[d]m] Arm 7 processors + -m[arm]8[10] Arm 8 processors + -m[arm]9[20][tdmi] Arm 9 processors + -mstrongarm[110[0]] StrongARM processors + -mxscale XScale processors + -m[arm]v[2345[t[e]]] Arm architectures + -mall All (except the ARM1) + FP variants: + -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions + -mfpe-old (No float load/store multiples) + -mvfpxd VFP Single precision + -mvfp All VFP + -mno-fpu Disable all floating point instructions + + The following CPU names are recognized: + arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, + arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, + arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, + arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, + arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, + arm10t arm10e, arm1020t, arm1020e, arm10200e, + strongarm, strongarm110, strongarm1100, strongarm1110, xscale. + + */ + +const char * md_shortopts = "m:k"; + +#ifdef ARM_BI_ENDIAN +#define OPTION_EB (OPTION_MD_BASE + 0) +#define OPTION_EL (OPTION_MD_BASE + 1) +#else +#if TARGET_BYTES_BIG_ENDIAN +#define OPTION_EB (OPTION_MD_BASE + 0) +#else +#define OPTION_EL (OPTION_MD_BASE + 1) +#endif +#endif +#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) + +struct option md_longopts[] = +{ +#ifdef OPTION_EB + {"EB", no_argument, NULL, OPTION_EB}, +#endif +#ifdef OPTION_EL + {"EL", no_argument, NULL, OPTION_EL}, +#endif + {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, + {NULL, no_argument, NULL, 0} +}; + +size_t md_longopts_size = sizeof (md_longopts); + +struct arm_option_table +{ + char *option; /* Option name to match. */ + char *help; /* Help information. */ + int *var; /* Variable to change. */ + int value; /* What to change it to. */ + char *deprecated; /* If non-null, print this message. */ +}; + +struct arm_option_table arm_opts[] = +{ + {"k", N_("generate PIC code"), &pic_code, 1, NULL}, + {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, + {"mthumb-interwork", N_("support ARM/Thumb interworking"), + &support_interwork, 1, NULL}, + {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, + {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, + {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, + 1, NULL}, + {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, + {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, + {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, + {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, + NULL}, + + /* These are recognized by the assembler, but have no affect on code. */ + {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, + {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, + + {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, + {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), + &warn_on_deprecated, 0, NULL}, + {NULL, NULL, NULL, 0, NULL} +}; + +struct arm_legacy_option_table +{ + char *option; /* Option name to match. */ + const arm_feature_set **var; /* Variable to change. */ + const arm_feature_set value; /* What to change it to. */ + char *deprecated; /* If non-null, print this message. */ +}; + +const struct arm_legacy_option_table arm_legacy_opts[] = +{ + /* DON'T add any new processors to this list -- we want the whole list + to go away... Add them to the processors table instead. */ + {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, + {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, + {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, + {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, + {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, + {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, + {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, + {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, + {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, + {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, + {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, + {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, + {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, + {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, + {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, + {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, + {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, + {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, + {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, + {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, + {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, + {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, + {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, + {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, + {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, + {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, + {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, + {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, + {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, + {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, + {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, + {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, + {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, + {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, + {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, + {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, + {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, + {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, + {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, + {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, + {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, + {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, + {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, + {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, + {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, + {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, + {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, + {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, + {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, + {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, + {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, + {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, + {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, + {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, + {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, + {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, + {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, + {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, + {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, + {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, + {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, + {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, + {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, + {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, + {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, + {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, + {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, + {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, + {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, + {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, + N_("use -mcpu=strongarm110")}, + {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, + N_("use -mcpu=strongarm1100")}, + {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, + N_("use -mcpu=strongarm1110")}, + {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, + {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, + {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, + + /* Architecture variants -- don't add any more to this list either. */ + {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, + {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, + {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, + {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, + {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, + {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, + {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, + {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, + {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, + {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, + {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, + {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, + {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, + {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, + {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, + {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, + {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, + {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, + + /* Floating point variants -- don't add any more to this list either. */ + {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, + {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, + {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, + {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, + N_("use either -mfpu=softfpa or -mfpu=softvfp")}, + + {NULL, NULL, ARM_ARCH_NONE, NULL} +}; + +struct arm_cpu_option_table +{ + char *name; + const arm_feature_set value; + /* For some CPUs we assume an FPU unless the user explicitly sets + -mfpu=... */ + const arm_feature_set default_fpu; + /* The canonical name of the CPU, or NULL to use NAME converted to upper + case. */ + const char *canonical_name; +}; + +/* This list should, at a minimum, contain all the cpu names + recognized by GCC. */ +static const struct arm_cpu_option_table arm_cpus[] = +{ + {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, + {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, + {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, + {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, + {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, + {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, + {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, + {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, + {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, + {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, + {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, + {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, + /* For V5 or later processors we default to using VFP; but the user + should really set the FPU type explicitly. */ + {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, + {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, + {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, + {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, + {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, + {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, + {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, + {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, + {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, + {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, + {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, + {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, + {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, + {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, + {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, + {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, + {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, + {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, + {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, + {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, + {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, + {"fa626te", ARM_ARCH_V5TE, FPU_NONE, NULL}, + {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, + {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, + {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, + {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, + {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, + {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, + {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, + {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, + {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, + {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, + {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, + {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 + | FPU_NEON_EXT_V1), + NULL}, + {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE (0, FPU_VFP_V3 + | FPU_NEON_EXT_V1), + NULL}, + {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, + {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, + {"cortex-m1", ARM_ARCH_V6M, FPU_NONE, NULL}, + {"cortex-m0", ARM_ARCH_V6M, FPU_NONE, NULL}, + /* ??? XSCALE is really an architecture. */ + {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, + /* ??? iwmmxt is not a processor. */ + {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, + {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, + {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, + /* Maverick */ + {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, + {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} +}; + +struct arm_arch_option_table +{ + char *name; + const arm_feature_set value; + const arm_feature_set default_fpu; +}; + +/* This list should, at a minimum, contain all the architecture names + recognized by GCC. */ +static const struct arm_arch_option_table arm_archs[] = +{ + {"all", ARM_ANY, FPU_ARCH_FPA}, + {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, + {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, + {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, + {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, + {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, + {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, + {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, + {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, + {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, + {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, + {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, + {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, + {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, + {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, + {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, + {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, + {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, + {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, + {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, + {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, + {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, + {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, + {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, + {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, + {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, + {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP}, + {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, + /* The official spelling of the ARMv7 profile variants is the dashed form. + Accept the non-dashed form for compatibility with old toolchains. */ + {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, + {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, + {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, + {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, + {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, + {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, + {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, + {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, + {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, + {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} +}; + +/* ISA extensions in the co-processor space. */ +struct arm_option_cpu_value_table +{ + char *name; + const arm_feature_set value; +}; + +static const struct arm_option_cpu_value_table arm_extensions[] = +{ + {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, + {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, + {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, + {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, + {NULL, ARM_ARCH_NONE} +}; + +/* This list should, at a minimum, contain all the fpu names + recognized by GCC. */ +static const struct arm_option_cpu_value_table arm_fpus[] = +{ + {"softfpa", FPU_NONE}, + {"fpe", FPU_ARCH_FPE}, + {"fpe2", FPU_ARCH_FPE}, + {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ + {"fpa", FPU_ARCH_FPA}, + {"fpa10", FPU_ARCH_FPA}, + {"fpa11", FPU_ARCH_FPA}, + {"arm7500fe", FPU_ARCH_FPA}, + {"softvfp", FPU_ARCH_VFP}, + {"softvfp+vfp", FPU_ARCH_VFP_V2}, + {"vfp", FPU_ARCH_VFP_V2}, + {"vfp9", FPU_ARCH_VFP_V2}, + {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ + {"vfp10", FPU_ARCH_VFP_V2}, + {"vfp10-r0", FPU_ARCH_VFP_V1}, + {"vfpxd", FPU_ARCH_VFP_V1xD}, + {"vfpv2", FPU_ARCH_VFP_V2}, + {"vfpv3", FPU_ARCH_VFP_V3}, + {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, + {"arm1020t", FPU_ARCH_VFP_V1}, + {"arm1020e", FPU_ARCH_VFP_V2}, + {"arm1136jfs", FPU_ARCH_VFP_V2}, + {"arm1136jf-s", FPU_ARCH_VFP_V2}, + {"maverick", FPU_ARCH_MAVERICK}, + {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, + {"neon-fp16", FPU_ARCH_NEON_FP16}, + {NULL, ARM_ARCH_NONE} +}; + +struct arm_option_value_table +{ + char *name; + long value; +}; + +static const struct arm_option_value_table arm_float_abis[] = +{ + {"hard", ARM_FLOAT_ABI_HARD}, + {"softfp", ARM_FLOAT_ABI_SOFTFP}, + {"soft", ARM_FLOAT_ABI_SOFT}, + {NULL, 0} +}; + +#ifdef OBJ_ELF +/* We only know how to output GNU and ver 4/5 (AAELF) formats. */ +static const struct arm_option_value_table arm_eabis[] = +{ + {"gnu", EF_ARM_EABI_UNKNOWN}, + {"4", EF_ARM_EABI_VER4}, + {"5", EF_ARM_EABI_VER5}, + {NULL, 0} +}; +#endif + +struct arm_long_option_table +{ + char * option; /* Substring to match. */ + char * help; /* Help information. */ + int (* func) (char * subopt); /* Function to decode sub-option. */ + char * deprecated; /* If non-null, print this message. */ +}; + +static bfd_boolean +arm_parse_extension (char * str, const arm_feature_set **opt_p) +{ + arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); + + /* Copy the feature set, so that we can modify it. */ + *ext_set = **opt_p; + *opt_p = ext_set; + + while (str != NULL && *str != 0) + { + const struct arm_option_cpu_value_table * opt; + char * ext; + int optlen; + + if (*str != '+') + { + as_bad (_("invalid architectural extension")); + return FALSE; + } + + str++; + ext = strchr (str, '+'); + + if (ext != NULL) + optlen = ext - str; + else + optlen = strlen (str); + + if (optlen == 0) + { + as_bad (_("missing architectural extension")); + return FALSE; + } + + for (opt = arm_extensions; opt->name != NULL; opt++) + if (strncmp (opt->name, str, optlen) == 0) + { + ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); + break; + } + + if (opt->name == NULL) + { + as_bad (_("unknown architectural extension `%s'"), str); + return FALSE; + } + + str = ext; + }; + + return TRUE; +} + +static bfd_boolean +arm_parse_cpu (char * str) +{ + const struct arm_cpu_option_table * opt; + char * ext = strchr (str, '+'); + int optlen; + + if (ext != NULL) + optlen = ext - str; + else + optlen = strlen (str); + + if (optlen == 0) + { + as_bad (_("missing cpu name `%s'"), str); + return FALSE; + } + + for (opt = arm_cpus; opt->name != NULL; opt++) + if (strncmp (opt->name, str, optlen) == 0) + { + mcpu_cpu_opt = &opt->value; + mcpu_fpu_opt = &opt->default_fpu; + if (opt->canonical_name) + strcpy (selected_cpu_name, opt->canonical_name); + else + { + int i; + + for (i = 0; i < optlen; i++) + selected_cpu_name[i] = TOUPPER (opt->name[i]); + selected_cpu_name[i] = 0; + } + + if (ext != NULL) + return arm_parse_extension (ext, &mcpu_cpu_opt); + + return TRUE; + } + + as_bad (_("unknown cpu `%s'"), str); + return FALSE; +} + +static bfd_boolean +arm_parse_arch (char * str) +{ + const struct arm_arch_option_table *opt; + char *ext = strchr (str, '+'); + int optlen; + + if (ext != NULL) + optlen = ext - str; + else + optlen = strlen (str); + + if (optlen == 0) + { + as_bad (_("missing architecture name `%s'"), str); + return FALSE; + } + + for (opt = arm_archs; opt->name != NULL; opt++) + if (streq (opt->name, str)) + { + march_cpu_opt = &opt->value; + march_fpu_opt = &opt->default_fpu; + strcpy (selected_cpu_name, opt->name); + + if (ext != NULL) + return arm_parse_extension (ext, &march_cpu_opt); + + return TRUE; + } + + as_bad (_("unknown architecture `%s'\n"), str); + return FALSE; +} + +static bfd_boolean +arm_parse_fpu (char * str) +{ + const struct arm_option_cpu_value_table * opt; + + for (opt = arm_fpus; opt->name != NULL; opt++) + if (streq (opt->name, str)) + { + mfpu_opt = &opt->value; + return TRUE; + } + + as_bad (_("unknown floating point format `%s'\n"), str); + return FALSE; +} + +static bfd_boolean +arm_parse_float_abi (char * str) +{ + const struct arm_option_value_table * opt; + + for (opt = arm_float_abis; opt->name != NULL; opt++) + if (streq (opt->name, str)) + { + mfloat_abi_opt = opt->value; + return TRUE; + } + + as_bad (_("unknown floating point abi `%s'\n"), str); + return FALSE; +} + +#ifdef OBJ_ELF +static bfd_boolean +arm_parse_eabi (char * str) +{ + const struct arm_option_value_table *opt; + + for (opt = arm_eabis; opt->name != NULL; opt++) + if (streq (opt->name, str)) + { + meabi_flags = opt->value; + return TRUE; + } + as_bad (_("unknown EABI `%s'\n"), str); + return FALSE; +} +#endif + +static bfd_boolean +arm_parse_it_mode (char * str) +{ + bfd_boolean ret = TRUE; + + if (streq ("arm", str)) + implicit_it_mode = IMPLICIT_IT_MODE_ARM; + else if (streq ("thumb", str)) + implicit_it_mode = IMPLICIT_IT_MODE_THUMB; + else if (streq ("always", str)) + implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; + else if (streq ("never", str)) + implicit_it_mode = IMPLICIT_IT_MODE_NEVER; + else + { + as_bad (_("unknown implicit IT mode `%s', should be "\ + "arm, thumb, always, or never."), str); + ret = FALSE; + } + + return ret; +} + +struct arm_long_option_table arm_long_opts[] = +{ + {"mcpu=", N_("\t assemble for CPU "), + arm_parse_cpu, NULL}, + {"march=", N_("\t assemble for architecture "), + arm_parse_arch, NULL}, + {"mfpu=", N_("\t assemble for FPU architecture "), + arm_parse_fpu, NULL}, + {"mfloat-abi=", N_("\t assemble for floating point ABI "), + arm_parse_float_abi, NULL}, +#ifdef OBJ_ELF + {"meabi=", N_("\t\t assemble for eabi version "), + arm_parse_eabi, NULL}, +#endif + {"mimplicit-it=", N_("\t controls implicit insertion of IT instructions"), + arm_parse_it_mode, NULL}, + {NULL, NULL, 0, NULL} +}; + +int +md_parse_option (int c, char * arg) +{ + struct arm_option_table *opt; + const struct arm_legacy_option_table *fopt; + struct arm_long_option_table *lopt; + + switch (c) + { +#ifdef OPTION_EB + case OPTION_EB: + target_big_endian = 1; + break; +#endif + +#ifdef OPTION_EL + case OPTION_EL: + target_big_endian = 0; + break; +#endif + + case OPTION_FIX_V4BX: + fix_v4bx = TRUE; + break; + + case 'a': + /* Listing option. Just ignore these, we don't support additional + ones. */ + return 0; + + default: + for (opt = arm_opts; opt->option != NULL; opt++) + { + if (c == opt->option[0] + && ((arg == NULL && opt->option[1] == 0) + || streq (arg, opt->option + 1))) + { + /* If the option is deprecated, tell the user. */ + if (warn_on_deprecated && opt->deprecated != NULL) + as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, + arg ? arg : "", _(opt->deprecated)); + + if (opt->var != NULL) + *opt->var = opt->value; + + return 1; + } + } + + for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) + { + if (c == fopt->option[0] + && ((arg == NULL && fopt->option[1] == 0) + || streq (arg, fopt->option + 1))) + { + /* If the option is deprecated, tell the user. */ + if (warn_on_deprecated && fopt->deprecated != NULL) + as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, + arg ? arg : "", _(fopt->deprecated)); + + if (fopt->var != NULL) + *fopt->var = &fopt->value; + + return 1; + } + } + + for (lopt = arm_long_opts; lopt->option != NULL; lopt++) + { + /* These options are expected to have an argument. */ + if (c == lopt->option[0] + && arg != NULL + && strncmp (arg, lopt->option + 1, + strlen (lopt->option + 1)) == 0) + { + /* If the option is deprecated, tell the user. */ + if (warn_on_deprecated && lopt->deprecated != NULL) + as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, + _(lopt->deprecated)); + + /* Call the sup-option parser. */ + return lopt->func (arg + strlen (lopt->option) - 1); + } + } + + return 0; + } + + return 1; +} + +void +md_show_usage (FILE * fp) +{ + struct arm_option_table *opt; + struct arm_long_option_table *lopt; + + fprintf (fp, _(" ARM-specific assembler options:\n")); + + for (opt = arm_opts; opt->option != NULL; opt++) + if (opt->help != NULL) + fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); + + for (lopt = arm_long_opts; lopt->option != NULL; lopt++) + if (lopt->help != NULL) + fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); + +#ifdef OPTION_EB + fprintf (fp, _("\ + -EB assemble code for a big-endian cpu\n")); +#endif + +#ifdef OPTION_EL + fprintf (fp, _("\ + -EL assemble code for a little-endian cpu\n")); +#endif + + fprintf (fp, _("\ + --fix-v4bx Allow BX in ARMv4 code\n")); +} + + +#ifdef OBJ_ELF +typedef struct +{ + int val; + arm_feature_set flags; +} cpu_arch_ver_table; + +/* Mapping from CPU features to EABI CPU arch values. Table must be sorted + least features first. */ +static const cpu_arch_ver_table cpu_arch_ver[] = +{ + {1, ARM_ARCH_V4}, + {2, ARM_ARCH_V4T}, + {3, ARM_ARCH_V5}, + {3, ARM_ARCH_V5T}, + {4, ARM_ARCH_V5TE}, + {5, ARM_ARCH_V5TEJ}, + {6, ARM_ARCH_V6}, + {7, ARM_ARCH_V6Z}, + {9, ARM_ARCH_V6K}, + {11, ARM_ARCH_V6M}, + {8, ARM_ARCH_V6T2}, + {10, ARM_ARCH_V7A}, + {10, ARM_ARCH_V7R}, + {10, ARM_ARCH_V7M}, + {0, ARM_ARCH_NONE} +}; + +/* Set an attribute if it has not already been set by the user. */ +static void +aeabi_set_attribute_int (int tag, int value) +{ + if (tag < 1 + || tag >= NUM_KNOWN_OBJ_ATTRIBUTES + || !attributes_set_explicitly[tag]) + bfd_elf_add_proc_attr_int (stdoutput, tag, value); +} + +static void +aeabi_set_attribute_string (int tag, const char *value) +{ + if (tag < 1 + || tag >= NUM_KNOWN_OBJ_ATTRIBUTES + || !attributes_set_explicitly[tag]) + bfd_elf_add_proc_attr_string (stdoutput, tag, value); +} + +/* Set the public EABI object attributes. */ +static void +aeabi_set_public_attributes (void) +{ + int arch; + arm_feature_set flags; + arm_feature_set tmp; + const cpu_arch_ver_table *p; + + /* Choose the architecture based on the capabilities of the requested cpu + (if any) and/or the instructions actually used. */ + ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); + ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); + ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); + /*Allow the user to override the reported architecture. */ + if (object_arch) + { + ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); + ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); + } + + tmp = flags; + arch = 0; + for (p = cpu_arch_ver; p->val; p++) + { + if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) + { + arch = p->val; + ARM_CLEAR_FEATURE (tmp, tmp, p->flags); + } + } + + /* Tag_CPU_name. */ + if (selected_cpu_name[0]) + { + char *p; + + p = selected_cpu_name; + if (strncmp (p, "armv", 4) == 0) + { + int i; + + p += 4; + for (i = 0; p[i]; i++) + p[i] = TOUPPER (p[i]); + } + aeabi_set_attribute_string (Tag_CPU_name, p); + } + /* Tag_CPU_arch. */ + aeabi_set_attribute_int (Tag_CPU_arch, arch); + /* Tag_CPU_arch_profile. */ + if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) + aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); + else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) + aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); + else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) + aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); + /* Tag_ARM_ISA_use. */ + if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) + || arch == 0) + aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); + /* Tag_THUMB_ISA_use. */ + if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) + || arch == 0) + aeabi_set_attribute_int (Tag_THUMB_ISA_use, + ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); + /* Tag_VFP_arch. */ + if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) + aeabi_set_attribute_int (Tag_VFP_arch, 3); + else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3)) + aeabi_set_attribute_int (Tag_VFP_arch, 4); + else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) + aeabi_set_attribute_int (Tag_VFP_arch, 2); + else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) + || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) + aeabi_set_attribute_int (Tag_VFP_arch, 1); + /* Tag_WMMX_arch. */ + if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) + aeabi_set_attribute_int (Tag_WMMX_arch, 2); + else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) + aeabi_set_attribute_int (Tag_WMMX_arch, 1); + /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ + if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) + aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); + /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ + if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_fp16)) + aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); +} + +/* Add the default contents for the .ARM.attributes section. */ +void +arm_md_end (void) +{ + if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) + return; + + aeabi_set_public_attributes (); +} +#endif /* OBJ_ELF */ + + +/* Parse a .cpu directive. */ + +static void +s_arm_cpu (int ignored ATTRIBUTE_UNUSED) +{ + const struct arm_cpu_option_table *opt; + char *name; + char saved_char; + + name = input_line_pointer; + while (*input_line_pointer && !ISSPACE (*input_line_pointer)) + input_line_pointer++; + saved_char = *input_line_pointer; + *input_line_pointer = 0; + + /* Skip the first "all" entry. */ + for (opt = arm_cpus + 1; opt->name != NULL; opt++) + if (streq (opt->name, name)) + { + mcpu_cpu_opt = &opt->value; + selected_cpu = opt->value; + if (opt->canonical_name) + strcpy (selected_cpu_name, opt->canonical_name); + else + { + int i; + for (i = 0; opt->name[i]; i++) + selected_cpu_name[i] = TOUPPER (opt->name[i]); + selected_cpu_name[i] = 0; + } + ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); + return; + } + as_bad (_("unknown cpu `%s'"), name); + *input_line_pointer = saved_char; + ignore_rest_of_line (); +} + + +/* Parse a .arch directive. */ + +static void +s_arm_arch (int ignored ATTRIBUTE_UNUSED) +{ + const struct arm_arch_option_table *opt; + char saved_char; + char *name; + + name = input_line_pointer; + while (*input_line_pointer && !ISSPACE (*input_line_pointer)) + input_line_pointer++; + saved_char = *input_line_pointer; + *input_line_pointer = 0; + + /* Skip the first "all" entry. */ + for (opt = arm_archs + 1; opt->name != NULL; opt++) + if (streq (opt->name, name)) + { + mcpu_cpu_opt = &opt->value; + selected_cpu = opt->value; + strcpy (selected_cpu_name, opt->name); + ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); + return; + } + + as_bad (_("unknown architecture `%s'\n"), name); + *input_line_pointer = saved_char; + ignore_rest_of_line (); +} + + +/* Parse a .object_arch directive. */ + +static void +s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) +{ + const struct arm_arch_option_table *opt; + char saved_char; + char *name; + + name = input_line_pointer; + while (*input_line_pointer && !ISSPACE (*input_line_pointer)) + input_line_pointer++; + saved_char = *input_line_pointer; + *input_line_pointer = 0; + + /* Skip the first "all" entry. */ + for (opt = arm_archs + 1; opt->name != NULL; opt++) + if (streq (opt->name, name)) + { + object_arch = &opt->value; + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); + return; + } + + as_bad (_("unknown architecture `%s'\n"), name); + *input_line_pointer = saved_char; + ignore_rest_of_line (); +} + +/* Parse a .fpu directive. */ + +static void +s_arm_fpu (int ignored ATTRIBUTE_UNUSED) +{ + const struct arm_option_cpu_value_table *opt; + char saved_char; + char *name; + + name = input_line_pointer; + while (*input_line_pointer && !ISSPACE (*input_line_pointer)) + input_line_pointer++; + saved_char = *input_line_pointer; + *input_line_pointer = 0; + + for (opt = arm_fpus; opt->name != NULL; opt++) + if (streq (opt->name, name)) + { + mfpu_opt = &opt->value; + ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); + *input_line_pointer = saved_char; + demand_empty_rest_of_line (); + return; + } + + as_bad (_("unknown floating point format `%s'\n"), name); + *input_line_pointer = saved_char; + ignore_rest_of_line (); +} + +/* Copy symbol information. */ + +void +arm_copy_symbol_attributes (symbolS *dest, symbolS *src) +{ + ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); +} + +#ifdef OBJ_ELF +/* Given a symbolic attribute NAME, return the proper integer value. + Returns -1 if the attribute is not known. */ + +int +arm_convert_symbolic_attribute (const char *name) +{ + static const struct + { + const char * name; + const int tag; + } + attribute_table[] = + { + /* When you modify this table you should + also modify the list in doc/c-arm.texi. */ +#define T(tag) {#tag, tag} + T (Tag_CPU_raw_name), + T (Tag_CPU_name), + T (Tag_CPU_arch), + T (Tag_CPU_arch_profile), + T (Tag_ARM_ISA_use), + T (Tag_THUMB_ISA_use), + T (Tag_VFP_arch), + T (Tag_WMMX_arch), + T (Tag_Advanced_SIMD_arch), + T (Tag_PCS_config), + T (Tag_ABI_PCS_R9_use), + T (Tag_ABI_PCS_RW_data), + T (Tag_ABI_PCS_RO_data), + T (Tag_ABI_PCS_GOT_use), + T (Tag_ABI_PCS_wchar_t), + T (Tag_ABI_FP_rounding), + T (Tag_ABI_FP_denormal), + T (Tag_ABI_FP_exceptions), + T (Tag_ABI_FP_user_exceptions), + T (Tag_ABI_FP_number_model), + T (Tag_ABI_align8_needed), + T (Tag_ABI_align8_preserved), + T (Tag_ABI_enum_size), + T (Tag_ABI_HardFP_use), + T (Tag_ABI_VFP_args), + T (Tag_ABI_WMMX_args), + T (Tag_ABI_optimization_goals), + T (Tag_ABI_FP_optimization_goals), + T (Tag_compatibility), + T (Tag_CPU_unaligned_access), + T (Tag_VFP_HP_extension), + T (Tag_ABI_FP_16bit_format), + T (Tag_nodefaults), + T (Tag_also_compatible_with), + T (Tag_conformance), + T (Tag_T2EE_use), + T (Tag_Virtualization_use), + T (Tag_MPextension_use) +#undef T + }; + unsigned int i; + + if (name == NULL) + return -1; + + for (i = 0; i < ARRAY_SIZE (attribute_table); i++) + if (streq (name, attribute_table[i].name)) + return attribute_table[i].tag; + + return -1; +} + + +/* Apply sym value for relocations only in the case that + they are for local symbols and you have the respective + architectural feature for blx and simple switches. */ +int +arm_apply_sym_value (struct fix * fixP) +{ + if (fixP->fx_addsy + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) + && !S_IS_EXTERNAL (fixP->fx_addsy)) + { + switch (fixP->fx_r_type) + { + case BFD_RELOC_ARM_PCREL_BLX: + case BFD_RELOC_THUMB_PCREL_BRANCH23: + if (ARM_IS_FUNC (fixP->fx_addsy)) + return 1; + break; + + case BFD_RELOC_ARM_PCREL_CALL: + case BFD_RELOC_THUMB_PCREL_BLX: + if (THUMB_IS_FUNC (fixP->fx_addsy)) + return 1; + break; + + default: + break; + } + + } + return 0; +} +#endif /* OBJ_ELF */