Please enable RISC-V on mir-team/mesa-core20-beta snaps
Asked by
Michał Sawicz
Please enable RISC-V on mir-team/
https:/
Thanks!
Question information
- Language:
- English Edit question
- Status:
- Solved
- Assignee:
- No assignee Edit question
- Solved by:
- Colin Watson
- Solved:
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