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Multiple Design Rules (Specifically Space) For A Single Net

Asked by Ian Woloschin

Is there any method for setting up multiple design rules for a single net? For instance, I'm trying route USB 2.0 signal lines (D+/D-) to a BGA part. From the USB connector to the BGA, I'd like to have one set of trace width/space, in order to create a transmission line (coupled microstrip?). However, once I get to the BGA, I need to slip one of the USB 2.0 lines in between some pads, which requires a small trace/space setting. I know I can set up some "generic" trace widths, but I can't find anywhere that would let me set up generic "trace spaces."

I've somewhat overcome the problem by setting up the Nets under one Design Rule, drawing that portion, and then moving the Nets to a second Design Rule and finishing the trace. This does appear to work, though I'm assuming it will throw errors when I try to run a DRC? I'm not sure if there's a better way to do this, or if anyone else even really has this problem.

Thanks!

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Seth Hillbrand
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Lorenzo Marcantonio (l-marcantonio) said : 		#1

On Thu, Jan 26, 2012 at 09:35:38PM -0000, Ian Woloschin wrote:
> New question #185949 on KiCad:
> https://answers.launchpad.net/kicad/+question/185949
>
> Is there any method for setting up multiple design rules for a single net? For instance, I'm trying route USB 2.0 signal lines (D+/D-) to a BGA part. From the USB connector to the BGA, I'd like to have one set of trace width/space, in order to create a transmission line (coupled microstrip?). However, once I get to the BGA, I need to slip one of the USB 2.0 lines in between some pads, which requires a small trace/space setting. I know I can set up some "generic" trace widths, but I can't find anywhere that would let me set up generic "trace spaces."

Had the *same* problem (not a BGA - only a SOP).

You can 'split' a net using dummy components (declared virtual, think about two pad attached...). Not the easiest thing but possible.

Since usually coupled stripline run mostly straight (and are carefully placed) I adopted another solution: standard design rules and manually placed tracks (the track length indicator also helps avoiding signal skew).

BTW the 'generic' space is simply that of the default netclass...

--
Lorenzo Marcantonio
Logos Srl

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Bruno A. Almeida (brunoeagle) said : 		#2

I have this same problem, but the nets that I most have problems is with the power lines.

What I always do is that what you've already do, draw the portion of the track with a design rule and after this I change again the design rule. But it dont generate erros when run DRC, at least it never occurred here.

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hds sdse (hsdsee443) said : 		#3

We tried and failed to reproduce this behavior on trying out hardware regionally however had been unable to achieve this. Looking into the logs of affected devices we typically see that the closing aspect wpa_supplicant wants to do is roam between get admission to points. See more here https://nftfrog.com/

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Seth Hillbrand (sethh) said : 		#4

Removing to delete comment spam