Inconsistent handling of unaligned read
The following occurs in Atmel Studio7, with the ARM GNU Toolchain 5.3.1 and an ARM M0+ target.
The -Wall and -Wextra compiler flags are set, but no warning or error message is given.
With no optimization, the c code
adclin = (*(volatile uint16_t*) 0x00806023);
compiles to
dc8e: 4b2f ldr r3, [pc, #188] ; (dd4c <InitADC+0xc4>)
dc90: 881b ldrh r3, [r3, #0]
which is an unaligned half-word read, and causes a HardFault exception.
With Optimization(-O1), the compiled code is
9406: 4a24 ldr r2, [pc, #144] ; (9498 <InitADC+0x94>)
9408: 7811 ldrb r1, [r2, #0]
940a: 7853 ldrb r3, [r2, #1]
940c: 021b lsls r3, r3, #8
940e: 430b orrs r3, r1
which performs two byte reads and assembles the half word, thus avoiding the exception.
Is this a compiler bug? I would expect the compiler to be consistent, and to either handle the case or issue an error message.
Question information
- Language:
- English Edit question
- Status:
- Solved
- Assignee:
- No assignee Edit question
- Solved by:
- Thomas Preud'homme
- Solved:
- Last query:
- Last reply: