GNU ARM Assembler conversion of ARM assembly source code

Asked by Steffen Sutton

Hello,

It's my understanding that the GNU ARM assembler is responsible for converting ARM assembly language source code into
binary object files.

I have a mixed project of C & assembly.
My assembly code is written in ARM assembly.
When building, the assembler is throwing an error on every assembly file line citing:

temp.s(x): error: bad instruction ' '

I changed the comment syntax from ARM assembly to GNU assembly for the description at the beginning of the file and those lines were removed from the assembly error messages.

Is my understanding of the GNU ARM assembly correct or do I need to rewrite my source in GNU syntax? Is there another alternative available?

Thank you,
steffensq

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Tejas Belagod (belagod-tejas) said :
#1

Hi,

I would recommend you read the documentation for GNU Assembler here:

https://sourceware.org/binutils/docs/as/

When you say ARM Assembler - do you mean the syntax described in the ARM Assembler Toolchain here:

http://infocenter.arm.com/help/topic/com.arm.doc.dui0489f/DUI0489F_arm_assembler_reference.pdf

To help you with the GNU ARM assembler errors that you're seeing, we'll need more information like the actual test case, the command-line you're using to assemble the test etc.

Thanks,
Tejas.

Revision history for this message
Steffen Sutton (steffensq) said :
#2

I'm building for a Samsung S3C2410 which has an arm920t core.

Assembler control string:

-mcpu=arm920t --gdwarf-2 -mthumb-interwork --MD *.d -mcpu=arm920t -I"C:/Program Files (x86)/GNU Tools ARM Embedded/5.4 2016q3/CMSIS/Include" -I"C:/Program Files (x86)/GNU Tools ARM Embedded/5.4 2016q3/Inc/Samsung" -I"C:/Program Files (x86)/GNU Tools ARM Embedded/5.4 2016q3/arm-none-eabi/include" -I"C:/Program Files (x86)/GNU Tools ARM Embedded/5.4 2016q3/lib/gcc/arm-none-eabi/5.4.1/include" -I"C:/Program Files (x86)/GNU Tools ARM Embedded/5.4 2016q3/arm-none-eabi/include/c++/5.4.1" -I"C:/Program Files (x86)/GNU Tools ARM Embedded/5.4 2016q3/arm-none-eabi/include/c++/5.4.1/arm-none-eabi" -alhms="*.lst" -o *.o

Yes, the syntax referenced is described in the ARM assembly toolchain link you provided.

Please let me know if anything else is needed.

Revision history for this message
Thomas Preud'homme (thomas-preudhomme) said :
#3

Hi Steffen,

It's difficult to tell you what's wrong without seeing the assembly file that you are trying to compile. I'm going to take a shot in the dark though: do you have .syntax unified at the top of the file?

Best regards.

Revision history for this message
Steffen Sutton (steffensq) said :
#4

;=====================================================================
; File Name : 2410slib.s
; Function : S3C2410 (Assembly)
; Program : Shin, On Pil (SOP)
; Date : March 20, 2002
; Version : 0.0
; History
; 0.0 : Programming start (February 26,2002) -> SOP
;=====================================================================

;Interrupt, FIQ/IRQ disable
NOINT EQU 0xc0 ;1100 0000

;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
   GBLL THUMBCODE
   [ {CONFIG} = 16
THUMBCODE SETL {TRUE}
        CODE32
   |
THUMBCODE SETL {FALSE}
   ]

   MACRO
       MOV_PC_LR
       [ THUMBCODE
           bx lr
       |
           mov pc,lr
       ]
   MEND

   AREA |C$$code|, CODE, READONLY
;==============
; CPSR I,F bit
;==============
;int SET_IF(void);
;The return value is current CPSR.
    EXPORT SET_IF
SET_IF
    ;This function works only if the processor is in previliged mode.
   mrs r0,cpsr
   mov r1,r0
   orr r1,r1,#NOINT
   msr cpsr_cxsf,r1
   MOV_PC_LR

;void WR_IF(int cpsrValue);
   EXPORT WR_IF
WR_IF
    ;This function works only if the processor is in previliged mode.
   msr cpsr_cxsf,r0
   MOV_PC_LR

;void CLR_IF(void);
   EXPORT CLR_IF
CLR_IF
    ;This function works only if the processor is in previliged mode.
   mrs r0,cpsr
   bic r0,r0,#NOINT
   msr cpsr_cxsf,r0
   MOV_PC_LR

;====================================
; MMU Cache/TLB/etc on/off functions
;====================================
R1_I EQU (1<<12)
R1_C EQU (1<<2)
R1_A EQU (1<<1)
R1_M EQU (1)
R1_iA EQU (1<<31)
R1_nF EQU (1<<30)

;void MMU_EnableICache(void)
   EXPORT MMU_EnableICache
MMU_EnableICache
   mrc p15,0,r0,c1,c0,0
   orr r0,r0,#R1_I
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_DisableICache(void)
   EXPORT MMU_DisableICache
MMU_DisableICache
   mrc p15,0,r0,c1,c0,0
   bic r0,r0,#R1_I
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_EnableDCache(void)
   EXPORT MMU_EnableDCache
MMU_EnableDCache
   mrc p15,0,r0,c1,c0,0
   orr r0,r0,#R1_C
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_DisableDCache(void)
   EXPORT MMU_DisableDCache
MMU_DisableDCache
   mrc p15,0,r0,c1,c0,0
   bic r0,r0,#R1_C
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_EnableAlignFault(void)
   EXPORT MMU_EnableAlignFault
MMU_EnableAlignFault
   mrc p15,0,r0,c1,c0,0
   orr r0,r0,#R1_A
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_DisableAlignFault(void)
   EXPORT MMU_DisableAlignFault
MMU_DisableAlignFault
   mrc p15,0,r0,c1,c0,0
   bic r0,r0,#R1_A
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_EnableMMU(void)
   EXPORT MMU_EnableMMU
MMU_EnableMMU
   mrc p15,0,r0,c1,c0,0
   orr r0,r0,#R1_M
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_DisableMMU(void)
   EXPORT MMU_DisableMMU
MMU_DisableMMU
   mrc p15,0,r0,c1,c0,0
   bic r0,r0,#R1_M
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_SetFastBusMode(void)
; FCLK:HCLK= 1:1
  EXPORT MMU_SetFastBusMode
MMU_SetFastBusMode
   mrc p15,0,r0,c1,c0,0
   bic r0,r0,#R1_iA:OR:R1_nF
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;void MMU_SetAsyncBusMode(void)
; FCLK:HCLK= 1:2
   EXPORT MMU_SetAsyncBusMode
MMU_SetAsyncBusMode
   mrc p15,0,r0,c1,c0,0
   orr r0,r0,#R1_nF:OR:R1_iA
   mcr p15,0,r0,c1,c0,0
   MOV_PC_LR

;=========================
; Set TTBase
;=========================
;void MMU_SetTTBase(int base)
   EXPORT MMU_SetTTBase
MMU_SetTTBase
   ;ro=TTBase
   mcr p15,0,r0,c2,c0,0
   MOV_PC_LR

;=========================
; Set Domain
;=========================
;void MMU_SetDomain(int domain)
   EXPORT MMU_SetDomain
MMU_SetDomain
   ;ro=domain
   mcr p15,0,r0,c3,c0,0
   MOV_PC_LR

;=========================
; ICache/DCache functions
;=========================
;void MMU_InvalidateIDCache(void)
   EXPORT MMU_InvalidateIDCache
MMU_InvalidateIDCache
   mcr p15,0,r0,c7,c7,0
   MOV_PC_LR

;void MMU_InvalidateICache(void)
   EXPORT MMU_InvalidateICache
MMU_InvalidateICache
   mcr p15,0,r0,c7,c5,0
   MOV_PC_LR

;void MMU_InvalidateICacheMVA(U32 mva)
   EXPORT MMU_InvalidateICacheMVA
MMU_InvalidateICacheMVA
   ;r0=mva
   mcr p15,0,r0,c7,c5,1
   MOV_PC_LR

;void MMU_PrefetchICacheMVA(U32 mva)
   EXPORT MMU_PrefetchICacheMVA
MMU_PrefetchICacheMVA
   ;r0=mva
   mcr p15,0,r0,c7,c13,1
   MOV_PC_LR

;void MMU_InvalidateDCache(void)
   EXPORT MMU_InvalidateDCache
MMU_InvalidateDCache
   mcr p15,0,r0,c7,c6,0
   MOV_PC_LR

;void MMU_InvalidateDCacheMVA(U32 mva)
   EXPORT MMU_InvalidateDCacheMVA
MMU_InvalidateDCacheMVA
   ;r0=mva
   mcr p15,0,r0,c7,c6,1
   MOV_PC_LR

;void MMU_CleanDCacheMVA(U32 mva)
   EXPORT MMU_CleanDCacheMVA
MMU_CleanDCacheMVA
   ;r0=mva
   mcr p15,0,r0,c7,c10,1
   MOV_PC_LR

;void MMU_CleanInvalidateDCacheMVA(U32 mva)
   EXPORT MMU_CleanInvalidateDCacheMVA
MMU_CleanInvalidateDCacheMVA
   ;r0=mva
   mcr p15,0,r0,c7,c14,1
   MOV_PC_LR

;void MMU_CleanDCacheIndex(U32 index)
   EXPORT MMU_CleanDCacheIndex
MMU_CleanDCacheIndex
   ;r0=index
   mcr p15,0,r0,c7,c10,2
   MOV_PC_LR

;void MMU_CleanInvalidateDCacheIndex(U32 index)
   EXPORT MMU_CleanInvalidateDCacheIndex
MMU_CleanInvalidateDCacheIndex
   ;r0=index
   mcr p15,0,r0,c7,c14,2
   MOV_PC_LR

;void MMU_WaitForInterrupt(void)
   EXPORT MMU_WaitForInterrupt
MMU_WaitForInterrupt
   mcr p15,0,r0,c7,c0,4
   MOV_PC_LR

;===============
; TLB functions
;===============
;voic MMU_InvalidateTLB(void)
   EXPORT MMU_InvalidateTLB
MMU_InvalidateTLB
   mcr p15,0,r0,c8,c7,0
   MOV_PC_LR

;void MMU_InvalidateITLB(void)
   EXPORT MMU_InvalidateITLB
MMU_InvalidateITLB
   mcr p15,0,r0,c8,c5,0
   MOV_PC_LR

;void MMU_InvalidateITLBMVA(U32 mva)
   EXPORT MMU_InvalidateITLBMVA
MMU_InvalidateITLBMVA
   ;ro=mva
   mcr p15,0,r0,c8,c5,1
   MOV_PC_LR

;void MMU_InvalidateDTLB(void)
   EXPORT MMU_InvalidateDTLB
MMU_InvalidateDTLB
   mcr p15,0,r0,c8,c6,0
   MOV_PC_LR

;void MMU_InvalidateDTLBMVA(U32 mva)
   EXPORT MMU_InvalidateDTLBMVA
MMU_InvalidateDTLBMVA
        ;r0=mva
   mcr p15,0,r0,c8,c6,1
   MOV_PC_LR

;=================
; Cache lock down
;=================
;void MMU_SetDCacheLockdownBase(U32 base)
   EXPORT MMU_SetDCacheLockdownBase
MMU_SetDCacheLockdownBase
   ;r0= victim & lockdown base
   mcr p15,0,r0,c9,c0,0
   MOV_PC_LR

;void MMU_SetICacheLockdownBase(U32 base)
   EXPORT MMU_SetICacheLockdownBase
MMU_SetICacheLockdownBase
   ;r0= victim & lockdown base
   mcr p15,0,r0,c9,c0,1
   MOV_PC_LR

;=================
; TLB lock down
;=================
;void MMU_SetDTLBLockdown(U32 baseVictim)
   EXPORT MMU_SetDTLBLockdown
MMU_SetDTLBLockdown
   ;r0= baseVictim
   mcr p15,0,r0,c10,c0,0
   MOV_PC_LR

;void MMU_SetITLBLockdown(U32 baseVictim)
   EXPORT MMU_SetITLBLockdown
MMU_SetITLBLockdown
   ;r0= baseVictim
   mcr p15,0,r0,c10,c0,1
   MOV_PC_LR

;============
; Process ID
;============
;void MMU_SetProcessId(U32 pid)
   EXPORT MMU_SetProcessId
MMU_SetProcessId
   ;r0= pid
   mcr p15,0,r0,c13,c0,0
   MOV_PC_LR

   END

Revision history for this message
Steffen Sutton (steffensq) said :
#5

Hi Thomas,

I've added the assembly file in question above. Forgive me, I don't know if there is a proper way to add files to launchpad.

Regards

Revision history for this message
Thomas Preud'homme (thomas-preudhomme) said :
#6

Hi Steffen,

It seems there is some define missing somewhere, such as MOV_LR_PC. Also the macro syntax is not the one GNU as understand. The instruction should work as per documented in the ARM ARM but all the capitalized directives are assembler specific and thus needs to be ported to GNU as. I suggest that you look at the GNU as directive syntax:

target-independent directives
https://sourceware.org/binutils/docs/as/Pseudo-Ops.html#Pseudo-Ops

ARM-specific directives
https://sourceware.org/binutils/docs/as/ARM-Directives.html#ARM-Directives

Best regards.

Revision history for this message
Steffen Sutton (steffensq) said :
#7

Hi Thomas,

I appreciate your help, with your clarification I've managed to port a majority of the assembly files I have.

I have one last question, would you be able to explain the code below, particularly the brackets?

.global FCLK
.set FCLK, 20000000

    [ FCLK = 20000000
.equ M_MDIV , 0x20 @Fin=12.0MHz Fout=30.0MHz
.equ M_PDIV , 0x4
.equ M_SDIV , 0x2
    ]

    [ FCLK = 30000000
.equ M_MDIV , 0x34 @Fin=12.0MHz Fout=30.0MHz
.equ M_PDIV , 0x4
.equ M_SDIV , 0x2
    ]

It looks like an if statement, but I'm having trouble finding the syntax for this expression.

Here is another example

ASSERT :DEF:BUSWIDTH
    [ BUSWIDTH=16
.equ B1_BWSCON , (DW16)
.equ B2_BWSCON , (DW16)
.equ B3_BWSCON , (DW16)
.equ B4_BWSCON , (DW16)
.equ B5_BWSCON , (DW16)
.equ B6_BWSCON , (DW16)
.equ B7_BWSCON , (DW16)
 | @BUSWIDTH=32
.equ B1_BWSCON , (DW32)
.equ B2_BWSCON , (DW16)
.equ B3_BWSCON , (DW16)
.equ B4_BWSCON , (DW16)
.equ B5_BWSCON , (DW16)
.equ B6_BWSCON , (DW32)
.equ B7_BWSCON , (DW32)
 ]

Can you help with this problem?

Provide an answer of your own, or ask Steffen Sutton for more information if necessary.

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