Cortex M0 - Issue with invalid assembly generation

Hey everyone,

I'm having an issue that I really cannot figure out for the life of me. I'm trying to port the ST VL53L0x API to an nRF51422_QFAC (the nRF DK). I'm calling the VL53L0X_DataInit function in vl53l0x_api.c, which calls VL53L0X_WrByte function, which is where I'm having my problem. Here is the source code:

 VL53L0X_Error VL53L0X_WrByte(VL53L0X_DEV Dev, uint8_t index, uint8_t data){
  VL53L0X_Error Status = VL53L0X_ERROR_NONE;
  int32_t status_int;
 uint8_t deviceAddress;

 deviceAddress = Dev->I2cDevAddr;

 status_int = VL53L0X_write_byte(deviceAddress, index, data);

 if (status_int != 0)
  Status = VL53L0X_ERROR_CONTROL_INTERFACE;

    return Status;
}

The problem (I think) is that my generated assembly tries to load 0x15C from r3 in an ldrb instruction. Here is the generated assembly from the above method:

                               VL53L0X_WrByte:
0001ee70: VL53L0X_WrByte+0 movs r3, #174 ; 0xae
146 VL53L0X_Error VL53L0X_WrByte(VL53L0X_DEV Dev, uint8_t index, uint8_t data){
0001ee72: VL53L0X_WrByte+2 push {r4, lr}
151 deviceAddress = Dev->I2cDevAddr;
0001ee74: VL53L0X_WrByte+4 lsls r3, r3, #1
153 status_int = VL53L0X_write_byte(deviceAddress, index, data);
0001ee76: VL53L0X_WrByte+6 ldrb r0, [r0, r3]
0001ee78: VL53L0X_WrByte+8 bl 0x1ed14 <VL53L0X_write_byte>
147 VL53L0X_Error Status = VL53L0X_ERROR_NONE;
0001ee7c: VL53L0X_WrByte+12 movs r3, #0
155 if (status_int != 0)
0001ee7e: VL53L0X_WrByte+14 cmp r0, #0
0001ee80: VL53L0X_WrByte+16 bne.n 0x1ee86 <VL53L0X_WrByte+22>
159 }
0001ee82: VL53L0X_WrByte+18 movs r0, r3
0001ee84: VL53L0X_WrByte+20 pop {r4, pc}
156 Status = VL53L0X_ERROR_CONTROL_INTERFACE;
0001ee86: VL53L0X_WrByte+22 subs r3, #20
0001ee88: VL53L0X_WrByte+24 b.n 0x1ee82 <VL53L0X_WrByte+18>
0001ee8a: nop ; (mov r8, r8)
166 deviceAddress = Dev->I2cDevAddr;

It happens at 0x0001ee76. As you can see, r3 is 174, then it's left shifted so it becomes 348. Then it's trying to offset a memory address with a byte, but 348 is too large.

Output of my GCC version

$ arm-none-eabi-gcc --version
arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]
Copyright (C) 2015 Free Software Foundation, Inc.

Am I on the right track here? What is the general thought process behind the optimizations that created this assembly? Should I file a bug on this? Are there any other details I should include?

Thanks in advance.