GNU Arm Embedded Toolchain

ARM GCC 4.6 : sprintf and float

Asked by Prakash K Balasubramanian

I have this in an ISR.
char pBuff[10];
sprintf(pBuff, "%5.1f", 12.5);

When the Stack pointer is aligned to a 8 Byte boundary just before invocation of the sprintf function,pBuff is filled quite correctly.

No joy when the SP is aligned to 4 Byte boundary.

The SP on our Cortex-M4 device is programmed to 0x20000800 when control to main() is given.

Has anybody dealt with this before?

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Prakash K Balasubramanian
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Prakash K Balasubramanian (prakash-balasubramanian) said : 		#1

How can it be ensured that the stack pointer is always 8 byte aligned upon invocation of a function/ISR? Is there a compilation option which would enforce the desired alignment?

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Joey Ye (jinyun-ye) said : 		#2

Prakash,

I'm suspecting a reason but need some information to confirm.

Can you please share:
- Which exact GCC release version (4.6 isn't accurat enough to locate)
- the whole isv function
- disasmble of your isv function

Thanks,
Joey

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Prakash K Balasubramanian (prakash-balasubramanian) said : 		#3

I have an update. This problem is solved.

Due to a silicon bug, I had to introduce a veneer to the ISRs. The veneer broke the 8byte alignment rule.
It is fixed now. When the ISR is called by the veneer, the SP is correctly aligned to 8 bytes and the sprintf works like charm.