Q about code generation for Cortex M3

I'm using GCC ARM Embedded 4.7-2013-q1-update and have -O3 turned on.

I've selected the ARM v7M architecture and set the core type to Cortex-M3.

I have variables that are 8 bit, 16 bit and 32 bit and I was looking to see how values are converted and saw the following which seemed not quite optimal.

Here is the code snippet and associated output. I don't understand why the uxth/uxtb instructions are there. If my understanding of the instruction set is correct, the load instructions sign extend on load.

Thanks.

volatile unsigned int vuiFoo;
volatile unsigned short vuwFoo;
volatile unsigned char vucFoo;

vuiFoo = vuwFoo;
    F8BD8008 ldrh.w r8, [sp, #8]
    FA1FF288 uxth r2, r8
    9200 str r2, [sp]

vuwFoo = vuiFoo;
    9F00 ldr r7, [sp]
    B2BE uxth r6, r7
    F8AD6008 strh.w r6, [sp, #8]

vuiFoo = vucFoo;
    F89D500B ldrb.w r5, [sp, #11]

vuiFoo = vucFoo;
    9500 str r5, [sp]

vucFoo = vuiFoo;
    9C00 ldr r4, [sp]
    B2E1 uxtb r1, r4
    F88D100B strb.w r1, [sp, #11]