gcc-arm-none-eabi-4_7-2012q4-20121208 broken for CMSIS

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Question

When compiling applications that contain or use the Cortex Microcontroller Software Interface Standard e.g. CMSIS (http://www.onarm.com/cmsis/) you may receive the following errors:
/tmp/ccaxp69S.s: Assembler messages:
/tmp/ccaxp69S.s:463: Error: registers may not be the same -- `strexb r0,r0,[r1]'
/tmp/ccaxp69S.s:488: Error: registers may not be the same -- `strexh r0,r0,[r1]'

How do I fix these "registers may not be the same" errors? Where do they come from?

Answer

Some versions of the CMSIS contain invalid inline assembly of the following form:
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
 uint32_t result=0;
 asm volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
 return(result);
}

The first constraint =r on variable result is not correct, it should be =&r to indicate that the two registers used should not be the same e.g. early-clobber (this is required by the ARM Instruction Set Architecture).

To fix the error you must locate the invalid inline assembly and change the =r to =&r for the result register variable.

Often it is difficult to determine which source file was used to generate /tmp/ccaxp69S.s, to help with that problem add -save-temps to the compiler invocation to save the intermediate output to the current directory for your review.

 This entry was last updated on 8 February 2012.

Thank both of you for trying our tool chain and share experience.

I just checked the M0 arch doc and found that the strexb is supported starting from armv7-m. So it makes sense to generate error message " selected processor does not support Thumb mode..." for cortex-m0.

For cortex-m3, it should work and we need to update "=r" to "=&r". In latest CMSIS, it is already updated. Here is the result of grep:

terguo01@sha-win-053 /cygdrive/d/work/cmsis/CMSIS_V3P00
$ grep -r "strexb" *
CMSIS/Include/core_cmInstr.h: __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );

You can upgrade your CMSIS to fix this issue. The latest CMSIS can be found at http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php.

Hmm, "=&r" could resolve the problem. But, why Rn and Rt in STREX could not be the same? ARM® v7-M Architecture Reference Manual(Derrata 2010_Q3) said:

STREXB<c> <Rd>,<Rt>,[<Rn>]
d = UInt(Rd); t = UInt(Rt); n = UInt(Rn);
if d IN {13,15} || t IN {13,15} || n == 15 then UNPREDICTABLE;
if d == n || d == t then UNPREDICTABLE;

But d == t is not a wrong case in the manual.

Besides, GCC 4.6 could compile the code. Which one is wrong?

Thanks Terry Guo, that solved my question.

Hello,

I have tested the original example here with my Cortex-M3 example too.
I have added the code:

#define __ASM __asm
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
   uint32_t result=0;

   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
   return(result);
}

And had no problems. I use the latest version under windows from 2012-12-24:

arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.7.3 20121207 (releas
e) [ARM/embedded-4_7-branch revision 194305]
Copyright (C) 2012 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

I have added the code to my example here:
http://www.emb4fun.de/download/arm/examples/STM32Test.zip

It is strange that I does not get the error.

Best regards,
Michael

Hi Michael,

Can you please share your command line options on Windows? The original example is compiled with -O2. And with -O2, the tool chain on windows can generate this error in my environment:

 $ arm-none-eabi-gcc -mthumb -mcpu=cortex-m3 -c m3.c -O2
D:\Cygwin\cygwin\tmp\ccjhexe2.s: Assembler messages:
D:\Cygwin\cygwin\tmp\ccjhexe2.s:26: Error: registers may not be the same -- `strexb r0,r0,[r1]'

And with -O0, there is no such error for tool chain on Windows and Linux.

So far I haven't observed any different behaviors between Windows and Linux tool chain.

Best regards,
Terry

Hello Terry,

ups, here the same. I have not test it before with optimization.
My example use -O0, with 1,2 or 3 I got the same error message.

Best regards,
Michael